LM3488MM
LM3488MM
LM3488, LM3488-Q1
SNVS089N JULY 2000 REVISED
DECEMBER 2014 www.kynix.com
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3488, LM3488-Q1
SNVS089N JULY 2000 REVISED DECEMBER 2014 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 12
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 16
3 Description ............................................................. 1 8 Application and Implementation ........................ 17
4 Revision History..................................................... 2 8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 3 9 Power Supply Recommendations...................... 28
6.1 Absolute Maximum Ratings ..................................... 3 10 Layout................................................................... 28
6.2 Handling Ratings : LM3488....................................... 4 10.1 Layout Guidelines ................................................. 28
6.3 Handling Ratings: LM3488-Q1.................................. 4 10.2 Layout Example .................................................... 29
6.4 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 29
6.5 Thermal Information .................................................. 4 11.1 Related Links ........................................................ 29
6.6 Electrical Characteristics........................................... 4 11.2 Trademarks ........................................................... 30
6.7 Typical Characteristics .............................................. 7 11.3 Electrostatic Discharge Caution ............................ 30
7 Detailed Description ............................................ 11 11.4 Glossary ................................................................ 30
7.1 Overview ................................................................. 11 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ....................................... 12 Information ........................................................... 30
4 Revision History
Changes from Revision M (March 2013) to Revision N Page
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
8-Pin DGK
VSSOP Package
Top View
Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
ISEN 1 I Current sense input pin. Voltage generated across an external sense resistor is fed into this pin.
COMP 2 A Compensation pin. A resistor, capacitor combination connected to this pin provides compensation for the
control loop.
FB 3 I Feedback pin. The output voltage should be adjusted using a resistor divider to provide 1.26 V at this pin.
AGND 4 P Analog ground pin.
PGND 5 P Power ground pin.
DR 6 O Drive pin of the IC. The gate of the external MOSFET should be connected to this pin.
FA/SYNC/S 7 A Frequency adjust, synchronization, and Shutdown pin. A resistor connected to this pin sets the oscillator
D frequency. An external clock signal at this pin will synchronize the controller to the frequency of the clock.
A high level on this pin for 30 s will turn the device off. The device will then draw less than 10A from
the supply.
VIN 8 P Power supply input pin.
6 Specifications
(1)
6.1 Absolute Maximum Ratings
MIN MAX UNIT
Input voltage 45 V
FB pin voltage 0.4 < VFB VFB < 7 V
FA/SYNC/SD pin voltage 0.4 < VFA/SYNC/SD VFA/SYNC/SD < 7 V
Peak driver output current (< 10 s) 1 A
Power dissipation Internally Limited
Junction temperature 150 C
Lead temperature Vapor Phase (60 s) 215 C
Infared (15 s) 260 C
DR pin voltage 0.4 VDR VDR 8 V
ILIM pin voltage 600 mV
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Conditions are
conditions under which operation of the device is intended to be functional. For specifications and test conditions, see the Electrical
Characteristics.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(1) The voltage on the drive pin, VDR is equal to the input voltage when input voltage is less than 7.2 V. VDR is equal to 7.2 V when the
input voltage is greater than or equal to 7.2 V.
(2) The limits for the maximum duty cycle can not be specified since the part does not permit less than 100% maximum duty cycle
operation.
(3) For this test, the FA/SYNC/SD Pin is pulled to ground using a 40K resistor .
(4) For this test, the FA/SYNC/SD Pin is pulled to 5 V using a 40K resistor.
(5) The over-voltage protection is specified with respect to the feedback voltage. This is because the over-voltage protection tracks the
feedback voltage. The over-voltage thresold can be calculated by adding the feedback voltage, VFB to the over-voltage protection
specification.
Copyright 20002014, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM3488 LM3488-Q1
LM3488, LM3488-Q1
SNVS089N JULY 2000 REVISED DECEMBER 2014 www.ti.com
(6) The FA/SYNC/SD pin should be pulled to VIN through a resistor to turn the regulator off.
Figure 1. IQ vs Temperature & Input Voltage Figure 2. ISupply vs Input Voltage (Non-Switching)
Figure 7. Current Sense Threshold vs Input Voltage Figure 8. COMP Pin Voltage vs Load Current
Figure 9. Efficiency vs Load Current (3.3 V In and 12 V Out) Figure 10. Efficiency vs Load Current (5 V In and 12 V Out)
Figure 11. Efficiency vs Load Current (9 V In and 12 V Out) Figure 12. Efficiency vs Load Current (3.3 V In and 5 V Out)
Figure 13. Error Amplifier Gain Figure 14. Error Amplifier Phase
Figure 15. COMP Pin Source Current vs Temperature Figure 16. Short Circuit Protection vs Input Voltage
Figure 17. Compensation Ramp vs Compensation Resistor Figure 18. Shutdown Threshold Hysteresis vs Temperature
7 Detailed Description
7.1 Overview
The LM3488 uses a fixed frequency, Pulse Width Modulated (PWM), current mode control architecture. In a
typical application circuit, the peak current through the external MOSFET is sensed through an external sense
resistor. The voltage across this resistor is fed into the ISEN pin. This voltage is then level shifted and fed into the
positive input of the PWM comparator. The output voltage is also sensed through an external feedback resistor
divider network and fed into the error amplifier negative input (feedback pin, FB). The output of the error amplifier
(COMP pin) is added to the slope compensation ramp and fed into the negative input of the PWM comparator.
At the start of any switching cycle, the oscillator sets the RS latch using the SET/Blank-out and switch logic
blocks. This forces a high signal on the DR pin (gate of the external MOSFET) and the external MOSFET turns
on. When the voltage on the positive input of the PWM comparator exceeds the negative input, the RS latch is
reset and the external MOSFET turns off.
The voltage sensed across the sense resistor generally contains spurious noise spikes, as shown in Figure 20.
These spikes can force the PWM comparator to reset the RS latch prematurely. To prevent these spikes from
resetting the latch, a blank-out circuit inside the IC prevents the PWM comparator from resetting the latch for a
short duration after the latch is set. This duration is about 150ns and is called the blank-out time.
Under extremely light load or no-load conditions, the energy delivered to the output capacitor when the external
MOSFET is on during the blank-out time is more than what is delivered to the load. An over-voltage comparator
inside the LM3488 prevents the output voltage from rising under these conditions. The over-voltage comparator
senses the feedback (FB pin) voltage and resets the RS latch under these conditions. The latch remains in reset
state till the output decays to the nominal value.
(1)
From the above equation, when D > 0.5, I1 will be greater than IO. In other words, the disturbance is divergent.
So a very small perturbation in the load will cause the disturbance to increase.
To prevent the sub-harmonic oscillations, a compensation ramp is added to the control signal, as shown in
Figure 22.
(2)
The compensation ramp has been added internally in LM3488. The slope of this compensation ramp has been
selected to satisfy most of the applications. The slope of the internal compensation ramp depends on the
frequency. This slope can be calculated using the formula:
MC = VSL.FS Volts/second (3)
In the above equation, VSL is the amplitude of the internal compensation ramp. Limits for VSL have been specified
in the electrical characteristics.
In order to provide the user additional flexibility, a patented scheme has been implemented inside the IC to
increase the slope of the compensation ramp externally, if the need arises. Adding a single external resistor,
RSL(as shown in Figure 23) increases the slope of the compensation ramp, MC by :
. .
40x10-6 RSL FS Amps
'MC = second
RSEN
(4)
-6
In this equation, VSL is equal to 40.10 RSL. Hence,
(5)
VSL versus RSL has been plotted in Figure 24 for different frequencies.
It is also necessary to have the width of the synchronization pulse wider than the duty cycle of the converter
(when DR pin is high and the switching point is low). It is also necessary to have the synchronization pulse width
300nsecs.
The FA/SYNC/SD pin also functions as a shutdown pin. If a high signal (see Electrical Characteristics for
definition of high signal) appears on the FA/SYNC/SD pin, the LM3488 stops switching and goes into a low
current mode. The total supply current of the IC reduces to less than 10A under these conditions.
Figure 27 and Figure 28 show implementation of shutdown function when operating in Frequency adjust mode
and synchronization mode respectively. In frequency adjust mode, connecting the FA/SYNC/SD pin to ground
forces the clock to run at a certain frequency. Pulling this pin high shuts down the IC. In frequency adjust or
synchronization mode, a high signal for more than 30s shuts down the IC.
Figure 29 shows implementation of both frequency adjust with RFA resistor and frequency synchronization with
RSYNC. The switching frequency is defined by RFA when a synchronization signal is not applied. When sync is
applied it overrides the RFA setting.
RSYNC CSYNC
FA/SYNC/SD
LM3488 270 pF
RFA
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
+
CIN
100 PF, 6.3V
L
10 PH
ISEN VIN
D MBRD340 VOUT = 5V, 2A
CC 22 nF RFA
COMP FA/SD/SYNC
+ COUT
RC 20k LM3488 40k
Q1 100 PF, 10V
4.7k FB DR
IRF7807 x2
RF1
AGND PGND 60k
RF2
CSN RSN
0.01 PF 0.025:
The most common topology for LM3488 is the boost or step-up topology. The boost converter converts a low
input voltage into a higher output voltage. The basic configuration for a boost regulator is shown in Figure 31. In
continuous conduction mode (when the inductor current never reaches zero at steady state), the boost regulator
operates in two cycles. In the first cycle of operation, MOSFET Q is turned on and energy is stored in the
inductor. During this cycle, diode D is reverse biased and load current is supplied by the output capacitor, COUT.
In the second cycle, MOSFET Q is off and the diode is forward biased. The energy stored in the inductor is
transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The
output voltage is defined as:
(6)
(ignoring the drop across the MOSFET and the diode), or
where
D is the duty cycle of the switch
VD is the forward voltage drop of the diode
VQ is the drop across the MOSFET when it is on (7)
(8)
IL (A)
t (s)
D*Ts Ts
(a)
ID (A)
VIN - V OUT
L
ID_AVG
=IOUT_AVG
t (s)
D*Ts Ts
(b)
ISW (A)
VIN
L
ISW_AVG
t (s)
D*Ts Ts
(C)
If VL(t) is constant, diL(t)/dt must be constant. Hence, for a given input voltage and output voltage, the current in
the inductor changes at a constant rate.
The important quantities in determining a proper inductance value are IL (the average inductor current) and iL
(the inductor current ripple). If iL is larger than IL, the inductor current will drop to zero for a portion of the cycle
and the converter will operate in discontinuous conduction mode. If iL is smaller than IL, the inductor current will
stay above zero and the converter will operate in continuous conduction mode. All the analysis in this datasheet
assumes operation in continuous conduction mode. To operate in continuous conduction mode, the following
conditions must be met:
IL > iL (9)
(10)
(11)
Choose the minimum IOUT to determine the minimum L. A common choice is to set iL to 30% of IL. Choosing an
appropriate core size for the inductor involves calculating the average and peak currents expected through the
inductor. In a boost converter,
(12)
and IL_peak = IL(max) + iL(max),
where
'iL = DVIN
2fSL (13)
A core size with ratings higher than these values should be chosen. If the core is not properly rated, saturation
will dramatically reduce overall efficiency.
The LM3488 can be set to switch at very high frequencies. When the switching frequency is high, the converter
can be operated with very small inductor values. With a small inductor value, the peak inductor current can be
extremely higher than the output currents, especially under light load conditions.
The LM3488 senses the peak current through the switch. The peak current through the switch is the same as the
peak current calculated above.
D
VOUT
COUT
DR Q
LM3488
ISEN
Rfb1
FB
RSEN
Rfb2
where
RSEN is the selected value based on current limit. With RSL installed, the control signal includes additional
external slope to stabilize the loop, which will also have an effect on the current limit threshold. Therefore, the
current limit threshold must be re-verified, as illustrated in the equations below : (20)
VCS = VSENSE (D x (VSL + VSL))
where
VSL is the additional slope compensation generated and calculated as: (21)
VSL = 40 A x RSL (22)
This changes the equation for current limit (or RSEN) to:
VSENSE - (D x(VSL + 'VSL))
ISWLIMIT =
RSEN (23)
The RSEN and RSL values may have to be calculated iteratively in order to achieve both the desired current limit
and stable operation. In some designs RSL can also help to filter noise on the ISEN pin.
If the inductor is selected such that ripple current is the recommended 30% value, and the current limit threshold
is 120% of the maximum peak, a simpler method can be used to determine RSEN. The equation below will
provide optimum stability without RSL, provided that the above 2 conditions are met:
VSENSE
RSEN =
Vo - Vi
ISWLIMIT + xD
L x fS
(24)
where
DMAX is the maximum duty cycle.
(26)
(27)
The turn-on and turn-off transitions of a MOSFET require times of tens of nano-seconds. CRSS and Qg are
needed to estimate the large instantaneous power loss that occurs during these transitions.
The amount of gate current required to turn the MOSFET on can be calculated using the formula:
IG = Qg.FS (28)
The required gate drive power to turn the MOSFET on is equal to the switching frequency times the energy
required to deliver the charge to bring the gate charge voltage to VDR (see the Electrical Characteristics table and
the Typical Characteristics section for the drive voltage specification).
PDrive = FS.Qg.VDR (29)
(30)
The input capacitor should be capable of handling the rms current. Although the input capacitor is not as critical
in a boost application, low values can cause impedance interactions. Therefore a good quality capacitor should
be chosen in the range of 10 F to 20 F. If a value lower than 10F is used, then problems with impedance
interactions or switching noise can affect the LM3488. To improve performance, especially with VIN below 8 volts,
it is recommended to use a 20 resistor at the input to provide a RC filter. The resistor is placed in series with
the VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 34). A 0.1-F or 1-F ceramic
capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the other side
of the resistor with the input power supply.
RIN VIN
VIN
(31)
Where
(32)
and D, the duty cycle is equal to (VOUT VIN)/VOUT.
The ESR and ESL of the output capacitor directly control the output ripple. Use capacitors with low ESR and ESL
at the output for high efficiency and low ripple voltage. Surface Mount tantalums, surface mount polymer
electrolytic and polymer tantalum, Sanyo- OSCON, or multi-layer ceramic capacitors are recommended at the
output.
Due to the presence of the inductor L1 at the input, the SEPIC inherits all the benefits of a boost converter. One
main advantage of SEPIC over boost converter is the inherent input to output isolation. The capacitor CS isolates
the input from the output and provides protection against shorted or malfunctioning load. Hence, the A SEPIC is
useful for replacing boost circuits when true shutdown is required. This means that the output voltage falls to 0V
when the switch is turned off. In a boost converter, the output can only fall to the input voltage minus a diode
drop.
(33)
In the above equation, VQ is the on-state voltage of the MOSFET, Q, and VDIODE is the forward voltage drop of
the diode.
(36)
The rms current through the switch is given by:
(37)
(38)
IL2AVE = IOUT (39)
(40)
(41)
maintains the condition IL > iL/2 to ensure constant current mode.
(VIN - VQ)(1-D)
L1 >
2IOUTfS (42)
(VIN - VQ)D
L2 >
2IOUTfS
(43)
Peak current in the inductor, to ensure the inductor does not saturate:
(44)
(45)
IL1PK must be lower than the maximum current rating set by the current sense resistor.
The value of L1 can be increased above the minimum recommended to reduce input ripple and output ripple.
However, once DIL1 is less than 20% of IL1AVE, the benefit to output ripple is minimal.
By increasing the value of L2 above the minimum recommended, IL2 can be reduced, which in turn will reduce
the output ripple voltage:
IOUT
'VOUT = ( 1-D +
'IL2
2 ) ESR
where
ESR is the effective series resistance of the output capacitor. (46)
If L1 and L2 are wound on the same core, then L1 = L2 = L. All the equations above will hold true if the
inductance is replaced by 2L. A good choice for transformer with equal turns is Coiltronics CTX series Octopack.
(48)
The SEPIC capacitor must be rated for a large ACrms current relative to the output power. This property makes
the SEPIC much better suited to lower power applications where the rms current through the capacitor is
relatively small (relative to capacitor technology). The voltage rating of the SEPIC capacitor must be greater than
the maximum input voltage. Tantalum capacitors are the best choice for SMT, having high rms current ratings
relative to size. Ceramic capacitors could be used, but the low C values will tend to cause larger changes in
voltage across the capacitor due to the large currents. High C value ceramics are expensive. Electrolytics work
well for through hole applications where the size required to meet the rms current rating can be accommodated.
There is an energy balance between CS and L1, which can be used to determine the value of the capacitor. The
basic energy balance equation is:
(49)
Where
(50)
is the ripple voltage across the SEPIC capacitor, and
(51)
is the ripple current through the inductor L1. The energy balance equation can be solved to provide a minimum
value for CS:
(52)
(53)
The input capacitor should be capable of handling the rms current. Although the input capacitor is not as critical
in a boost application, low values can cause impedance interactions. Therefore a good quality capacitor should
be chosen in the range of 10F to 20F. If a value lower than 10F is used, then problems with impedance
interactions or switching noise can affect the LM3488. To improve performance, especially with VIN below 8 volts,
it is recommended to use a 20 resistor at the input to provide a RC filter. The resistor is placed in series with
the VIN pin with only a bypass capacitor attached to the VIN pin directly (see Figure 34). A 0.1F or 1F ceramic
capacitor is necessary in this configuration. The bulk input capacitor and inductor will connect on the other side
of the resistor with the input power supply.
The ESR and ESL of the output capacitor directly control the output ripple. Use low capacitors with low ESR and
ESL at the output for high efficiency and low ripple voltage. Surface mount tantalums, surface mount polymer
electrolytic and polymer tantalum, Sanyo- OSCON, or multi-layer ceramic capacitors are recommended at the
output for low ripple.
10 Layout
To Output
Tune Performance
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 1-Nov-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM3488MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM -40 to 125 S21B
& no Sb/Br)
LM3488MMX NRND VSSOP DGK 8 TBD Call TI Call TI -40 to 125 S21B
LM3488MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS CU NIPDAUAG | CU SN Level-1-260C-UNLIM -40 to 125 S21B
& no Sb/Br)
LM3488QMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SSKB
& no Sb/Br)
LM3488QMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SSKB
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Sep-2015
Pack Materials-Page 2
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