Uc3842 PDF
Uc3842 PDF
NC 2 13 NC
FEATURES 3 12 V
Low start-up current (1mA)
VFB CC
NC 4 11 V
C
Automatic feed-forward compensation ISENSE 5 10 OUTPUT
BLOCK DIAGRAM
7(11)
(12)7
VCC
34V UVLO V
8(14) REF
(9)5 S/R 5V 5.0V
GND REF 50mA
6V
16V
2.5V INTERNAL
BIAS
(7)4
RT/CT OSC
6(10)
OUTPUT
ERROR S
AMP
2R
(3)2 + PWM
VFB R LATCH
R
(1)1 1V CURRENT
COMP SENSE
COMPARATOR
(5)3
CURRENT
SENSE
5(8)
NOTE:
Pin numbers in parentheses refer to the D package.
ORDERING INFORMATION
DESCRIPTION TEMPERATURE RANGE ORDER CODE DWG #
8-Pin Plastic Dual In-Line Package (DIP) 0 to +70C UC3842N 0404B
14-Pin Plastic Small Outline (SO) Package 0 to +70C UC3842D 0405B
7
2.5V
VCC ON/OFF COMMAND 0.5mA
TO REST OF IC
+
ZI 2
VFB
1
UC3842 COMP
VON 16V
VOFF 10V NOTE:
Error AMP can source or sink up to 0.5mA.
ICC
<15mA
<1mA
VCC
VOFF VON
NOTE:
During Undervoltage Lock-Out, the output driver is biased to a high
impedance state. Pin 6 should be shunted to ground with a bleeder
resistor to prevent activating the power switch with output leakage current.
ERROR
AMP
IS 2R
CURRENT
SENSE
COMPARATOR
1 R 1V
COMP
R 3
CURRENT
SENSE
RS
5
GND
NOTE:
Peak current (IS) is determined by the formula:
1.0V
I MAX
S Rs
80 0
SATURATION VOLTAGE (V)
3 0
Av
45
PHASE (DEG)
60
2 40 90
20 135
1 0 180
20 225
10 100 1k 10k 100k 1M 10M
0
0.01 0.03 0.05 0.1 0.3 0.5 1.0 FREQUENCY (Hz)
OUTPUT CURRENT, SOURCE OR SINK (A)
VREF
RT A VCC
2N2222
4.7k UC3842
100k 1 8
COMP VREF 0.1F
ERROR AMP 2 7
ADJUST 0.1F 1k
VFB VCC
1W
3 6
5k OUTPUT
ISENSE OUTPUT
4.7k ISENSE 5
ADJUST 4
RT/CT GND
GND
CT
NOTE:
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to Pin 5 in a single point
ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Pin 3.
SHUTDOWN TECHNIQUES
4.7k 8
1
COMP
3
4.7k
ISENSE SHUTDOWN
500
SHUTDOWN
TO CURRENT
SENSE RESISTOR
NOTE:
Shutdown of the UC3842 can be accomplished by two methods; either raise Pin 3 above 1V or pull Pin 1 below a voltage two diode drops above ground. Either method causes the
output of the PWM comparator to be high (refer to Block Diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown
condition at Pins 1 and/or 3 is removed. In the examples shown, an externally-latched shutdown may be accomplished by adding an SCR which will be reset by cycling
VCC below the lower UVLO threshold (10V). At this point all internal bias is removed, allowing the SCR to reset.
16V
0.01F 10F
UC3842 820pF
VCC 7 20V
1N3613
20k
2.5k
2
150k VFB
6 27
1 OUT UFN432
20k
COMP NOTES:
T1: Coilcraft E-4140-B
3.6k 3 Primary 97 turns
100pF single AWG24
8 CUR 1k Secondary 4 turns
SEN 4 parallel
VREF AWG22
10k 470pF 0.85 control 9 turns
3 parallel AWG28
4
RT/CT
0.01F
0.0047F
5 ISOLATION
GND BOUNDARY
SPECIFICATIONS
NOTE:
Input line voltage: 90VAC to 130VAC
This circuit uses a low-cost feedback scheme in which the DC
Input frequency: 50 or 60Hz voltage developed from the primary-side control winding is sensed
Switching frequency: 40kHz10% by the UC3842 error amplifier. Load regulation is therefore
dependent on the coupling between secondary and control
Output power: 25W maximum
windings, and on transformer leakage inductance. For applications
Output voltage: 5V5% requiring better load regulation, a UC1901 Isolated Feedback
Output current: 2 to 5A Generator can be used to directly sense the output voltage.
VCC
4 8
RA RESET VCC 7
7
DISCH
3 RT/CT
RB OUT UC3842
NE555 4
2 TRIG
6 THRESH 5
GND
GND
C 1
NOTES: TO OTHER
UC3842s
1.44
f +
(R A ) 2R B) C
RB
D +
MAX RA ) 2R B