PS0199
PS0199
PS0199
Z8 Encore! XP F64xx
Series
Product Specification
PS019926-1114
ii
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-
cal component is any component in a life support device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
2014 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, Z8 Encore! XP and Z8 Encore! MC are trademarks or registered trademarks of Zilog, Inc.
All other product or service names are the property of their respective owners.
iii
Revision History
Each instance in the Revision History table reflects a change to this document from its pre-
vious revision. For more details, refer to the corresponding pages or appropriate links
listed in the table below.
Revision
Date Level Description Page
Nov 26 Corrected IPU Units value in DC Characteristics table to A from incorrect mA. 203
2014
Feb 25 Added footnote to Z8 Encore! XP F64xx Series Ordering Matrix table spe- 287
2014 cific to 64-pin LQFP packages.
Jan 24 Restored 40-pin PDIP package to Signal and Pin Descriptions and Packag- 7, 286
2013 ing chapters.
Feb 23 Corrected formatting of IDDS section, Table 107; corrected language in the 202, 248
2012 General Purpose RAM section of Appendix A;
Sep 22 Revised Flash Sector Protect Register description; revised Packaging 178, 286
2011 chapter.
Mar 21 Changed title to Z8 Encore! XP F64xx Series. All
2008
Feb 20 Changed Z8 Encore! XP 64K Series Flash Microcontrollers to Z8 Encore! 287, 234
2008 XP F64xx Series Flash Microcontrollers. Deleted three sentences that men-
tioned Z8R642. Removed the 40 PDIP package. Added
ZENETSC0100ZACG to the end of the Ordering Information table.
Changed the flag status to unaffected for BIT, BSET, and BCLR in the eZ8
CPU Instruction Summary table.
Dec 19 Updated Zilog logo, Disclaimer section, and implemented style guide. All
2007 Updated Table 113. Changed Z8 Encore! 64K Series to Z8 Encore! XP 64K
Series Flash Microcontrollers throughout the document.
Dec 18 Updated Flash Memory Electrical Characteristics and Timing table and 213, 287
2006 Ordering Information chapter.
Nov 17 Updated Part Number Suffix Designations section. 292
2006
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset and Stop Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
vi
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Timer Output Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Timer 03 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Timer 03 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 75
Timer 03 Control 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Timer 03 Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Watchdog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Watchdog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . . . 85
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Transmitting Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Transmitting Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . 90
Receiving Data using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Receiving Data using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . . . 92
Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Multiprocessor (9-Bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . 105
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
vii
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . . . . 112
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SPI Clock Phase and Polarity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Multimaster Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SPI Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SPI Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SPI Diagnostic State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SPI Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . 126
I2C Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SDA and SCL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
I2C Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Software Control of I2C Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Master Write and Read Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Address Only Transaction with a 7-bit Address . . . . . . . . . . . . . . . . . . . . . . . 133
Write Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Address Only Transaction with a 10-bit Address . . . . . . . . . . . . . . . . . . . . . . 135
Write Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Read Transaction with a 7-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Read Transaction with a 10-Bit Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
I2C Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
I2C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
I2C Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
I2C Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
I2C Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . 145
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xi
List of Figures
Figure 1. Z8 Encore! XP F64xx Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Z8 Encore! XP F64xx Series in 40-Pin Dual Inline Package (PDIP) . . . . . . 8
Figure 3. Z8 Encore! XP F64xx Series in 44-Pin Plastic Leaded Chip Carrier (PLCC) 9
Figure 4. Z8 Encore! XP F64xx Series in 44-Pin Low-Profile Quad Flat
Package (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Z8 Encore! XP F64xx Series in 64-Pin Low-Profile Quad Flat
Package (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Z8 Encore! XP F64xx Series in 68-Pin Plastic Leaded Chip
Carrier (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Z8 Encore! XP F64xx Series in 80-Pin Quad Flat Package (QFP) . . . . . . . 13
Figure 8. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 12. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 13. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 14. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . . . . . 89
Figure 15. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . . . . . 89
Figure 16. UART Asynchronous Multiprocessor Mode Data Format . . . . . . . . . . . . . 93
Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) . 95
Figure 18. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . . . . 97
Figure 19. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . 109
Figure 20. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 21. Infrared Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 22. SPI Configured as a Master in a Single-Master, Single-Slave System . . . 113
Figure 23. SPI Configured as a Master in a Single-Master, Multiple-Slave System . 114
Figure 24. SPI Configured as a Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 25. SPI Timing When PHASE is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 26. SPI Timing When PHASE is 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 27. I2C Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 28. 7-Bit Address Only Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 29. 7-Bit Addressed Slave Data Transfer Format . . . . . . . . . . . . . . . . . . . . . . 134
Figure 30. 10-Bit Address Only Transaction Format . . . . . . . . . . . . . . . . . . . . . . . . . 135
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List of Tables
Table 1. Z8 Encore! XP F64xx Series Part Selection Guide . . . . . . . . . . . . . . . . . . . . 2
Table 2. Z8 Encore! XP F64xx Series Package Options . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Pin Characteristics of the Z8 Encore! XP F64xx Series . . . . . . . . . . . . . . . 17
Table 5. Z8 Encore! XP F64xx Series Program Memory Maps . . . . . . . . . . . . . . . . 19
Table 6. Z8 Encore! XP F64xx Series Information Area Map . . . . . . . . . . . . . . . . . 21
Table 7. Z8 Encore! XP F64xx Series Register File Address Map . . . . . . . . . . . . . . 22
Table 8. Reset and Stop Mode Recovery Characteristics and Latency . . . . . . . . . . . 28
Table 9. Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. Stop Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . . 33
Table 11. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. Port Alternate Function Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. GPIO Port Registers and Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. Port AH GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . 40
Table 15. Port AH Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 16. Port AH Data Direction Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. Port AH Alternate Function Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 18. Port AH Output Control Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 19. Port AH High Drive Enable Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 20. Port AH Stop Mode Recovery Source Enable Subregisters . . . . . . . . . . . 45
Table 21. Port AH Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 22. Port AH Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 23. Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 24. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 25. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 26. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 27. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 28. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 55
Table 29. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 30. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 31. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 33. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
xiv
xv
Table 70. SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . . . . . . . . . . . . . . 127
Table 71. I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 72. I2C Status Register (I2CSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 73. I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 74. I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . . 146
Table 75. I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . . 146
Table 76. I2C Diagnostic State Register (I2CDST) . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 77. I2C Diagnostic Control Register (I2CDIAG) . . . . . . . . . . . . . . . . . . . . . . 149
Table 78. DMAx Control Register (DMAxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 79. DMAx I/O Address Register (DMAxIO) . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 80. DMAx Address High Nibble Register (DMAxH) . . . . . . . . . . . . . . . . . . . 155
Table 81. DMAx Start/Current Address Low Byte Register (DMAxSTART) . . . . . 156
Table 82. DMAx End Address Low Byte Register (DMAxEND) . . . . . . . . . . . . . . 156
Table 83. DMA_ADC Register File Address Example . . . . . . . . . . . . . . . . . . . . . . . 157
Table 84. DMA_ADC Control Register (DMAACTL) . . . . . . . . . . . . . . . . . . . . . . . 158
Table 85. DMA_ADC Address Register (DMAA_ADDR) . . . . . . . . . . . . . . . . . . . 158
Table 86. DMA_ADC Status Register (DMAA_STAT) . . . . . . . . . . . . . . . . . . . . . . 159
Table 87. ADC Control Register (ADCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 88. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 89. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 90. Flash Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 91. Flash Memory Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 92. Z8 Encore! XP F64xx Series Information Area Map . . . . . . . . . . . . . . . . 171
Table 93. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 94. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 95. Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 96. Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 97. Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . 179
Table 98. Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . 179
Table 99. Flash Option Bits At Flash Memory Address 0000h . . . . . . . . . . . . . . . . . 181
Table 100. Options Bits at Flash Memory Address 0001h . . . . . . . . . . . . . . . . . . . . . 182
Table 101. OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 102. On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 103. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 104. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 105. Recommended Crystal Oscillator Specifications (20 MHz Operation) . . . 197
xvi
xvii
xviii
Table 177. UART Baud Rate High Byte Register (UxBRH) . . . . . . . . . . . . . . . . . . . 258
Table 178. UART Baud Rate Low Byte Register (UxBRL) . . . . . . . . . . . . . . . . . . . . 259
Table 179. UART Transmit Data Register (UxTXD) . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 180. UART Receive Data Register (UxRXD) . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 181. UART Status 0 Register (UxSTAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 182. UART Control 0 Register (UxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 183. UART Control 1 Register (UxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 184. UART Status 1 Register (UxSTAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 185. UART Address Compare Register (UxADDR) . . . . . . . . . . . . . . . . . . . . . 260
Table 186. UART Baud Rate High Byte Register (UxBRH) . . . . . . . . . . . . . . . . . . . 261
Table 187. UART Baud Rate Low Byte Register (UxBRL) . . . . . . . . . . . . . . . . . . . . 261
Table 188. I2C Data Register (I2CDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 189. I2C Status Register (I2CSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 190. I2C Control Register (I2CCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 191. I2C Baud Rate High Byte Register (I2CBRH) . . . . . . . . . . . . . . . . . . . . . 262
Table 192. I2C Baud Rate Low Byte Register (I2CBRL) . . . . . . . . . . . . . . . . . . . . . . 262
Table 193. I2C Diagnostic State Register (I2CDST) . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 194. I2C Diagnostic Control Register (I2CDIAG) . . . . . . . . . . . . . . . . . . . . . . 263
Table 195. SPI Data Register (SPIDATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Table 196. SPI Control Register (SPICTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 197. SPI Status Register (SPISTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 198. SPI Mode Register (SPIMODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 199. SPI Diagnostic State Register (SPIDST) . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 200. SPI Baud Rate High Byte Register (SPIBRH) . . . . . . . . . . . . . . . . . . . . . 265
Table 201. SPI Baud Rate Low Byte Register (SPIBRL) . . . . . . . . . . . . . . . . . . . . . . 265
Table 202. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 203. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 204. DMAx Control Register (DMAxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 205. DMAx I/O Address Register (DMAxIO) . . . . . . . . . . . . . . . . . . . . . . . . . 267
Table 206. DMAx Address High Nibble Register (DMAxH) . . . . . . . . . . . . . . . . . . . 267
Table 207. DMAx Start/Current Address Low Byte Register (DMAxSTART) . . . . . 267
Table 208. DMAx End Address Low Byte Register (DMAxEND) . . . . . . . . . . . . . . 268
Table 209. DMAx Control Register (DMAxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 210. DMAx I/O Address Register (DMAxIO) . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 211. DMAx Address High Nibble Register (DMAxH) . . . . . . . . . . . . . . . . . . . 269
Table 212. DMAx Start/Current Address Low Byte Register (DMAxSTART) . . . . . 269
xix
Table 213. DMAx End Address Low Byte Register (DMAxEND) . . . . . . . . . . . . . . 269
Table 214. DMA_ADC Address Register (DMAA_ADDR) . . . . . . . . . . . . . . . . . . . 269
Table 215. DMA_ADC Control Register (DMAACTL) . . . . . . . . . . . . . . . . . . . . . . . 270
Table 216. DMA_ADC Status Register (DMAA_STAT) . . . . . . . . . . . . . . . . . . . . . . 270
Table 217. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Table 218. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . 271
Table 219. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . 271
Table 220. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 221. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . 271
Table 222. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . 272
Table 223. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 224. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . 272
Table 225. IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . 272
Table 226. Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 227. Interrupt Port Select Register (IRQPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 228. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 229. Port AH GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . 274
Table 230. Port AH Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 231. Port AH Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 232. Port AH Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 233. Port AH GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . 275
Table 234. Port AH Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 235. Port AH Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 236. Port AH Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 237. Port AH GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . 276
Table 238. Port AH Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 239. Port AH Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 240. Port AH Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 241. Port AH GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . 277
Table 242. Port AH Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 243. Port AH Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 244. Port AH Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 245. Port AH GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . 278
Table 246. Port AH Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 247. Port AH Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 248. Port AH Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 279
xx
Introduction
Zilogs Z8 Encore! XP F64xx Series MCU family of products are a line of Zilog micro-
controller products based upon the 8-bit eZ8 CPU. The Z8 Encore! XP F64xx Series adds
Flash memory to Zilogs extensive line of 8-bit microcontrollers. The Flash in-circuit pro-
gramming capability allows for faster development time and program changes in the field.
The new eZ8 CPU is upward-compatible with existing Z8 instructions. The rich-periph-
eral set of the Z8 Encore! XP F64xx Series makes it suitable for a variety of applications
including motor control, security systems, home appliances, personal electronic devices,
and sensors.
Features
The features of Z8 Encore! XP F64xx Series include:
20 MHz eZ8 CPU
Up to 64 KB Flash with in-circuit programming capability
Up to 4 KB register RAM
12-channel, 10-bit Analog-to-Digital Converter (ADC)
Two full-duplex 9-bit UARTs with bus transceiver Driver Enable control
Inter-integrated circuit (I2C)
Serial Peripheral Interface (SPI)
Two Infrared Data Association (IrDA)-compliant infrared encoder/decoders
Up to four 16-bit timers with capture, compare and PWM capability
Watchdog Timer (WDT) with internal RC oscillator
Three-channel DMA
Up to 60 input/output (I/O) pins
24 interrupts with configurable priority
On-Chip Debugger
Voltage Brown-Out (VBO) Protection
Power-On Reset (POR)
Operating voltage of 3.0 V to 3.6 V with 5 V-tolerant inputs
0C to +70C, 40C to +105C, and 40C to +125C operating temperature ranges
16-bit 40-/
Part Flash RAM Timers ADC UARTs 44-Pin 64/68-Pin 80-Pin
Number (KB) (KB) I/O with PWM Inputs with IrDA I2C SPI Package Package Package
Z8F1621 16 2 31 3 8 2 1 1 X
Z8F1622 16 2 46 4 12 2 1 1 X
Z8F2421 24 2 31 3 8 2 1 1 X
Z8F2422 24 2 46 4 12 2 1 1 X
Z8F3221 32 2 31 3 8 2 1 1 X
Z8F3222 32 2 46 4 12 2 1 1 X
Z8F4821 48 4 31 3 8 2 1 1 X
Z8F4822 48 4 46 4 12 2 1 1 X
Z8F4823 48 4 60 4 12 2 1 1 X
Z8F6421 64 4 31 3 8 2 1 1 X
Z8F6422 64 4 46 4 12 2 1 1 X
Z8F6423 64 4 60 4 12 2 1 1 X
Note: For die form sales, contact your local Zilog Sales Office.
Block Diagram
Figure 1 displays the architecture of the Z8 Encore! XP F64xx Series.
XTAL/RC On-Chip
Oscillator Debugger
POR/VBO
eZ8TM
Interrupt and Reset WDT with
CPU
Controller Controller RC Oscillator
System
Clock
Memory Busses
Register Bus
IrDA
Flash
RAM
Memory
GPIO
Software stack allows much greater depth in subroutine calls and interrupts than hard-
ware stacks
Compatible with existing Z8 code
Expanded internal register file allows access of up to 4 KB
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT and SRL
New instructions support 12-bit linear addressing of the register file
Up to 10 MIPS operation
C-Compiler friendly
2 to 9 clock cycles per instruction
For more information about the eZ8 CPU, refer to the eZ8 CPU Core User Manual
(UM0128), which is available for download on www.zilog.com.
General-Purpose Input/Output
The Z8 Encore! XP F64xx Series features seven 8-bit ports (ports AG) and one 4-bit port
(Port H) for general-purpose input/output (GPIO). Each pin is individually programmable.
All ports (except B and H) support 5 V-tolerant inputs.
Flash Controller
The Flash Controller programs and erases the contents of Flash memory.
UARTs
Each UART is full-duplex and capable of handling asynchronous data transfers. The
UARTs support 8- and 9-bit data modes, selectable parity, and an efficient bus transceiver
Driver Enable signal for controlling a multitransceiver bus, such as RS-485.
I2C
The I2C controller makes the Z8 Encore! XP F64xx Series compatible with the I2C proto-
col. The I2C controller consists of two bidirectional bus lines, a serial data (SDA) line and
a serial clock (SCL) line.
Timers
Up to four 16-bit reloadable timers can be used for timing/counting events or for motor
control operations. These timers provide a 16-bit programmable reload counter and oper-
ate in One-Shot, Continuous, Gated, Capture, Compare, Capture/Compare and PWM
modes. Only 3 timers (Timer 02) are available in the 44-pin package.
Interrupt Controller
The Z8 Encore! XP F64xx Series products support up to 24 interrupts. These interrupts
consist of 12 internal and 12 GPIO pins. The interrupts have 3 levels of programmable
interrupt priority.
Reset Controller
The Z8 Encore! XP F64xx Series can be reset using the RESET pin, Power-On Reset,
Watchdog Timer, Stop Mode exit, or Voltage Brown-Out (VBO) warning signal.
On-Chip Debugger
The Z8 Encore! XP F64xx Series features an integrated On-Chip Debugger. The OCD
provides a rich set of debugging capabilities, such as reading and writing registers, pro-
gramming the Flash, setting breakpoints and executing code. A single-pin interface pro-
vides communication to the OCD.
DMA Controller
The Z8 Encore! XP F64xx Series feature three channels of DMA. Two of the channels are
for register RAM to and from I/O operations. The third channel automatically controls the
transfer of data from the ADC to the memory.
Available Packages
Table 2 identifies the package styles that are available for each device within the Z8
Encore! XP F64xx Series product line.
Pin Configurations
Figures 2 through 7 display the pin configurations for all of the packages available in the
Z8 Encore! XP F64xx Series. For signal descriptions, see Table 3 on page 14.
PD4/RXD1 1 40 PD5/TXD1
PD3/DE1 PC4/MOSI
PC5/MISO PA4/RXD0
PA3/CTS0 PA5/TXD0
PA2/DE0 5 PA6/SCL
PA1/T0OUT 35 PA7/SDA
PA0/T0IN PD6/CTS1
PC2/SS PC3/SCK
RESET VSS
VDD 10 VDD
VSS 30 PC6/T2IN
PD1 DBG
PD0 PC1/T1OUT
XOUT PC0/T1IN
XIN 15 AVSS
AVDD 25 VREF
PB0/ANA0 PB2/ANA2
PB1/ANA1 PB3/ANA3
PB4/ANA4 PB7/ANA7
PB5/ANA5 20 21 PB6/ANA6
Note: Timer 3 and T2OUT are not supported in the 40-pin PDIP package.
PA1/T0OUT
PD4/RXD1
PA4/RXD0
PA5/TXD0
PC5/MISO
PC4/MOSI
PA3/CTS0
PD5/TXD1
PA6/SCL
PD3/DE1
PA2/DE0
6 1 40
PA0/T0IN 7 39 PA7/SDA
PD2 PD6/CTS1
PC2/SS PC3/SCK
RESET VSS
VDD VDD
VSS 12 34 PC7/T2OUT
PD1 PC6/T2IN
PD0 DBG
XOUT PC1/T1OUT
XIN PC0/T1IN
VDD 17 29 VSS
18 23 28
AVSS
AVDD
PB0/ANA0
PB1/ANA1
PB4/ANA4
PB5/ANA5
PB6/ANA6
PB7/ANA7
PB3/ANA3
PB2/ANA2
VREF
Figure 3. Z8 Encore! XP F64xx Series in 44-Pin Plastic Leaded Chip Carrier (PLCC)
10
PA1/T0OUT
PD4/RXD1
PA4/RXD0
PA5/TXD0
PC5/MISO
PC4/MOSI
PA3/CTS0
PD5/TXD1
PA6/SCL
PD3/DE1
PA2/DE0
33 28 23
PA0/T0IN 34 22 PA7/SDA
PD2 PD6/CTS1
PC2/SS PC3/SCK
RESET VSS
VDD VDD
VSS 39 17 PC7/T2OUT
PD1 PC6/T2IN
PD0 DBG
XOUT PC1/T1OUT
XIN PC0/T1IN
VDD 44 12 VSS
1 6 11
AVSS
AVDD
PB0/ANA0
PB1/ANA1
PB4/ANA4
PB5/ANA5
PB6/ANA6
PB7/ANA7
PB3/ANA3
PB2/ANA2
VREF
Figure 4. Z8 Encore! XP F64xx Series in 44-Pin Low-Profile Quad Flat Package (LQFP)
11
PA1/T0OUT
PD4/RXD1
PA4/RXD0
PC4/MOSI
PD5/TXD1
PA3/CTS0
PA5/TXD0
PC5/MISO
PD3/DE1
PA2/DE0
PA6/SCL
PF7
VDD
VDD
VSS
VSS
48 40 33
PA0/T0IN 49 32 PA7/SDA
PD2 PD6/CTS1
PC2/SS PC3/SCK
RESET PD7/RCOUT
VDD VSS
PE4 PE5
PE3 PE6
VSS 56 25 PE7
PE2 VDD
PE1 PG3
PE0 VDD
VSS PC7/T2OUT
PD1/T3OUT PC6/T2IN
PD0/T3IN DBG
XOUT PC1/T1OUT
XIN 64 17 PC0/T1IN
1 8 16
VSS
AVSS
AVDD
PH0/ANA8
PH1/ANA9
PB0/ANA0
PB1/ANA1
PB4/ANA4
PB5/ANA5
PB6/ANA6
PB7/ANA7
PB3/ANA3
PH2/ANA10
PH3/ANA11
VREF
PB2/ANA2
Figure 5. Z8 Encore! XP F64xx Series in 64-Pin Low-Profile Quad Flat Package (LQFP)
12
PA1/T0OUT
PD4/RXD1
PA4/RXD0
PC4/MOSI
PD5/TXD1
PA3/CTS0
PA5/TXD0
PC5/MISO
PD3/DE1
PA2/DE0
PA6/SCL
VDD
VDD
PF7
VDD
VSS
VSS
9 1 61
PA0/T0IN 10 60 PA7/SDA
PD2 PD6/CTS1
PC2/SS PC3/SCK
RESET PD7/RCOUT
VDD VSS
PE4 PE5
PE3 PE6
VSS PE7
PE2 18 52 VDD
PE1 PG3
PE0 VDD
VSS PC7/T2OUT
VDD PC6/T2IN
PD1/T3OUT DBG
PD0/T3IN PC1/T1OUT
XOUT PC0/T1IN
XIN 26 44 VSS
27 35 43
PB2/ANA2
AVSS
AVSS
VSS
AVDD
PH0/ANA8
PH1/ANA9
PB0/ANA0
PB1/ANA1
PB4/ANA4
PB5/ANA5
PB6/ANA6
PB7/ANA7
PB3/ANA3
PH2/ANA10
PH3/ANA11
VREF
Figure 6. Z8 Encore! XP F64xx Series in 68-Pin Plastic Leaded Chip Carrier (PLCC)
13
PA1/T0OUT
PD4/RXD1
PA4/RXD0
PC4/MOSI
PD5/TXD1
PA3/CTS0
PA5/TXD0
PC5/MISO
PD3/DE1
PA2/DE0
PA6/SCL
PF7
VDD
VDD
VSS
VSS
80 75 70 65
PA0/T0IN 1 64 PA7/SDA
PD2 PD6/CTS1
PC2/SS PC3/SCK
PF6 PD7/RCOUT
RESET 5 60 PG0
VDD VSS
PF5 PG1
PF4 PG2
PF3 PE5
PE4 10 55 PE6
PE3 PE7
VSS VDD
PE2 PG3
PE1 PG4
PE0 15 50 PG5
VSS PG6
PF2 VDD
PF1 PG7
PF0 PC7/T2OUT
VDD 20 45 PC6/T2IN
PD1/T3OUT DBG
PD0/T3IN PC1/T1OUT
XOUT PC0/T1IN
XIN 24 41 VSS
25 30 35 40
PB2/ANA2
VSS
AVSS
AVDD
PH0/ANA8
PH1/ANA9
PB0/ANA0
PB1/ANA1
PB4/ANA4
PB5/ANA5
PB6/ANA6
PB7/ANA7
PB3/ANA3
PH2/ANA10
PH3/ANA11
VREF
14
Signal Descriptions
Table 3 lists the Z8 Encore! XP signals. To determine the available signals for a specific
package style, see the Pin Configurations section on page 8.
Signal
Mnemonic I/O Description
General-Purpose I/O Ports AH
PA[7:0] I/O Port A[7:0]. These pins are used for general-purpose I/O and support 5 V-toler-
ant inputs.
PB[7:0] I/O Port B[7:0]. These pins are used for general-purpose I/O.
PC[7:0] I/O Port C[7:0]. These pins are used for general-purpose I/O. These pins are used
for general-purpose I/O and support 5 V-tolerant inputs
PD[7:0] I/O Port D[7:0]. These pins are used for general-purpose I/O. These pins are used
for general-purpose I/O and support 5 V-tolerant inputs
PE[7:0] I/O Port E[7:0]. These pins are used for general-purpose I/O. These pins are used
for general-purpose I/O and support 5 V-tolerant inputs.
PF[7:0] I/O Port F[7:0]. These pins are used for general-purpose I/O. These pins are used
for general-purpose I/O and support 5 V-tolerant inputs.
PG[7:0] I/O Port G[7:0]. These pins are used for general-purpose I/O. These pins are used
for general-purpose I/O and support 5 V-tolerant inputs.
PH[3:0] I/O Port H[3:0]. These pins are used for general-purpose I/O.
2
I C Controller
SCL O Serial Clock. This is the output clock for the I2C. This pin is multiplexed with a
general-purpose I/O pin. When the general-purpose I/O pin is configured for
alternate function to enable the SCL function, this pin is open-drain.
SDA I/O Serial Data. This open-drain pin transfers data between the I2C and a slave.
This pin is multiplexed with a general-purpose I/O pin. When the general-pur-
pose I/O pin is configured for alternate function to enable the SDA function,
this pin is open-drain.
SPI Controller
SS I/O Slave Select. This signal can be an output or an input. If the Z8 Encore! XP
F64xx Series is the SPI master, this pin may be configured as the Slave Select
output. If the Z8 Encore! XP F64xx Series is the SPI slave, this pin is the input
slave select. It is multiplexed with a general-purpose I/O pin.
SCK I/O SPI Serial Clock. The SPI master supplies this pin. If the Z8 Encore! XP F64xx
Series is the SPI master, this pin is an output. If the Z8 Encore! XP F64xx
Series is the SPI slave, this pin is an input. It is multiplexed with a general-pur-
pose I/O pin.
15
Signal
Mnemonic I/O Description
SPI Controller (continued)
MOSI I/O Master-Out/Slave-In. This signal is the data output from the SPI master device
and the data input to the SPI slave device. It is multiplexed with a general-pur-
pose I/O pin.
MISO I/O Master-In/Slave-Out. This pin is the data input to the SPI master device and
the data output from the SPI slave device. It is multiplexed with a
general-purpose I/O pin.
UART Controllers
TXD0/TXD1 O Transmit Data. These signals are the transmit outputs from the UARTs. The
TxD signals are multiplexed with general-purpose I/O pins.
RXD0/RXD1 I Receive Data. These signals are the receiver inputs for the UARTs and IrDAs.
The RxD signals are multiplexed with general-purpose I/O pins.
CTS0/CTS1 I Clear To Send. These signals are control inputs for the UARTs. The CTS sig-
nals are multiplexed with general-purpose I/O pins.
DE0/DE1 O Driver Enable. This signal allows automatic control of external RS-485 drivers.
This signal is approximately the inverse of the Transmit Empty (TXE) bit in the
UART Status 0 Register. The DE signal may be used to ensure an external
RS-485 driver is enabled when data is transmitted by the UART.
Timers
T0OUT/ O Timer Output 0-3. These signals are output pins from the timers. The timer
T1OUT/ output signals are multiplexed with general-purpose I/O pins. T3OUT is not
T2OUT/ available in 44-pin package devices.
T3OUT
T0IN/T1IN/ I Timer Input 0-3. These signals are used as the capture, gating and counter
T2IN/T3IN inputs. The timer input signals are multiplexed with general-purpose I/O pins.
T3IN is not available in 44-pin package devices.
Analog
ANA[11:0] I Analog Input. These signals are inputs to the ADC. The ADC analog inputs are
multiplexed with general-purpose I/O pins.
VREF I Analog-to-Digital converter reference voltage input. The VREF pin must be left
unconnected (or capacitively coupled to analog ground) if the internal voltage
reference is selected as the ADC reference voltage.
16
Signal
Mnemonic I/O Description
Oscillators
XIN I External Crystal Input. This is the input pin to the crystal oscillator. A crystal
can be connected between it and the XOUT pin to form the oscillator. This sig-
nal is usable with external RC networks and an external clock driver.
XOUT O External Crystal Output. This pin is the output of the crystal oscillator. A crystal
can be connected between it and the XIN pin to form the oscillator. When the
system clock is referred to in this manual, it refers to the frequency of the sig-
nal at this pin. This pin must be left unconnected when not using a crystal.
RCOUT O RC Oscillator Output. This signal is the output of the RC oscillator. It is multi-
plexed with a general-purpose I/O pin. This signal must be left unconnected
when not using a crystal.
On-Chip Debugger
DBG I/O Debug. This pin is the control and data input and output to and from the On-
Chip Debugger. This pin is open-drain.
Caution: For operation of the On-Chip Debugger, all power pins (VDD and
AVDD) must be supplied with power and all ground pins (VSS and AVSS) must
be properly grounded. The DBG pin is open-drain and must have an external
pull-up resistor to ensure proper operation.
Reset
RESET I RESET. Generates a Reset when asserted (driven Low).
Power Supply
VDD I Power Supply.
AVDD I Analog Power Supply.
VSS I Ground.
AVSS I Analog Ground.
17
Pin Characteristics
Table 4 lists the characteristics for each pin available on the Z8 Encore! XP F64xx Series
products and the data is sorted alphabetically by the pin symbol mnemonic.
18
Address Space
The eZ8 CPU can access three distinct address spaces:
The register file contains addresses for the general-purpose registers and the eZ8 CPU,
peripheral and general-purpose I/O port control registers
The program memory contains addresses for all memory locations having executable
code and/or data
The Data Memory consists of the addresses for all memory locations that hold only data
These three address spaces are covered briefly in the following sections. For more infor-
mation about the eZ8 CPU and its address space, refer to the eZ8 CPU Core User Manual
(UM0128), which is available for download on www.zilog.com.
Register File
The register file address space in the Z8 Encore! XP F64xx Series is 4 KB (4096 bytes).
The register file is composed of two sections: control registers and general-purpose regis-
ters. When instructions are executed, registers are read from when defined as sources and
written to when defined as destinations. The architecture of the eZ8 CPU allows all gen-
eral-purpose registers to function as accumulators, address pointers, index registers, stack
areas, or scratch pad memory.
The upper 256 bytes of the 4 KB register file address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00h to FFFh. Some of the addresses within the 256-byte control register
section are reserved (unavailable). Reading from an reserved register file addresses returns
an undefined value. Writing to reserved register file addresses is not recommended and
can produce unpredictable results.
The on-chip RAM always begins at address 000h in the register file address space. The Z8
Encore! XP F64xx Series provide 2 KB to 4 KB of on-chip RAM depending upon the
device. Reading from register file addresses outside the available RAM addresses (and not
within the control register address space) returns an undefined value. Writing to these reg-
ister file addresses produces no effect. To determine the amount of RAM available for the
specific Z8 Encore! XP F64xx Series device, see the Part Selection Guide section on
page 2.
19
Program Memory
The eZ8 CPU supports 64 KB of program memory address space. The Z8 Encore! XP
F64xx Series contains 16 KB to 64 KB of on-chip Flash in the program memory address
space, depending upon the device. Reading from program memory addresses outside the
available Flash memory addresses returns FFh. Writing to these unimplemented program
memory addresses produces no effect. Table 5 describes the program memory maps for
the Z8 Encore! XP F64xx Series products.
20
Data Memory
The Z8 Encore! XP F64xx Series does not use the eZ8 CPUs 64 KB data memory address
space.
Information Area
Table 6 describes the Z8 Encore! XP F64xx Series Information Area. This 512-byte
Information Area is accessed by setting bit 7 of the Page Select Register to 1. When access
is enabled, the Information Area is mapped into program memory and overlays the 512
bytes at addresses FE00h to FFFFh. When the Information Area access is enabled, execu-
tion of the LDC and LDCI instructions from these program memory addresses return the
Information Area data rather than the program memory data. Reads of these addresses
through the On-Chip Debugger also returns the Information Area data. Execution of code
from these addresses continues to correctly use program memory. Access to the Informa-
tion Area is read-only.
21
Program Memory
Address (Hex) Function
FE00hFE3Fh Reserved
FE40hFE53h Part Number
20-character ASCII alphanumeric code
Left-justified and filled with zeros (ASCII Null character)
FE54hFFFFh Reserved
22
23
24
25
26
27
28
When the Z8 Encore! XP F64xx Series devices are in Stop Mode, a Stop Mode Recovery
is initiated by either of the following events:
Watchdog Timer time-out
GPIO port input pin transition on an enabled Stop Mode Recovery source
DBG pin driven Low
Reset Types
The Z8 Encore! XP F64xx Series provides two different types of reset operation (system
reset and Stop Mode Recovery). The type of Reset is a function of both the current operat-
ing mode of the Z8 Encore! XP F64xx Series devices and the source of the Reset. Table 8
lists the types of Reset and their operating characteristics.
29
System Reset
During a system reset, the Z8 Encore! XP F64xx Series devices are held in Reset for 66
cycles of the Watchdog Timer oscillator followed by 16 cycles of the system clock. At the
beginning of Reset, all GPIO pins are configured as inputs.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run. The system clock begins operat-
ing following the Watchdog Timer oscillator cycle count. The eZ8 CPU and on-chip
peripherals remain idle through the 16 cycles of the system clock.
Upon Reset, control registers within the register file that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at program memory addresses 0002h and 0003h and loads
that value into the program counter. Program execution begins at the Reset vector address.
Reset Sources
Table 9 lists the reset sources as a function of the operating mode. The text following pro-
vides more detailed information about the individual Reset sources. A Power-On Reset/
Voltage Brown-Out event always takes priority over all other possible reset sources to
ensure a full system reset occurs.
Power-On Reset
Each device in the Z8 Encore! XP F64xx Series contains an internal Power-On Reset cir-
cuit. The POR circuit monitors the supply voltage and holds the device in the Reset state
30
until the supply voltage reaches a safe operating level. After the supply voltage exceeds
the POR voltage threshold (VPOR), the POR counter is enabled and counts 66 cycles of the
Watchdog Timer oscillator. After the POR counter times out, the XTAL counter is enabled
to count a total of 16 system clock pulses. The devices are held in the Reset state until both
the POR counter and XTAL counter have timed out. After the Z8 Encore! XP F64xx
Series devices exit the Power-On Reset state, the eZ8 CPU fetches the Reset vector. Fol-
lowing Power-On Reset, the POR status bit in the Watchdog Timer Control (WDTCTL)
Register is set to 1.
Figure 8 displays Power-On Reset operation. For the POR threshold voltage (VPOR), see
the Electrical Characteristics chapter on page 200.
VCC = 3.3V
VPOR
VVBO
WDT Clock
Primary
Oscillator
Oscillator
Start-up
Internal RESET
signal
POR XTAL
Counter Delay Counter Delay
31
After the supply voltage again exceeds the Power-On Reset voltage threshold, the devices
progress through a full system reset sequence, as described in the Power-On Reset section.
Following Power-On Reset, the POR status bit in the Watchdog Timer Control
(WDTCTL) Register is set to 1. Figure 9 displays Voltage Brown-Out operation. For the
VBO and POR threshold voltages (VVBO and VPOR), see the Electrical Characteristics
chapter on page 200.
The Voltage Brown-Out circuit can be either enabled or disabled during Stop Mode. Oper-
ation during Stop Mode is set by the VBO_AO option bit. For information about configur-
ing VBO_AO, see the Option Bits chapter on page 180.
WDT Clock
Primary
Oscillator
Internal RESET
Signal
POR XTAL
Counter Delay Counter Delay
32
33
Caution: In Stop Mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the Port transition only if the signal stays on the Port pin through
the end of the Stop Mode Recovery delay. Thus, short pulses on the Port pin can initiate
Stop Mode Recovery without being written to the Port Input Data Register or without ini-
tiating an interrupt (if enabled for that pin).
34
Low-Power Modes
The Z8 Encore! XP F64xx Series products contain power-saving features. The highest
level of power reduction is provided by Stop Mode. The next level of power reduction is
provided by Halt Mode.
Stop Mode
Execution of the eZ8 CPUs stop instruction places the device into Stop Mode. In Stop
Mode, the operating characteristics are:
Primary crystal oscillator is stopped; the XIN pin is driven High and the XOUT pin is
driven Low
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
The Watchdog Timer and its internal RC oscillator continue to operate, if enabled for
operation during Stop Mode
The Voltage Brown-Out protection circuit continues to operate, if enabled for operation
in Stop Mode using the associated option bit
All other on-chip peripherals are idle
To minimize current in Stop Mode, all GPIO pins that are configured as digital inputs must
be driven to one of the supply rails (VCC or GND), the Voltage Brown-Out protection must
be disabled, and the Watchdog Timer must be disabled. The devices can be brought out of
Stop Mode using Stop Mode Recovery. For more information about Stop Mode Recovery,
see the Reset and Stop Mode Recovery chapter on page 28.
Caution: Stop Mode must not be used when driving the Z8 Encore! XP F64xx Series devices with
an external clock driver source.
35
Halt Mode
Execution of the eZ8 CPUs HALT instruction places the device into Halt Mode. In Halt
Mode, the operating characteristics are:
Primary crystal oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter stops incrementing
Watchdog Timers internal RC oscillator continues to operate
The Watchdog Timer continues to operate, if enabled
All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of Halt Mode by any of the following operations:
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
Voltage Brown-Out Reset
External RESET pin assertion
To minimize current in Halt Mode, all GPIO pins which are configured as inputs must be
driven to one of the supply rails (VCC or GND).
36
General-Purpose I/O
The Z8 Encore! XP F64xx Series products support a maximum of seven 8-bit ports (ports
AG) and one 4-bit port (Port H) for general-purpose input/output (GPIO) operations.
Each port consists of control and data registers. The GPIO control registers are used to
determine data direction, open-drain, output drive current and alternate pin functions.
Each port pin is individually programmable. All ports (except B and H) support 5 V-toler-
ant inputs.
Device Packages Port A Port B Port C Port D Port E Port F Port G Port H
Z8X1621 40-pin [7:0] [7:0] [7:0] [6:3,1:0]
44-pin [7:0] [7:0] [7:0] [6:0]
Z8X1622 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8X2421 40-pin [7:0] [7:0] [7:0] [6:3,1:0]
44-pin [7:0] [7:0] [7:0] [6:0]
Z8X2422 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8X3221 40-pin [7:0] [7:0] [7:0] [6:3,1:0]
44-pin [7:0] [7:0] [7:0] [6:0]
Z8X3222 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8X4821 40-pin [7:0] [7:0] [7:0] [6:3,1:0]
44-pin [7:0] [7:0] [7:0] [6:0]
Z8X4822 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8X4823 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0]
Z8X6421 40-pin [7:0] [7:0] [7:0] [6:3,1:0]
44-pin [7:0] [7:0] [7:0] [6:0]
Z8X6422 64- and 68-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7] [3] [3:0]
Z8X6423 80-pin [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [3:0]
37
Architecture
Figure 10 displays a simplified block diagram of a GPIO port pin. In this figure, the ability
to accommodate alternate functions and variable port current drive strength are not illus-
trated.
Q D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus D Q Port
Pin
System
Clock
38
39
GPIO Interrupts
Many of the GPIO port pins can be used as interrupt sources. Some port pins may be con-
figured to generate an interrupt request on either the rising edge or falling edge of the pin
input signal. Other port pin interrupts generate an interrupt when any edge occurs (both
rising and falling). For more information about interrupts using the GPIO pins, see the
Interrupt Controller chapter on page 47.
Port Register
Mnemonic Port Register Name
PxADDR Port AH Address Register (selects subregisters)
PxCTL Port AH Control Register (provides access to subregisters)
PxIN Port AH Input Data Register
PxOUT Port AH Output Data Register
Port Subregister
Mnemonic Port Register Name
PxDD Data Direction
PxAF Alternate Function
PxOC Output Control (Open-Drain)
PxDD High Drive Enable
PxSMRE Stop Mode Recovery Source Enable
40
Bit 7 6 5 4 3 2 1 0
Field PADDR[7:0]
RESET 00h
R/W R/W
Address FD0h, FD4h, FD8h, FDCh, FE0h, FE4h, FE8h, FECh
Bit Description
[7:0] Port Address
PADDR This port address selects one of the subregisters accessible through the Port AH Control
Registers.
00h = No function. Provides some protection against accidental port reconfiguration.
01h = Data Direction.
02h = Alternate Function.
03h = Output Control (Open-Drain).
04h = High Drive Enable.
05h = Stop Mode Recovery Source Enable.
06hFFh = No function.
41
Bit 7 6 5 4 3 2 1 0
Field PCTL
RESET 00h
R/W R/W
Address FD1h, FD5h, FD9h, FDDh, FE1h, FE5h, FE9h, FEDh
Bit Description
[7:0] Port Control
PCTL The Port Control Register provides access to all subregisters that configure the GPIO Port
operation.
Bit 7 6 5 4 3 2 1 0
Field DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
RESET 1
R/W R/W
Address See note.
Note: If a 01h exists in the Port AH Address Register, it is accessible through the Port AH Control Register.
Bit Description
[7:0] Data Direction
DDx These bits control the direction of the associated port pin. Port Alternate Function operation
overrides the Data Direction Register setting.
0 = Output. Data in the Port AH Output Data Register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port AH Input Data Register.
The output driver is tri-stated.
Note: x indicates register bits in the range [7:0].
42
Caution: Do not enable alternate function for GPIO port pins which do not have an associated al-
ternate function. Failure to follow this guideline may result in unpredictable operation.
Bit 7 6 5 4 3 2 1 0
Field AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0
RESET 0
R/W R/W
Address See note.
Note: If a 02h exists in the Port AH Address Register, it is accessible through the Port AH Control Register.
Bit Description
[7:0] Port Alternate Function Enabled
AFx 0 = The port pin is in Normal Mode and the DDx bit in the Port AH Data Direction Subregister
determines the direction of the pin.
1 = The alternate function is selected. Port pin operation is controlled by the alternate function.
Note: x indicates register bits in the range [7:0].
43
Bit 7 6 5 4 3 2 1 0
Field POC7 POC6 POC5 POC4 POC3 POC2 POC1 POC0
RESET 0
R/W R/W
Address See note.
Note: If a 03h exists in the Port AH Address Register, it is accessible through the Port AH Control Register.
Bit Description
[7:0] Port Output Control
POCx These bits function independently of the alternate function bit and disables the drains if set to 1.
0 = The drains are enabled for any output mode.
1 = The drain of the associated pin is disabled (open-drain mode).
Note: x indicates register bits in the range [7:0].
44
Bit 7 6 5 4 3 2 1 0
Field PHDE7 PHDE6 PHDE5 PHDE4 PHDE3 PHDE2 PHDE1 PHDE0
RESET 0
R/W R/W
Address See note.
Note: If a 04h exists in the Port AH Address Register, it is accessible through the Port AH Control Register.
Bit Description
[7:0] Port High Drive Enabled
PHDEx 0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Note: x indicates register bits in the range [7:0].
45
Bit 7 6 5 4 3 2 1 0
Field PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
RESET 0
R/W R/W
Address See note.
Note: If a 05h exists in the Port AH Address Register, it is accessible through the Port AH Control Register.
Bit Description
[7:0] Port Stop Mode Recovery Source Enabled
PSMRE 0 = The port pin is not configured as a Stop Mode Recovery source. Transitions on this pin dur-
ing Stop Mode do not initiate Stop Mode Recovery.
1 = The port pin is configured as a Stop Mode Recovery source. Any logic transition on this pin
during Stop Mode initiates Stop Mode Recovery.
Note: x indicates register bits in the range [7:0].
46
Bit 7 6 5 4 3 2 1 0
Field PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET X
R/W R
Address FD2h, FD6h, FDAh, FDEh, FE2h, FE6h, FEAh, FEEh
Bit Description
[7:0] Port Input Data
PxIN Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Note: x indicates register bits in the range [7:0].
Bit 7 6 5 4 3 2 1 0
Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0
R/W R/W
Address FD3h, FD7h, FDBh, FDFh, FE3h, FE7h, FEBh, FEFh
Bit Description
[7:0] Port Output Data
PxOUT These bits contain the data to be driven out from the port pins. The values are only driven if the
corresponding pin is configured as an output and the pin is not configured for alternate function
operation.
0 = Drive a logical 0 (Low).
1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting
the corresponding Port Output Control Register bit to 1.
Note: x indicates register bits in the range [7:0].
47
Interrupt Controller
The interrupt controller on the Z8 Encore! XP F64xx Series products prioritizes the inter-
rupt requests from the on-chip peripherals and the GPIO port pins. The features of the
interrupt controller include:
24 unique interrupt vectors:
12 GPIO port pin interrupt sources
12 on-chip peripheral interrupt sources
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt control has no effect on operation. For more information about interrupt ser-
vicing by the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128), which is
available for download on www.zilog.com.
48
Program Memory
Priority Vector Address Interrupt Source
Highest 0002h Reset (not an interrupt)
0004h Watchdog Timer (see the Watchdog Timer chapter on page 80)
0006h Illegal Instruction Trap (not an interrupt)
0008h Timer 2
000Ah Timer 1
000Ch Timer 0
000Eh UART 0 receiver
0010h UART 0 transmitter
0012h I 2C
0014h SPI
0016h ADC
0018h Port A7 or Port D7, rising or falling input edge
001Ah Port A6 or Port D6, rising or falling input edge
001Ch Port A5 or Port D5, rising or falling input edge
001Eh Port A4 or Port D4, rising or falling input edge
0020h Port A3 or Port D3, rising or falling input edge
0022h Port A2 or Port D2, rising or falling input edge
0024h Port A1 or Port D1, rising or falling input edge
0026h Port A0 or Port D0, rising or falling input edge
0028h Timer 3 (not available in the 44-pin package)
002Ah UART 1 receiver
002Ch UART 1 transmitter
002Eh DMA
0030h Port C3, both input edges
0032h Port C2, both input edges
0034h Port C1, both input edges
Lowest 0036h Port C0, both input edges
49
Architecture
Figure 11 displays a block diagram of the interrupt controller.
High
Port Interrupts Interrupt Request Latches and Control Priority
Vector
Priority
Mux IRQ Request
Medium
Priority
Internal Interrupts
Low
Priority
Operation
This section describes the operational aspects of the following functions.
Master Interrupt Enable: see page 49
Interrupt Vectors and Priority: see page 50
Interrupt Assertion: see page 50
Software Interrupt Assertion: see page 51
50
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the Interrupt Request Register is cleared until the next interrupt occurs. Writing a
0 to the corresponding bit in the Interrupt Request Register likewise clears the interrupt
request.
Caution: Zilog recommends not using a coding style that clears bits in the Interrupt Request reg-
isters. All incoming interrupts received between execution of the first LDX command
and the final LDX command are lost. See Example 1, which follows.
Example 1. A poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
51
To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt
Request 0 Register:
Example 2. A good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Caution: Zilog recommends not using a coding style to generate software interrupts by setting bits
in the Interrupt Request registers. All incoming interrupts received between execution of
the first LDX command and the final LDX command are lost. See Example 3, which fol-
lows.
Example 3. A poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt
Request registers:
Example 4. A good coding style that avoids lost interrupt requests:
ORX IRQ0, MASK
52
Bit 7 6 5 4 3 2 1 0
Field T2I T1I T0I U0RXI U0TXI I2CI SPII ADCI
RESET 0
R/W R/W
Address FC0h
Bit Description
[7] Timer 2 Interrupt Request
T2I 0 = No interrupt request is pending for Timer 2.
1 = An interrupt request from Timer 2 is awaiting service.
[6] Timer 1 Interrupt Request
T1I 0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
[5] Timer 0 Interrupt Request
T0I 0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
[4] UART 0 Receiver Interrupt Request
U0RXI 0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
[3] UART 0 Transmitter Interrupt Request
U0TXI 0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
[2] I2C Interrupt Request
I2CI 0 = No interrupt request is pending for the I2C.
1 = An interrupt request from the I2C is awaiting service.
[1] SPI Interrupt Request
SPII 0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service.
[0] ADC Interrupt Request
ADCI 0 = No interrupt request is pending for the Analog-to-Digital Converter.
1 = An interrupt request from the Analog-to-Digital Converter is awaiting service.
53
Bit 7 6 5 4 3 2 1 0
Field PAD7I PAD6I PAD5I PAD4I PAD3I PAD2I PAD1I PAD0I
RESET 0
R/W R/W
Address FC3h
Bit Description
[7:0] Port A or Port D Pin x Interrupt Request
PADxI 0 = No interrupt request is pending for GPIO Port A or Port D pin x.
1 = An interrupt request from GPIO Port A or Port D pin x is awaiting service.
Note: x indicates the specific GPIO Port A or D pin in the range [7:0].
54
Bit 7 6 5 4 3 2 1 0
Field T3I U1RXI U1TXI DMAI PC3I PC2I PC1I PC0I
RESET 0
R/W R/W
Address FC6h
Bit Description
[7] Timer 3 Interrupt Request
T3I 0 = No interrupt request is pending for Timer 3.
1 = An interrupt request from Timer 3 is awaiting service.
[6] UART 1 Receive Interrupt Request
U1RXI 0 = No interrupt request is pending for the UART1 receiver.
1 = An interrupt request from UART1 receiver is awaiting service.
[5] UART 1 Transmit Interrupt Request
U1TXI 0 = No interrupt request is pending for the UART 1 transmitter.
1 = An interrupt request from the UART 1 transmitter is awaiting service.
[4] DMA Interrupt Request
DMAI 0 = No interrupt request is pending for the DMA.
1 = An interrupt request from the DMA is awaiting service.
[3:0] Port C Pin x Interrupt Request
PCxI 0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
Note: x indicates the specific GPIO Port C pin in the range [3:0].
55
Bit 7 6 5 4 3 2 1 0
Field T2ENH T1ENH T0ENH U0RENH U0TENH I2CENH SPIENH ADCENH
RESET 0
R/W R/W
Address FC1h
Bit Description
[7] Timer 2 Interrupt Request Enable High Bit
T2ENH
[6] Timer 1 Interrupt Request Enable High Bit
T1ENH
[5] Timer 0 Interrupt Request Enable High Bit
T0ENH
[4] UART 0 Receive Interrupt Request Enable High Bit
U0RENH
[3] UART 0 Transmit Interrupt Request Enable High Bit
U0TENH
[2] I2C Interrupt Request Enable High Bit
I2CENH
[1] SPI Interrupt Request Enable High Bit
SPIENH
[0] ADC Interrupt Request Enable High Bit
ADCENH
56
Bit 7 6 5 4 3 2 1 0
Field T2ENL T1ENL T0ENL U0RENL U0TENL I2CENL SPIENL ADCENL
RESET 0
R/W R/W
Address FC2h
Bit Description
[7] Timer 2 Interrupt Request Enable Low Bit
T2ENL
[6] Timer 1 Interrupt Request Enable Low Bit
T1ENL
[5] Timer 0 Interrupt Request Enable Low Bit
T0ENL
[4] UART 0 Receive Interrupt Request Enable Low Bit
U0RENL
[3] UART 0 Transmit Interrupt Request Enable Low Bit
U0TENL
[2] I2C Interrupt Request Enable Low Bit
I2CENL
[1] SPI Interrupt Request Enable Low Bit
SPIENL
[0] ADC Interrupt Request Enable Low Bit
ADCENL
57
Bit 7 6 5 4 3 2 1 0
Field PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
RESET 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address FC4h
Bit Description
[7:0] Port A or Port D Bit[x] Interrupt Request Enable High Bit
PADxENH To select either Port A or Port D as the interrupt source, see the Interrupt Port Select Regis-
ter on page 60.
Note: x indicates register bits in the range [7:0].
Bit 7 6 5 4 3 2 1 0
Field PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
RESET 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address FC5h
Bit Description
[7:0] Port A or Port D Bit[x] Interrupt Request Enable Low Bit
PADxENL To select either Port A or Port D as the interrupt source, see the Interrupt Port Select Regis-
ter on page 60.
Note: x indicates register bits in the range [7:0].
58
Bit 7 6 5 4 3 2 1 0
Field T3ENH U1RENH U1TENH DMAENH C3ENH C2ENH C1ENH C0ENH
RESET 0
R/W R/W
Address FC7h
Bit Description
[7] Timer 3 Interrupt Request Enable High Bit
T3ENH
[6] UART 1 Receive Interrupt Request Enable High Bit
U1RENH
[5] UART 1 Transmit Interrupt Request Enable High Bit
U1TENH
[4] DMA Interrupt Request Enable High Bit
DMAENH
[3] Port C3 Interrupt Request Enable High Bit
C3ENH
[2] Port C2 Interrupt Request Enable High Bit
C2ENH
[1] Port C1 Interrupt Request Enable High Bit
C1ENH
[0] Port C0 Interrupt Request Enable High Bit
C0ENH
59
Bit 7 6 5 4 3 2 1 0
Field T3ENL U1RENL U1TENL DMAENL C3ENL C2ENL C1ENL C0ENL
RESET 0
R/W R/W
Address FC8h
Bit Description
[7] Timer 3 Interrupt Request Enable Low Bit
T3ENL
[6] UART 1 Receive Interrupt Request Enable Low Bit
U1RENL
[5] UART 1 Transmit Interrupt Request Enable Low Bit
U1TENL
[4] DMA Interrupt Request Enable Low Bit
DMAENL
[3] Port C3 Interrupt Request Enable Low Bit
C3ENL
[2] Port C2 Interrupt Request Enable Low Bit
C2ENL
[1] Port C1 Interrupt Request Enable Low Bit
C1ENL
[0] Port C0 Interrupt Request Enable Low Bit
C0ENL
60
Bit 7 6 5 4 3 2 1 0
Field IES7 IES6 IES5 IES4 IES3 IES2 IES1 IES0
RESET 0
R/W R/W
Address FCDh
Bit Description
[7:0] Interrupt Edge Select x
IESx The minimum pulse width should be greater than 1 system clock to guarantee capture of the
edge triggered interrupt. Shorter pulses may be captured but not guaranteed.
0 = An interrupt request is generated on the falling edge of the PAx/PDx input.
1 = An interrupt request is generated on the rising edge of the PAx/PDx input.
Note: x indicates specific GPIO port pins in the range [7:0].
Bit 7 6 5 4 3 2 1 0
Field PAD7S PAD6S PAD5S PAD4S PAD3S PAD2S PAD1S PAD0S
RESET 0
R/W R/W
Address FCEh
Bit Description
[7:0] PAx/PDx Selection
PADxS 0 = PAx is used for the interrupt for PAx/PDx interrupt request.
1 = PDx is used for the interrupt for PAx/PDx interrupt request.
Note: x indicates specific GPIO port pins in the range [7:0].
61
Bit 7 6 5 4 3 2 1 0
Field IRQE Reserved
RESET 0
R/W R/W R
Address FCFh
Bit Description
[7] Interrupt Request Enable
IRQE This bit is set to 1 by execution of an EI or IRET instruction, or by a direct register write of a 1
to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of an inter-
rupt request, or a Reset.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
[6:0] Reserved
These pins are reserved and must be programmed to 000000.
62
Timers
The Z8 Encore! XP F64xx Series products contain up to four 16-bit reloadable timers that
can be used for timing, event counting or generation of pulse-width modulated signals.
The timers features include:
16-bit reload counter
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating, or capture signal. External input pin
signal frequency is limited to a maximum of one-fourth the system clock frequency.
Timer output pin
Timer interrupt
In addition to the timers described in this chapter, the baud rate generators for any unused
UART, SPI or I2C peripherals can also be used to provide basic timing functionality. For
information about using the baud rate generators as timers, see the respective serial com-
munication peripheral. Timer 3 is unavailable in the 44-pin package devices.
Architecture
Figure 12 displays the architecture of the timers.
63
Timer Block
Data Timer
Bus Control
Block
Control
16-Bit Interrupt, Timer
Compare
Reload Register PWM, Interrupt
and
Timer Output Timer
System Control
Clock 16-Bit Counter Output
Gate
16-Bit Compare
Input
PWM/Compare
Capture
Input
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001h into the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000h into the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFh, the timer rolls over to 0000h and continues counting.
One-Shot Mode
In One-Shot Mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001h. Then, the timer is automatically disabled and
stops counting.
Also, if the timer output alternate function is enabled, the timer output pin changes state
for one system clock cycle (from Low to High or from High to Low) upon timer reload. If
64
it is appropriate to have the timer output make a permanent state change upon a One-Shot
time-out, first set the TPOL bit in the Timer Control 1 Register to the start value before
beginning One-Shot Mode. Then, after starting the timer, set TPOL to the opposite bit
value.
Observe the following procedure for configuring a timer for One-Shot Mode and initiating
the count:
1. Write to the Timer Control 1 Register to:
Disable the timer
Configure the timer for One-Shot Mode
Set the prescale value
If using the timer output alternate function, set the initial output level (High or
Low)
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
In One-Shot Mode, the system clock always provides the timer input. The timer period is
calculated using the following equation:
Continuous Mode
In Continuous Mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the reload value, the timer generates an interrupt, the count value in the Timer High and
Low Byte registers is reset to 0001h and counting resumes. Also, if the timer output alter-
nate function is enabled, the timer output pin changes state (from Low to High or from
High to Low) upon timer reload.
Observe the following procedure for configuring a timer for Continuous Mode and initiat-
ing the count:
1. Write to the Timer Control 1 Register to:
65
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001h), affecting only the first pass in Continuous Mode. After the first timer reload
in Continuous Mode, counting always begins at the reset value of 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
In Continuous Mode, the system clock always provides the timer input. The timer period
is calculated using the following equation:
If an initial starting value other than 0001h is loaded into the Timer High and Low Byte
registers, the One-Shot Mode equation must be used to determine the first time-out period.
Counter Mode
In Counter Mode, the timer counts input transitions from a GPIO port pin. The timer input
is taken from the GPIO port pin timer input alternate function. The TPOL bit in the Timer
Control 1 Register selects whether the count occurs on the rising edge or the falling edge
of the timer input signal. In Counter Mode, the prescaler is disabled.
Caution: The input frequency of the timer input signal must not exceed one-fourth the system
clock frequency.
Upon reaching the reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001h and counting resumes. Also, if the timer output alternate function is
enabled, the timer output pin changes state (from Low to High or from High to Low) at
timer reload.
66
Observe the following procedure for configuring a timer for Counter Mode and initiating
the count:
1. Write to the Timer Control 1 Register to:
Disable the timer.
Configure the timer for Counter Mode.
Select either the rising edge or falling edge of the timer input signal for the count.
This also sets the initial logic level (High or Low) for the timer output alternate
function. However, the timer output function does not have to be enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Counter Mode. After the first timer reload in Counter
Mode, counting always begins at the reset value of 0001h. Generally, in Counter
Mode the Timer High and Low Byte registers must be written with the value 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
7. Write to the Timer Control 1 Register to enable the timer.
In Counter Mode, the number of timer input transitions since the timer start is calculated
using the following equation:
COUNTER Mode Timer Input Transitions = Current Count Value Start Value
PWM Mode
In PWM Mode, the timer outputs a Pulse-Width Modulator (PWM) output signal through
a GPIO port pin. The timer input is the system clock. The timer first counts up to the 16-
bit PWM match value stored in the Timer PWM High and Low Byte registers. When the
timer count value matches the PWM value, the timer output toggles. The timer continues
counting until it reaches the reload value stored in the Timer Reload High and Low Byte
registers. Upon reaching the reload value, the timer generates an interrupt, the count value
in the Timer High and Low Byte registers is reset to 0001h and counting resumes.
If the TPOL bit in the Timer Control 1 Register is set to 1, the timer output signal begins
as a High (1) and then transitions to a Low (0) when the timer value matches the PWM
value. The timer output signal returns to a High (1) after the timer reaches the reload value
and is reset to 0001h.
67
If the TPOL bit in the Timer Control 1 Register is set to 0, the timer output signal begins
as a Low (0) and then transitions to a High (1) when the timer value matches the PWM
value. The timer output signal returns to a Low (0) after the timer reaches the reload value
and is reset to 0001h.
Observe the following procedure for configuring a timer for PWM Mode and initiating the
PWM operation:
1. Write to the Timer Control 1 Register to:
Disable the timer
Configure the timer for PWM Mode
Set the prescale value
Set the initial logic level (High or Low) and PWM High/Low transition for the
timer output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001h). This only affects the first pass in PWM Mode. After the first timer reset
in PWM Mode, counting always begins at the reset value of 0001h.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM
period). The reload value must be greater than the PWM value.
5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
6. Configure the associated GPIO port pin for the timer output alternate function.
7. Write to the Timer Control 1 Register to enable the timer and initiate counting.
If an initial starting value other than 0001h is loaded into the Timer High and Low Byte
registers, the One-Shot Mode equation must be used to determine the first PWM time-out
period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is calculated
using the following equation:
68
If TPOL is set to 1, the ratio of the PWM output High time to the total period is calculated
using the following equation:
PWM Value
PWM Output High Time Ratio (%) = -------------------------------- 100
Reload Value
Capture Mode
In Capture Mode, the current timer count value is recorded when the appropriate external
timer input transition occurs. The capture count value is written to the Timer PWM High
and Low Byte Registers. The timer input is the system clock. The TPOL bit in the Timer
Control 1 Register determines if the capture occurs on a rising edge or a falling edge of the
timer input signal. When the capture event occurs, an interrupt is generated and the timer
continues counting.
The timer continues counting up to the 16-bit reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the reload value, the timer generates an inter-
rupt and continues counting.
Observe the following procedure for configuring a timer for Capture Mode and initiating
the count:
1. Write to the Timer Control 1 Register to:
Disable the timer
Configure the timer for Capture Mode
Set the prescale value
Set the capture edge (rising or falling) for the timer input
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001h).
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000h. This allows the soft-
ware to determine if interrupts were generated by either a capture event or a reload. If
the PWM High and Low Byte registers still contain 0000h after the interrupt, then the
interrupt was generated by a reload.
5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
6. Configure the associated GPIO port pin for the timer input alternate function.
7. Write to the Timer Control 1 Register to enable the timer and initiate counting.
In Capture Mode, the elapsed time from timer start to capture event can be calculated
using the following equation:
69
Compare Mode
In Compare Mode, the timer counts up to the 16-bit maximum compare value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the compare value, the timer generates an interrupt and counting continues (the
timer value is not reset to 0001h). Also, if the timer output alternate function is enabled,
the timer output pin changes state (from Low to High or from High to Low) upon com-
pare.
If the Timer reaches FFFFh, the timer rolls over to 0000h and continue counting.
Observe the following procedure for configuring a timer for Compare Mode and initiating
the count:
1. Write to the Timer Control 1 Register to:
Disable the timer
Configure the timer for Compare Mode
Set the prescale value
Set the initial logic level (High or Low) for the timer output alternate function, if
appropriate
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the compare value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the timer output function, configure the associated GPIO port pin for the timer
output alternate function.
6. Write to the Timer Control 1 Register to enable the timer and initiate counting.
In Compare Mode, the system clock always provides the timer input. The compare time is
calculated using the following equation:
70
Gated Mode
In Gated Mode, the timer counts only when the timer input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control 1 Register. When the timer
input signal is asserted, counting begins. A timer interrupt is generated when the timer
input signal is deasserted or a timer reload occurs. To determine if a timer input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001h and counting resumes (assuming the timer input signal is still asserted).
Also, if the timer output alternate function is enabled, the timer output pin changes state
(from Low to High or from High to Low) at timer reset.
Observe the following procedure for configuring a timer for Gated Mode and initiating the
count:
1. Write to the Timer Control 1 Register to:
Disable the timer
Configure the timer for Gated Mode
Set the prescale value
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Gated Mode. After the first timer reset in Gated Mode,
counting always begins at the reset value of 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the Timer Control 1 Register to enable the timer.
7. Assert the timer input signal to initiate the counting.
Capture/Compare Mode
In Capture/Compare Mode, the timer begins counting on the first external timer input tran-
sition. The appropriate transition (rising edge or falling edge) is set by the TPOL bit in the
Timer Control 1 Register. The timer input is the system clock.
Every subsequent appropriate transition (after the first) of the timer input signal captures
the current count value. The capture value is written to the Timer PWM High and Low
Byte Registers. When the capture event occurs, an interrupt is generated, the count value
in the Timer High and Low Byte registers is reset to 0001h, and counting resumes.
71
If no capture event occurs, the timer counts up to the 16-bit compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001h and counting resumes.
Observe the following procedure for configuring a timer for Capture/Compare Mode and
initiating the count:
1. Write to the Timer Control 1 Register to:
Disable the timer
Configure the timer for Capture/Compare Mode
Set the prescale value
Set the capture edge (rising or falling) for the timer input
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001h).
3. Write to the Timer Reload High and Low Byte registers to set the compare value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the timer input alternate function.
6. Write to the Timer Control 1 Register to enable the timer.
7. Counting begins on the first appropriate transition of the timer input signal. No inter-
rupt is generated by this first edge.
In Compare Mode, the elapsed time from timer start to capture event can be calculated
using the following equation:
72
Timers 02 are available in all packages. Timer 3 is only available in 64-, 68- and 80-pin
packages.
Bit 7 6 5 4 3 2 1 0
Field TH
RESET 0
R/W R/W
Address F00h, F08h, F10h, F18h
73
Bit 7 6 5 4 3 2 1 0
Field TL
RESET 0 1
R/W R/W
Address F01h, F09h, F11h, F19h
Bit Description
[7:0] Timer High and Low Bytes
TH, TL These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value.
74
Bit 7 6 5 4 3 2 1 0
Field TRH
RESET 1
R/W R/W
Address F02h, F0Ah, F12h, F1Ah
Bit 7 6 5 4 3 2 1 0
Field TRL
RESET 1
R/W R/W
Address F03h, F0Bh, F13h, F1Bh
Bit Description
[7:0] Timer Reload Register High and Low
TRH, These two bytes form the 16-bit reload value, {TRH[7:0], TRL[7:0]}. This value sets the maxi-
TRL mum count value which initiates a timer reload to 0001h. In Compare Mode, these two bytes
form the 16-bit compare value.
75
Bit 7 6 5 4 3 2 1 0
Field PWMH
RESET 0
R/W R/W
Address F04h, F0Ch, F14h, F1Ch
Bit 7 6 5 4 3 2 1 0
Field PWML
RESET 0
R/W R/W
Address F05h, F0Dh, F15h, F1Dh
Bit Description
[7:0] Pulse-Width Modulator High and Low Bytes
PWMH, These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current
PWML 16-bit timer count. When a match occurs, the PWM output changes state. The PWM output
value is set by the TPOL bit in the Timer Control 1 Register (TxCTL1) Register. The TxPWMH
and TxPWML registers also store the 16-bit captured timer value when operating in Capture or
Capture/Compare modes.
76
Bit 7 6 5 4 3 2 1 0
Field Reserved CSC Reserved
RESET 0
R/W R/W
Address F06h, F0Eh, F16h, F1Eh
Bit Description
[7:5] Reserved
These bits are reserved and must be programmed to 000.
[4] Cascade Timers
CSC 0 = Timer input signal comes from the pin.
1 = For Timer 0, the input signal is connected to Timer 3 output.
For Timer 1, the input signal is connected to the Timer 0 output.
For Timer 2, the input signal is connected to the Timer 1 output.
For Timer 3, the input signal is connected to the Timer 2 output.
[3:0] Reserved
These bits are reserved and must be programmed to 0000.
77
Bit 7 6 5 4 3 2 1 0
Field TEN TPOL PRES TMODE
RESET 0
R/W R/W
Address F07h, F0Fh, F17h, F1Fh
78
Bit Description
[7] Timer Enable
TEN 0 = Timer is disabled.
1 = Timer enabled to count.
[6] Timer Input/Output Polarity
TPOL Operation of this bit is a function of the current operating mode of the timer.
One-Shot Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
Continuous Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
Counter Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
0 = Count occurs on the rising edge of the timer input signal.
1 = Count occurs on the falling edge of the timer input signal.
PWM Mode
0 = timer output is forced Low (0) when the timer is disabled. When enabled, the timer output is
forced High (1) upon PWM count match and forced Low (0) upon reload.
1 = timer output is forced High (1) when the timer is disabled. When enabled, the timer output
is forced Low (0) upon PWM count match and forced High (1) upon reload.
Capture Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
Compare Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When the timer
is enabled, the timer output signal is complemented upon timer reload.
Gated Mode
0 = Timer counts when the timer input signal is High (1) and interrupts are generated on the
falling edge of the timer input.
1 = Timer counts when the timer input signal is Low (0) and interrupts are generated on the ris-
ing edge of the timer input.
Capture/Compare Mode
0 = Counting is started on the first rising edge of the timer input signal. The current count is
captured on subsequent rising edges of the timer input signal.
1 = Counting is started on the first falling edge of the timer input signal. The current count is
captured on subsequent falling edges of the timer input signal.
Caution: When the timer output alternate function TxOUT on a GPIO port pin is enabled,
TxOUT will change to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Also, the Port Data Direction Subregister is not needed to be set to output
on TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately
change the TxOUT.
79
80
Watchdog Timer
The Watchdog Timer (WDT) helps protect against corrupt or unreliable software, power
faults and other system-level problems which can place the Z8 Encore! XP F64xx Series
MCU into unsuitable operating states. The features of the Watchdog Timer include:
On-chip RC oscillator
A selectable time-out response
WDT time-out response: Reset or interrupt
24-bit programmable time-out value
Operation
The Watchdog Timer is a retriggerable one-shot timer that resets or interrupts the Z8
Encore! XP F64xx Series devices when the WDT reaches its terminal count. The Watch-
dog Timer uses its own dedicated on-chip RC oscillator as its clock source. The Watchdog
Timer has only two modes of operation: ON and OFF. After it is enabled, it always counts
and must be refreshed to prevent a time-out. An enable can be performed by executing the
WDT instruction or by setting the WDT_AO option bit. This WDT_AO bit enables the
Watchdog Timer to operate continuously, even if a WDT instruction has not been exe-
cuted.
The Watchdog Timer is a 24-bit reloadable downcounter that uses three 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
calculated using the following equation:
In the above equation, the WDT reload value is the decimal value of the 24-bit value pro-
vided by {WDTU[7:0], WDTH[7:0], WDTL[7:0]}; the typical Watchdog Timer RC oscil-
lator frequency is 10 kHz. The Watchdog Timer cannot be refreshed after it reaches
000002h. The WDT reload value must not be set to values below 000004h.
Table 47 lists approximate time-out delays for the minimum and maximum WDT reload
values.
81
82
Mode. For more information about Stop Mode Recovery, see the Reset and Stop Mode
Recovery chapter on page 28.
If interrupts are enabled, following completion of the Stop Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe-
cuting code from the vector address.
83
unlock the Watchdog Timer Reload Byte registers (WDTU, WDTH, and WDTL) for write
access.
1. Write 55h to the Watchdog Timer Control Register (WDTCTL).
2. Write AAh to the Watchdog Timer Control Register (WDTCTL).
3. Write the Watchdog Timer Reload Upper Byte Register (WDTU).
4. Write the Watchdog Timer Reload High Byte Register (WDTH).
5. Write the Watchdog Timer Reload Low Byte Register (WDTL).
All steps of the Watchdog Timer reload unlock sequence must be written in the sequence
described above; there must be no other register writes between each of these operations.
If a register write occurs, the lock state machine resets and no further writes can occur,
unless the sequence is restarted. The value in the Watchdog Timer Reload registers is
loaded into the counter when the Watchdog Timer is first enabled and every time a WDT
instruction is executed.
84
Bit 7 6 5 4 3 2 1 0
Field POR STOP WDT EXT Reserved SM
RESET See Table 49. 0
R/W R
Address FF0h
Bit Description
[7] Power-On Reset Indicator
POR If this bit is set to 1, a Power-On Reset event occurred. This bit is reset to 0 if a WDT time-out
or Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read.
[6] Stop Mode Recovery Indicator
STOP If this bit is set to 1, a Stop Mode Recovery occurred. If the stop and WDT bits are both set to
1, the Stop Mode Recovery occurred due to a WDT time-out. If the stop bit is 1 and the WDT
bit is 0, the Stop Mode Recovery was not caused by a WDT time-out. This bit is reset by a
Power-On Reset or a WDT time-out that occurred while not in Stop Mode. Reading this register
also resets this bit.
[5] Watchdog Timer Time-Out Indicator
WDT If this bit is set to 1, a WDT time-out occurred. A Power-On Reset resets this pin. A Stop Mode
Recovery from a change in an input pin also resets this bit. Reading this register resets this bit.
[4] External Reset Indicator
EXT If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On Reset
or a Stop Mode Recovery from a change in an input pin resets this bit. Reading this register
resets this bit.
[3:1] Reserved
These bits are reserved and must be programmed to 000.
[0] Stop Mode Configuration Indicator
SM 0 = Watchdog Timer and its internal RC oscillator will continue to operate in Stop Mode.
1 = Watchdog Timer and its internal RC oscillator will be disabled in Stop Mode.
85
Caution: The 24-bit WDT reload value must not be set to a value less than 000004h.
Bit 7 6 5 4 3 2 1 0
Field WDTU
RESET 1
R/W R/W*
Address FF1h
Note: *R/W = Read returns the current WDT count value; write sets the appropriate reload value.
Bit Description
[7:0] WDT Reload Upper Byte
WDTU Most significant byte, bits[23:16] of the 24-bit WDT reload value.
86
Bit 7 6 5 4 3 2 1 0
Field WDTH
RESET 1
R/W R/W*
Address FF2h
Note: *R/W = Read returns the current WDT count value; write sets the appropriate reload value.
Bit Description
[7:0] WDT Reload High Byte
WDTH Middle byte, bits[15:8] of the 24-bit WDT reload value.
Bit 7 6 5 4 3 2 1 0
Field WDTL
RESET 1
R/W R/W*
Address FF3h
Note: *R/W = Read returns the current WDT count value; write sets the appropriate reload value.
Bit Description
[7:0] WDT Reload Low
WDTL Least significant byte, bits[7:0] of the 24-bit WDT reload value.
87
Architecture
The UART consists of three primary functional blocks: Transmitter, Receiver and Baud
Rate Generator. The UARTs transmitter and receiver function independently, but employ
the same baud rate and data format. Figure 13 displays the UART architecture.
88
Parity Checker
Receiver Control
with address compare
RxD
Receive Shifter
Receive Data
Register Control Registers
System Bus
Transmit Data
Register Status Register Baud Rate
Generator
Transmit Shift
TxD Register
Transmitter Control
Parity Generator
CTS
DE
Operation
The UART always transmits and receives data in an 8-bit data format, least significant bit
first. An even or odd parity bit can be optionally added to the data stream. Each character
begins with an active Low start bit and ends with either 1 or 2 active High stop bits.
Figures 14 and 15 display the asynchronous data format employed by the UART without
parity and with parity, respectively.
89
90
Set or clear the CTSE bit to enable or disable control from the remote receiver
using the CTS pin
5. Check the TDRE bit in the UART Status 0 Register to determine if the Transmit Data
Register is empty (indicated by a 1). If empty, continue to Step 6. If the Transmit Data
Register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit
Data Register becomes available to receive new data.
6. Write the UART Control 1 Register to select the outgoing address bit.
7. Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte; clear it if
sending a data byte.
8. Write the data byte to the UART Transmit Data Register. The transmitter automati-
cally transfers the data to the Transmit Shift Register and transmits the data.
9. If appropriate and Multiprocessor Mode is enabled, make any changes to the Multi-
processor Bit Transmitter (MPBT) value.
10. To transmit additional bytes, return to Step 5.
91
Set or clear the CTSE bit to enable or disable control from the remote receiver via
the CTS pin
The UART is now configured for interrupt-driven data transmission. Because the UART
Transmit Data Register is empty, an interrupt is generated immediately. When the UART
transmit interrupt is detected, the associated interrupt service routine performs the follow-
ing functions:
1. Write the UART Control 1 Register to select the outgoing address bit:
Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte; clear it
if sending a data byte.
2. Write the data byte to the UART Transmit Data Register. The transmitter automati-
cally transfers the data to the Transmit Shift Register and transmits the data.
3. Clear the UART transmit interrupt bit in the applicable Interrupt Request Register.
4. Execute the IRET instruction to return from the interrupt service routine and wait for
the Transmit Data Register to again become empty.
5. Check the RDA bit in the UART Status 0 Register to determine if the Receive Data
Register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate
available data, continue to Step 6. If the Receive Data Register is empty (indicated by
a 0), continue to monitor the RDA bit awaiting reception of the valid data.
92
6. Read data from the UART Receive Data Register. If operating in Multiprocessor (9-
Bit) Mode, further actions may be required depending on the Multiprocessor Mode
bits MPMD[1:0].
7. Return to Step 5 to receive additional data.
93
1. Check the UART Status 0 Register to determine the source of the interrupt: error,
break, or received data.
2. If the interrupt was caused by data available, read the data from the UART Receive
Data Register. If operating in Multiprocessor (9-Bit) Mode, further actions may be
required depending on the Multiprocessor Mode bits MPMD[1:0].
3. Clear the UART Receiver interrupt in the applicable Interrupt Request Register.
4. Execute the IRET instruction to return from the interrupt service routine and await
more data.
In Multiprocessor (9-Bit) Mode, the parity bit location (9th bit) becomes the Multiproces-
sor control bit. The UART Control 1 and Status 1 registers provide Multiprocessor (9-Bit)
94
Mode control and status information. If an automatic address matching scheme is enabled,
the UART Address Compare Register holds the network address of the device.
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all Mul-
tiprocessor modes, bit MPEN of the UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine must manually check the address byte that caused triggered the interrupt. If
it matches the UART address, the software clears MPMD[0]. At this point, each new
incoming byte interrupts the CPU. The software is then responsible for determining the
end of the frame. It checks for end-of-frame by reading the MPRX bit of the UART Status
1 Register for each incoming byte. If MPRX=1, a new frame has begun. If the address of
this new frame is different from the UARTs address, then set MPMD[0] to 1 causing the
UART interrupts to go inactive until the next address byte. If the new frames address
matches the UARTs, the data in the new frame is processed as well.
The second scheme is enabled by setting MPMD[1:0] to 10b and writing the UARTs
address into the UART Address Compare Register. This mode introduces more hardware
control, interrupting only on frames that match the UARTs address. When an incoming
address byte does not match the UARTs address, it is ignored. All successive data bytes in
this frame are also ignored. When a matching address byte occurs, an interrupt is issued
and further interrupts now occur on each successive data byte. The first data byte in the
frame contains the NEWFRM = 1 in the UART Status 1 Register. When the next address
byte occurs, the hardware compares it to the UARTs address. If there is a match, the inter-
rupts continue sand the NEWFRM bit is set for the first byte of the new frame. If there is
no match, then the UART ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0] to 11b and by writing the UARTs
address into the UART Address Compare Register. This mode is identical to the second
scheme, except that there are no interrupts on address bytes. The first data byte of each
frame is still accompanied by a NEWFRM assertion.
95
1
DE
0
Figure 17. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
------------------------------------
1
- DE to Start Bit Setup Time (s) -------------------------------------
2
Baud Rate (Hz) Baud Rate (Hz)
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also func-
tion as a basic timer with interrupt capability.
96
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
mission. The TDRE interrupt occurs after the Transmit Shift Register has shifted the first
bit of data out. At this point, the Transmit Data Register can be written with the next char-
acter to send. This provides 7 bit-periods of latency to load the Transmit Data Register
before the Transmit Shift Register completes shifting the current character. Writing to the
UART Transmit Data Register clears the TDRE bit to 0.
Receiver Interrupts
The receiver generates an interrupt when any of the following events occurs:
A data byte has been received and is available in the UART Receive Data Register. This
interrupt can be disabled independent of the other receiver interrupt sources. The re-
ceived data interrupt occurs once the receive character has been received and placed in
the Receive Data Register. Software must respond to this received data available con-
dition before the next character is completely received to avoid an overrun error.
Note: In Multiprocessor Mode (MPEN = 1), the receive data interrupts are dependent on the mul-
tiprocessor configuration and the most recent address byte.
A break is received
An overrun is detected
A data framing error is detected
97
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
98
When the UART is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt
on time-out, complete the following procedure:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 Register
to 0.
2. Load the appropriate 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BRGCTL bit in the UART Control 1 Register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
99
Bit 7 6 5 4 3 2 1 0
Field TXD
RESET X
R/W W
Address F40h and F48h
Bit Description
[7:0] Transmit Data
TXD UART transmitter data byte to be shifted out through the TXDx pin.
Bit 7 6 5 4 3 2 1 0
Field RXD
RESET X
R/W R
Address F40h and F48h
Bit Description
[7:0] Receive Data
RXD UART receiver data byte from the RXDx pin.
100
Bit 7 6 5 4 3 2 1 0
Field RDA PE OE FE BRKD TDRE TXE CTS
RESET 0 1 X
R/W R
Address F41h and F49h
Bit Description
[7] Receive Data Available
RDA This bit indicates that the UART Receive Data Register has received data. Reading the UART
Receive Data Register clears this bit.
0 = The UART Receive Data Register is empty.
1 = There is a byte in the UART Receive Data Register.
[6] Parity Error
PE This bit indicates that a parity error has occurred. Reading the UART Receive Data Register
clears this bit.
0 = No parity error occurred.
1 = A parity error occurred.
[5] Overrun Error
OE This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data Register has not been read. If the RDA bit is reset to 0,
then reading the UART Receive Data Register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
[4] Framing Error
FE This bit indicates that a framing error (no stop bit following data reception) was detected. Read-
ing the UART Receive Data Register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
[3] Break Detect
BRKD This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and stop bit(s)
are all zeros then this bit is set to 1. Reading the UART Receive Data Register clears this bit.
0 = No break occurred.
1 = A break occurred.
101
Bit 7 6 5 4 3 2 1 0
Field Reserved NEWFRM MPRX
RESET 0
R/W R R/W R
Address F44h and F4Ch
Bit Description
[7:2] Reserved
These bits are reserved and must be programmed to 000000.
[1] New Frame
NEWFRM Status bit denoting the start of a new frame. Reading the UART Receive Data Register
resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
[0] Multiprocessor Receive
MPRX Returns the value of the last multiprocessor bit received. Reading from the UART Receive
Data Register resets this bit to 0.
102
Bit 7 6 5 4 3 2 1 0
Field TEN REN CTSE PEN PSEL SBRK STOP LBEN
RESET 0
R/W R/W
Address F42h and F4Ah
Bit Description
[7] Transmit Enable
TEN This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
[6] Receive Enable
REN This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
[5] CTS Enable
CTSE 0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
[4] Parity Enable
PEN This bit enables or disables parity. Even or odd is determined by the PSEL bit. It is overridden
by the MPEN bit.
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an addi-
tional parity bit.
[3] Parity Select
PSEL 0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
[2] Send Break
SBRK This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent.
1 = The output of the transmitter is zero.
103
Bit 7 6 5 4 3 2 1 0
Field MPMD[1] MPEN MPMD[0] MPBT DEPOL BRGCTL RDAIRQ IREN
RESET 0
R/W R/W
Address F43h and F4Bh
Bit Description
[7,5] Multiprocessor Mode
MPMD[1,0] If Multiprocessor (9-Bit) Mode is enabled,
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches the
value stored in the Address Compare Register and on all successive data bytes until
an address mismatch occurs.
11 = The UART generates an interrupt request on all received data bytes for which the most
recent address byte matched the value in the Address Compare Register.
[6] Multiprocessor (9-Bit) Enable
MPEN This bit is used to enable Multiprocessor (9-Bit) Mode.
0 = Disable Multiprocessor (9-Bit) Mode.
1 = Enable Multiprocessor (9-Bit) Mode.
[4] Multiprocessor Bit Transmit
MPBT This bit is applicable only when Multiprocessor (9-Bit) Mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
[3] Driver Enable Polarity
DEPOL 0 = DE signal is Active High.
1 = DE signal is Active Low.
104
105
Bit 7 6 5 4 3 2 1 0
Field COMP_ADDR
RESET 0
R/W R/W
Address F45h and F4Dh
Bit Description
[7:0] Compare Address
COMP_ADDR This 8-bit value is compared to the incoming address bytes.
When configured as a general-purpose timer, the UART BRG interrupt interval is calcu-
lated using the following equation:
UART BRG Interrupt Interval s = System Clock Period (s) BRG 15:0
106
Bit 7 6 5 4 3 2 1 0
Field BRH
RESET 1
R/W R/W
Address F46h and F4Eh
Bit7 7 6 5 4 3 2 1 0
Field BRL
RESET 1
R/W R/W
Address F47h and F4Fh
For a given UART data rate, the integer baud rate divisor value is calculated using the fol-
lowing equation:
The baud rate error relative to the appropriate baud rate is calculated using the following
equation:
For reliable communication, the UART baud rate error must never exceed 5 percent.
Table 62 lists data rate errors for popular baud rates and commonly used crystal oscillator
frequencies.
107
108
109
Infrared Encoder/Decoder
The Z8 Encore! XP F64xx Series products contain two fully-functional, high-performance
UART-to-infrared encoders/decoders (endecs). Each infrared endec is integrated with an
on-chip UART to allow easy communication between the Z8 Encore! XP F64xx Series
and IrDA Physical Layer Specification Version 1.3-compliant infrared transceivers. Infra-
red communication provides secure, reliable, low-cost, point-to-point communication
between PCs, PDAs, cell phones, printers, and other infrared enabled devices.
Architecture
Figure 19 displays the architecture of the infrared endec.
System
Clock Zilog
ZHX1810
RxD RxD
RxD
TxD Infrared TxD
UART Encoder/Decoder TxD
Baud Rate (Endec) Infrared
Clock
Transceiver
Operation
When the infrared endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the infra-
red transceiver via the TxD pin. Likewise, data received from the infrared transceiver is
passed to the infrared endec via the RxD pin, decoded by the infrared endec, and then
110
16-clock
period
Baud Rate
Clock
UARTs Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
TxD
3-clock
pulse
IR_TXD
7-clock
delay
111
16-clock
period
Baud Rate
Clock
Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
IR_RXD
min. 1.6s
pulse
UARTs
RxD Start Bit = 0 Data Bit 0 = 1 Data Bit 1 = 0 Data Bit 2 = 1 Data Bit 3 = 1
8-clock
delay 16-clock 16-clock 16-clock 16-clock
period period period period
Caution: The system clock frequency must be at least 1.0 MHz to ensure proper reception of the
1.6 s minimum width pulses allowed by the IrDA standard.
112
since the previous pulse was detected). This gives the endec a sampling window of minus
four baud rate clocks to plus eight baud rate clocks around the expected time of an incom-
ing pulse. If an incoming pulse is detected inside this window this process is repeated. If
the incoming data is a logical 1 (no pulse), the endec returns to the initial state and waits
for the next falling edge. As each falling edge is detected, the endec clock counter is reset,
resynchronizing the endec to the incoming signal. This action allows the endec to tolerate
jitter and baud rate errors in the incoming data stream. Resynchronizing the endec does
not alter the operation of the UART, which ultimately receives the data. The UART is only
synchronized to the incoming data stream when a start bit is received.
Caution: To prevent spurious signals during IrDA data transmission, set the IREN bit in the
UARTx Control 1 Register to 1 to enable the Infrared Encoder/Decoder before enabling
the GPIO Port alternate function for the corresponding pin.
113
Architecture
The SPI may be configured as either a Master (in single or multimaster systems) or a Slave
as displayed in Figures 22 through 24.
SPI Master
To Slaves SS Pin SS
To Slave MOSI
114
VCC
SPI Master
SS
To Slave #2s SS Pin GPIO
To Slave #1s SS Pin GPIO
8-bit Shift Register
From Slave
MISO Bit 0 Bit 7
To Slave MOSI
SPI Slave
From Master SS
SCK
From Master
115
Operation
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire
interface (serial clock, transmit, receive and Slave select). The SPI block consists of a
transmit/receive shift register, a baud rate (clock) generator and a control unit.
During an SPI transfer, data is sent and received simultaneously by both the Master and
the Slave SPI devices. Separate signals are required for data and the serial clock. When an
SPI transfer occurs, a multibit (typically 8-bit) character is shifted out one data pin and an
multibit character is simultaneously shifted in on a second data pin. An 8-bit shift register
in the Master and another 8-bit shift register in the Slave are connected as a circular buffer.
The SPI Shift Register is single-buffered in the transmit and receive directions. New data
to be transmitted cannot be written into the shift register until the previous transmission is
complete and receive data (if valid) has been read.
SPI Signals
The four basic SPI signals are:
Master-In/Slave-Out
Master-Out/Slave-In
Serial Clock
Slave Select
Master-In/Slave-Out
The Master-In/Slave-Out (MISO) pin is configured as an input in a Master device and as
an output in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance
state if the Slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.
Master-Out/Slave-In
The Master-Out/Slave-In (MOSI) pin is configured as an output in a Master device and as
an input in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
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Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the device
through its MOSI and MISO pins. In MASTER Mode, the SPIs Baud Rate Generator cre-
ates the serial clock. The Master drives the serial clock out its own SCK pin to the Slaves
SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the clock sig-
nal from the Master synchronizes the data transfer between the Master and Slave devices.
Slave devices ignore the SCK signal, unless the SS pin is asserted. When configured as a
slave, the SPI block requires a minimum SCK period of greater than or equal to 8 times
the system (XIN) clock period.
The Master and Slave are each capable of exchanging a character of data during a
sequence of NUMBITS clock cycles (see the NUMBITS field in the SPI Mode Register
section on page 125). In both Master and Slave SPI devices, data is shifted on one edge of
the SCK and is sampled on the opposite edge where data is stable. Edge polarity is deter-
mined by the SPI phase and polarity control.
Slave Select
The active Low Slave Select (SS) input signal selects a Slave SPI device. SS must be Low
prior to all data communication to and from the Slave device. SS must stay Low for the
full duration of each character transferred. The SS signal may stay Low during the transfer
of multiple characters or may deassert between each character.
When the SPI is configured as the only Master in an SPI system, the SS pin can be set as
either an input or an output. Other GPIO output pins can also be employed to select exter-
nal SPI Slave devices.
When the SPI is configured as one Master in a multimaster SPI system, the SS pin must be
set as an input. The SS input signal on the Master must be High. If the SS signal goes Low
(indicating another Master is driving the SPI bus), a collision error flag is set in the SPI
Status Register.
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Table 63. SPI Clock Phase (PHASE) and Clock Polarity (CLKPOL) Operation
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
SS
118
SCK
(CLKPOL = 0)
SCK
(CLKPOL = 1)
SS
Multimaster Operation
In a multimaster SPI system, all SCK pins are tied together, all MOSI pins are tied
together and all MISO pins are tied together. All SPI pins must then be configured in
Open-Drain Mode to prevent bus contention. At any one time, only one SPI device is con-
figured as the Master and all other SPI devices on the bus are configured as Slaves. The
Master enables a single Slave by asserting the SS pin on that Slave only. Then, the single
Master drives data out its SCK and MOSI pins to the SCK and MOSI pins on the Slaves
(including those which are not enabled). The enabled Slave drives data out its MISO pin to
the MISO Master pin.
For a Master device operating in a multimaster system, if the SS pin is configured as an
input and is driven Low by another Master, the COL bit is set to 1 in the SPI Status Regis-
ter. The COL bit indicates the occurrence of a multimaster collision (mode fault error con-
dition).
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Slave Operation
The SPI block is configured for SLAVE Mode operation by setting the SPIEN bit to 1 and
the MMEN bit to 0 in the SPICTL Register and setting the SSIO bit to 0 in the SPIMODE
Register. The IRQE, PHASE, CLKPOL, WOR bits in the SPICTL Register and the
NUMBITS field in the SPIMODE Register must be set to be consistent with the other SPI
devices. The STR bit in the SPICTL Register may be used if appropriate to force a start-
up interrupt. The BIRQ bit in the SPICTL Register and the SSV bit in the SPIMODE Reg-
ister are not used in SLAVE Mode. The SPI baud rate generator is not used in SLAVE
Mode so the SPIBRH and SPIBRL registers need not be initialized.
If the slave has data to send to the master, the data must be written to the SPIDAT Register
before the transaction starts (first edge of SCK when SS is asserted). If the SPIDAT Regis-
ter is not written prior to the slave transaction, the MISO pin outputs whatever value is
currently in the SPIDAT Register.
Due to the delay resulting from synchronization of the SPI input signals to the internal sys-
tem clock, the maximum SPICLK baud rate that can be supported in SLAVE Mode is the
system clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.
Error Detection
The SPI contains error detection logic to support SPI communication protocols and recog-
nize when communication errors have occurred. The SPI Status Register indicates when a
data transmission error has been detected.
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The next time SS asserts, the MISO pin outputs SPIDAT[7], regardless of where the previ-
ous transaction left off. Writing a 1 to ABT clears this error flag.
SPI Interrupts
When SPI interrupts are enabled, the SPI generates an interrupt after character transmis-
sion/reception completes in both MASTER and SLAVE modes. A character can be
defined to be 1 through 8 bits by the NUMBITS field in the SPI Mode Register. In Slave
Mode, it is not necessary for SS to deassert between characters to generate the interrupt.
The SPI in Slave mode can also generate an interrupt if the SS signal deasserts prior to
transfer of all the bits in a character (see description of slave abort error above). Writing a
1 to the IRQ bit in the SPI Status Register clears the pending SPI interrupt request. The
IRQ bit must be cleared to 0 by the Interrupt Service Routine to generate future interrupts.
To start the transfer process, an SPI interrupt may be forced by software writing a 1 to the
STR bit in the SPICTL Register.
If the SPI is disabled, an SPI interrupt can be generated by a Baud Rate Generator time-
out. This timer function must be enabled by setting the BIRQ bit in the SPICTL Register.
This Baud Rate Generator time-out does not set the IRQ bit in the SPISTAT Register, just
the SPI interrupt bit in the interrupt controller.
Minimum baud rate is obtained by setting BRG[15:0] to 0000h for a clock divisor value
of (2 X 65536 = 131072).
When the SPI is disabled, the Baud Rate Generator can function as a basic 16-bit timer
with interrupt on time-out. Observe the following procedure to configure the Baud Rate
Generator as a timer with interrupt on time-out:
1. Disable the SPI by clearing the SPIEN bit in the SPI Control Register to 0.
2. Load the appropriate 16-bit count value into the SPI Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the SPI Control Register to 1.
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When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
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Bit 7 6 5 4 3 2 1 0
Field DATA
RESET X
R/W R/W
Address F60h
Bit Description
[7:0] Data
DATA Transmit and/or receive data.
Bit 7 6 5 4 3 2 1 0
Field IRQE STR BIRQ PHASE CLKPOL WOR MMEN SPIEN
RESET 0
R/W R/W
Address F61h
Bit Description
[7] Interrupt Request Enable
IRQE 0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.
1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.
[6] Start an SPI Interrupt Request
STR 0 = No effect.
1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status Register to 1. Setting this bit
forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by
software for a function similar to transmit buffer empty in a UART. Writing a 1 to the IRQ bit
in the SPI Status Register clears this bit to 0.
[5] BRG Timer Interrupt Request
BIRQ If the SPI is enabled, this bit has no effect. If the SPI is disabled:
0 = The Baud Rate Generator timer function is disabled.
1 = The Baud Rate Generator timer function and time-out interrupt are enabled.
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Bit 7 6 5 4 3 2 1 0
Field IRQ OVR COL ABT Reserved TXST SLAS
RESET 0 1
R/W R/W* R
Address F62h
Note: R/W* = Read access. Write a 1 to clear the bit to 0.
Bit Description
[7] Interrupt Request
IRQ If SPIEN = 1, this bit is set if the STR bit in the SPICTL Register is set, or upon completion of
an SPI master or slave transaction. This bit does not set if SPIEN = 0 and the SPI Baud Rate
Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
[6] Overrun
OVR 0 = An overrun error has not occurred.
1 = An overrun error has been detected.
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125
Bit 7 6 5 4 3 2 1 0
Field Reserved DIAG NUMBITS[2:0] SSIO SSV
RESET 0
R/W R R/W
Address F63h
Bit Description
[7:6] Reserved
These bits are reserved and must be programmed to 00.
[5] Diagnostic Mode Control bit
DIAG This bit is for SPI diagnostics. Setting this bit allows the Baud Rate Generator value to be
read using the SPIBRH and SPIBRL Register locations.
0 = Reading SPIBRH, SPIBRL returns the value in the SPIBRH and SPIBRL registers.
1 = Reading SPIBRH returns bits [15:8] of the SPI Baud Rate Generator; and reading
SPIBRL returns bits [7:0] of the SPI Baud Rate Counter. The Baud Rate Counter High
and Low byte values are not buffered.
Caution: Exercise caution if reading the values while the BRG is counting.
[4] Number of Data Bits Per Character to Transfer
NUMBITS[2:0] This field contains the number of bits to shift for each character transfer. For information
about valid bit positions when the character length is less than 8 bits, see the SPI Data
Register (SPIDATA) description.
000 = 8 bits.
001 = 1 bit.
010 = 2 bits.
011 = 3 bits.
100 = 4 bits.
101 = 5 bits.
110 = 6 bits.
111 = 7 bits.
[1] Slave Select I/O
SSIO 0 = SS pin configured as an input.
1 = SS pin configured as an output (Master Mode only).
[0] Slave Select Value
SSV If SSIO = 1 and SPI is configured as a Master, the following conditions are true:
0 = SS pin driven Low (0).
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or if SPI is configured as a Slave.
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Bit 7 6 5 4 3 2 1 0
Field SCKEN TCKEN SPISTATE
RESET 0
R/W R
Address F64h
Bit Description
[7] Shift Clock Enable
SCKEN 0 = The internal Shift Clock Enable signal is deasserted.
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next sys-
tem clock).
[6] Transmit Clock Enable
TCKEN 0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial
data out is updated on the next system clock (MOSI or MISO).
[5:0] SPI State Machine
SPISTATE Defines the current state of the internal SPI State Machine.
SPI BRG Interrupt Interval (s) = System Clock Period (s) BRG[15:0]
127
Bit 7 6 5 4 3 2 1 0
Field BRH
RESET 1
R/W R/W
Address F66h
Bit Description
[7:0] SPI Baud Rate High Byte
BRH Most significant byte, BRG[15:8], of the SPI Baud Rate Generators reload value.
Bit 7 6 5 4 3 2 1 0
Field BRL
RESET 1
R/W R/W
Address F67h
Bit Description
[7:0] SPI Baud Rate Low Byte
BRL Least significant byte, BRG[7:0], of the SPI Baud Rate Generators reload value.
128
I2C Controller
The I2C Controller makes the Z8 Encore! XP F64xx Series products bus-compatible with
the I2C protocol. The I2C Controller consists of two bidirectional bus lines: a serial data
signal (SDA) and a serial clock signal (SCL). Features of the I2C Controller include:
Transmit and Receive Operation in MASTER Mode
Maximum data rate of 400 kilobit/sec
7- and 10-bit addressing modes for Slaves
Unrestricted number of data bytes transmitted per transfer
The I2C Controller in the Z8 Encore! XP F64xx Series products does not operate in
SLAVE Mode.
Architecture
Figure 27 displays the architecture of the I2C Controller.
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SDA
SCL
Shift
ISHIFT
Load
I2CDATA
Baud Rate Generator
I2CBRH Receive
I2CBRL
I2CCTL I2CSTAT
Register Bus
I2C Interrupt
Operation
The I2C Controller operates in MASTER Mode to transmit and receive data. Only a single
master is supported. Arbitration between two masters must be accomplished in software.
I2C supports the following operations:
Master transmits to a 7-bit slave
Master transmits to a 10-bit slave
Master receives from a 7-bit slave
Master receives from a 10-bit slave
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I2C Interrupts
The I2C Controller contains four sources of interruptsTransmit, Receive, Not Acknowl-
edge and baud rate generator. These four interrupt sources are combined into a single
interrupt request signal to the Interrupt Controller. The transmit interrupt is enabled by the
IEN and TXI bits of the Control Register. The Receive and Not Acknowledge interrupts
are enabled by the IEN bit of the Control Register. The baud rate generator interrupt is
enabled by the BIRQ and IEN bits of the Control Register.
Not Acknowledge interrupts occur when a Not Acknowledge condition is received from
the slave or sent by the I2C Controller and neither the start or stop bit is set. The Not
Acknowledge event sets the NCKI bit of the I2C Status Register and can only be cleared
by setting the start or stop bit in the I2C Control Register. When this interrupt occurs, the
I2C Controller waits until either the stop or start bit is set before performing any action. In
an interrupt service routine, the NCKI bit should always be checked prior to servicing
transmit or receive interrupt conditions because it indicates the transaction is being termi-
nated.
Receive interrupts occur when a byte of data has been received by the I2C Controller
(master reading data from slave). This procedure sets the RDRF bit of the I2C Status Reg-
ister. The RDRF bit is cleared by reading the I2C Data Register. The RDRF bit is set dur-
ing the acknowledge phase. The I2C Controller pauses after the acknowledge phase until
the receive interrupt is cleared before performing any other action.
Transmit interrupts occur when the TDRE bit of the I2C Status Register sets and the TXI
bit in the I2C Control Register is set. transmit interrupts occur under the following condi-
tions when the transmit data register is empty:
The I2C Controller is enabled
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The first bit of the byte of an address is shifting out and the RD bit of the I2C Status
Register is deasserted.
The first bit of a 10-bit address shifts out
The first bit of write data shifts out
Note: Writing to the I2C Data Register always clears the TRDE bit to 0. When TDRE is asserted,
the I2C Controller pauses at the beginning of the Acknowledge cycle of the byte currently
shifting out. It does not resume until the Data Register is written with the next value to
send or until the stop or start bits are set, indicating that the current byte is the last one to
send.
The fourth interrupt source is the baud rate generator. If the I2C Controller is disabled
(IEN bit in the I2CCTL Register = 0) and the BIRQ bit in the I2CCTL Register = 1, an
interrupt is generated when the baud rate generator counts down to 1. This allows the I2C
baud rate generator to be used by software as a general purpose timer when IEN = 0.
Caution: A transmit (write) DMA operation hangs if the slave responds with a Not Acknowledge
before the last byte has been sent. After receiving the Not Acknowledge, the I2C Control-
ler sets the NCKI bit in the Status Register and pauses until either the stop or start bits in
the Control Register are set.
For a receive (read) DMA transaction to send a Not Acknowledge on the last byte, the
receive DMA must be set up to receive n-1 bytes, then software must set the NAK bit and
receive the last (nth) byte directly.
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133
Observe the following procedure for an address only transaction to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty (TDRE = 1)
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (= 0)
to the I2C Data Register. As an alternative this could be a read operation instead of a
write operation.
5. Software sets the start and stop bits of the I2C Control Register and clears the TXI bit.
6. The I2C Controller sends the start condition to the I2C slave.
7. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
8. Software polls the stop bit of the I2C Control Register. Hardware deasserts the stop bit
when the address only transaction is completed.
9. Software checks the ACK bit of the I2C Status Register. If the slave acknowledged,
the ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt does not occur in the not acknowledge case because the stop bit was set.
134
Observe the following procedure for a transmit operation to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
to the I2C Data Register.
5. Software asserts the start bit of the I2C Control Register.
6. The I2C Controller sends the start condition to the I2C slave.
7. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
8. After one bit of address has been shifted out by the SDA signal, the transmit interrupt
is asserted (TDRE = 1).
9. Software responds by writing the transmit data into the I2C Data Register.
10. The I2C Controller shifts the rest of the address and write bit out by the SDA signal.
11. If the I2C slave sends an acknowledge (by pulling the SDA signal Low) during the
next High period of SCL the I2C Controller sets the ACK bit in the I2C Status Regis-
ter. Continue with Step 12.
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status Register, ACK bit is cleared). Software responds to the Not Acknowl-
edge interrupt by setting the stop and flush bits and clearing the TXI bit. The I2C Con-
troller sends the stop condition on the bus and clears the stop and NCKI bits. The
transaction is complete (ignore the following steps).
12. The I2C Controller loads the contents of the I2C Shift Register with the contents of the
I2C Data Register.
13. The I2C Controller shifts the data out of using the SDA signal. After the first bit is
sent, the transmit interrupt is asserted.
14. If more bytes remain to be sent, return to Step 9.
15. Software responds by setting the stop bit of the I2C Control Register (or start bit to ini-
tiate a new transaction). In the stop case, software clears the TXI bit of the I2C Control
Register at the same time.
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16. The I2C Controller completes transmission of the data on the SDA signal.
17. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
the stop or start bit is already set, the NCKI interrupt does not occur.
18. The I2C Controller sends the stop (or RESTART) condition to the I2C bus. The stop or
start bit is cleared.
Observe the following procedure for an address only transaction to a 10-bit addressed
slave:
1. Software asserts the IEN bit in the I2C Control Register.
2. Software asserts the TXI bit of the I2C Control Register to enable transmit interrupts.
3. The I2C interrupt asserts, because the I2C Data Register is empty (TDRE = 1)
4. Software responds to the TDRE interrupt by writing the first slave address byte. The
least significant bit must be 0 for the write operation.
5. Software asserts the start bit of the I2C Control Register.
6. The I2C Controller sends the start condition to the I2C slave.
7. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
8. After one bit of address is shifted out by the SDA signal, the transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I2C
Data Register.
136
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I2C slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL the I2C Controller sets the ACK bit in the I2C Status Register.
Continue with Step 12.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I2C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore following steps).
12. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister (2nd byte of address).
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the transmit interrupt is asserted.
14. Software responds by setting the stop bit in the I2C Control Register. The TXI bit can
be cleared at the same time.
15. Software polls the stop bit of the I2C Control Register. Hardware deasserts the stop bit
when the transaction is completed (stop condition has been sent).
16. Software checks the ACK bit of the I2C Status Register. If the slave acknowledged,
the ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt do not occur because the stop bit was set.
The first seven bits transmitted in the first byte are 11110XX. The two bits XX are the two
most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
read/write control bit (=0). The transmit operation is carried out in the same manner as 7-
bit addressing.
Observe the following procedure for a transmit operation on a 10-bit addressed slave:
1. Software asserts the IEN bit in the I2C Control Register.
137
2. Software asserts the TXI bit of the I2C Control Register to enable transmit interrupts.
3. The I2C interrupt asserts because the I2C Data Register is empty.
4. Software responds to the TDRE interrupt by writing the first slave address byte to the
I2C Data Register. The least significant bit must be 0 for the write operation.
5. Software asserts the start bit of the I2C Control Register.
6. The I2C Controller sends the start condition to the I2C slave.
7. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
8. After one bit of address is shifted out by the SDA signal, the transmit interrupt is
asserted.
9. Software responds by writing the second byte of address into the contents of the I2C
Data Register.
10. The I2C Controller shifts the rest of the first byte of address and write bit out the SDA
signal.
11. If the I2C slave acknowledges the first address byte by pulling the SDA signal Low
during the next High period of SCL, the I2C Controller sets the ACK bit in the I2C
Status Register. Continue with Step 12.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I2C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore the following steps).
12. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
13. The I2C Controller shifts the second address byte out the SDA signal. After the first
bit has been sent, the transmit interrupt is asserted.
14. Software responds by writing a data byte to the I2C Data Register.
15. The I2C Controller completes shifting the contents of the shift register on the SDA
signal.
16. If the I2C slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL, the I2C Controller sets the ACK bit in the I2C Status Register.
Continue with Step 17.
If the slave does not acknowledge the second address byte or one of the data bytes, the
I2C Controller sets the NCKI bit and clears the ACK bit in the I2C Status Register.
Software responds to the Not Acknowledge interrupt by setting the stop and flush bits
and clearing the TXI bit. The I2C Controller sends the stop condition on the bus and
138
clears the stop and NCKI bits. The transaction is complete (ignore the following
steps).
17. The I2C Controller shifts the data out by the SDA signal. After the first bit is sent, the
transmit interrupt is asserted.
18. If more bytes remain to be sent, return to Step 14.
19. If the last byte is currently being sent, software sets the stop bit of the I2C Control
Register (or start bit to initiate a new transaction). In the stop case, software also clears
the TXI bit of the I2C Control Register at the same time.
20. The I2C Controller completes transmission of the last data byte on the SDA signal.
21. The slave may either Acknowledge or Not Acknowledge the last byte. Because either
the stop or start bit is already set, the NCKI interrupt does not occur.
22. The I2C Controller sends the stop (or RESTART) condition to the I2C bus and clears
the stop (or start) bit.
Figure 32. Receive Data Transfer Format for a 7-Bit Addressed Slave
Observe the following procedure for a read operation to a 7-bit addressed slave:
1. Software writes the I2C Data Register with a 7-bit slave address plus the read bit (= 1).
2. Software asserts the start bit of the I2C Control Register.
3. If this is a single byte transfer, Software asserts the NAK bit of the I2C Control Regis-
ter so that after the first byte of data has been read by the I2C Controller, a Not
Acknowledge is sent to the I2C slave.
4. The I2C Controller sends the start condition.
5. The I2C Controller shifts the address and read bit out the SDA signal.
6. If the I2C slave acknowledges the address by pulling the SDA signal Low during the
next High period of SCL, the I2C Controller sets the ACK bit in the I2C Status Regis-
ter. Continue with Step 7.
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
139
set in the Status Register, ACK bit is cleared). Software responds to the Not Acknowl-
edge interrupt by setting the stop bit and clearing the TXI bit. The I2C Controller
sends the stop condition on the bus and clears the stop and NCKI bits. The transaction
is complete (ignore the following steps).
7. The I2C Controller shifts in the byte of data from the I2C slave on the SDA signal. The
I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
8. The I2C Controller asserts the receive interrupt (RDRF bit set in the Status Register).
9. Software responds by reading the I2C Data Register which clears the RDRF bit. If
there is only one more byte to receive, set the NAK bit of the I2C Control Register.
10. If there are more bytes to transfer, return to Step 7.
11. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C
Controller.
12. Software responds by setting the stop bit of the I2C Control Register.
13. A stop condition is sent to the I2C slave, the stop and NCKI bits are cleared.
The first seven bits transmitted in the first byte are 11110XX. The two (XX) bits are the two
most significant bits of the 10-bit address. The lowest bit of the first byte transferred is the
write control bit.
Observe the following procedure for the data transfer for a read operation to a 10-bit
addressed slave:
1. Software writes 11110B followed by the two address bits and a 0 (write) to the I2C
Data Register.
2. Software asserts the start and TXI bits of the I2C Control Register.
3. The I2C Controller sends a start condition.
4. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister.
140
5. After the first bit has been shifted out, a transmit interrupt is asserted.
6. Software responds by writing the lower eight bits of address to the I2C Data Register.
7. The I2C Controller completes shifting of the two address bits and a 0 (write).
8. If the I2C slave acknowledges the first address byte by pulling the SDA signal Low
during the next High period of SCL, the I2C Controller sets the ACK bit in the I2C
Status Register. Continue with Step 9.
If the slave does not acknowledge the first address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I2C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore following steps).
9. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister (second address byte).
10. The I2C Controller shifts out the second address byte. After the first bit is shifted, the
I2C Controller generates a transmit interrupt.
11. Software responds by setting the start bit of the I2C Control Register to generate a
repeated start by clearing the TXI bit.
12. Software responds by writing 11110B followed by the 2-bit slave address and a 1
(read) to the I2C Data Register.
13. If only one byte is to be read, software sets the NAK bit of the I2C Control Register.
14. After the I2C Controller shifts out the 2nd address byte, the I2C slave sends an
acknowledge by pulling the SDA signal Low during the next High period of SCL, the
I2C Controller sets the ACK bit in the I2C Status Register. Continue with Step 15.
If the slave does not acknowledge the second address byte, the I2C Controller sets the
NCKI bit and clears the ACK bit in the I2C Status Register. Software responds to the
Not Acknowledge interrupt by setting the stop and flush bits and clearing the TXI bit.
The I2C Controller sends the stop condition on the bus and clears the stop and NCKI
bits. The transaction is complete (ignore the following steps).
15. The I2C Controller sends the repeated start condition.
16. The I2C Controller loads the I2C Shift Register with the contents of the I2C Data Reg-
ister (third address transfer).
17. The I2C Controller sends 11110B followed by the two most significant bits of the
slave read address and a 1 (read).
18. The I2C slave sends an acknowledge by pulling the SDA signal Low during the next
High period of SCL
141
If the slave were to Not Acknowledge at this point (this should not happen because the
slave did acknowledge the first two address bytes), software would respond by setting
the stop and flush bits and clearing the TXI bit. The I2C Controller sends the stop con-
dition on the bus and clears the stop and NCKI bits. The transaction is complete
(ignore the following steps).
19. The I2C Controller shifts in a byte of data from the I2C slave on the SDA signal. The
I2C Controller sends a Not Acknowledge to the I2C slave if the NAK bit is set (last
byte), else it sends an Acknowledge.
20. The I2C Controller asserts the receive interrupt (RDRF bit set in the Status Register).
21. Software responds by reading the I2C Data Register which clears the RDRF bit. If
there is only one more byte to receive, set the NAK bit of the I2C Control Register.
22. If there are one or more bytes to transfer, return to Step 19.
23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I2C
Controller.
24. Software responds by setting the stop bit of the I2C Control Register.
25. A stop condition is sent to the I2C slave and the stop and NCKI bits are cleared.
142
Bit 7 6 5 4 3 2 1 0
Field DATA
RESET 0
R/W R/W
Address F50h
Bit 7 6 5 4 3 2 1 0
Field TDRE RDRF ACK 10B RD TAS DSS NCKI
RESET 1 0
R/W R
Address F51h
Bit Description
[7] Transmit Data Register Empty
TDRE When the I2C Controller is enabled, this bit is 1 when the I2C Data Register is empty. When this
bit is set, an interrupt is generated if the TXI bit is set, except when the I2C Controller is shifting
in data during the reception of a byte or when shifting an address and the RD bit is set. This bit
is cleared by writing to the I2CDATA Register.
[6] Receive Data Register Full
RDRF This bit is set = 1 when the I2C Controller is enabled and the I2C Controller has received a byte
of data. When asserted, this bit causes the I2C Controller to generate an interrupt. This bit is
cleared by reading the I2C Data Register (unless the read is performed using execution of the
On-Chip Debuggers Read Register command).
143
144
Bit 7 6 5 4 3 2 1 0
Field IEN START STOP BIRQ TXI NAK FLUSH FILTEN
RESET 0
R/W R/W R/W1 R/W1 R/W R/W R/W1 W1 R/W
Address F52h
Bit Description
[7] I2C Enable
IEN 1 = The I2C transmitter and receiver are enabled.
0 = The I2C transmitter and receiver are disabled.
[6] Send Start Condition
START This bit sends a start condition. Once asserted, it is cleared by the I2C Controller after it sends
a start condition or if the IEN bit is deasserted. If this bit is 1, it cannot be cleared to 0 by writing
to the register. After this bit is set, a start condition is sent if there is data in the I2C Data Regis-
ter or I2C Shift Register. If there is no data in one of these registers, the I2C Controller waits
until the Data Register is written. If this bit is set while the I2C Controller is shifting out data, it
generates a start condition after the byte shifts and the acknowledge phase completes. If the
stop bit is also set, it also waits until the stop condition is sent before the sending the start con-
dition.
[5] Send Stop Condition
STOP This bit causes the I2C Controller to issue a stop condition after the byte in the I2C Shift Regis-
ter has completed transmission or after a byte has been received in a receive operation. AFter
it is set, this bit is reset by the I2C Controller after a stop condition has been sent or by deas-
serting the IEN bit. If this bit is 1, it cannot be cleared to 0 by writing to the register.
[4] Baud Rate Generator Interrupt Request
BIRQ This bit allows the I2C Controller to be used as an additional timer when the I2C Controller is
disabled. This bit is ignored when the I2C Controller is enabled.
1 = An interrupt occurs every time the baud rate generator counts down to one.
0 = No baud rate generator interrupt occurs.
[3] Enable TDRE Interrupts
TXI This bit enables the transmit interrupt when the I2C Data Register is empty (TDRE = 1).
1 = Transmit interrupt (and DMA transmit request) is enabled.
0 = Transmit interrupt (and DMA transmit request) is disabled.
[2] Send NAK
NAK This bit sends a Not Acknowledge condition after the next byte of data has been read from the
I2C slave. Once asserted, it is deasserted after a Not Acknowledge is sent or the IEN bit is
deasserted. If this bit is 1, it cannot be cleared to 0 by writing to the register.
145
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
146
Bit 7 6 5 4 3 2 1 0
Field BRH
RESET FFh
R/W R/W
Address F53h
Bit Description
[7:0] I2C Baud Rate High Byte
BRH Most significant byte, BRG[15:8], of the I2C Baud Rate Generators reload value.
Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRH
Register returns the current value of the I2C Baud Rate Counter[15:8].
Bit 7 6 5 4 3 2 1 0
Field BRL
RESET FFh
R/W R/W
Address F54h
Bit Description
[7:0] I2C Baud Rate Low Byte
BRL Least significant byte, BRG[7:0], of the I2C Baud Rate Generators reload value.
Note: If the DIAG bit in the I2C Diagnostic Control Register is set to 1, a read of the I2CBRL
Register returns the current value of the I2C Baud Rate Counter[7:0].
147
Bit 7 6 5 4 3 2 1 0
Field SCLIN SDAIN STPCNT TXRXSTATE
RESET X 0
R/W R
Address F55h
Bit Description
[7] Serial Clock Input
SCLIN Value of the Serial Clock input signal.
[6] Serial Data Input
SDAIN Value of the Serial Data input signal.
[5] Stop Count
STPCNT Value of the internal Stop Count control signal.
148
149
Bit 7 6 5 4 3 2 1 0
Field Reserved DIAG
RESET 0
R/W R R/W
Address F56h
Bit Description
[7:1] Reserved
These bits are reserved and must be programmed to 0000000.
[0] Diagnostic Control Bit
DIAG Selects read back value of the Baud Rate Reload registers.
0 = Normal Mode. Reading the Baud Rate High and Low Byte registers returns the baud rate
reload value.
1 = DIAGNOSTIC Mode. Reading the Baud Rate High and Low Byte registers returns the baud
rate counter value.
150
Operation
DMA0 and DMA1, referred to collectively as DMAx, transfer data either from the on-chip
peripheral control registers to the register file, or from the register file to the on-chip
peripheral control registers. The sequence of operations in a DMAx data transfer is:
1. DMAx trigger source requests a DMA data transfer.
2. DMAx requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMAx transfers either a single byte
or a two-byte word (depending upon configuration) and then returns system bus con-
trol to the eZ8 CPU.
4. If the Current Address equals the End Address, then the following conditions are true:
DMAx reloads the original Start Address
If configured to generate an interrupt, DMAx sends an interrupt request to the
Interrupt Controller
If configured for single-pass operation, DMAx resets the DEN bit in the DMAx
Control Register to 0 and the DMA is disabled
If the Current Address does not equal the End Address, then the Current Address
increments by 1 (single-byte transfer) or 2 (two-byte word transfer).
151
3. Write the start and end register file address high nibbles to the DMAx End/Start
Address High Nibble Register.
4. Write the lower byte of the Start Address to the DMAx Start/Current Address Register.
5. Write the lower byte of the End Address to the DMAx End Address Register.
6. Write to the DMAx Control Register to complete the following operations:
Select loop or single-pass mode operation
Select the data transfer direction (either from the register file RAM to the on-chip
peripheral control register; or from the on-chip peripheral control register to the
register file RAM)
Enable the DMAx interrupt request, if appropriate
Select Word or Byte mode
Select the DMAx request trigger
Enable the DMAx channel
DMA_ADC Operation
DMA_ADC transfers data from the ADC to the register file. The sequence of operations
in a DMA_ADC data transfer is:
1. ADC completes conversion on the current ADC input channel and signals the DMA
controller that two-bytes of ADC data are ready for transfer.
2. DMA_ADC requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMA_ADC transfers the two-byte
ADC output value to the register file and then returns system bus control back to the
eZ8 CPU.
4. If the current ADC analog input is the highest-numbered input to be converted:
The DMA_ADC resets the ADC analog input number to 0 and initiates data con-
version on ADC analog input 0
If configured to generate an interrupt, the DMA_ADC sends an interrupt request
to the Interrupt Controller
If the current ADC analog input is not the highest-numbered input to be converted,
then the DMA_ADC initiates data conversion in the next higher-numbered ADC
analog input.
152
1. Write the DMA_ADC Address Register with the 7 most significant bits of the register
file address for data transfers.
2. Write to the DMA_ADC Control Register to complete the following operations:
Enable the DMA_ADC interrupt request, if appropriate
Select the number of ADC analog inputs to convert
Enable the DMA_ADC channel
Caution: When using the DMA_ADC to perform conversions on multiple ADC inputs, the Ana-
log-to-Digital Converter must be configured for SINGLE-SHOT Mode. If the ADC_IN
field in the DMA_ADC Control Register is greater than 000b, the ADC must be in SIN-
GLE-SHOT Mode.
Continuous Mode operation of the ADC can only be used in conjunction with the
DMA_ADC if the ADC_IN field in the DMA_ADC Control Register is reset to 000b to
enable conversion on ADC analog input 0 only.
153
Bit 7 6 5 4 3 2 1 0
Field DEN DLE DDIR IRQEN WSEL RSS
RESET 0
R/W R/W
Address FB0h, FB8h
Bit Description
[7] DMAx Enable
DEN 0 = DMAx is disabled and data transfer requests are disregarded.
1 = DMAx is enabled and initiates a data transfer upon receipt of a request from the trigger
source.
[6] DMAx Loop Enable
DLE 0 = DMAx reloads the original Start Address and is then disabled after the End Address data is
transferred.
1 = DMAx, after the End Address data is transferred, reloads the original Start Address and
continues operating.
[5] DMAx Data Transfer Direction
DDIR 0 = Register file on-chip peripheral control register.
1 = On-chip peripheral control register file.
[4] DMAx Interrupt Enable
IRQEN 0 = DMAx does not generate any interrupts.
1 = DMAx generates an interrupt when the End Address data is transferred.
154
Bit 7 6 5 4 3 2 1 0
Field DMA_IO
RESET X
R/W R/W
Address FB1h, FB9h
Bit Description
[7:0] DMA On-Chip Peripheral Control Register Address
DMA_IO This byte sets the low byte of the on-chip peripheral control register address on register file
page Fh (addresses F00h to FFFh).
155
Bit 7 6 5 4 3 2 1 0
Field DMA_END_H DMA_START_H
RESET X
R/W R/W
Address FB2h, FBAh
Bit Description
[7:4] DMAx End Address High Nibble
DMA_END_H These bits, used with the DMAx End Address Low Register, form a 12-bit End Address.
The full 12-bit address is provided by {DMA_END_H[3:0], DMA_END[7:0]}.
[3:0] DMAx Start/Current Address High Nibble
DMA_START_H These bits, used with the DMAx Start/Current Address Low Register, form a 12-bit Start/
Current Address. The full 12-bit address is provided by {DMA_START_H[3:0],
DMA_START[7:0]}.
156
Bit 7 6 5 4 3 2 1 0
Field DMA_START
RESET X
R/W R/W
Address FB3h, FBBh
Bit Description
[7:0] DMAx Start/Current Address Low
DMA_START These bits, with the four lower bits of the DMAx_H Register, form the 12-bit Start/Current
address. The full 12-bit address is provided by {DMA_START_H[3:0], DMA_START[7:0]}.
Bit 7 6 5 4 3 2 1 0
Field DMA_END
RESET X
R/W R/W
Address FB4h, FBCh
Bit Description
[7] DMAx End Address Low
DMA_END These bits, with the four upper bits of the DMAx_H Register, form a 12-bit address. This
address is the ending location of the DMAx transfer. The full 12-bit address is provided by
{DMA_END_H[3:0], DMA_END[7:0]}.
157
158
Bit 7 6 5 4 3 2 1 0
Field DMAA_ADDR Reserved
RESET X
R/W R/W
Address FBDh
Bit Description
[7:1] DMA_ADC Address
DMAA_ADDR These bits specify the seven most significant bits of the 12-bit register file addresses
used for storing the ADC output data. The ADC analog input Number defines the five
least significant bits of the register file address. Full 12-bit address is {DMAA_ADDR[7:1],
4-bit ADC analog input Number, 0}.
0 Reserved
This bit is reserved and must be programmed to 0.
Bit 7 6 5 4 3 2 1 0
Field DAEN IRQEN Reserved ADC_IN
RESET 0
R/W R/W
Address FBEh
Bit Description
[7] DMA_ADC Enable
DAEN 0 = DMA_ADC is disabled and the ADC analog input Number (ADC_IN) is reset to 0.
1 = DMA_ADC is enabled.
[6] Interrupt Enable
IRQEN 0 = DMA_ADC does not generate any interrupts.
1 = DMA_ADC generates an interrupt after transferring data from the last ADC analog input
specified by the ADC_IN field.
159
Bit 7 6 5 4 3 2 1 0
Field CADC[3:0] Reserved IRQA IRQ1 IRQ0
RESET 0
R/W R
Address FBFh
Bit Description
[7:4] Current ADC Analog Input
CADC[3:0] This field identifies the Analog Input that the ADC is currently converting.
[3] Reserved
This bit is reserved and must be programmed to 0.
160
161
Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) converts an analog input signal to a 10-bit binary
number. The features of the sigma-delta ADC include:
12 analog input sources are multiplexed with general-purpose I/O ports
Interrupt upon completion of conversion
Internal voltage reference generator
A Direct Memory Access (DMA) controller that can automatically initiate data conver-
sion and transfer the data from 1 to 12 analog inputs
Architecture
Figure 34 displays the three major functional blocks (converter, analog multiplexer, and
voltage reference generator) of the ADC. The ADC converts an analog input signal to its
digital representation. The 12-input analog multiplexer selects one of the 12 analog input
sources. The ADC requires an input reference voltage for the conversion. The voltage ref-
erence for the conversion may be input through the external VREF pin or generated inter-
nally by the voltage reference generator.
162
VREF
Internal Voltage
Reference Generator Analog Input
Multiplexer
ANA0
ANA1
ANA2
Analog-to-Digital
Converter ANA3
ANA4
ANA5
Reference Input
ANA6
ANA7
ANA8
Analog Input
ANA9
ANA10
ANA11
ANAIN[3:0]
The sigma-delta ADC architecture provides alias and image attenuation below the ampli-
tude resolution of the ADC in the frequency range of DC to one-half the ADC clock rate
(one-fourth the system clock rate). The ADC provides alias free conversion for frequen-
cies up to one-half the ADC clock rate. Therefore, the sigma-delta ADC exhibits high
noise immunity, which makes it ideal for embedded applications. In addition, monotonic-
ity (no missing codes) is guaranteed by design.
163
Operation
This section describes the operational aspects of the ADCs power-down and conversion
features.
Automatic Power-Down
If the ADC is idle (i.e., no conversions are in progress) for 160 consecutive system clock
cycles, portions of the ADC are automatically powered down. From this powered-down
state, the ADC requires 40 system clock cycles to power up. The ADC powers up when a
conversion is requested using the ADC Control Register.
Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Observe the following procedure for setting up the ADC and initiating a
single-shot conversion:
1. Enable the appropriate analog inputs by configuring the general-purpose I/O pins for
alternate function. This configuration disables the digital input and output drivers.
2. Write to the ADC Control Register to configure the ADC and begin the conversion.
The bit fields in the ADC Control Register can be written simultaneously:
Write to the ANAIN[3:0] field to select one of the 12 analog input sources
Clear CONT to 0 to select a single-shot conversion
Write to the VREF bit to enable or disable the internal voltage reference generator
Set CEN to 1 to start the conversion
5. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
powered down.
164
Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an analog-
to-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated after each con-
version.
Caution: In Continuous Mode, you must be aware that ADC updates are limited by the input signal
bandwidth of the ADC and the latency of the ADC and its digital filter. Step changes at
the input are not seen at the next output from the ADC. The response of the ADC (in all
modes) is limited by the input signal bandwidth and the latency.
Observe the following procedure for setting up the ADC and initiating continuous conver-
sion:
1. Enable the appropriate analog input by configuring the general-purpose I/O pins for
alternate function. This disables the digital input and output driver.
2. Write to the ADC Control Register to configure the ADC for continuous conversion.
The bit fields in the ADC Control Register may be written simultaneously:
Write to the ANAIN[3:0] field to select one of the 12 analog input sources
Set CONT to 1 to select continuous conversion
Write to the VREF bit to enable or disable the internal voltage reference generator
Set CEN to 1 to start the conversions
3. When the first conversion in continuous operation is complete (after 5129 system
clock cycles, plus the 40 cycles required to power up, if necessary), the ADC control
logic performs the following operations:
CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all
subsequent conversions in continuous operation
An interrupt request is sent to the Interrupt Controller to indicate the conversion is
complete
165
Bit 7 6 5 4 3 2 1 0
Field CEN Reserved VREF CONT ANAIN[3:0]
RESET 0 1 0
R/W R/W
Address F70h
Bit Description
[7] Conversion Enable
CEN 0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
this bit to 0 when a conversion has been completed.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already in
progress, the conversion restarts. This bit remains 1 until the conversion is complete.
[6] Reserved
This bit is reserved and must be programmed to 0.
[5] Voltage Reference
VREF 0 = Internal voltage reference generator enabled. The VREF pin should be left unconnected
(or capacitively coupled to analog ground) if the internal voltage reference is selected as
the ADC reference voltage.
1 = Internal voltage reference generator disabled. An external voltage reference must be
provided through the VREF pin.
166
167
Bit 7 6 5 4 3 2 1 0
Field ADCD_H
RESET X
R/W R
Address F72h
Bit Description
[7:0] ADC Data High Byte
ADCD_H This byte contains the upper eight bits of the 10-bit ADC output. These bits are not valid during
a single-shot conversion. During a continuous conversion, the last conversion output is held in
this register. These bits are undefined after a Reset.
168
Bit 7 6 5 4 3 2 1 0
Field ADCD_L Reserved
RESET X
R/W R
Address F73h
Bit Description
[7:6] ADC Data Low Bits
ADCD_L These are the least significant two bits of the 10-bit ADC output. These bits are undefined after
a Reset.
[5:0] Reserved
These bits are reserved and are always undefined.
169
Flash Memory
The products in the Z8 Encore! XP F64xx Series feature up to 64 KB (65,536 bytes) of
non-volatile Flash memory with read/write/erase capability. The Flash memory can be
programmed and erased in-circuit by either user code or through the On-Chip Debugger.
The Flash memory array is arranged in 512 byte per page. The 512 byte page is the mini-
mum Flash block size that can be erased. The Flash memory is also divided into 8 sectors
which can be protected from programming and erase operations on a per sector basis.
Table 90 describes the Flash memory configuration for each device in the Z8 Encore! XP
F64xx Series. Table 91 lists the sector address ranges. Figure 35 displays the Flash mem-
ory arrangement.
170
64KB Flash
Program Memory
Addresses
FFFFh
FE00h
FDFFh
FC00h
FBFFh
FA00h
128 Pages
512 Bytes per Page
05FFh
0400h
03FFh
0200h
01FFh
0000h
Information Area
Table 92 describes the Z8 Encore! XP F64xx Series Information Area. This 512-byte
Information Area is accessed by setting bit 7 of the Page Select Register to 1. When access
is enabled, the Information Area is mapped into Flash memory and overlays the 512 bytes
at addresses FE00h to FFFFh. When the Information Area access is enabled, LDC instruc-
tions return data from the Information Area. CPU instruction fetches always comes from
Flash memory regardless of the Information Area access bit. Access to the Information
Area is read-only.
171
Flash Memory
Address (Hex) Function
FE00hFE3Fh Reserved
FE40hFE53h Part Number
20-character ASCII alphanumeric code
Left-justified and filled with zeros
FE54hFFFFh Reserved
Operation
The Flash Controller provides the proper signals and timing for the Byte Programming,
Page Erase, and Mass Erase operations within Flash memory. The Flash Controller con-
tains a protection mechanism, via the Flash Control Register (FCTL), to prevent acciden-
tal programming or erasure. The following subsections provide details about the Lock,
Unlock, Sector Protect, Byte Programming, Page Erase and Mass Erase operations.
Caution: Flash programming and erasure are not supported for system clock frequencies below
20 kHz, above 20 MHz, or outside of the devices operating frequency range. The Flash
Frequency High and Low Byte registers must be loaded with the correct value to ensure
proper Flash programming and erase operations.
172
173
Observe the following procedure to setup the Flash Sector Protect Register from user
code:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
2. Write 5Eh to the Flash Control Register to select the Flash Sector Protect Register.
3. Read and/or write the Flash Sector Protect Register which is now at register file
address FF9h.
4. Write 00h to the Flash Control Register to return the Flash Controller to its reset state.
Byte Programming
When the Flash Controller is unlocked, writes to Flash memory from user code will pro-
gram a byte into the Flash if the address is located in the unlocked page. An erased Flash
byte contains all ones (FFh). The programming operation can only be used to change bits
from one to zero. To change a Flash bit (or multiple bits) from zero to one requires a Page
Erase or Mass Erase operation.
Byte programming can be accomplished using the eZ8 CPUs LDC or LDCI instructions.
For a description of the LDC and LDCI instructions, refer to the eZ8 CPU Core User Man-
ual (UM0128), which is available for download on www.zilog.com.
While the Flash Controller programs Flash memory, the eZ8 CPU idles but the system
clock and on-chip peripherals continue to operate. Interrupts that occur when a program-
ming operation is in progress are serviced after the programming operation is complete. To
exit programming mode and lock the Flash Controller, write 00h to the Flash Control
Register.
User code cannot program Flash memory on a page that resides in a protected sector.
When user code writes memory locations, only addresses located in the unlocked page are
programmed. Memory writes outside of the unlocked page are ignored.
Caution: Each memory location must not be programmed more than twice before an erase occurs.
Observe the following procedure to program the Flash from user code:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
2. Write the page of memory to be programmed to the Page Select Register.
3. Write the first unlock command 73h to the Flash Control Register.
174
4. Write the second unlock command 8Ch to the Flash Control Register.
5. Rewrite the page written in Step 2 to the Page Select Register.
6. Write Flash memory using LDC or LDCI instructions to program the Flash.
7. Repeat Step 6 to program additional memory locations on the same page.
8. Write 00h to the Flash Control Register to lock the Flash Controller.
Page Erase
Flash memory can be erased one page (512 bytes) at a time. Page-erasing Flash memory
sets all bytes in a page to the value FFh. The Page Select Register identifies the page to be
erased. While the Flash Controller executes the Page Erase operation, the eZ8 CPU idles;
however, the system clock and on-chip peripherals continue to operate. The eZ8 CPU
resumes operation after the Page Erase operation completes. Interrupts that occur when
the Page Erase operation is in progress are serviced after the Page Erase operation is com-
plete. When the Page Erase operation is complete, the Flash Controller returns to its
locked state. Only pages located in unprotected sectors can be erased.
Observe the following procedure to perform a Page Erase operation:
1. Write 00h to the Flash Control Register to reset the Flash Controller.
2. Write the page to be erased to the Page Select Register.
3. Write the first unlock command 73h to the Flash Control Register.
4. Write the second unlock command 8Ch to the Flash Control Register.
5. Rewrite the page written in Step 2 to the Page Select Register.
6. Write the Page Erase command 95h to the Flash Control Register.
Mass Erase
The Flash memory cannot be mass-erased by user code.
175
For more information about bypassing the Flash Controller, refer to the Third Party Flash
Programming Support for Z8 Encore! MCUs Application Note (AN0117), which is avail-
able for download at www.zilog.com.
Caution: For security reasons, the Flash Controller allows only a single page to be opened for
write/erase operations. When writing multiple Flash pages, the Flash Controller must go
through the unlock sequence again to select another page.
176
The write-only Flash Control Register shares its register file address with the read-only
Flash Status Register.
Bit 7 6 5 4 3 2 1 0
Field FCMD
RESET 0
R/W W
Address FF8h
Bit Description
[7:0] Flash Command*
FCMD 73h = First unlock command.
8Ch = Second unlock command.
95h = Page erase command.
63h = Mass erase command
5Eh = Flash Sector Protect Register select.
Note: *All other commands, or any command out of sequence, lock the Flash Controller.
177
Bit 7 6 5 4 3 2 1 0
Field Reserved FSTAT
RESET 0
R/W R
Address FF8h
Bit Description
[7:6] Reserved
These bits are reserved and must be programmed to 00.
[5:0] Flash Controller Status
FSTAT 00_0000 = Flash Controller locked.
00_0001 = First unlock command received.
00_0010 = Second unlock command received.
00_0011 = Flash Controller unlocked.
00_0100 = Flash Sector Protect Register selected.
00_1xxx = Program operation in progress.
01_0xxx = Page erase operation in progress.
10_0xxx = Mass erase operation in progress.
178
Bit 7 6 5 4 3 2 1 0
Field INFO_EN PAGE
RESET 0
R/W R/W
Address FF9h
Bit Description
[7] Information Area Enable
INFO_EN 0 = Information Area is not selected.
1 = Information Area is selected. The Information area is mapped into the Flash memory
address space at addresses FE00h through FFFFh.
[6:0] Page Select
PAGE This 7-bit field selects the Flash memory page for programming and Page Erase operations.
Flash Memory Address[15:9] = PAGE[6:0].
Bit 7 6 5 4 3 2 1 0
Field SECT7 SECT6 SECT5 SECT4 SECT3 SECT2 SECT1 SECT0
RESET 0
R/W R/W*
Address FF9h
Note: *R/W = This register is accessible for read operations; it can be written to 1 only via user code.
Bit Description
[7:0] Sector Protect**
SECTn 0 = Sector n can be programmed or erased from user code.
1 = Sector n is protected and cannot be programmed or erased from user code.
Note: **User code can only write bits from 0 to 1.
179
Caution: Flash programming and erasure is not supported for system clock frequencies below
20 kHz, above 20 MHz, or outside of the valid operating frequency range for the device.
The Flash Frequency High and Low Byte registers must be loaded with the correct value
to ensure proper program and erase times.
Bit 7 6 5 4 3 2 1 0
Field FFREQH
RESET 0
R/W R/W
Address FFAh
Bit 7 6 5 4 3 2 1 0
Field FFREQL
RESET 0
R/W R/W
Address FFBh
Bit Description
[7:0] Flash Frequency High and Low Bytes
FFREQH, These 2 bytes, {FFREQH[7:0], FFREQL[7:0]}, contain the 16-bit Flash Frequency value.
FFREQL
180
Option Bits
Option bits allow user configuration of certain aspects of the Z8 Encore! XP F64xx Series
operation. The feature configuration data is stored in the Flash memory and read during
Reset. The features available for control via the option bits are:
Watchdog Timer time-out response selectioninterrupt or Reset
Watchdog Timer enabled at Reset
The ability to prevent unwanted read access to user code in Flash memory
The ability to prevent accidental programming and erasure of the user code in Flash
memory
Voltage Brown-Out configuration is always enabled or disabled during Stop Mode to
reduce Stop Mode power consumption
Oscillator mode selection for high-, medium-, and low-power crystal oscillators or an
external RC oscillator
Operation
This section describes the type and configuration of the programmable Flash option bits.
181
Bit 7 6 5 4 3 2 1 0
Field WDT_RES WDT_AO OSC_SEL[1:0] VBO_AO RP Reserved FWP
RESET U
R/W R/W
Address Program Memory 0000h
Note: U = Unchanged by Reset; R/W = Read/Write.
Bit Description
[7] Watchdog Timer Reset
WDT_RES 0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watchdog Timer time-out causes a Short Reset. This setting is the default for unpro-
grammed (erased) Flash.
[6] Watchdog Timer Always On
WDT_AO 0 = Watchdog Timer is automatically enabled upon application of system power. Watch-
dog Timer can not be disabled except during Stop Mode (if configured to power down
during Stop Mode).
1 = Watchdog Timer is enabled upon execution of the WDT instruction. Once enabled,
the Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery. This
setting is the default for unprogrammed (erased) Flash.
[5:4] Oscillator Mode Selection
OSC_SEL[1:0] 00 = On-chip oscillator configured for use with external RC networks (< 4 MHz).
01 = Minimum power for use with very low frequency crystals (32 kHz to 1.0 MHz).
10 = Medium power for use with medium frequency crystals or ceramic resonators
(0.5 MHz to 10.0 MHz).
11 = Maximum power for use with high frequency crystals (8.0 MHz to 20.0 MHz). This
setting is the default for unprogrammed (erased) Flash.
[3] Voltage Brown-Out Protection Always On
VBO_AO 0 = Voltage Brown-Out Protection is disabled in Stop Mode to reduce total power con-
sumption.
1 = Voltage Brown-Out Protection is always enabled including during Stop Mode. This
setting is the default for unprogrammed (erased) Flash.
[2] Read Protect
RP 0 = User program code is inaccessible. Limited control features are available through the
On-Chip Debugger.
1 = User program code is accessible. All On-Chip Debugger commands are enabled.
This setting is the default for unprogrammed (erased) Flash.
182
Bit 7 6 5 4 3 2 1 0
Field Reserved
RESET U
R/W R/W
Address Program Memory 0001h
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit Description
[7:0] Reserved
These option bits are reserved for future use and must always be 1. This setting is the default
for unprogrammed (erased) Flash.
183
On-Chip Debugger
The Z8 Encore! XP F64xx Series products contain an integrated On-Chip Debugger
(OCD) that provides advanced debugging features including:
Reading and writing of the register file
Reading and writing of Program and Data memory
Setting of breakpoints
Execution of eZ8 CPU instructions
Architecture
The On-Chip Debugger consists of four primary functional blocks: transmitter, receiver,
autobaud generator, and debug controller. Figure 36 displays the architecture of the On-
Chip Debugger.
Transmitter
Debug Controller
DBG
Pin Receiver
184
Operation
The following section describes the operation of the OCD.
OCD Interface
The On-Chip Debugger uses the DBG pin for communication with an external host. This
one-pin interface is a bidirectional open-drain interface that transmits and receives data.
Data transmission is half-duplex, meaning that transmit and receive operations cannot
occur simultaneously. The serial data on the DBG pin is sent using the standard asynchro-
nous data format defined in RS-232. This pin can interface the Z8 Encore! XP F64xx
Series products to the serial port of a host PC using minimal external hardware.Two differ-
ent methods for connecting the DBG pin to an RS-232 interface are depicted in Figures 37
and 38.
Caution: For proper operation of the On-Chip Debugger, all power pins (VDD and AVDD) must be
supplied with power, and all ground pins (VSS and AVSS) must be properly grounded.
The DBG pin is open-drain and must always be connected to VDD through an external
pull-up resistor to ensure proper operation.
VDD
RS-232
Transceiver 10k
Diode
RS-232 TX DBG Pin
RS-232 RX
Figure 37. Interfacing the On-Chip Debuggers DBG Pin with an RS-232 Interface, #1 of 2
185
VDD
RS-232
Transceiver 10k
Open-Drain
Buffer
RS-232 TX DBG Pin
RS-232 RX
Figure 38. Interfacing the On-Chip Debuggers DBG Pin with an RS-232 Interface, #2 of 2
Debug Mode
The operating characteristics of the Z8 Encore! XP F64xx Series devices in Debug Mode
are:
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex-
ecute specific instructions
The system clock operates unless in Stop Mode
All enabled on-chip peripherals operate unless in Stop Mode
Automatically exits Halt Mode
Constantly refreshes the Watchdog Timer, if enabled
186
START D0 D1 D2 D3 D4 D5 D6 D7 STOP
Recommended
System Clock Maximum Baud Rate Minimum Baud Rate
Frequency (MHz) (kbits/s) (kbits/s)
20.0 2500 39.1
1.0 125.0 1.96
0.032768 (32 kHz) 4.096 0.064
187
If the OCD receives a serial break (nine or more continuous bits Low) the Autobaud
Detector/Generator resets. The Autobaud Detector/Generator can then be reconfigured by
sending 80h.
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a serial break 4096 system clock cycles long back to the host, and resets the
Autobaud Detector/Generator. A framing error or transmit collision may be caused by the
host sending a serial break to the OCD. Because of the open-drain nature of the interface,
returning a serial break back to the host only extends the length of the serial break if the
host releases the serial break early.
The host transmits a serial break on the DBG pin when first connecting to the Z8 Encore!
XP F64xx Series devices or when recovering from an error. A serial break from the host
resets the Autobaud Generator/Detector but does not reset the OCD Control Register. A
serial break leaves the device in Debug Mode if that is the current mode. The OCD is held
in Reset until the end of the serial break when the DBG pin returns High. Because of the
open-drain nature of the DBG pin, the host can send a serial break to the OCD even if the
OCD is transmitting a character.
Breakpoints
Execution breakpoints are generated using the BRK instruction (op code 00h). When the
eZ8 CPU decodes a BRK instruction, it signals the On-Chip Debugger. If breakpoints are
enabled, the OCD idles the eZ8 CPU and enters Debug Mode. If breakpoints are not
enabled, the OCD ignores the BRK signal and the BRK instruction operates as an NOP.
If breakpoints are enabled, the OCD can be configured to automatically enter Debug
Mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU is still enabled to service DMA and interrupt requests.
The loop on BRK instruction can be used to service interrupts in the background. For
interrupts to be serviced in the background, there cannot be any breakpoints in the inter-
rupt service routine. Otherwise, the CPU stops on the breakpoint in the interrupt routine.
For interrupts to be serviced in the background, interrupts must also be enabled. Debug-
ging software should not automatically enable interrupts when using this feature, since
188
interrupts are typically disabled during critical sections of code where interrupts should
not occur (such as adjusting the stack pointer or modifying shared data).
Software can poll the IDLE bit of the OCDSTAT Register to determine if the OCD is loop-
ing on a BRK instruction. When software stops the CPU on the BRK instruction that it is
looping on, it should not set the DBGMODE bit of the OCDCTL Register. The CPU may
have vectored to and be in the middle of an interrupt service routine when this bit gets set.
Instead, software must clear the BRKLP bit. This action allows the CPU to finish the inter-
rupt service routine it may be in and return the BRK instruction. When the CPU returns to
the BRK instruction it was previously looping on, it automatically sets the DBGMODE bit
and enters Debug Mode.
Software detects that the majority of the OCD commands are still disabled when the eZ8
CPU is looping on a BRK instruction. The eZ8 CPU must be stopped and the part must be
in Debug Mode before these commands can be issued.
189
Enabled when
Command NOT in Debug
Debug Command Byte Mode? Disabled by Read Protect Option Bit
Read OCD Revision 00h Yes
Read OCD Status 02h Yes
Register
Read Runtime Counter 03h
Write OCD Control 04h Yes Cannot clear DBGMODE bit
Register
Read OCD Control 05h Yes
Register
Write Program Counter 06h Disabled
Read Program Counter 07h Disabled
Write Register 08h Only writes of the Flash memory control
registers are allowed. Additionally, only the
Mass Erase command is allowed to be
written to the Flash Control Register.
Read Register 09h Disabled
Write Program Memory 0Ah Disabled
Read Program Memory 0Bh Disabled
Write Data Memory 0Ch Disabled
Read Data Memory 0Dh Disabled
Read Program Memory 0Eh
CRC
Reserved 0Fh
Step Instruction 10h Disabled
Stuff Instruction 11h Disabled
Execute Instruction 12h Disabled
Reserved 13hFFh
In the following list of OCD commands, data and commands sent from the host to the On-
Chip Debugger are identified by DBG Command/Data. Data sent from the On-Chip
Debugger back to the host is identified by DBG Data.
Read OCD Revision (00h). The Read OCD Revision command determines the version of
the On-Chip Debugger. If OCD commands are added, removed, or changed, this revision
number changes.
190
DBG 00h
DBG OCDREV[15:8] (Major revision number)
DBG OCDREV[7:0] (Minor revision number)
Read OCD Status Register (02h). The Read OCD Status Register command reads the
OCDSTAT Register.
DBG 02h
DBG OCDSTAT[7:0]
Write OCD Control Register (04h). The Write OCD Control Register command writes
the data that follows to the OCDCTL Register. When the Read Protect option bit is
enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared to 0
and the only method of putting the device back into normal operating mode is to reset the
device.
DBG 04h
DBG OCDCTL[7:0]
Read OCD Control Register (05h). The Read OCD Control Register command reads the
value of the OCDCTL Register.
DBG 05h
DBG OCDCTL[7:0]
Write Program Counter (06h). The Write Program Counter command writes the data that
follows to the eZ8 CPUs program counter (PC). If the device is not in Debug Mode or if
the Read Protect option bit is enabled, the PC values are discarded.
DBG 06h
DBG ProgramCounter[15:8]
DBG ProgramCounter[7:0]
Read Program Counter (07h). The Read Program Counter command reads the value in
the eZ8 CPUs program counter (PC). If the device is not in Debug Mode or if the Read
Protect option bit is enabled, this command returns FFFFh.
DBG 07h
DBG ProgramCounter[15:8]
DBG ProgramCounter[7:0]
Write Register (08h). The Write Register command writes data to the register file. Data
can be written 1-256 bytes at a time (256 bytes can be written by setting size to zero). If
the device is not in Debug Mode, the address and data values are discarded. If the Read
Protect option bit is enabled, then only writes to the Flash Control Registers are allowed
and all other register write data values are discarded.
DBG 08h
DBG {4h0,Register Address[11:8]}
DBG Register Address[7:0]
DBG Size[7:0]
DBG 1-256 data bytes
191
Read Register (09h). The Read Register command reads data from the register file. Data
can be read 1-256 bytes at a time (256 bytes can be read by setting size to zero). If the
device is not in Debug Mode or if the Read Protect option bit is enabled, this command
returns FFh for all the data values.
DBG 09h
DBG {4h0,Register Address[11:8]
DBG Register Address[7:0]
DBG Size[7:0]
DBG 1-256 data bytes
Write Program Memory (0Ah). The Write Program Memory command writes data to
program memory. This command is equivalent to the LDC and LDCI instructions. Data
can be written 1-65536 bytes at a time (65536 bytes can be written by setting size to zero).
The on-chip Flash Controller must be written to and unlocked for the programming opera-
tion to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is
not in Debug Mode or if the Read Protect option bit is enabled, the data is discarded.
DBG 0Ah
DBG Program Memory Address[15:8]
DBG Program Memory Address[7:0]
DBG Size[15:8]
DBG Size[7:0]
DBG 1-65536 data bytes
Read Program Memory (0Bh). The Read Program Memory command reads data from
program memory. This command is equivalent to the LDC and LDCI instructions. Data
can be read 1-65536 bytes at a time (65536 bytes can be read by setting size to zero). If the
device is not in Debug Mode or if the Read Protect option bit is enabled, this command
returns FFh for the data.
DBG 0Bh
DBG Program Memory Address[15:8]
DBG Program Memory Address[7:0]
DBG Size[15:8]
DBG Size[7:0]
DBG 1-65536 data bytes
Write Data Memory (0Ch). The Write Data Memory command writes data to Data Mem-
ory. This command is equivalent to the LDE and LDEI instructions. Data can be written 1-
65536 bytes at a time (65536 bytes can be written by setting size to zero). If the device is
not in Debug Mode or if the Read Protect option bit is enabled, the data is discarded.
DBG 0Ch
DBG Data Memory Address[15:8]
DBG Data Memory Address[7:0]
DBG Size[15:8]
DBG Size[7:0]
DBG 1-65536 data bytes
Read Data Memory (0Dh). The Read Data Memory command reads from Data Memory.
This command is equivalent to the LDE and LDEI instructions. Data can be read 1-65536
192
bytes at a time (65536 bytes can be read by setting size to zero). If the device is not in
Debug Mode, this command returns FFh for the data.
DBG 0Dh
DBG Data Memory Address[15:8]
DBG Data Memory Address[7:0]
DBG Size[15:8]
DBG Size[7:0]
DBG 1-65536 data bytes
Read Program Memory CRC (0Eh). The Read Program Memory CRC command com-
putes and returns the CRC (cyclic redundancy check) of program memory using the 16-bit
CRC-CCITT polynomial. If the device is not in Debug Mode, this command returns
FFFFh for the CRC value. Unlike most other OCD Read commands, there is a delay from
issuing of the command until the OCD returns the data. The OCD reads program memory,
calculates the CRC value, and returns the result. The delay is a function of the program
memory size and is approximately equal to the system clock period multiplied by the num-
ber of bytes in program memory.
DBG 0Eh
DBG CRC[15:8]
DBG CRC[7:0]
Step Instruction (10h). The Step Instruction command steps one assembly instruction at
the current program counter (PC) location. If the device is not in Debug Mode or the Read
Protect option bit is enabled, the OCD ignores this command.
DBG 10h
Stuff Instruction (11h). The Stuff Instruction command steps one assembly instruction
and allows specification of the first byte of the instruction. The remaining 0-4 bytes of the
instruction are read from program memory. This command is useful for stepping over
instructions where the first byte of the instruction has been overwritten by a breakpoint. If
the device is not in Debug Mode or the Read Protect option bit is enabled, the OCD
ignores this command.
DBG 11h
DBG opcode[7:0]
Execute Instruction (12h). The Execute Instruction command allows sending an entire
instruction to be executed to the eZ8 CPU. This command can also step over breakpoints.
The number of bytes to send for the instruction depends on the op code. If the device is not
in Debug Mode or the Read Protect option bit is enabled, the OCD ignores this command
DBG 12h
DBG 1-5 byte opcode
193
Bit 7 6 5 4 3 2 1 0
Field DBGMODE BRKEN DBGACK BRKLOOP Reserved RST
RESET 0
R/W R/W R R/W
Bit Description
[7] Debug Mode
DBGMODE Setting this bit to 1 causes the device to enter Debug Mode. When in Debug Mode, the eZ8
CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to start running
again. This bit is automatically set when a BRK instruction is decoded and breakpoints are
enabled. If the Read Protect option bit is enabled, this bit can only be cleared by resetting
the device, it cannot be written to 0.
0 = TheZ8 Encore! XP F64xx Series device is operating in Normal Mode.
1 = The Z8 Encore! XP F64xx Series device is in Debug Mode.
[6] Breakpoint Enable
BRKEN This bit controls the behavior of the BRK instruction (op code 00h). By default, breakpoints
are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1 and a BRK
instruction is decoded, the OCD takes action dependent upon the BRKLOOP bit.
0 = BRK instruction is disabled.
1 = BRK instruction is enabled.
[5] Debug Acknowledge
DBGACK This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
an Debug Acknowledge character (FFh) to the host when a breakpoint occurs.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
194
Bit 7 6 5 4 3 2 1 0
Field IDLE HALT RPEN Reserved
RESET 0
R/W R
Bit Description
[7] CPU Idle
IDLE This bit is set if the part is in Debug Mode (DBGMODE is 1), or if a BRK instruction occurred
since the last time OCDCTL was written. This can be used to determine if the CPU is running
or if it is idling.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
[6] Halt Mode
HALT 0 = The device is not in Halt Mode.
1 = The device is in Halt Mode.
195
196
On-Chip Oscillator
The products in the Z8 Encore! XP F64xx Series feature an on-chip oscillator for use with
external crystals with frequencies from 32 kHz to 20 MHz. In addition, the oscillator can
support external RC networks with oscillation frequencies up to 4 MHz or ceramic resona-
tors with oscillation frequencies up to 20 MHz. This oscillator generates the primary sys-
tem clock for the internal eZ8 CPU and the majority of the on-chip peripherals.
Alternatively, the XIN input pin can also accept a CMOS-level clock input signal
(32 kHz20 MHz). If an external clock generator is used, the XOUT pin must be left uncon-
nected.
When configured for use with crystal oscillators or external clock drivers, the frequency of
the signal on the XIN input pin determines the frequency of the system clock (that is, no
internal clock divider). In RC operation, the system clock is driven by a clock divider
(divide by 2) to ensure 50% duty cycle.
Operating Modes
The Z8 Encore! XP F64xx Series products support four different oscillator modes:
On-chip oscillator configured for use with external RC networks (< 4 MHz)
Minimum power for use with very low frequency crystals (32 kHz to 1.0 MHz)
Medium power for use with medium frequency crystals or ceramic resonators (0.5 MHz
to 10.0 MHz)
Maximum power for use with high frequency crystals or ceramic resonators (8.0 MHz
to 20.0 MHz)
The oscillator mode is selected through user-programmable option bits. For more informa-
tion, see the Option Bits chapter on page 180.
197
On-Chip Oscillator
XIN XOUT
R1 = 220
Crystal
C1 = 22pF C2 = 22pF
198
VDD
XIN
6
1 10
Oscillator Frequency (kHz) = ---------------------------------------------------------
0.4 R C + 4 C
Figure 42 displays the typical (3.3 V and 25C) oscillator frequency as a function of the
capacitor (C in pF) employed in the RC network assuming a 45 k external resistor. For
very small values of C, the parasitic capacitance of the oscillator XIN pin and the printed
circuit board should be included in the estimation of the oscillator frequency.
It is possible to operate the RC oscillator using only the parasitic capacitance of the pack-
age and printed circuit board. To minimize sensitivity to external parasitics, external
capacitance values in excess of 20 pF are recommended.
199
4000
3750
3500
3250
3000
2750
2500
Frequency (kHz)
2250
2000
1750
1500
1250
1000
750
500
250
0
0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 460 480 500
C (pF)
Caution: When using the external RC oscillator mode, the oscillator may stop oscillating if the
power supply drops below 2.7 V, but before the power supply drops to the voltage brown-
out threshold. The oscillator will resume oscillation as soon as the supply voltage exceeds
2.7 V.
200
Electrical Characteristics
The data in this chapter represents all known data prior to qualification and characteriza-
tion of the Z8 Encore! XP F64xx Series of products, and is therefore subject to change.
Additional electrical characteristics may be found in the individual chapters of this docu-
ment.
201
202
DC Characteristics
Table 107 lists the DC characteristics of the Z8 Encore! XP F64xx Series products. All
voltages are referenced to VSS, the primary system ground.
TA = 40C to 125C
Symbol Parameter Minimum Typical Maximum Units Conditions
VDD Supply Voltage 3.0 3.6 V
VIL1 Low Level Input 0.3 0.3*VDD V For all input pins except
Voltage RESET, DBG, XIN
VIL2 Low Level Input 0.3 0.2*VDD V For RESET, DBG, and
Voltage XIN.
VIH1 High Level Input 0.7*VDD 5.5 V Port A, C, D, E, F, and G
Voltage pins.
VIH2 High Level Input 0.7*VDD VDD+0.3 V Port B and H pins.
Voltage
VIH3 High Level Input 0.8*VDD VDD+0.3 V RESET, DBG, and XIN
Voltage pins
VOL1 Low Level Output 0.4 V IOL = 2 mA; VDD = 3.0 V
Voltage Standard Drive High Output Drive dis-
abled.
VOH1 High Level Output 2.4 V IOH = 2 mA; VDD = 3.0 V
Voltage Standard Drive High Output Drive dis-
abled.
VOL2 Low Level Output 0.6 V IOL = 20 mA; VDD = 3.3 V
Voltage High Drive High Output Drive
enabled
TA = 40C to +70C
VOH2 High Level Output 2.4 V IOH = 20 mA; VDD = 3.3 V
Voltage High Output Drive
High Drive enabled;
TA = 40C to +70C
VOL3 Low Level Output 0.6 V IOL = 15 mA; VDD = 3.3 V
Voltage High Output Drive
High Drive enabled;
TA = +70C to +105C
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
203
TA = 40C to 125C
Symbol Parameter Minimum Typical Maximum Units Conditions
VOH3 High Level Output 2.4 V IOH = 15 mA; VDD = 3.3 V
Voltage High Output Drive
High Drive enabled;
TA = +70C to +105C
VRAM RAM Data Retention 0.7 V
IIL Input Leakage Current 5 +5 A VDD = 3.6 V;
VIN = VDD or VSS1
ITL Tri-State Leakage 5 +5 A VDD = 3.6 V
Current
CPAD GPIO Port Pad 8.02 pF
Capacitance
CXIN XIN Pad Capacitance 8.02 pF
CXOUT XOUT Pad Capacitance 9.52 pF
IPU Weak Pull-up Current 30 100 350 A VDD = 3.03.6 V
IDDA Active Mode Supply 11 16 mA VDD = 3.6 V, FSYSCLK =
Current; GPIO pins are 20 MHz
configured as outputs 12 mA VDD = 3.3 V
(see Figure 43 on page
205 and Figure 44 on 9 11 mA VDD = 3.6 V, FSYSCLK =
page 206) 10 MHz
9 mA VDD = 3.3 V
IDDH Halt Mode Supply 4 7 mA VDD = 3.6 V, FSYSCLK =
Current; GPIO pins 20 MHz
configured as outputs 5 mA VDD = 3.3 V
(see Figure 45 on page
207 and Figure 46 on 3 5 mA VDD = 3.6 V, FSYSCLK =
page 208) 10 MHz
4 mA VDD = 3.3 V
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
204
TA = 40C to 125C
Symbol Parameter Minimum Typical Maximum Units Conditions
IDDS Stop Mode Supply 520 A VBO and WDT enabled
Current; GPIO pins 700 VDD = 3.6 V
configured as outputs
(see Figure 47 on page 650 VDD = 3.3 V
209 and Figure 48 on 10 A VBO disabled,
page 210) WDT enabled,
TA = 0 to 70C
25 VDD = 3.6 V
20 VDD = 3.3 V
A VBO disabled,
WDT enabled,
TA = 40 to +105C
80 VDD = 3.6 V
70 VDD = 3.3 V
A VBO disabled,
WDT enabled,
TA = 40 to +125C
250 VDD = 3.6 V
150 VDD = 3.3 V
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
205
Figure 43 displays the typical active mode current consumption while operating at 25 C
plotted opposite the system clock frequency. All GPIO pins are configured as outputs and
driven High.
15
12
Idd (mA)
0
0 5 10 15 20
System Clock Frequency (MHz)
Figure 43. Typical Active Mode IDD vs. System Clock Frequency
206
Figure 44 displays the maximum active mode current consumption across the full operat-
ing temperature range of the device and plotted opposite the system clock frequency. All
GPIO pins are configured as outputs and driven High.
15
12
9
Idd (mA)
0
0 5 10 15 20
System Clock Frequency (MHz)
Figure 44. Maximum Active Mode IDD vs. System Clock Frequency
207
Figure 45 displays the typical current consumption in Halt Mode while operating at 25C
plotted opposite the system clock frequency. All GPIO pins are configured as outputs and
driven High.
4
HALT Idd (mA)
0
0 5 10 15 20
System Clock Frequency (MHz)
Figure 45. Typical Halt Mode IDD vs. System Clock Frequency
208
Figure 46 displays the maximum Halt Mode current consumption across the full operating
temperature range of the device and plotted opposite the system clock frequency. All
GPIO pins are configured as outputs and driven High.
5
Halt Idd (mA)
0
0 5 10 15 20
System Clock Frequency (MHz)
Figure 46. Maximum Halt Mode ICC vs. System Clock Frequency
209
Figure 47 displays the maximum current consumption in Stop Mode with the VBO and
Watchdog Timer enabled plotted opposite the power supply voltage. All GPIO pins are
configured as outputs and driven High.
700
STOP Idd (microamperes)
650
600
550
500
450
400
3.0 3.2 3.4 3.6
Vdd (V)
Figure 47. Maximum Stop Mode IDD with VBO Enabled vs. Power Supply Voltage
210
Figure 48 displays the maximum current consumption in Stop Mode with the VBO dis-
abled and Watchdog Timer enabled plotted opposite the power supply voltage. All GPIO
pins are configured as outputs and driven High. Disabling the Watchdog Timer and its
internal RC oscillator in Stop Mode will provide some additional reduction in Stop Mode
current consumption. This small current reduction would be indistinguishable on the scale
shown in the figure.
120.00
100.00
STOP Idd (microamperes)
80.00
60.00
40.00
20.00
0.00
3.0 3.2 3.4 3.6
Vdd (V)
25C Typical 0/70C -40/105C -40/+125C
Figure 48. Maximum Stop Mode IDD with VBO Disabled vs. Power Supply Voltage
211
Table 108. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing
TA = 40C to 125C
Symbol Parameter Minimum Typical* Maximum Units Conditions
VPOR Power-On Reset 2.40 2.70 2.90 V VDD = VPOR
Voltage Threshold
VVBO Voltage Brown-Out 2.30 2.60 2.85 V VDD = VVBO
Reset Voltage
Threshold
VPOR to VVBO 50 100 mV
hysteresis
Starting VDD voltage to VSS V
ensure valid Power-On
Reset.
TANA Power-On Reset 50 s VDD > VPOR; TPOR Digital
Analog Delay Reset delay follows TANA
TPOR Power-On Reset Digital 6.6 ms 66 WDT Oscillator cycles
Delay (10 kHz) + 16 System
Clock cycles (20 MHz)
TVBO Voltage Brown-Out 10 s VDD < VVBO to generate a
Pulse Rejection Period Reset.
TRAMP Time for VDD to 0.10 100 ms
transition from VSS to
VPOR to ensure valid
Reset
Note: *Data in the typical column is from characterization at 3.3 V and 0C. These values are provided for design guid-
ance only and are not tested in production.
212
TA = 40C to 125C
Symbol Parameter Minimum Typical* Maximum Units Conditions
VDD Operating Voltage 2.701 V
Range
REXT External Resistance 40 45 200 k VDD = VVBO
from XIN to VDD
CEXT External Capacitance 0 20 1000 pF
from XIN to VSS
FOSC External RC Oscillation 4 MHz
Frequency
Note: *When using the external RC oscillator mode, the oscillator may stop oscillating if the power supply drops below
2.7 V, but before the power supply drops to the voltage brown-out threshold. The oscillator will resume oscilla-
tion as soon as the supply voltage exceeds 2.7 V.
TA = 40C to 125C
Symbol Parameter Minimum Typical Maximum Units Conditions
TRESET RESET pin assertion to 4 TCLK Not in Stop Mode.
initiate a system reset. TCLK = System Clock
period.
TSMR Stop Mode Recovery 10 20 40 ns RESET, DBG, and GPIO
pin Pulse Rejection pins configured as SMR
Period sources.
213
Table 111 list the Flash memory electrical characteristics and timing.
VDD = 3.03.6 V
TA = 40C to 125C
Parameter Minimum Typical Maximum Units Notes
Flash Byte Read Time 50 ns
Flash Byte Program 20 40 s
Time
Flash Page Erase Time 10 ms
Flash Mass Erase Time 200 ms
Writes to Single 2
Address Before Next
Erase
Flash Row Program 8 ms Cumulative program time for single
Time row cannot exceed limit before next
erase. This parameter is only an
issue when bypassing the Flash
Controller.
Data Retention 100 years 25C
Endurance, 40C to 10,000 cycles Program/erase cycles
105C
Endurance, 106C to 1,000 cycles Program/erase cycles
125C
Table 112 lists the Watchdog Timer electrical characteristics and timing.
VDD = 3.03.6 V
TA = 40C to 125C
Symbol Parameter Minimum Typical Maximum Units Conditions
FWDT WDT Oscillator 5 10 20 kHz
Frequency
IWDT WDT Oscillator Current <1 5 A
including internal RC
Oscillator
214
Table 113 provides electrical characteristics and timing information for the Analog-to-
Digital Converter. Figure 49 displays the input frequency response of the ADC.
215
0.9
0.8
3 dB
0.7
Frequency Response
0.6
0.5
6 dB
0.4
0.3
0.2
0.1
0
0 5 10 15 20 25 30
Frequency (kHz)
216
AC Characteristics
This section provides AC characteristics and timing data which assumes a standard load of
50 pF on all outputs. Table 114 lists the Z8 Encore! XP F64xx Series AC characteristics
and timing.
217
TCLK
System
Clock
Port Value
Changes to 0
GPIO Pin
Input Value
GPIO Input
0 Latched
Data Latch
Into Port Input
Data Register
Delay (ns)
Parameter Abbreviation Min Max
TS_PORT Port Input Transition to XIN Fall Setup Time (not pictured) 5
TH_PORT XIN Fall to Port Input Transition Hold Time (not pictured) 6
TSMR GPIO Port Pin Pulse Width to Insure Stop Mode Recovery (for 1 s
GPIO Port pins enabled as SMR sources)
218
TCLK
XIN
T1 T2
Port Output
Delay (ns)
Parameter Abbreviation Minimum Maximum
GPIO port pins
T1 XIN Rise to Port Output Valid Delay 20
T2 XIN Rise to Port Output Hold Time 2
219
TCLK
XIN
T1 T2
T3 T4
Delay (ns)
Parameter Abbreviation Minimum Maximum
DBG
T1 XIN Rise to DBG Valid Delay 30
T2 XIN Rise to DBG Output Hold Time 2
T3 DBG to XIN Rise Input Setup Time 10
T4 DBG to XIN Rise Input Hold Time 5
DBG frequency System Clock/4
220
SCK
T1
T2 T3
Delay (ns)
Parameter Abbreviation Min Max
SPI Master
T1 SCK Rise to MOSI output Valid Delay 5 +5
T2 MISO input to SCK (receive edge) Setup Time 20
T3 MISO input to SCK (receive edge) Hold Time 0
221
SCK
T1
T2 T3
SS
(Input)
Delay (ns)
Parameter Abbreviation Minimum Maximum
SPI Slave
T1 SCK (transmit edge) to MISO output Valid Delay 2 * XIN period 3 * XIN period +
20 nsec
T2 MOSI input to SCK (receive edge) Setup Time 0
T3 MOSI input to SCK (receive edge) Hold Time 3 * XIN period
T4 SS input assertion to SCK setup 1 * XIN period
222
I2C Timing
Figure 55 and Table 120 provide timing information for I2C pins.
SCL
(Output)
T1
T3
T2
Delay (ns)
Parameter Abbreviation Minimum Maximum
I 2C
T1 SCL Fall to SDA output delay SCL period/4
T2 SDA Input to SCL rising edge Setup Time 0
T3 SDA Input to SCL falling edge Hold Time 0
223
UART Timing
Figure 56 and Table 121 provide timing information for UART pins for the case where the
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data Register
has been loaded with data prior to CTS assertion.
CTS
(Input)
T1
DE
(Output)
T2 T3
TxD Stop
Start Bit 0 Bit 1 Bit 7 Parity
(Output)
End of
Stop Bit(s)
Delay (ns)
Parameter Abbreviation Minimum Maximum
T1 CTS Fall to DE Assertion Delay 2 * XIN period 2 * XIN period +
1 bit period
T2 DE Assertion to TxD Falling Edge (Start) Delay 1 bit period 1 bit period +
1 * XIN period
T3 End of stop bit(s) to DE Deassertion Delay 1 * XIN period 2 * XIN period
224
Figure 57 and Table 122 provide timing information for UART pins for the case where the
Clear To Send input signal (CTS) is not used for flow control. In this example, it is
assumed that the Driver Enable polarity has been configured to be Active Low and is rep-
resented here by DE. DE asserts after the UART Transmit Data Register has been written.
DE remains asserted for multiple characters as long as the Transmit Data Register is writ-
ten with the next character before the current character has completed.
DE
(Output)
T1 T2
TxD Stop
Start Bit 0 Bit 1 Bit 7 Parity
(Output)
End of
Stop Bit(s)
Delay (ns)
Parameter Abbreviation Minimum Maximum
T1 DE Assertion to TxD Falling Edge (Start) Delay 1 bit period 1 bit period +
1 * XIN period
T2 End of stop bit(s) to DE Deassertion Delay 1 * XIN period 2 * XIN period
225
226
Example 2. In general, when an instruction format requires an 8-bit register address, that
address can specify any register location in the range 0255 or, using Escaped Mode
Addressing, a Working Register R0R15. If the contents of Register 43h and Working
Register R8 are added and the result is stored in 43h, the assembly syntax and resulting
object code result is shown in Table 124.
227
Refer to the device-specific Product Specification to determine the exact register file range
available. The register file size varies, depending on the device type.
228
Table 126 contains additional symbols that are used throughout the Instruction Summary
and Instruction Set Description sections.
Symbol Definition
dst Destination Operand
src Source Operand
@ Indirect Address Prefix
SP Stack Pointer
PC Program Counter
FLAGS Flags Register
RP Register Pointer
# Immediate Operand Prefix
B Binary Number Suffix
% Hexadecimal Number Prefix
H Hexadecimal Number Suffix
229
Condition Codes
The C, Z, S and V flags control the operation of the conditional jump (JP cc and JR cc)
instructions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit
field called the condition code (cc), which forms bits 7:4 of the conditional jump instruc-
tions. The condition codes are summarized in Table 127. Some binary condition codes can
be created using more than one assembly code mnemonic. The result of the flag test oper-
ation decides if the conditional jump is executed.
Assembly
Binary Hex Mnemonic Definition Flag Test Operation
0000 0 F Always False
0001 1 LT Less Than (S XOR V) = 1
0010 2 LE Less Than or Equal (Z OR (S XOR V)) = 1
0011 3 ULE Unsigned Less Than or Equal (C OR Z) = 1
0100 4 OV Overflow V=1
0101 5 Ml Minus S=1
0110 6 Z Zero Z=1
0110 6 EQ Equal Z=1
0111 7 C Carry C=1
0111 7 ULT Unsigned Less Than C=1
1000 8 T (or blank) Always True
1001 9 GE Greater Than or Equal (S XOR V) = 0
1010 A GT Greater Than (Z OR (S XOR V)) = 0
1011 B UGT Unsigned Greater Than (C = 0 AND Z = 0) = 1
1100 C NOV No Overflow V=0
1101 D PL Plus S=0
1110 E NZ Non-Zero Z=0
1110 E NE Not Equal Z=0
1111 F NC No Carry C=0
1111 F UGE Unsigned Greater Than or Equal C=0
230
Tables 128 through 135 contain the instructions belonging to each group and the number
of operands required for each instruction. Some instructions appear in more than one
table; these instructions can be considered to be a subset of more than one category.
Within these tables, the source operand is identified as src, the destination operand is dst
and a condition code is cc.
231
232
233
234
Address
Mode Flags
Assembly Opcode(s) Fetch Instr.
Mnemonic Symbolic Operation dst src (Hex) C Z S V D H Cycles Cycles
ADC dst, src dst dst + src + C r r 12 * * * * 0 * 2 3
r Ir 13 2 4
R R 14 3 3
R IR 15 3 4
R IM 16 3 3
IR IM 17 3 4
ADCX dst, src dst dst + src + C ER ER 18 * * * * 0 * 4 3
ER IM 19 4 3
Note: Flags Notation:
* = Value is a function of the result of the operation.
= Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
235
Address
Mode Flags
Assembly Opcode(s) Fetch Instr.
Mnemonic Symbolic Operation dst src (Hex) C Z S V D H Cycles Cycles
ADD dst, src dst dst + src r r 02 * * * * 0 * 2 3
r Ir 03 2 4
R R 04 3 3
R IR 05 3 4
R IM 06 3 3
IR IM 07 3 4
ADDX dst, src dst dst + src ER ER 08 * * * * 0 * 4 3
ER IM 09 4 3
AND dst, src dst dst AND src r r 52 * * 0 2 3
r Ir 53 2 4
R R 54 3 3
R IR 55 3 4
R IM 56 3 3
IR IM 57 3 4
ANDX dst, src dst dst AND src ER ER 58 * * 0 4 3
ER IM 59 4 3
ATM Block all interrupt and 2F 1 2
DMA requests during
execution of the next 3
instructions
BCLR bit, dst dst[bit] 0 r E2 2 2
BIT p, bit, dst dst[bit] p r E2 2 2
BRK Debugger Break 00 1 1
BSET bit, dst dst[bit] 1 r E2 2 2
BSWAP dst dst[7:0] dst[0:7] R D5 X * * 0 2 2
BTJ p, bit, src, if src[bit] = p r F6 3 3
dst PC PC + X Ir F7 3 4
Note: Flags Notation:
* = Value is a function of the result of the operation.
= Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
236
Address
Mode Flags
Assembly Opcode(s) Fetch Instr.
Mnemonic Symbolic Operation dst src (Hex) C Z S V D H Cycles Cycles
BTJNZ bit, src, if src[bit] = 1 r F6 3 3
dst PC PC + X Ir F7 3 4
BTJZ bit, src, if src[bit] = 0 r F6 3 3
dst PC PC + X Ir F7 3 4
CALL dst SP SP 2 IRR D4 2 6
@SP PC DA D6 3 3
PC dst
CCF C ~C EF * 1 2
CLR dst dst 00h R B0 2 2
IR B1 2 3
COM dst dst ~dst R 60 * * 0 2 2
IR 61 2 3
CP dst, src dst src r r A2 * * * * 2 3
r Ir A3 2 4
R R A4 3 3
R IR A5 3 4
R IM A6 3 3
IR IM A7 3 4
CPC dst, src dst src C r r 1F A2 * * * * 3 3
r Ir 1F A3 3 4
R R 1F A4 4 3
R IR 1F A5 4 4
R IM 1F A6 4 3
IR IM 1F A7 4 4
CPCX dst, src dst src C ER ER 1F A8 * * * * 5 3
ER IM 1F A9 5 3
CPX dst, src dst src ER ER A8 * * * * 4 3
ER IM A9 4 3
Note: Flags Notation:
* = Value is a function of the result of the operation.
= Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
237
Address
Mode Flags
Assembly Opcode(s) Fetch Instr.
Mnemonic Symbolic Operation dst src (Hex) C Z S V D H Cycles Cycles
DA dst dst DA(dst) R 40 * * * X 2 2
IR 41 2 3
DEC dst dst dst 1 R 30 * * * 2 2
IR 31 2 3
DECW dst dst dst 1 RR 80 * * * 2 5
IRR 81 2 6
DI IRQCTL[7] 0 8F 1 2
DJNZ dst, RA dst dst 1 r 0AFA 2 3
if dst 0
PC PC + X
EI IRQCTL[7] 1 9F 1 2
HALT Halt Mode 7F 1 2
INC dst dst dst + 1 R 20 * * * 2 2
IR 21 2 3
r 0EFE 1 2
INCW dst dst dst + 1 RR A0 * * * 2 5
IRR A1 2 6
IRET FLAGS @SP BF * * * * * * 1 5
SP SP + 1
PC @SP
SP SP + 2
IRQCTL[7] 1
JP dst PC dst DA 8D 3 2
IRR C4 2 3
JP cc, dst if cc is true DA 0DFD 3 2
PC dst
JR dst PC PC + X DA 8B 2 2
JR cc, dst if cc is true DA 0BFB 2 2
PC PC + X
Note: Flags Notation:
* = Value is a function of the result of the operation.
= Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
238
Address
Mode Flags
Assembly Opcode(s) Fetch Instr.
Mnemonic Symbolic Operation dst src (Hex) C Z S V D H Cycles Cycles
LD dst, rc dst src r IM 0CFC 2 2
r X(r) C7 3 3
X(r) r D7 3 4
r Ir E3 2 3
R R E4 3 2
R IR E5 3 4
R IM E6 3 2
IR IM E7 3 3
Ir r F3 2 3
IR R F5 3 3
LDC dst, src dst src r Irr C2 2 5
Ir Irr C5 2 9
Irr r D2 2 5
LDCI dst, src dst src Ir Irr C3 2 9
r r + 1 Irr Ir D3 2 9
rr rr + 1
LDE dst, src dst src r Irr 82 2 5
Irr r 92 2 5
LDEI dst, src dst src Ir Irr 83 2 9
r r + 1 Irr Ir 93 2 9
rr rr + 1
LDWX dst, src dst src ER ER 1F E8 5 4
Note: Flags Notation:
* = Value is a function of the result of the operation.
= Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
239
Address
Mode Flags
Assembly Opcode(s) Fetch Instr.
Mnemonic Symbolic Operation dst src (Hex) C Z S V D H Cycles Cycles
LDX dst, src dst src r ER 84 3 2
Ir ER 85 3 3
R IRR 86 3 4
IR IRR 87 3 5
r X(rr) 88 3 4
X(rr) r 89 3 4
ER r 94 3 2
ER Ir 95 3 3
IRR R 96 3 4
IRR IR 97 3 5
ER ER E8 4 2
ER IM E9 4 2
LEA dst, X(src) dst src + X r X(r) 98 3 3
rr X(rr) 99 3 5
MULT dst dst[15:0] RR F4 2 8
dst[15:8] * dst[7:0]
NOP No operation 0F 1 2
OR dst, src dst dst OR src r r 42 * * 0 2 3
r Ir 43 2 4
R R 44 3 3
R IR 45 3 4
R IM 46 3 3
IR IM 47 3 4
ORX dst, src dst dst OR src ER ER 48 * * 0 4 3
ER IM 49 4 3
POP dst dst @SP R 50 2 2
SP SP + 1 IR 51 2 3
Note: Flags Notation:
* = Value is a function of the result of the operation.
= Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
240
Address
Mode Flags
Assembly Opcode(s) Fetch Instr.
Mnemonic Symbolic Operation dst src (Hex) C Z S V D H Cycles Cycles
POPX dst dst @SP ER D8 3 2
SP SP + 1
PUSH src SP SP 1 R 70 2 2
@SP src IR 71 2 3
IM 1F 70 3 2
PUSHX src SP SP 1 ER C8 3 2
@SP src
RCF C0 CF 0 1 2
RET PC @SP AF 1 4
SP SP + 2
RL dst R 90 * * * * 2 2
C D7 D6 D5 D4 D3 D2 D1 D0
dst
IR 91 2 3
RLC dst R 10 * * * * 2 2
C D7 D6 D5 D4 D3 D2 D1 D0
dst IR 11 2 3
RR dst R E0 * * * * 2 2
D7 D6 D5 D4 D3 D2 D1 D0 C
dst
IR E1 2 3
RRC dst R C0 * * * * 2 2
D7 D6 D5 D4 D3 D2 D1 D0 C
dst IR C1 2 3
SBC dst, src dst dst src C r r 32 * * * * 1 * 2 3
r Ir 33 2 4
R R 34 3 3
R IR 35 3 4
R IM 36 3 3
IR IM 37 3 4
SBCX dst, src dst dst src C ER ER 38 * * * * 1 * 4 3
ER IM 39 4 3
SCF C1 DF 1 1 2
Note: Flags Notation:
* = Value is a function of the result of the operation.
= Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
241
Address
Mode Flags
Assembly Opcode(s) Fetch Instr.
Mnemonic Symbolic Operation dst src (Hex) C Z S V D H Cycles Cycles
SRA dst R D0 * * * 0 2 2
D7 D6 D5 D4 D3 D2 D1 D0 C
dst
IR D1 2 3
SRL dst 0 D7 D6 D5 D4 D3 D2 D1 D0 C R 1F C0 * * 0 * 3 2
dst
IR 1F C1 3 3
SRP src RP src IM 01 2 2
STOP Stop Mode 6F 1 2
SUB dst, src dst dst src r r 22 * * * * 1 * 2 3
r Ir 23 2 4
R R 24 3 3
R IR 25 3 4
R IM 26 3 3
IR IM 27 3 4
SUBX dst, src dst dst src ER ER 28 * * * * 1 * 4 3
ER IM 29 4 3
SWAP dst dst[7:4] dst[3:0] R F0 X * * X 2 2
IR F1 2 3
TCM dst, src (NOT dst) AND src r r 62 * * 0 2 3
r Ir 63 2 4
R R 64 3 3
R IR 65 3 4
R IM 66 3 3
IR IM 67 3 4
TCMX dst, src (NOT dst) AND src ER ER 68 * * 0 4 3
ER IM 69 4 3
Note: Flags Notation:
* = Value is a function of the result of the operation.
= Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
242
Address
Mode Flags
Assembly Opcode(s) Fetch Instr.
Mnemonic Symbolic Operation dst src (Hex) C Z S V D H Cycles Cycles
TM dst, src dst AND src r r 72 * * 0 2 3
r Ir 73 2 4
R R 74 3 3
R IR 75 3 4
R IM 76 3 3
IR IM 77 3 4
TMX dst, src dst AND src ER ER 78 * * 0 4 3
ER IM 79 4 3
TRAP Vector SP SP 2 Vecto F2 2 6
@SP PC r
SP SP 1
@SP FLAGS
PC @Vector
WDT 5F 1 2
XOR dst, src dst dst XOR src r r B2 * * 0 2 3
r Ir B3 2 4
R R B4 3 3
R IR B5 3 4
R IM B6 3 3
IR IM B7 3 4
XORX dst, src dst dst XOR src ER ER B8 * * 0 4 3
ER IM B9 4 3
Note: Flags Notation:
* = Value is a function of the result of the operation.
= Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
243
Flags Register
The Flags Register contains the status information regarding the most recent arithmetic,
logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits
of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z
and S) can be tested for use with conditional jump instructions. Two flags, H and D, can-
not be tested and are used for Binary-Coded Decimal (BCD) arithmetic.
The two remaining bits, user flags F1 and F2, are available as general-purpose status bits.
User flags are unaffected by arithmetic operations and must be set or cleared by instruc-
tions. The user flags cannot be used with conditional jumps. They are undefined at initial
power-up and are unaffected by Reset. Figure 58 displays the flags and their bit positions
in the Flags Register.
Bit Bit
7 0
C Z S V D H F2 F1 Flags Register
User Flags
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
Note:U = Undefined.
Figure 58. Flags Register
Interrupts, the software trap (TRAP) instruction, and illegal instruction traps all write the
value of the Flags Register to the stack. Executing an interrupt return (IRET) instruction
restores the value saved on the stack into the Flags Register.
244
Op Code Maps
A description of the op code map data and the abbreviations are provided in Figure 59 and
Table 137. Figures 60 and 61 provide information about each of the eZ8 CPU instructions.
Op Code
Lower Nibble
3.3
Opcode
Upper Nibble A CP
R2,R1
245
246
2.2 2.3 2.3 2.4 3.3 3.4 3.3 3.4 4.3 4.3 1.2
7 PUSH PUSH TM TM TM TM TM TM TMX TMX HALT
R2 IR2 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1
2.5 2.6 2.5 2.9 3.2 3.3 3.4 3.5 3.4 3.4 1.2
8 DECW DECW LDE LDEI LDX LDX LDX LDX LDX LDX DI
RR1 IRR1 r1,Irr2 Ir1,Irr2 r1,ER2 Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X rr1,r2,X
2.2 2.3 2.5 2.9 3.2 3.3 3.4 3.5 3.3 3.5 1.2
9 RL RL LDE LDEI LDX LDX LDX LDX LEA LEA EI
R1 IR1 r2,Irr1 Ir2,Irr1 r2,ER1 Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X rr1,rr2,X
2.5 2.6 2.3 2.4 3.3 3.4 3.3 3.4 4.3 4.3 1.4
A INCW INCW CP CP CP CP CP CP CPX CPX RET
RR1 IRR1 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1
2.2 2.3 2.3 2.4 3.3 3.4 3.3 3.4 4.3 4.3 1.5
B CLR CLR XOR XOR XOR XOR XOR XOR XORX XORX IRET
R1 IR1 r1,r2 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1
2.2 2.3 2.5 2.9 2.3 2.9 3.4 3.2 1.2
C RRC RRC LDC LDCI JP LDC LD PUSHX RCF
R1 IR1 r1,Irr2 Ir1,Irr2 IRR1 Ir1,Irr2 r1,r2,X ER2
2.2 2.3 2.5 2.9 2.6 2.2 3.3 3.4 3.2 1.2
D SRA SRA LDC LDCI CALL BSWAP CALL LD POPX SCF
R1 IR1 r2,Irr1 Ir2,Irr1 IRR1 R1 DA r2,r1,X ER1
2.2 2.3 2.2 2.3 3.2 3.3 3.2 3.3 4.2 4.2 1.2
E RR RR BIT LD LD LD LD LD LDX LDX CCF
R1 IR1 p,b,r1 r1,Ir2 R2,R1 IR2,R1 R1,IM IR1,IM ER2,ER1 IM,ER1
2.2 2.3 2.6 2.3 2.8 3.3 3.3 3.4
F SWAP SWAP TRAP LD MULT LD BTJ BTJ
R1 IR1 Vector Ir1,r2 RR1 R2,IR1 p,b,r1,X p,b,Ir1,X
247
6
Upper Nibble (Hex)
3,2
7 PUSH
IM
3.2 3.3
C SRL SRL
R1 IR1
5,4
E LDWX
ER2,ER1
248
Timer 0
For more information about these Timer Control registers, see the Timer Control Register
Definitions section on page 72.
Bit 7 6 5 4 3 2 1 0
Field TH
RESET 0
R/W R/W
Address F00h, F08h, F10h, F18h
249
Bit 7 6 5 4 3 2 1 0
Field TL
RESET 0 1
R/W R/W
Address F01h, F09h, F11h, F19h
Bit 7 6 5 4 3 2 1 0
Field TRH
RESET 1
R/W R/W
Address F02h, F0Ah, F12h, F1Ah
Bit 7 6 5 4 3 2 1 0
Field TRL
RESET 1
R/W R/W
Address F03h, F0Bh, F13h, F1Bh
Bit 7 6 5 4 3 2 1 0
Field PWMH
RESET 0
R/W R/W
Address F04h, F0Ch, F14h, F1Ch
250
Bit 7 6 5 4 3 2 1 0
Field PWML
RESET 0
R/W R/W
Address F05h, F0Dh, F15h, F1Dh
Bit 7 6 5 4 3 2 1 0
Field Reserved CSC Reserved
RESET 0
R/W R/W
Address F06h, F0Eh, F16h, F1Eh
Bit 7 6 5 4 3 2 1 0
Field TEN TPOL PRES TMODE
RESET 0
R/W R/W
Address F07h, F0Fh, F17h, F1Fh
Bit 7 6 5 4 3 2 1 0
Field TH
RESET 0
R/W R/W
Address F00h, F08h, F10h, F18h
251
Bit 7 6 5 4 3 2 1 0
Field TL
RESET 0 1
R/W R/W
Address F01h, F09h, F11h, F19h
Bit 7 6 5 4 3 2 1 0
Field TRH
RESET 1
R/W R/W
Address F02h, F0Ah, F12h, F1Ah
Bit 7 6 5 4 3 2 1 0
Field TRL
RESET 1
R/W R/W
Address F03h, F0Bh, F13h, F1Bh
Bit 7 6 5 4 3 2 1 0
Field PWMH
RESET 0
R/W R/W
Address F04h, F0Ch, F14h, F1Ch
252
Bit 7 6 5 4 3 2 1 0
Field PWML
RESET 0
R/W R/W
Address F05h, F0Dh, F15h, F1Dh
Bit 7 6 5 4 3 2 1 0
Field Reserved CSC Reserved
RESET 0
R/W R/W
Address F06h, F0Eh, F16h, F1Eh
Bit 7 6 5 4 3 2 1 0
Field TEN TPOL PRES TMODE
RESET 0
R/W R/W
Address F07h, F0Fh, F17h, F1Fh
Bit 7 6 5 4 3 2 1 0
Field TH
RESET 0
R/W R/W
Address F00h, F08h, F10h, F18h
253
Bit 7 6 5 4 3 2 1 0
Field TL
RESET 0 1
R/W R/W
Address F01h, F09h, F11h, F19h
Bit 7 6 5 4 3 2 1 0
Field TRH
RESET 1
R/W R/W
Address F02h, F0Ah, F12h, F1Ah
Bit 7 6 5 4 3 2 1 0
Field TRL
RESET 1
R/W R/W
Address F03h, F0Bh, F13h, F1Bh
Bit 7 6 5 4 3 2 1 0
Field PWMH
RESET 0
R/W R/W
Address F04h, F0Ch, F14h, F1Ch
254
Bit 7 6 5 4 3 2 1 0
Field PWML
RESET 0
R/W R/W
Address F05h, F0Dh, F15h, F1Dh
Bit 7 6 5 4 3 2 1 0
Field Reserved CSC Reserved
RESET 0
R/W R/W
Address F06h, F0Eh, F16h, F1Eh
Bit 7 6 5 4 3 2 1 0
Field TEN TPOL PRES TMODE
RESET 0
R/W R/W
Address F07h, F0Fh, F17h, F1Fh
Bit 7 6 5 4 3 2 1 0
Field TH
RESET 0
R/W R/W
Address F00h, F08h, F10h, F18h
255
Bit 7 6 5 4 3 2 1 0
Field TL
RESET 0 1
R/W R/W
Address F01h, F09h, F11h, F19h
Bit 7 6 5 4 3 2 1 0
Field TRH
RESET 1
R/W R/W
Address F02h, F0Ah, F12h, F1Ah
Bit 7 6 5 4 3 2 1 0
Field TRL
RESET 1
R/W R/W
Address F03h, F0Bh, F13h, F1Bh
Bit 7 6 5 4 3 2 1 0
Field PWMH
RESET 0
R/W R/W
Address F04h, F0Ch, F14h, F1Ch
256
Bit 7 6 5 4 3 2 1 0
Field PWML
RESET 0
R/W R/W
Address F05h, F0Dh, F15h, F1Dh
Bit 7 6 5 4 3 2 1 0
Field Reserved CSC Reserved
RESET 0
R/W R/W
Address F06h, F0Eh, F16h, F1Eh
Bit 7 6 5 4 3 2 1 0
Field TEN TPOL PRES TMODE
RESET 0
R/W R/W
Address F07h, F0Fh, F17h, F1Fh
257
Bit 7 6 5 4 3 2 1 0
Field TXD
RESET X
R/W W
Address F40h and F48h
Bit 7 6 5 4 3 2 1 0
Field RXD
RESET X
R/W R
Address F40h and F48h
Bit 7 6 5 4 3 2 1 0
Field RDA PE OE FE BRKD TDRE TXE CTS
RESET 0 1 X
R/W R
Address F41h and F49h
Bit 7 6 5 4 3 2 1 0
Field TEN REN CTSE PEN PSEL SBRK STOP LBEN
RESET 0
R/W R/W
Address F42h and F4Ah
258
Bit 7 6 5 4 3 2 1 0
Field MPMD[1] MPEN MPMD[0] MPBT DEPOL BRGCTL RDAIRQ IREN
RESET 0
R/W R/W
Address F43h and F4Bh
Bit 7 6 5 4 3 2 1 0
Field Reserved NEWFRM MPRX
RESET 0
R/W R R/W R
Address F44h and F4Ch
Bit 7 6 5 4 3 2 1 0
Field COMP_ADDR
RESET 0
R/W R/W
Address F45h and F4Dh
Bit 7 6 5 4 3 2 1 0
Field BRH
RESET 1
R/W R/W
Address F46h and F4Eh
259
Bit7 7 6 5 4 3 2 1 0
Field BRL
RESET 1
R/W R/W
Address F47h and F4Fh
Bit 7 6 5 4 3 2 1 0
Field TXD
RESET X
R/W W
Address F40h and F48h
Bit 7 6 5 4 3 2 1 0
Field RXD
RESET X
R/W R
Address F40h and F48h
Bit 7 6 5 4 3 2 1 0
Field RDA PE OE FE BRKD TDRE TXE CTS
RESET 0 1 X
R/W R
Address F41h and F49h
260
Bit 7 6 5 4 3 2 1 0
Field TEN REN CTSE PEN PSEL SBRK STOP LBEN
RESET 0
R/W R/W
Address F42h and F4Ah
Bit 7 6 5 4 3 2 1 0
Field MPMD[1] MPEN MPMD[0] MPBT DEPOL BRGCTL RDAIRQ IREN
RESET 0
R/W R/W
Address F43h and F4Bh
Bit 7 6 5 4 3 2 1 0
Field Reserved NEWFRM MPRX
RESET 0
R/W R R/W R
Address F44h and F4Ch
Bit 7 6 5 4 3 2 1 0
Field COMP_ADDR
RESET 0
R/W R/W
Address F45h and F4Dh
261
Bit 7 6 5 4 3 2 1 0
Field BRH
RESET 1
R/W R/W
Address F46h and F4Eh
Bit7 7 6 5 4 3 2 1 0
Field BRL
RESET 1
R/W R/W
Address F47h and F4Fh
Bit 7 6 5 4 3 2 1 0
Field DATA
RESET 0
R/W R/W
Address F50h
262
Bit 7 6 5 4 3 2 1 0
Field TDRE RDRF ACK 10B RD TAS DSS NCKI
RESET 1 0
R/W R
Address F51h
Bit 7 6 5 4 3 2 1 0
Field IEN START STOP BIRQ TXI NAK FLUSH FILTEN
RESET 0
R/W R/W R/W1 R/W1 R/W R/W R/W1 W1 R/W
Address F52h
Bit 7 6 5 4 3 2 1 0
Field BRH
RESET FFh
R/W R/W
Address F53h
Bit 7 6 5 4 3 2 1 0
Field BRL
RESET FFh
R/W R/W
Address F54h
263
Bit 7 6 5 4 3 2 1 0
Field SCLIN SDAIN STPCNT TXRXSTATE
RESET X 0
R/W R
Address F55h
Bit 7 6 5 4 3 2 1 0
Field Reserved DIAG
RESET 0
R/W R R/W
Address F56h
Bit 7 6 5 4 3 2 1 0
Field DATA
RESET X
R/W R/W
Address F60h
264
Bit 7 6 5 4 3 2 1 0
Field IRQE STR BIRQ PHASE CLKPOL WOR MMEN SPIEN
RESET 0
R/W R/W
Address F61h
Bit 7 6 5 4 3 2 1 0
Field IRQ OVR COL ABT Reserved TXST SLAS
RESET 0 1
R/W R/W* R
Address F62h
Note: R/W* = Read access. Write a 1 to clear the bit to 0.
Bit 7 6 5 4 3 2 1 0
Field Reserved DIAG NUMBITS[2:0] SSIO SSV
RESET 0
R/W R R/W
Address F63h
265
Bit 7 6 5 4 3 2 1 0
Field SCKEN TCKEN SPISTATE
RESET 0
R/W R
Address F64h
Bit 7 6 5 4 3 2 1 0
Field BRH
RESET 1
R/W R/W
Address F66h
Bit 7 6 5 4 3 2 1 0
Field BRL
RESET 1
R/W R/W
Address F67h
266
Bit 7 6 5 4 3 2 1 0
Field ADCD_H
RESET X
R/W R
Address F72h
Bit 7 6 5 4 3 2 1 0
Field ADCD_L Reserved
RESET X
R/W R
Address F73h
267
Bit 7 6 5 4 3 2 1 0
Field DEN DLE DDIR IRQEN WSEL RSS
RESET 0
R/W R/W
Address FB0h, FB8h
Bit 7 6 5 4 3 2 1 0
Field DMA_IO
RESET X
R/W R/W
Address FB1h, FB9h
Bit 7 6 5 4 3 2 1 0
Field DMA_END_H DMA_START_H
RESET X
R/W R/W
Address FB2h, FBAh
Bit 7 6 5 4 3 2 1 0
Field DMA_START
RESET X
R/W R/W
Address FB3h, FBBh
268
Bit 7 6 5 4 3 2 1 0
Field DMA_END
RESET X
R/W R/W
Address FB4h, FBCh
Bit 7 6 5 4 3 2 1 0
Field DEN DLE DDIR IRQEN WSEL RSS
RESET 0
R/W R/W
Address FB0h, FB8h
Bit 7 6 5 4 3 2 1 0
Field DMA_IO
RESET X
R/W R/W
Address FB1h, FB9h
269
Bit 7 6 5 4 3 2 1 0
Field DMA_END_H DMA_START_H
RESET X
R/W R/W
Address FB2h, FBAh
Bit 7 6 5 4 3 2 1 0
Field DMA_START
RESET X
R/W R/W
Address FB3h, FBBh
Bit 7 6 5 4 3 2 1 0
Field DMA_END
RESET X
R/W R/W
Address FB4h, FBCh
Bit 7 6 5 4 3 2 1 0
Field DMAA_ADDR Reserved
RESET X
R/W R/W
Address FBDh
270
Bit 7 6 5 4 3 2 1 0
Field DAEN IRQEN Reserved ADC_IN
RESET 0
R/W R/W
Address FBEh
Bit 7 6 5 4 3 2 1 0
Field CADC[3:0] Reserved IRQA IRQ1 IRQ0
RESET 0
R/W R
Address FBFh
Bit 7 6 5 4 3 2 1 0
Field T2I T1I T0I U0RXI U0TXI I2CI SPII ADCI
RESET 0
R/W R/W
Address FC0h
271
Bit 7 6 5 4 3 2 1 0
Field T2ENH T1ENH T0ENH U0RENH U0TENH I2CENH SPIENH ADCENH
RESET 0
R/W R/W
Address FC1h
Bit 7 6 5 4 3 2 1 0
Field T2ENL T1ENL T0ENL U0RENL U0TENL I2CENL SPIENL ADCENL
RESET 0
R/W R/W
Address FC2h
Bit 7 6 5 4 3 2 1 0
Field PAD7I PAD6I PAD5I PAD4I PAD3I PAD2I PAD1I PAD0I
RESET 0
R/W R/W
Address FC3h
Bit 7 6 5 4 3 2 1 0
Field PAD7ENH PAD6ENH PAD5ENH PAD4ENH PAD3ENH PAD2ENH PAD1ENH PAD0ENH
RESET 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address FC4h
272
Bit 7 6 5 4 3 2 1 0
Field PAD7ENL PAD6ENL PAD5ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PAD0ENL
RESET 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address FC5h
Bit 7 6 5 4 3 2 1 0
Field T3I U1RXI U1TXI DMAI PC3I PC2I PC1I PC0I
RESET 0
R/W R/W
Address FC6h
Bit 7 6 5 4 3 2 1 0
Field T3ENH U1RENH U1TENH DMAENH C3ENH C2ENH C1ENH C0ENH
RESET 0
R/W R/W
Address FC7h
Bit 7 6 5 4 3 2 1 0
Field T3ENL U1RENL U1TENL DMAENL C3ENL C2ENL C1ENL C0ENL
RESET 0
R/W R/W
Address FC8h
273
Bit 7 6 5 4 3 2 1 0
Field IES7 IES6 IES5 IES4 IES3 IES2 IES1 IES0
RESET 0
R/W R/W
Address FCDh
Bit 7 6 5 4 3 2 1 0
Field PAD7S PAD6S PAD5S PAD4S PAD3S PAD2S PAD1S PAD0S
RESET 0
R/W R/W
Address FCEh
Bit 7 6 5 4 3 2 1 0
Field IRQE Reserved
RESET 0
R/W R/W R
Address FCFh
274
Bit 7 6 5 4 3 2 1 0
Field PADDR[7:0]
RESET 00h
R/W R/W
Address FD0h, FD4h, FD8h, FDCh, FE0h, FE4h, FE8h, FECh
Bit 7 6 5 4 3 2 1 0
Field PCTL
RESET 00h
R/W R/W
Address FD1h, FD5h, FD9h, FDDh, FE1h, FE5h, FE9h, FEDh
Bit 7 6 5 4 3 2 1 0
Field PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET X
R/W R
Address FD2h, FD6h, FDAh, FDEh, FE2h, FE6h, FEAh, FEEh
275
Bit 7 6 5 4 3 2 1 0
Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0
R/W R/W
Address FD3h, FD7h, FDBh, FDFh, FE3h, FE7h, FEBh, FEFh
Bit 7 6 5 4 3 2 1 0
Field PADDR[7:0]
RESET 00h
R/W R/W
Address FD0h, FD4h, FD8h, FDCh, FE0h, FE4h, FE8h, FECh
Bit 7 6 5 4 3 2 1 0
Field PCTL
RESET 00h
R/W R/W
Address FD1h, FD5h, FD9h, FDDh, FE1h, FE5h, FE9h, FEDh
Bit 7 6 5 4 3 2 1 0
Field PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET X
R/W R
Address FD2h, FD6h, FDAh, FDEh, FE2h, FE6h, FEAh, FEEh
276
Bit 7 6 5 4 3 2 1 0
Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0
R/W R/W
Address FD3h, FD7h, FDBh, FDFh, FE3h, FE7h, FEBh, FEFh
Bit 7 6 5 4 3 2 1 0
Field PADDR[7:0]
RESET 00h
R/W R/W
Address FD0h, FD4h, FD8h, FDCh, FE0h, FE4h, FE8h, FECh
Bit 7 6 5 4 3 2 1 0
Field PCTL
RESET 00h
R/W R/W
Address FD1h, FD5h, FD9h, FDDh, FE1h, FE5h, FE9h, FEDh
Bit 7 6 5 4 3 2 1 0
Field PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET X
R/W R
Address FD2h, FD6h, FDAh, FDEh, FE2h, FE6h, FEAh, FEEh
277
Bit 7 6 5 4 3 2 1 0
Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0
R/W R/W
Address FD3h, FD7h, FDBh, FDFh, FE3h, FE7h, FEBh, FEFh
Bit 7 6 5 4 3 2 1 0
Field PADDR[7:0]
RESET 00h
R/W R/W
Address FD0h, FD4h, FD8h, FDCh, FE0h, FE4h, FE8h, FECh
Bit 7 6 5 4 3 2 1 0
Field PCTL
RESET 00h
R/W R/W
Address FD1h, FD5h, FD9h, FDDh, FE1h, FE5h, FE9h, FEDh
Bit 7 6 5 4 3 2 1 0
Field PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET X
R/W R
Address FD2h, FD6h, FDAh, FDEh, FE2h, FE6h, FEAh, FEEh
278
Bit 7 6 5 4 3 2 1 0
Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0
R/W R/W
Address FD3h, FD7h, FDBh, FDFh, FE3h, FE7h, FEBh, FEFh
Bit 7 6 5 4 3 2 1 0
Field PADDR[7:0]
RESET 00h
R/W R/W
Address FD0h, FD4h, FD8h, FDCh, FE0h, FE4h, FE8h, FECh
Bit 7 6 5 4 3 2 1 0
Field PCTL
RESET 00h
R/W R/W
Address FD1h, FD5h, FD9h, FDDh, FE1h, FE5h, FE9h, FEDh
Bit 7 6 5 4 3 2 1 0
Field PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET X
R/W R
Address FD2h, FD6h, FDAh, FDEh, FE2h, FE6h, FEAh, FEEh
279
Bit 7 6 5 4 3 2 1 0
Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0
R/W R/W
Address FD3h, FD7h, FDBh, FDFh, FE3h, FE7h, FEBh, FEFh
Bit 7 6 5 4 3 2 1 0
Field PADDR[7:0]
RESET 00h
R/W R/W
Address FD0h, FD4h, FD8h, FDCh, FE0h, FE4h, FE8h, FECh
Bit 7 6 5 4 3 2 1 0
Field PCTL
RESET 00h
R/W R/W
Address FD1h, FD5h, FD9h, FDDh, FE1h, FE5h, FE9h, FEDh
Bit 7 6 5 4 3 2 1 0
Field PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET X
R/W R
Address FD2h, FD6h, FDAh, FDEh, FE2h, FE6h, FEAh, FEEh
280
Bit 7 6 5 4 3 2 1 0
Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0
R/W R/W
Address FD3h, FD7h, FDBh, FDFh, FE3h, FE7h, FEBh, FEFh
Bit 7 6 5 4 3 2 1 0
Field PADDR[7:0]
RESET 00h
R/W R/W
Address FD0h, FD4h, FD8h, FDCh, FE0h, FE4h, FE8h, FECh
Bit 7 6 5 4 3 2 1 0
Field PCTL
RESET 00h
R/W R/W
Address FD1h, FD5h, FD9h, FDDh, FE1h, FE5h, FE9h, FEDh
Bit 7 6 5 4 3 2 1 0
Field PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET X
R/W R
Address FD2h, FD6h, FDAh, FDEh, FE2h, FE6h, FEAh, FEEh
281
Bit 7 6 5 4 3 2 1 0
Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0
R/W R/W
Address FD3h, FD7h, FDBh, FDFh, FE3h, FE7h, FEBh, FEFh
Bit 7 6 5 4 3 2 1 0
Field PADDR[7:0]
RESET 00h
R/W R/W
Address FD0h, FD4h, FD8h, FDCh, FE0h, FE4h, FE8h, FECh
Bit 7 6 5 4 3 2 1 0
Field PCTL
RESET 00h
R/W R/W
Address FD1h, FD5h, FD9h, FDDh, FE1h, FE5h, FE9h, FEDh
Bit 7 6 5 4 3 2 1 0
Field PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
RESET X
R/W R
Address FD2h, FD6h, FDAh, FDEh, FE2h, FE6h, FEAh, FEEh
282
Bit 7 6 5 4 3 2 1 0
Field POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0
RESET 0
R/W R/W
Address FD3h, FD7h, FDBh, FDFh, FE3h, FE7h, FEBh, FEFh
Watchdog Timer
For more information about these Watchdog Timer Control registers, see the Watchdog
Timer Control Register Definitions section on page 83.
Bit 7 6 5 4 3 2 1 0
Field POR STOP WDT EXT Reserved SM
RESET See Table 48 on page 84. 0
R/W R
Address FF0h
Bit 7 6 5 4 3 2 1 0
Field WDTU
RESET 1
R/W R/W*
Address FF1h
Note: *R/W = Read returns the current WDT count value; write sets the appropriate reload value.
283
Bit 7 6 5 4 3 2 1 0
Field WDTH
RESET 1
R/W R/W*
Address FF2h
Note: *R/W = Read returns the current WDT count value; write sets the appropriate reload value.
Bit 7 6 5 4 3 2 1 0
Field WDTL
RESET 1
R/W R/W*
Address FF3h
Note: *R/W = Read returns the current WDT count value; write sets the appropriate reload value.
284
Flash
For more information about these Flash Control registers, see the Flash Control Register
Definitions section on page 175.
Bit 7 6 5 4 3 2 1 0
Field FCMD
RESET 0
R/W W
Address FF8h
Bit 7 6 5 4 3 2 1 0
Field Reserved FSTAT
RESET 0
R/W R
Address FF8h
Bit 7 6 5 4 3 2 1 0
Field INFO_EN PAGE
RESET 0
R/W R/W
Address FF9h
285
Bit 7 6 5 4 3 2 1 0
Field SECT7 SECT6 SECT5 SECT4 SECT3 SECT2 SECT1 SECT0
RESET 0
R/W R/W*
Address FF9h
Note: *R/W = This register is accessible for read operations; it can be written to 1 only via user code.
Bit 7 6 5 4 3 2 1 0
Field FFREQH
RESET 0
R/W R/W
Address FFAh
Bit 7 6 5 4 3 2 1 0
Field FFREQL
RESET 0
R/W R/W
Address FFBh
286
Packaging
Zilogs F64xx Series of MCUs includes the Z8F1621, Z8F2421, Z8F3221, Z8F4821 and
Z8F6421 devices, which are available in the following packages:
40-pin Pin Dual Inline Package (PDIP)
44-pin Low Profile Quad Flat Package (LQFP)
44-pin Plastic Lead Chip Carrier (PLCC)
Zilogs F64xx Series of MCUs also includes the Z8F1622, Z8F2422, Z8F3222, Z8F4822
and Z8F6422 devices, which are available in the following packages:
64-pin Low-Profile Quad Flat Package (LQFP)
68-pin Plastic Lead Chip Carrier (PLCC)
Lastly, Zilogs F64xx Series of MCUs includes the Z8F4823 and Z8F6423 devices, which
are available in the following package:
80-pin Quad Flat Package (QFP)
Current diagrams for each of these packages are published in Zilogs Packaging Product
Specification (PS0072), which is available free for download from the Zilog website.
287
Ordering Information
Order your F64xx Series products from Zilog using the part numbers shown in Table 271.
For more information about ordering, please consult your local Zilog sales office. The
Sales Location page on the Zilog website lists all regional offices.
288
289
290
291
292
Z8 F 64 21 A N 020 S C
Environmental Flow
G = Lead Free Package
Speed
020 = 20 MHz
Pin Count
M = 40 pins, N = 44 pins, R = 64 pins, S = 68
pins, T = 80 pins
Package
A = LQFP
F = QFP
P = PDIP
V = PLCC
Device Type
21 = Devices with 29 or 31 I/O lines, 23 inter-
rupts, 3 timers and 8 ADC channels
22 = Devices with 46 I/O Lines, 24 interrupts,
4 Timers and 12 ADC channels
23 = Devices with 60 I/O Lines, 24 interrupts,
4 Timers and 12 ADC channels
Memory Size
64 KB Flash, 4 KB RAM
48 KB Flash, 4 KB RAM
32 KB Flash, 2 KB RAM
24 KB Flash, 2 KB RAM
16 KB Flash, 2 KB RAM
Memory Type
F = Flash
Device Family
293
Index
Numerics B
10-bit ADC 5 baud rate generator, UART 99
BCLR 232
binary number suffix 229
A BIT 232
absolute maximum ratings 201 bit 228
AC characteristics 217 clear 232
ADC 231 manipulation instructions 232
architecture 162 set 232
automatic power-down 164 set or clear 232
block diagram 163 swap 232
continuous conversion 165 test and jump 234
control register 166 test and jump if non-zero 234
control register definitions 166 test and jump if zero 234
data high byte register 168 bit jump and test if non-zero 234
data low bits register 169 bit swap 235
DMA control 166 block diagram 4
electrical characteristics and timing 215 block transfer instructions 232
operation 164 BRK 234
single-shot conversion 164 BSET 232
ADCCTL register 166 BSWAP 232, 235
ADCDH register 168 BTJ 234
ADCDL register 169 BTJNZ 234
ADCX 231 BTJZ 234
ADD 231
add - extended addressing 231
add with carry 231 C
add with carry - extended addressing 231 CALL procedure 234
additional symbols 229 Capture Mode 79
address space 19 Capture/Compare modes 79
ADDX 231 cc 228
analog signals 16 CCF 233
analog-to-digital converter (ADC) 162 characteristics, electrical 201
AND 234 clear 233
ANDX 234 clock phase (SPI) 117
arithmetic instructions 231 CLR 233
assembly language programming 226 COM 234
assembly language syntax 227 compare 79
compare - extended addressing 231
Compare Mode 79
294
D
DA 228, 231 E
data register, I2C 142 EI 233
DC characteristics 203 electrical characteristics 201
debugger, on-chip 184 ADC 215
DEC 231 flash memory and timing 214
decimal adjust 231 GPIO input data sample timing 218
decrement 231 watch-dog timer 214
decrement and jump non-zero 234 enable interrupt 233
decrement word 231 ER 228
DECW 231 extended addressing register 228
destination operand 229 external pin reset 33
device, port availability 37 external RC oscillator 213
DI 233 eZ8 CPU features 4
direct address 228 eZ8 CPU instruction classes 231
direct memory access controller 151 eZ8 CPU instruction notation 228
disable interrupts 233 eZ8 CPU instruction set 226
DJNZ 234 eZ8 CPU instruction summary 235
DMA
address high nibble register 156
configuring DMA0-1 data transfer 151 F
configuring for DMA_ADC data transfer 153 FCTL register 177, 285
control of ADC 166 features, Z8 Encore! 1
295
296
297
298
299
300
301
302
V
vector 229
voltage brownout reset (VBR) 32
W
watch-dog timer
approximate time-out delay 82
CNTL 32
control register 84
refresh 82
watchdog timer
electrical characteristics and timing 214
interrupt in normal operation 82
interrupt in Stop Mode 82
refresh 233
reload unlock sequence 83
reload upper, high and low registers 86
reset 33
reset in normal operation 83
reset in Stop Mode 83
time-out response 82
WDTCTL register 85, 283
WDTH register 87, 284
WDTL register 87, 284
working register 228
working register pair 229
WTDU register 86, 283
X
X 229
303
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