SP6 MB Tutorial 01
SP6 MB Tutorial 01
com
SP6 Microblaze
Author:jinry tang
Data:2013-6-15
Addr:NanJin China
Tutorial_01 HelloWorld
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Tutorial_01 HelloWorld
Start Xilinx ISE Project Navigator, Start Programs Xilinx ISE Design Suite 13.2 ISE
Design Tools Project Navigator and create a new project: File > New Project…
Set the Project Location to F:\Xilinx\Embedded\ and the Project Name to Tutorial.
Click Next.
Select Spartan6, xc6slx9-tqg144-2. For this tutorial, pick Verilog as the Preferred
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Select Embedded Processor. Type mb_system for the File name. Click Next.
Click Finish
Click YES
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Set as follows
Finish
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The Base System Builder wizard created all the files needed to get started with an
embedded MicroBlaze system. Once finished the Xilinx Platform Studio IDE has all the
information for the project. We will look at the interface and the files created. Xilinx
platform. We will explore all of the windows and necessary files as shown in the figure
below.
1. The System Assembly View shows each peripheral used and the connections between the peripherals
when the Bus Interface tab is selected. We will learn more about the System Assembly View as well as
the IP Catalog tab in the next tutorial.
2. The Project window provides information on the project options used, gives access to the main project
files, and log files. The main Project Files are:
MHS File. The Microprocessor Hardware Specification file contains the hardware specification of
the entire system. The MHS file contains the bus architecture, list of peripherals, connectivity for
the system, interrupt request priorities, and address space. The MHS file can also call out custom IP.
§ MSS File. The Microprocessor Software Specification file defines the software drivers associated
with peripherals, standard input/output devices, interrupt handler routines,
RTOS and libraries used, and other related software features.
§ UCF File. The User Constraints File contains the timing and placement constraints for the FPGA.
§ Download.cmd - iMPACT Command File contains JTAG chain information to download the
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design to the FPGA on the development board.
§ Fast_runtime.opt - Implementation Options File lists implementation options for all the phases of
the FPGA hardware implementation. The options are used to run the standard ISE tools.
§ Bitgen.ut - Bitgen Options File provides options when generating the bit file for the FPGA.
3. The Applications tab shows the software applications available for the processor. For this lab, the
Xilinx Software Development Kit (SDK) will be used to edit and compile the software.
4. The Addresses tab shows the address map for the system.
5. Click on the Block Diagram tab to view the block diagram for the project. The block diagram shows
the connections between the different busses and components in the system. Also, you can export this
Block Diagram to a jpeg image by clicking Project > Generate Block Diagram Image. This image gets
saved in your under your project in a folder named blockdiagram.
6. A datasheet of the system can also be generated. Go to Project > Generate and View Design Report to
view the design report. This is an html file that is generated in a report subfolder.
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Select Project
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Return to Project Navigator and Go to Project > Add Copy of Source to add the FPGA
Click OK.
Select mb_system
Workspace: F:\Xilinx\Embedded\Tutorial_03\WorkSpace
Click OK.
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Select the HelloWorld application from the project templates then click Next.
Change the Board Support Package project name to Standalone >Click Finish.
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The system contains internal BRAM memory as well as external SDRAM memory. We
can select where the code will be physically located through a linker script. Right-click on
Use the drop-down list to select the internal BRAM memory, ilmb_cntlr_dlmb_cntlr, for
Click Yes.
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a. For the Bitstream, browse to the Tutorial_01 directory and select mb_system.bit
b. For the BMM File, browse to the Tutorial_01 directory and select edkBmmFile_bd.bmm
c. Click on Program.
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In the SDK Project Explorer View, right-click on the helloworld_0 project and select Run
Select Xilinx C/C++ ELF and click on the New Launch Configuration icon
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Select the COM port from step 4 above and leave the BAUD Rate at 9600 this depend
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On the console We can see the COM received data send by our board.
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