Hardware Architectures For Deep Neural Networks-MIT'16
Hardware Architectures For Deep Neural Networks-MIT'16
MICRO Tutorial
1
2 Speakers
2
Outline
3
Participant Takeaways
• Understand the key design considerations for
DNNs
4
Background of
Deep Neural Networks
5
AI and Machine Learning
Artificial Intelligence
Machine Learning
6
Brain-Inspired Machine Learning
Artificial Intelligence
Machine Learning
Brain-Inspired
7
How Does the Brain Work?
Artificial Intelligence
Machine Learning
Brain-Inspired
Spiking
9
Spiking Architecture
• Brain-inspired
• Integrate and fire
• Example: IBM TrueNorth
Artificial Intelligence
Machine Learning
Brain-Inspired
Spiking Neural
Networks
11
Neural Networks: Weighted Sum
Artificial Intelligence
Machine Learning
Brain-Inspired
Spiking Neural
Networks
Deep
Learning
14
What is Deep Learning?
“Volvo
Image XC90”
350M images
uploaded per
day
2.5 Petabytes
of customer
data hourly
300 hours of
video uploaded
every minute
16
ImageNet Challenge
17
ImageNet: Image Classification Task
15
10
0
2010 2011 2012 2013 2014 2015 Human
19
Deep Learning on Images
20
Deep Learning for Speech
• Speech Recognition
• Natural Language Processing
• Speech Translation
• Audio Generation
21
Deep Learning on Games
Google DeepMind AlphaGo
22
Medical Applications of Deep Learning
24
Connectomics – Finding Synapses
Machine Learning requires orders of
(2) ML Magnitude more computation than other parts
Membrane
(1) EM Detection (3) Watershed (4) Agglomeration
26
Emerging Applications
• Medical (Cancer Detection, Pre-Natal)
• Finance (Trading, Energy Forecasting, Risk)
• Infrastructure (Structure Safety and Traffic)
• Weather Forecasting and Event Detection
29
Overview of
Deep Neural Networks
30
DNN Timeline
• 1940s: Neural networks were proposed
• 1960s: Deep neural networks were proposed
• 1990s: Early hardware for shallow neural nets
– Example: Intel ETANN (1992)
• 1998: LeNet for MNIST
• 2011: Speech recognition using DNN (Microsoft)
• 2012: Deep learning starts supplanting traditional ML
– AlexNet for image classification
• Early 2010s: Rise of DNN accelerator research
– Examples: Neuflow, DianNao, etc.
31
Publications at Architecture Conferences
32
So Many Neural Networks!
http://www.asimovinstitute.org/neural-network-zoo/ 33
DNN Terminology 101
Neurons
W11 Y1
X1
Y2
X2
Y3
X3
W34 Y4
W11 Y1
X1
Y2
X2
Y3
X3
W34 Y4
L2 Output
Activations
Sparsely-Connected
• Fully-Connected NN
– feed forward, a.k.a. multilayer perceptron (MLP)
• Convolutional NN (CNN)
– feed forward, sparsely-connected w/ weight sharing
• Recurrent NN (RNN)
– feedback
42
Inference vs. Training
43
Deep Convolutional Neural Networks
Low-Level High-Level
CONV CONV FC
Layer
Features …
Layer
Features Layer Classes
1 – 3 Layers
44
Deep Convolutional Neural Networks
Low-Level High-Level
CONV CONV FC
Layer
Features …
Layer
Features Layer Classes
Convolution Activation
45
Deep Convolutional Neural Networks
Low-Level High-Level
CONV CONV FC
Layer
Features …
Layer
Features Layer Classes
Fully Activation
Connected
×
46
Deep Convolutional Neural Networks
Normalization Pooling
47
Deep Convolutional Neural Networks
High-Level
CONV NORM POOL CONV FC
Layer Layer Layer Layer
Features Layer Classes
48
Convolution (CONV) Layer
a plane of input activations
a.k.a. input feature map (fmap)
filter (weights)
H
R
S W
49
Convolution (CONV) Layer
input fmap
filter (weights)
H
R
S W
Element-wise
Multiplication
50
Convolution (CONV) Layer
S W F
Element-wise Partial Sum (psum)
Multiplication Accumulation
51
Convolution (CONV) Layer
S W F
Sliding Window Processing
52
Convolution (CONV) Layer
input fmap
filter C
output fmap
C
H
R E
S W F
Many Input Channels (C)
53
Convolution (CONV) Layer
C
H M
R E
1
S W F
…
Many
Output Channels (M)
C
R
M
S
54
Convolution (CONV) Layer
Many
Input fmaps (N) Many
C
Output fmaps (N)
filters
M
C
H
R E
1 1
S W F
…
…
C C
R E
H
S
N
N F
W
55
CONV Layer Implementation
Output fmaps Biases Input fmaps Filter weights
56
CONV Layer Implementation
Naïve 7-layer for-loop implementation:
57
Traditional Activation Functions
0 0
-1 -1
-1 0 1 -1 0 1
y=1/(1+e-x) y=(ex-e-x)/(ex+e-x)
0 0 0
-1 -1 -1
-1 0 1 -1 0 1 -1 0 1
x,
x≥0
y=max(0,x) y=
y=max(αx,x) α(ex-1),
x<0
α = small const. (e.g. 0.1)
CHW
M × = M
60
FC Layer – from CONV Layer POV
input fmaps
C
output fmaps
filters
M
C
H
H 1
1 1
W W 1
…
…
C C
H 1
H
W
N
N 1
W
61
Pooling (POOL) Layer
• Reduce resolution of each channel independently
• Increase translation-invariance and noise-resilience
• Overlapping or non-overlapping à depending on stride
63
Normalization (NORM) Layer
• Batch Normalization (BN)
– Normalize activations towards mean=0 and std.
dev.=1 based on the statistics of the training dataset
Convolution Activation
CONV
Layer BN
×
65
Normalization (NORM) Layer
• Local Response Normalization (LRN)
• Tries to mimic the inhibition scheme in the brain
Now deprecated!
Image Source: Caffe Tutorial 66
Relevant Components for Tutorial
67
Survey of DNN
Development Resources
Clarifai
2
0
2012 2013 2014 2015 Human
Inception module
12
Frameworks
http://caffe.berkeleyvision.org/tutorial/layers.html 14
Image Classification Datasets
• Image Classification/Recognition
– Given an entire image à Select 1 of N classes
– No localization (detection)
LeNet in 1998
(0.95% error)
ICML 2013
(0.21% error)
http://yann.lecun.com/exdb/mnist/ 16
CIFAR-10/CIFAR-100
Object Classification
32x32 pixels (color)
10 or 100 Classes
50,000 Training
10,000 Testing
CIFAR-10
RBM+finetuning in 2009
(35.16% error)
ArXiv 2015
(3.47% error)
Image Source: http://karpathy.github.io/
https://www.cs.toronto.edu/~kriz/cifar.html 17
ImageNet
Object Classification
~256x256 pixels (color)
1000 Classes
1.3M Training
100,000 Testing (50,000 Validation)
Image Source: http://karpathy.github.io/
http://www.image-net.org/challenges/LSVRC/ 18
ImageNet
Fine grained
Classes
(120 breeds)
Image Source: http://karpathy.github.io/
Winner 2016
(2.99% error)
http://www.image-net.org/challenges/LSVRC/ 19
Image Classification Summary
http://rodrigob.github.io/are_we_there_yet/build/
classification_datasets_results.html 20
Next Tasks: Localization and Detection
http://host.robots.ox.ac.uk/pascal/VOC/ http://mscoco.org/ 22
Recently Introduced Datasets
23
Survey of
DNN Hardware
• 7 TFLOPS FP32
• 245W TDP
• 29 GFLOPS/W (FP32)
• 14nm process
Knights Mill: next gen Xeon Phi “optimized for deep learning”
Intel announced the addition of new vector instructions for deep learning
(AVX512-4VNNIW and AVX512-4FMAPS), October 2016
Source: Nvidia 3
Systems for Deep Learning
Nvidia DGX-1 (2016)
• 170 TFLOPS
• 8× Tesla P100, Dual Xeon
• 3RU – 3200W
Source: Nvidia 4
Cloud Systems for Deep Learning
Facebook’s Deep Learning Machine
Source: Facebook 5
SOCs for Deep Learning Inference
Nvidia Tegra - Parker
Source: Nvidia 6
Mobile SOCs for Deep Learning
Samsung Exynos (ARM Mali)
• 14nm process
Source: Wikipedia 7
FPGAs for Deep Learning
Intel/Altera Stratix 10
• 10 TFLOPS FP32
• HBM2 integrated
• Up to 1 GHz
• 14nm process
• 80 GFLOPS/W
Xilinx Virtex UltraSCALE+
• DSP: up to 21.2 TMACS
• DSP: up to 890 MHz
• Up to 500Mb On-Chip Memory
• 16nm process
8
Kernel
Computation
9
Fully-Connected (FC) Layer
• Matrix–Vector Multiply:
• Multiply all inputs in all channels by a weight and sum
M × CHW = M
10
Fully-Connected (FC) Layer
CHW
M × = M
11
Fully-Connected (FC) Layer
12
Convolution (CONV) Layer
• Convert to matrix mult. using the Toeplitz Matrix
Toeplitz Matrix
(w/ redundant data)
1 2 3 4 × 1 2 4 5 = 1 2 3 4
Matrix Mult: 2 3 5 6
4 5 7 8
5 6 8 9
13
Convolution (CONV) Layer
• Convert to matrix mult. using the Toeplitz Matrix
Toeplitz Matrix
(w/ redundant data)
1 2 3 4 × 1 2 4 5 = 1 2 3 4
Matrix Mult: 2 3 5 6
4 5 7 8
5 6 8 9
Data is repeated
14
Convolution (CONV) Layer
Input Fmap
1 2 1 2 1 2 3 1 2 3 1 2
=
Filter 1
3 4 3 4 * 4 5 6
7 8 9
4 5 6
7 8 9
3 4
Output Fmap 1
1 2 1 2 1 2
Filter 2 Chnl 1 Chnl 2 Output Fmap 2
3 4 3 4 3 4
Chnl 1 Chnl 2
15
Convolution (CONV) Layer
Toeplitz Matrix
Chnl 1 Chnl 2 (w/ redundant data) Output Fmap 1
Filter 1 1 2 3 4 1 2 3 4 1 2 4 5 1 2 3 4
Filter 2 1 2 3 4 1 2 3 4
× 2 3 5 6
= 1 2 3 4
4 5 7 8
Output Fmap 2
5 6 8 9 Chnl 1
1 2 4 5
2 3 5 6
4 5 7 8
5 6 8 9 Chnl 2
16
Computational
Transforms
17
Computation Transformations
18
Gauss’s Multiplication Algorithm
4 multiplications + 3 additions
3 multiplications + 5 additions
19
Strassen
8 multiplications + 4 additions
P1 = a(f – h) P5 = (a + d)(e + h)
P2 = (a + b)h P6 = (b - d)(g + h)
P3 = (c + d)e P7 = (a – c)(e + f)
P4 = d(g – e)
7 multiplications + 18 additions
Naïve
Strassen
N
Image Source: http://www.stoimen.com/blog/2012/11/26/computer-algorithms-strassens-matrix-multiplication/ 21
Winograd 1D – F(2,3)
• Targeting convolutions instead of matrix multiply
• Notation: F(size of output, filter size)
input filter
=[█#0@#1 ]
6 multiplications + 4 additions
Original: 36 multiplications
Winograd: 16 multiplications à 2.25 times reduction
23
Winograd Halos
• Winograd works on a small region of output at a
time, and therefore uses inputs repeatedly
Halo columns
24
Winograd Performance Varies
Source: Nvidia 25
Winograd Summary
26
Winograd as a Transform
Transform inputs
Dot-product
filter
input Transform output
S W F
F F I
F F F
T T F
T
28
FFT Overview
30
Optimization opportunities
31
cuDNN: Speed up with Transformations
Source: Nvidia 32
GPU/CPU Benchmarking
• DeepBench
– Profile layer by layer (Dense Matrix Multiplication, Convolutions,
Recurrent Layer, All-Reduce)
33
GPU/CPU Benchmarking
• Minibatch = 16
• Image size 224x224
• cuDNN 5.0 or 5.1
• Torch Speed (ms)
Platform AlexNet VGG-16 GoogLeNet ResNet-50
(v1)
Pascal Titan X (F+B) 14.56 128.62 39.14 103.58
Pascal Titan X (F) 5.04 41.59 11.94 35.03
GTX 1080 (F) 7.00 59.37 16.08 50.64
Maxwell Titan X 7.09 62.30 19.27 55.75
Dual Xeon E5-2630 v3 n/a 3101.76 n/a 2477.61
https://github.com/jcjohnson/cnn-benchmarks 34
GPU/CPU Benchmarking
• Minibatch = 1
• Image size 224x224
Speed (ms)
https://svail.github.io/DeepBench/ 36
DNN Accelerator
Architectures
2
Memory Access is the Bottleneck
Memory Read MAC* Memory Write
* multiply-and-accumulate
3
Memory Access is the Bottleneck
Memory Read MAC* Memory Write
ALU
DRAM DRAM
* multiply-and-accumulate
4
Memory Access is the Bottleneck
Memory Read MAC* Memory Write
ALU
DRAM Mem Mem DRAM
5
Memory Access is the Bottleneck
Memory Read MAC* Memory Write
1
ALU
DRAM Mem Mem DRAM
6
Types of Data Reuse in DNN
Convolutional Reuse
CONV layers only
(sliding window)
Input Fmap
Filter
Activations
Reuse:
Filter weights
7
Types of Data Reuse in DNN
Convolutional Reuse Fmap Reuse
CONV layers only CONV and FC layers
(sliding window)
Filters
Input Fmap Input Fmap
Filter
1
Activations
Reuse: Reuse: Activations
Filter weights
8
Types of Data Reuse in DNN
Convolutional Reuse Fmap Reuse Filter Reuse
CONV layers only CONV and FC layers CONV and FC layers
(sliding window) (batch size > 1)
Input Fmaps
Filters
Input Fmap Input Fmap
Filter Filter
1 1
2
2
Activations
Reuse: Reuse: Activations Reuse: Filter weights
Filter weights
9
Memory Access is the Bottleneck
Memory Read MAC* Memory Write
1
ALU
DRAM Mem Mem DRAM
10
Memory Access is the Bottleneck
Memory Read MAC* Memory Write
1
ALU
DRAM Mem Mem DRAM
2
11
Memory Access is the Bottleneck
Memory Read MAC* Memory Write
1
ALU
DRAM Mem Mem DRAM
2
13
Low-Cost Local Data Access
PE PE
Global
DRAM
Buffer fetch data to run
PE ALU
a MAC here
Global Buffer
Psum Activations
W0 W1 W2 W3 W4 W5 W6 W7 PE
Weight
18
WS Example: nn-X (NeuFlow)
A 3×3 2D Convolution Engine
Global Buffer
Activations Weight
P0 P1 P2 P3 P4 P5 P6 P7 PE
Psum
21
OS Example: ShiDianNao
Input Fmap Dataflow in the PE Array
Global Buffer
Weight
Activation
PE
Psum
24
NLR Example: UCLA
27
Energy Efficiency Comparison
• Same total area • 256 PEs
• AlexNet CONV layers • Batch size = 16
2 Variants of OS
Norm. Energy/Op
1.5
Normalized
1
Energy/MAC
0.5
0
WS
WS OSA
OSA OSB
OSB OSC
OSC NLR
NLR RS
Dataflows
CNN Dataflows
28
[Chen et al., ISCA 2016]
Energy Efficiency Comparison
• Same total area • 256 PEs
• AlexNet CONV layers • Batch size = 16
2 Variants of OS
Norm. Energy/Op
1.5
Normalized
1
Energy/MAC
0.5
0
WS
WS OSA
OSA OSB
OSB OSC
OSC NLR
NLR Row
RS
Stationary
Dataflows
CNN Dataflows
[Chen et al., ISCA 2016] 29
Energy-Efficient Dataflow:
Row Stationary (RS)
Input Fmap
Filter Output Fmap
* =
31
32 1D Row Convolution in PE
Input Fmap
Filter a b c d e Partial Sums
a b c a b c
* =
Reg File PE
c b a
e d c b a
32
33 1D Row Convolution in PE
Input Fmap
Filter a b c d e Partial Sums
a b c a b c
* =
Reg File PE
c b a
e d c b a
33
34 1D Row Convolution in PE
Input Fmap
Filter a b c d e Partial Sums
a b c a b c
* =
Reg File PE
c b a
e d c b
a
b
34
35 1D Row Convolution in PE
Input Fmap
Filter a b c d e Partial Sums
a b c a b c
* =
Reg File PE
c b a
e d c
b a
c
35
36 1D Row Convolution in PE
Reg File PE
c b a
e d c
b a
c
36
37 2D Convolution in PE Array
PE 1
Row 1 * Row 1
* =
37
38 2D Convolution in PE Array
Row 1
PE 1
Row 1 * Row 1
PE 2
Row 2 * Row 2
PE 3
Row 3 * Row 3
* =
38
39 2D Convolution in PE Array
Row 1 Row 2
PE 1 PE 4
Row 1 * Row 1 Row 1 * Row 2
PE 2 PE 5
Row 2 * Row 2 Row 2 * Row 3
PE 3 PE 6
Row 3 * Row 3 Row 3 * Row 4
* =
* =
39
40 2D Convolution in PE Array
PE 1 PE 4 PE 7
Row 1 * Row 1 Row 1 * Row 2 Row 1 * Row 3
PE 2 PE 5 PE 8
Row 2 * Row 2 Row 2 * Row 3 Row 2 * Row 4
PE 3 PE 6 PE 9
Row 3 * Row 3 Row 3 * Row 4 Row 3 * Row 5
* =
* =
* =
40
41 Convolutional Reuse Maximized
PE 1 PE 4 PE 7
Row 1 * Row 1 Row 1 * Row 2 Row 1 * Row 3
PE 2 PE 5 PE 8
Row 2 * Row 2 Row 2 * Row 3 Row 2 * Row 4
PE 3 PE 6 PE 9
Row 3 * Row 3 Row 3 * Row 4 Row 3 * Row 5
41
42 Convolutional Reuse Maximized
PE 1 PE 4 PE 7
Row 1 * Row 1 Row 1 * Row 2 Row 1 * Row 3
PE 2 PE 5 PE 8
Row 2 * Row 2 Row 2 * Row 3 Row 2 * Row 4
PE 3 PE 6 PE 9
Row 3 * Row 3 Row 3 * Row 4 Row 3 * Row 5
42
43 Maximize 2D Accumulation in PE Array
PE 1 PE 4 PE 7
Row 1 * Row 1 Row 1 * Row 2 Row 1 * Row 3
PE 2 PE 5 PE 8
Row 2 * Row 2 Row 2 * Row 3 Row 2 * Row 4
PE 3 PE 6 PE 9
Row 3 * Row 3 Row 3 * Row 4 Row 3 * Row 5
43
Dimensions Beyond 2D Convolution
1 Multiple Fmaps 2 Multiple Filters 3 Multiple Channels
44
Filter Reuse in PE
1 Multiple Fmaps 2 Multiple Filters 3 Multiple Channels
C
Filter 1 Fmap 1 Psum 1
C
H
H
Channel 1 Row 1
* Row 1 = Row 1
R
C
R
Filter 1 Fmap 2 Psum 2
H Channel 1 Row 1
* Row 1 = Row 1
45
Filter Reuse in PE
1 Multiple Fmaps 2 Multiple Filters 3 Multiple Channels
C
Filter 1 Fmap 1 Psum 1
C
H
H
Channel 1 Row 1
* Row 1 = Row 1
R
C
R
Filter 1 Fmap 2 Psum 2
H Channel 1 Row 1
*
share the same filter row
Row 1 = Row 1
46
Filter Reuse in PE
1 Multiple Fmaps 2 Multiple Filters 3 Multiple Channels
C
Filter 1 Fmap 1 Psum 1
C
H
H
Channel 1 Row 1
* Row 1 = Row 1
R
C
R
Filter 1 Fmap 2 Psum 2
H Channel 1 Row 1
*
share the same filter row
Row 1 = Row 1
47
Fmap Reuse in PE
1 Multiple Fmaps 2 Multiple Filters 3 Multiple Channels
R
C
Channel 1 Row 1
* Row 1 = Row 1
H
C
Filter 2 Fmap 1 Psum 2
* =
H
R
Channel 1 Row 1 Row 1 Row 1
R
48
Fmap Reuse in PE
1 Multiple Fmaps 2 Multiple Filters 3 Multiple Channels
R
C
Channel 1 Row 1
* Row 1 = Row 1
H
C
Filter 2 Fmap 1 Psum 2
* =
H
R
Channel 1 Row 1 Row 1 Row 1
R
share the same fmap row
49
Fmap Reuse in PE
1 Multiple Fmaps 2 Multiple Filters 3 Multiple Channels
R
C
Channel 1 Row 1
* Row 1 = Row 1
H
C
Filter 2 Fmap 1 Psum 2
* =
H
R
Channel 1 Row 1 Row 1 Row 1
R
share the same fmap row
50
Channel Accumulation in PE
1 Multiple Fmaps 2 Multiple Filters 3 Multiple Channels
C
C
Channel 1 Row 1
* Row 1 = Row 1
R H
R
Filter 1 Fmap 1 Psum 1
* =
H
Channel 2 Row 1 Row 1 Row 1
51
Channel Accumulation in PE
1 Multiple Fmaps 2 Multiple Filters 3 Multiple Channels
C
C
Channel 1 Row 1
* Row 1 = Row 1
R H
R
Filter 1 Fmap 1 Psum 1
* =
H
Channel 2 Row 1 Row 1 Row 1
accumulate psums
Row 1 + Row 1 = Row 1
52
Channel Accumulation in PE
1 Multiple Fmaps 2 Multiple Filters 3 Multiple Channels
C
C
Channel 1 Row 1
* Row 1 = Row 1
R H
R
Filter 1 Fmap 1 Psum 1
* =
H
Channel 2 Row 1 Row 1 Row 1
accumulate psums
53
54 DNN Processing – The Full Picture
PE PE PE
Row 1 * Row 1 Row 1 * Row 2 Row 1 * Row 3
PE PE PE
Row 2 * Row 2 Row 2 * Row 3 Row 2 * Row 4
PE PE PE
Row 3 * Row 3 Row 3 * Row 4 Row 3 * Row 5
Filter 1 Image
Fmap 1 & 2 Psum 1 & 2
Multiple fmaps:
* =
Filter 1 & 2 Image
Fmap 1 Psum 1 & 2
Multiple filters:
* =
Filter 1 Image
Fmap 1 Psum
Multiple channels:
* =
54
Optimal Mapping in Row Stationary
CNN Configurations
C
M
C
H
R E
1 1 1
R H E
Optimization
…
…
C C
Compiler
R E
M H
N
R N E
H
PE PE PE
Row 3 * Row 3 Row 3 * Row 4 Row 3 * Row 5
ALU ALU ALU ALU
Filter 1 Image
Fmap 1 & 2 Psum 1 & 2
ALU ALU ALU ALU Multiple fmaps:
* =
Filter 1 & 2 Image
Fmap 1 Psum 1 & 2
Multiple filters:
ALU ALU ALU ALU
* =
Filter 1 Image
Fmap 1 Psum
Multiple channels:
* =
56
57 Evaluate Reuse in Different Dataflows
• Weight Stationary
– Minimize movement of filter weights
• Output Stationary
– Minimize movement of partial sums
• No Local Reuse
– No PE local storage. Maximize global buffer size.
• Row Stationary
Normalized Energy Cost*
Evaluation Setup
ALU 1× (Reference)
• same total area RF ALU 1×
• 256 PEs PE ALU 2×
• AlexNet Buffer ALU 6×
• batch size = 16 DRAM ALU 200×
57
Variants of Output Stationary
Parallel
Output Region E E E
E E E
Targeting Targeting
Notes
CONV layers FC layers
58
Dataflow Comparison: CONV Layers
2
psums
weights
1.5
activations
Normalized
1
Energy/MAC
0.5
0
WS OSA OSB OSC NLR RS
CNN Dataflows
1.5 ALU
RF
Normalized
1 NoC
Energy/MAC
buffer
0.5 DRAM
0
WS OSA OSB OSC NLR RS
CNN Dataflows
2 psums
weights
1.5 activations
Normalized
Energy/MAC 1
0.5
0
WS OSA OSB OSC NLR RS
CNN Dataflows
1.5e10 ALU
Normalized RF
Energy 1.0e10 NoC
(1 MAC = 1) buffer
0.5e10 DRAM
0
L1 L2 L3 L4 L5 L6 L7 L8
CONV Layers FC Layers
1.5e10 ALU
Normalized RF
Energy 1.0e10 NoC
(1 MAC = 1) buffer
0.5e10 DRAM
0
L1 L2 L3 L4 L5 L6 L7 L8
CONV Layers FC Layers
RF dominates
63
Row Stationary: Layer Breakdown
2.0e10
1.5e10 ALU
Normalized RF
Energy 1.0e10 NoC
(1 MAC = 1) buffer
0.5e10 DRAM
0
L1 L2 L3 L4 L5 L6 L7 L8
CONV Layers FC Layers
Normalized RF
Energy 1.0e10 NoC
(1 MAC = 1) buffer
0.5e10 DRAM
0
L1 L2 L3 L4 L5 L6 L7 L8
CONV Layers FC Layers
66
67 Eyeriss Deep CNN Accelerator
Link Clock Core Clock DCNN Accelerator
14×12 PE Array
Filter Filt
…
Global Fmap
Input Fmap Buffer …
Decomp SRAM Psum
…
Output Fmap 108KB Psum
…
Comp ReLU
…
Off-Chip DRAM
64 bits
[Chen et al., ISSCC 2016] 67
Data Delivery with On-Chip Network
Link Clock Core Clock DCNN Accelerator
14×12 PE Array
Filter Patterns
Data Delivery Filt
…
Buffer Fmap
Input Image SRAM …
Decomp Psum
108K …
Output Image B
Filter Fmap
ReL Psum
…
DeliveryCompDelivery
U
…
..
..
..
..
.. ..
14 14
3 13
14
3 13 5
12 12
3 13
13
5
3 13
..
..
..
..
.. ..
14 14
3 13
14
3 13 5
12 Unused PEs 12
3 13 are
13
3 13 Clock Gated 5
Global
Y-Bus
71
Data Delivery with On-Chip Network
Link Clock Core Clock DCNN Accelerator
14×12 PE Array
Filter Patterns
Data Delivery Filt
…
Buffer Img
Input Image SRAM …
Decomp Psum
108K …
Output Image B
Filter Image
ReL Psum
…
DeliveryCompDelivery
U
…
Compared to Broadcast,Off-Chip
Multicast saves >80% of NoC energy
DRAM
64 bits
72
Chip Spec & Measurement Results
Technology TSMC 65nm LP 1P9M
On-Chip Buffer 108 KB
4000 µm
# of PEs 168
Scratch Pad / PE 0.5 KB Global Spatial Array
Core Frequency 100 – 250 MHz Buffer (168 PEs)
Peak Performance 33.6 – 84.0 GOPS
4000 µm
Word Bit-width 16-bit Fixed-Point
Filter Width: 1 – 32
Filter Height: 1 – 12
Natively Supported Num. Filters: 1 – 1024
DNN Shapes Num. Channels: 1 – 1024
Horz. Stride: 1–12
Vert. Stride: 1, 2, 4
To support 2.66 GMACs [8 billion 16-bit inputs (16GB) and 2.7 billion
outputs (5.4GB)], only requires 208.5MB (buffer) and 15.4MB (DRAM)
74
Benchmark – AlexNet Performance
Image Batch Size of 4 (i.e. 4 frames of 227x227)
Core Frequency = 200MHz / Link Frequency = 60 MHz
Power Latency # of MAC Active # Buffer Data DRAM Data
Layer
(mW) (ms) (MOPs) of PEs (%) Access (MB) Access (MB)
1 332 20.9 422 154 (92%) 18.5 5.0
2 288 41.9 896 135 (80%) 77.6 4.0
3 266 23.6 598 156 (93%) 50.2 3.0
4 235 18.4 449 156 (93%) 37.4 2.1
5 236 10.5 299 156 (93%) 24.9 1.3
Total 278 115.3 2663 148 (88%) 208.5 15.4
51682 operand* access/input image pixel
à 506 access/pixel from buffer + 37 access/pixel from DRAM
*operand = weight, activation, psum 75
Comparison with GPU
This Work NVIDIA TK1 (Jetson Kit)
Technology 65nm 28nm
Clock Rate 200MHz 852MHz
# Multipliers 168 192
Buffer: 108KB Shared Mem: 64KB
On-Chip Storage
Spad: 75.3KB Reg File: 256KB
Word Bit-Width 16b Fixed 32b Float
Throughput1 34.7 fps 68 fps
Measured Power 278 mW Idle/Active2: 3.7W/10.2W
DRAM Bandwidth 127 MB/s 1120 MB/s 3
1. AlexNet CONV Layers
2. Board Power
3. Modeled from [Tan, SC 2011]
76
From Architecture to System
https://vimeo.com/154012013
77
Summary of DNN Dataflows
• Weight Stationary
– Minimize movement of filter weights
– Popular with processing-in-memory architectures
• Output Stationary
– Minimize movement of partial sums
– Different variants optimized for CONV or FC layers
• No Local Reuse
– No PE local storage à maximize global buffer size
• Row Stationary
– Adapt to the NN shape and hardware constraints
– Optimized for overall system energy efficiency
78
MICRO 2016 Papers in the Taxonomy
79
Fused Layer
• Dataflow across multiple layers
2
eDRAM (DaDianNao)
• Advantages of eDRAM
– 2.85x higher density than SRAM
– 321x more energy-efficient than DRAM (DDR3)
• Store weights in eDRAM (36MB)
– Target fully connected layers since dominated by weights
16 Parallel
Tiles
• Conductance = Weight V1
• Voltage = Input G1
• Current = Voltage × Conductance
• Sum currents for addition I1 = V1×G1
V2
G2
Output = ∑Weight × Input
I2 = V2×G2
Input = V1, V2, …
I = I1 + I2
Filter Weights = G1, G2, … (conductance)
= V1×G1 + V2×G2
• Advantages
– High Density (< 10nm x 10nm size*)
• ~30x smaller than SRAM**
• 1.5x smaller than DRAM**
– Non-Volatile
– Operates at low voltage
– Computation within memory (in situ)
• Reduce data movement
ADC
Eight 128x128
arrays per IMA
2
Number Representation
23 Range Accuracy
1 8
FP32 S E M 10-38 – 1038 .000006%
1 5 10
FP16 S E M 6x10-5 - 6x104 .05%
1 31
Int32 S M 0 – 2x109 ½
1 15
Int16 S M 0 – 6x104 ½
1 7
Int8 S M 0 – 127 ½
Weight
(N-bits)
Round Round to
X + to N Acc 1.5N of 2N
NxN
multiply
Activation
(2N-bits)
(N-bits)
5
Methods to Reduce Bits
Example: 16-bit à 8-bits
• Quantization/Rounding
211 + 29 + 26 + 21 = 2626 (overflow)
• Dynamic Fixed Point
– Rescale and Reduce bits 0100101001000010
AlexNet AlexNet
(Layer 1) (Layer 6)
Image Source:
Moons et al,
WACV 2016
Top-1 accuracy
on of CaffeNet
on ImageNet
8
Nvidia PASCAL
Reduce Bit-width à
Shorter Critical Path
à Reduce Voltage
Power reduction of
2.56x vs. 16-bit fixed
On AlexNet Layer 2
• Network Compression
– Low Rank Approximation
– Weight Sharing and Vector Quantization
• Pruning
– Weights
– Activations
• Network Architectures
14
Low Rank Approximation
• Low Rank approximation
– Tensor decomposition
based on singular value
decomposition (SVD)
– Filter Clustering with
modified K-means
– Fine Tuning
• Speed up by 1.6 – 2.7x on CPU/GPU for CONV1,
CONV2 layers
• Reduce size by 5 - 13x for FC layer
• < 1% drop in accuracy
[Denton et al., NIPS 2014] 15
Low Rank Approximation on Phone
• Rank selection per Layer
• Tucker Decomposition (extension of SVD)
• Fine tuning
18
Sparsity in Fmaps
Many zeros in output fmaps after ReLU
ReLU
9 -1 -3 9 0 0
1 -5 5 1 0 5
-2 6 -1 0 6 0
0.2
0
1 2 3 4 5
CONV Layer 19
I/O Compression in Eyeriss
Link Clock Core Clock DCNN Accelerator
14×12 PE Array
Filter Filt
…
Run-Length Compression (RLC)
Input Image Buffer Img
…
Example:
SRAM
Decomp Psum
Input: 0, 0, 12, 0, 0, 0, 0, 53, 0, 0, 22, …
…
108KB (64b): RunLevelRunLevel RunLevelTerm
Output Image Output
Psum 2 12 4 53 2 22 0
…
Comp ReLU
5b 16b 5b 16b 5b 16b 1b
…
Off-Chip DRAM
64 bits
[Chen et al., ISSCC 2016] 20
Compression Reduces DRAM BW
Uncompressed Compressed
1.2×
66 1.4×
DRAM Access (MB)
5 1.7×
DRAM 44 1.8× Uncompressed
Access 3 1.9× Fmaps + Weights
(MB) 22
1 RLE Compressed
00 Fmaps + Weights
11 22 33 44 55
AlexNet Conv Layer
AlexNet Conv Layer
1
Input
Psum 0 1
Partial Sum
Scratch Pad 0
(24x16b REG) Reset
Pruned Weights
CONV Layers: 42-78%
Fully Connected Layers: 77-96%
27
Speed up of Weight Pruning on CPU/GPU
On Fully Connected Layers
Average Speed up of 3.2x on GPU, 3x on CPU, 5x on mGPU
Batch size = 1
Input ~a 0 a 1 0 a3
⇥ Output
~b Dequantize Weight
0 1 0 1 0 1
P E0 w0,0 w0,1 0 w0,3 b0 b0
B C B C B C
P E1 B 0 0 w1,2 0 C B b1 C B b1 C
B C B C B C
P E2 B 0 w2,1 0 w2,3 C B b2 C B 0 C
Weights B C B C B C
P E3 B 0 0 0 0 C
B B
C B b3 C
C ReLU
B
B b3 C
C
B C=B C ) B C
B 0 0 w4,2 w4,3 C B b4 C B 0 C
B C B C B C
Bw5,0 0 0 0 C B b5 C B b5 C
B C B C B C
B C B C B C Keep track of location
@ 0 0 0 w6,3 A @ b6 A @ b6 A
0 w7,1 0 0 b7 0
Figure Source:
Stanford cs231n
Figure Source:
Stanford cs231n
Figure Source:
Stanford cs231n
• Input (http://image-net.org/)
– Sample subset from ImageNet Validation Dataset
3
Metrics for DNN Algorithm
• Accuracy
• Network Architecture
– # Layers, filter size, # of filters, # of channels
• # of Weights (storage capacity)
– Number of non-zero (NZ) weights
• # of MACs (operations)
– Number of non-zero (NZ) MACS
4
Metrics of DNN Algorithms
Metrics AlexNet VGG-16 GoogLeNet (v1) ResNet-50
Accuracy (top-5 error)* 19.8 8.80 10.7 7.02
Input 227x227 224x224 224x224 224x224
# of CONV Layers 5 16 21 49
Filter Sizes 3, 5,11 3 1, 3 , 5, 7 1, 3, 7
# of Channels 3 - 256 3 - 512 3 - 1024 3 - 2048
# of Filters 96 - 384 64 - 512 64 - 384 64 - 2048
Stride 1, 4 1 1, 2 1, 2
# of Weights 2.3M 14.7M 6.0M 23.5M
# of MACs 666M 15.3G 1.43G 3.86G
# of FC layers 3 3 1 1
# of Weights 58.6M 124M 1M 2M
# of MACs 58.6M 124M 1M 2M
Total Weights 61M 138M 7M 25.5M
Total MACs 724M 15.5G 1.43G 3.9G
*Single crop results: https://github.com/jcjohnson/cnn-benchmarks
5
Metrics of DNN Algorithms
Metrics AlexNet VGG-16 GoogLeNet (v1) ResNet-50
Accuracy (top-5 error)* 19.8 8.80 10.7 7.02
# of CONV Layers 5 16 21 49
# of Weights 2.3M 14.7M 6.0M 23.5M
# of MACs 666M 15.3G 1.43G 3.86G
# of NZ MACs** 394M 7.3G 806M 1.5G
# of FC layers 3 3 1 1
# of Weights 58.6M 124M 1M 2M
# of MACs 58.6M 124M 1M 2M
# of NZ MACs** 14.4M 17.7M 639k 1.8M
Total Weights 61M 138M 7M 25.5M
Total MACs 724M 15.5G 1.43G 3.9G
# of NZ MACs** 409M 7.3G 806M 1.5G
8
ASIC Benchmark (e.g. Eyeriss)
ASIC Specs
Process Technology 65nm LP TSMC (1.0V)
Total core area (mm2) /total # of multiplier 0.073
Total on-Chip memory (kB) / total # of multiplier 1.14
Measured or Simulated Measured
If Simulated, Syn or PnR? Which corner? n/a
9
ASIC Benchmark (e.g. Eyeriss)
Layer by layer breakdown for AlexNet CONV layers
Example: FPGAs
12
Hardware for Training
Error:
e = (y-z)
Minimize S(y-z)2
2
Training Optimization Problem
qn+1 = qn – a∙dE(qn)/dq
• E(q) = Se(q)2
= S(y(q)-z)2
error e back-propagation
5
Chain rule -> Back propagation
6
Per Layer Calculations
y = f(x)
Where
xjk = yjk-1
or
yk = fk(yk-1,q)
7
Layer Operation Composition
8
Chain rule
9
Back propagation
• y00 = (a*x0 + b*x1)
y01 = ….
y10 = y00*c + y01*d
• dy10/da = dy10/dy00 * dy00/da = c * x0
a
c
*
x0 *
+ y00
+
x1 * y10
y01 *
b
d
10
Back Propagation for Addition
dy1/dy0 * 1
• y0 = a + b
a
• y1 = f(y0) dy1/dy0
y0 y1
+ F()
• dy0/da = 1
b
• dy0/db = 1
dy1/dy0 * 1
• dy1/dy0 = f’(y0)
• dy1/da = dy1/dy0 * dy0/da = dy1/dy0 * 1 = dy1/dy0
• dy1/db = dy1/dy0 * dy0/db = dy1/dy0 * 1 = dy1/dy0
11
Back Propagation for Multiplication
dy1/dy0 * b
• y0 = a * b
a
• y1 = f(y0) dy1/dy0
y0 y1
* F()
• dy0/da = b b
• dy0/db = a dy1/dy0 * a
• dy1/dy0 = f’(y0)
• dy1/da = dy1/dy0 * dy0/da = dy1/dy0 * b
• dy1/db = dy1/dy0 * dy0/db = dy1/dy0 * a
12
Back propagation for Network
• y00 = (a*x0 + b*x1)
y01 = ….
y10 = y00*c + y01*d
• dy10/da = dy10/dy00 * dy00/da = c * x0
a
c*x0 c
1*y00
* c
x0 1*c * 1
+ 1
y00 +
x1 * y10
* 1
b
d 13
Back Propagation Recipe
Start point
• Select a initial set of weights (q) and an input (x)
Forward pass
• For all layers
– Compute layer outputs use as input for next layer (and save for later)
Backward pass
• For all layers (with output of previous layer and gradient of next layer)
– Compute gradient, i.e., (partial) derivative, for layer
– Back-propagate gradient to previous layer
– Compute (partial) derivatives for (local) weights of layer
14
Back Propagation
Forward Pass ->
M M
C a
(
F a C
(
n F n
p
o e p e o
- a
Convolution (n) a n
+
n O 1
1 t I t v
v u
)
)
n t
C
(
(
n GG n
O
o r rr II B
- a
u Back propagation (n) P
+
n aa nn
1 t 1
v d dd
)
)
a Dw very small
aj +
x Dwij SR Dw’ij wij
x E(Dw’ij) = Dwij
gj
Issue:
• N = 1 is often too noisy, weights
may oscillate around the
minimum
Solution:
• Use batches of N inputs…
• Max theoretical speed up: N
17
Parallel creation of gradient
18
Batchto Parameter
One method achieve scaleUpdate
is parallelization
Parameter Server p’ = p + ∆p
∆p p’
Model!
Workers
Data!
Shards
Large scale distributed deep networks
J Dean et al (2012)
[Dean et al., NIPS 2012] 19
Training Uses a Lot of Memory
GPU memory usage proportional GPU
to network depth memory
Feature
maps
Network
topology
40000
Gradients
GPU memory usage (MB)
Feature maps
32000
Weights
24000
16000
8000
0
10 layers 110 layers 210 layers 310 layers 410 layers
VGG-16
Issue
Sigmoid • A null gradient results in no
learning, which happens if:
Solution
• Initialize weighs so the average
value is zero, i.e., work in the
interesting zone of the activation
functions
ReLU 23
Non-differential operations
Issue
• Discrete activation function / weights
– extreme case is binary net
• Derivative not well defined
Solution
• Use approximate derivative, or
• Discretize a-posteriori
24
Model Overfitting
Problem:
• Neural net learns too specifically from input set,
rather than generalizing from input, called overfitting
• Overfitting can be a result of too many parameters in
model
Solution:
• Dropout – turn off neurons at random; other neurons
will take care of their job.
– + Reliability
– - Redundancy (-> pruning)
25
Architecture Challenges for Training
26
References
2
References (Alphabetical by Author)
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3
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