EC6612 VLSI DESIGN Laboratory Question Set
EC6612 VLSI DESIGN Laboratory Question Set
Regulations-R-2013
SIXTH SEMESTER
1) Design and simulate a 4-bit ripple carry adder using Verilog and verify its
functionality using a test bench and implement the same in FPGA. (100)
2) Design and simulate a 4-bit carry save adder using Verilog and verify its
functionality using a test bench and implement the same in FPGA. (100)
3) Design and simulate a 4-bit Carry look ahead adder using Verilog and
verify its functionality using a test bench and implement the same in FPGA.
(100)
4) Design and simulate a CMOS inverter using a cadence tool and verify the
DC transfer characteristics’ and transient analysis. (100)
5) Design and simulate a 4-bit array multiplier using Verilog and verify its
functionality using a test bench.(100)
6) Design and simulate a 4-bit up counter using Verilog and verify its
functionality using a test bench and implement the same in FPGA. (100)
10) Design and simulate a 1 to 8 de-multiplexer using Verilog and verify its
functionality using a test bench and implement the same in FPGA.(100)
11) Design and simulate a Wallace tree multiplier using Verilog and verify
its functionality using a test bench.(100)
12 a) Design and simulate the full adder using two half adders using Verilog and
verify its functionality using a test bench. (50)
b) Design and simulate the full subtractor using Verilog and verify its
functionality using a test bench.(50)
13) Design and simulate a 4 bit booth multiplier using Verilog and verify
its functionality using a test bench.(100)
15) Design and simulate Mealy model using Verilog and verify its
functionality using a test bench. (100)
16) Design and simulate Moore model using Verilog and verify its
functionality using a test bench. (100)
17) Design and simulate a 4 bit signed multiplier using Verilog and verify
its functionality using a test bench.(100)
18) Design and simulate a up-down counter using Verilog verify its
functionality using a test bench and implement the same in FPGA. (100)
19) Design and simulate a 4 bit Johnson counter using Verilog verify its
functionality using a test bench and implement the same in FPGA. (100)
Aim/Identification - 10
Procedure/Algorithm -10
Program - 30
Execution/Outputs - 30
Results - 10
Viva - 10
Total - 100