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Huawei OSN 3500 cxl4 Hardware Description
Huawei OSN 3500 cxl4 Hardware Description
Hardware Description
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1.1 CXL4
This topic describes the version, application, functions, working principle,
front panel, and technical specifications of the CXL4 (1xSTM-4 SCC unit,
cross-connect unit, timing unit, and line unit integrated board). This topic also
describes how to configure and commission the CXL4.
5.2.1 Version Description
The CXL4 is available in several functional versions. The functions provided
by the functional versions are different.
5.2.2 Application
The CXL4 provides service processing, service grooming, clock input/output,
and communication control functions in the OptiX OSN system.
5.2.3 Functions and Features
The CXL4 processes SDH signals, controls communication, grooms services,
and inputs/outputs clock signals.
5.2.4 Working Principle and Signal Flow
The CXL4 consists of the synchronous timing module, O/E converting
module, MUX/DEMUX module, SDH overhead processing module,
communication and control module, cross-connect module, power module,
and other modules.
5.2.5 Front Panel
The front panel of the Q2CXL4 has indicators, an optical interface, functional
button switches, a bar code, and a laser safety class label. The front panel of
the Q3CXL4 has indicators, an optical interface, a bar code, functional button
switches, and a laser safety class label.
5.2.6 Jumpers and DIP Switches
The CXL4 has a jumper, which is used to set the enable state of the battery,
and a DIP switch, which is used to set the running state of the equipment.
5.2.7 Valid Slots
The CXL4 must be installed in a valid slot in the subrack. Otherwise, the
CXL4 cannot work normally.
5.2.8 Feature Code
The number code that follows the board name in the bar code is the feature
code of the board. The feature code of the CXL4 indicates the type of optical
interface.
5.2.9 Configuring and Commissioning the Board
After you select a correct board, you need to configure and commission the
board. The following tasks need to be performed: checking the hardware of
the board, configuring the board, commissioning the board, and checking the
operation of the board.
5.2.10 Parameter Settings
The physical slot that houses the CXL4 is different from the logical slot
displayed on the U2000. You can set parameters for the CXL4 by using the
U2000.
5.2.11 Maintaining the Board
This topic describes the alarms and faults that may occur when the board
operates. This topic also provides the methods and precautions to be taken for
rectifying the faults.
5.2.12 List of Alarms
This topic lists the alarms that may occur when the board operates. The alarms
are reported according to the logical board on the U2000.
5.2.13 List of Performance Events
This topic lists the performance events that may occur when the board
operates. The performance events are reported according to the logical board
on the U2000.
5.2.14 Technical Specifications
The technical specifications of the CXL4 include the parameters specified for
optical interfaces, cross-connect capacity, clock access capability, laser safety
class, mechanical specifications, and power consumption.
Functional versions The CXL4 is available in two functional versions, namely, Q2 and
Q3. The Q3CXL4 is discontinued.
Differences The differences between the Q3CXL4 and the Q2CXL4 are as
follows:
The Q3CXL4 supports the transmission of the DCC information
over the two-channel external clock interface.
The Q3CXL4 hardware supports the CF card.
The Q3CXL4 supports the transparent transmission of DCC bytes
when the TPS protection group is configured.
Substitution The Q5CXLLN can substitute for the Q2CXL4 that operates at the
same line rate by using the board version replacement function.
1.1.2 Application
The CXL4 provides service processing, service grooming, clock input/output,
and communication control functions in the OptiX OSN system.
The CXL provides the other boards in the system with the timing information,
processes the SDH signals, grooms the services between line boards or
tributary boards, communicates with the other boards in the system, and
performs the configuration and management functions for the other boards in
the system.
Figure 5-8 shows the position of the CXL in the system.
CXL
Line O/E Line
SDH converting
processing unit unit
Auxiliary
Auxiliary interface
SCC unit unit
Table 1-2 Functions and features of the SDH processing unit of the CXL4
Function and Feature CXL4
Specifications of the optical module Supports the detection and query of the
information about the optical module.
Provides the ALS function. The optical
interface supports the setting of the on/off
state of a laser.
Table 1-3 Functions and features of the SCC unit of the CXL4
Function and Feature CXL4
Table 1-5 Functions and features of the clock unit of the CXL4
Function and Feature CXL4
Power monitor
F&f interface
Phone
Phoneinterface
interface
Boot SEI
Flash RAM NVRAM S1-S4 interface
ROM
+3.3 V Power Fuse -48 V/-60 V
module -48 V/-60 V
Power
module
Power monitor
F&f interface
CF Phone
Phoneinterface
interface
Boot Flash RAM NVRAM SEI
card ROM S1-S4 interface
+3.3 V Power Fuse -48 V/-60 V
module -48 V/-60 V
Power
module
CXL4
STAT
ACTX
ACTC
PROG
SRVX
SRVL
SYNC
ALMC
CLASS 1
LASER
PRODUCT
OUT
IN
RESET
ALM CUT
CXL4
Figure 5-12 shows the appearance of the front panel of the Q3CXL4.
Figure 1-5 Front panel the Q3CXL4
CXL4
STAT
ACTX
ACTC
PROG
SRVX
SRVL
SYNC
ALMC
CLASS 1
LASER
PRODUCT
OUT
IN
RESET
ALM CUT
CF R/W
CF ON/OFF
CXL4
1.1.5.0.15 Indicators
The front panel of the board has the following indicators:
Board hardware status indicator (STAT) – two colors (red and green)
Active/Standby state indicator of the cross-connect unit (ACTX) – one
color (green)
Active/Standby state indicator of the SCC unit (ACTC) – one color
(green)
Board software status indicator (PROG) – two colors (red and green)
Service alarm indicator of the cross-connect unit (SRVX) – three colors
(red, green, and yellow)
Service alarm indicator of the line unit (SRVL) – three colors (red, green,
and yellow)
Synchronization clock status indicator (SYNC) – two colors (red and
green)
Alarm mute indicator (ALMC) – one color (yellow)
For the meanings of the status of the indicators, see 19 Indicators.
1.1.5.0.16 Interfaces
The front panel of the CXL4 has one optical interface and three switches.
Table 5-19 describes the types and usage of the optical interfaces and switches
of the CXL4.
RESET Warm reset Press the switch to perform a warm reset for the SCC
switch unit.
ALM CUT Alarm cut Press the switch to mute the alarm. Press the switch for
switch five seconds to mute the alarm permanently. Press the
switch again for five seconds to resume the alarm sound.
Only the Q3CXL4 supports the CF card. The Q2CXL4 does not support the CF card.
The jumper and DIP switch are used for test and maintenance. Do not change
the setting of the jumper at random. Otherwise, the board may become faulty.
Figure 5-13 shows the jumper and DIP switch of the Q2CXL4.
Figure 1-6 Positions of the jumper and DIP switch of the Q2CXL4
3 2 1
J3
CF
card
SCC unit
1
2
3 SW1
4
Figure 5-14 shows the jumper and DIP switch of the Q3CXL4.
Figure 1-7 Positions of the jumper and DIP switch of the Q3CXL4
J7
1 2 3 SCC unit
4
3
2 SW2
1
CF
card
J3/J7 To enable the 1–2: If jumper bits (positions) 1 and 2 are capped, the
battery battery is enabled.
2–3: If jumper bits (positions) 2 and 3 are capped, the
database and clock are cleared.
Table 5-21 describes DIP switch SW1 of the Q2CXL4 and DIP switch SW2 of
the Q3CXL4.
Table 1-8 DIP switch SW1 of the Q2CXL4 and DIP switch SW2 of the Q3CXL4
DIP Switch Function Description
SW1/SW2 To set the running When a DIP switch bit is at the on position, it
state of the board indicates the binary value 1.
SW1 is a four-bit DIP switch. The values of the DIP
switch bits are queued in the descending order of the
switch bit numbers. The DIP switch bit numbered 4 is
the most significant bit. For details, refer to Table
5-22.
0b0000 Indicates the running state when the watchdog is started. It is the default
state.
0b1111 Erases the extended BIOS and system parameter area in the file system
and flash memory.
Table 1-10 Relationship between the feature code of the CXL4 and the type of
optical interface
Board Feature Code Type of Optical Interface
Table 1-11 Logical slots displayed on the U2000 for the CXL4
Board Logical Board Logical Slot
1.1.11.0.23 Troubleshooting
Table 5-25 lists the faults that occur on the CXL4 frequently and the
troubleshooting methods.
Table 1-12 Methods used to troubleshoot the faults that occur on the CXL4
frequently
Fault Symptom Common Fault Troubleshooting Method
Cause
Clock tracing failure The clock source See 23.3 Troubleshooting the Clock
priority table is Tracing Failure.
incorrectly
configured.
ECC failure The running status of Check whether the running status
the board becomes of the board is correct. See 19.2
abnormal. Alarm Indicators on the Boards to
The optical fibers are obtain the meanings of the status
incorrectly of the indicators.
connected. Check whether the optical fibers
are correctly connected.
Power supply alarm The jumper that Check whether the jumper that
controls the input controls the input voltage is
voltage is incorrectly correctly set. For information on
set. how to set the jumper, see 5.2.6
Jumpers and DIP Switches.
See General Precautions to get familiar with the precautions to be taken for replacing
a board before you replace the board.
For information on how to replace the CXL4, see Replacing a CXL Board.
1.1.12.1 Q2CXL4
1.1.12.1.25 ECXL
APS_FAIL APS_INDI BD_STATUS
CHIP_FAIL BUS_ERR CHIP_ABN
EXT_SYNC_LOS CLK_NO_TRACE_MODE COMMUN_FAIL
HSC_UNAVAIL FPGA_ABN HARD_BAD
LPS_UNI_BI_M K1_K2_M K2_M
NO_BD_SOFT LTI MS_APS_INDI_EX
OTH_HARD_FAIL OOL OTH_BD_STATUS
SWITCH_DISABLE POWER_ABNORMAL S1_SYN_CHANGE
SYNC_F_M_SWITCH SYN_BAD SYNC_C_LOS
TEST_STATUS SYNC_LOCKOFF TEMP_OVER
W_OFFLINE W_R_FAIL TIME_NOT_SUPPORT
TIME_NO_TRACE_MOD TIME_LOS TIME_FORCE_SWITCH
E
EXT_TIME_LOC NP1_SW_INDI NP1_SW_FAIL
RPS_INDI
1.1.12.1.26 GSCC
APS_MANUAL_STOP BD_AT_LOWPOWER BD_NOT_INSTALLED
BD_STATUS BOOTROM_BAD CFCARD_FAILED
CFCARD_OFFLINE CFCARD_W_R_DISABLED COMMUN_FAIL
DBMS_ERROR DBMS_PROTECT_MODE DCC_CHAN_LACK
FPGA_ABN HARD_BAD HSC_UNAVAIL
MSSW_DIFFERENT NE_POWER_OVER NESF_LOST
NESTATE_INSTALL LAN_LOC PATCH_ERR
PATCH_PKGERR PATCH_NOT_CONFIRM PATCHFILE_NOTEXIST
POWER_ABNORMAL POWER_FAIL REG_MM
RINGMAPM_MM RTC_FAIL SECU_ALM
SQUTABM_MM SWDL_ACTIVATED_TIME SWDL_AUTOMATCH_IN
OUT H
SWDL_INPROCESS SWDL_CHGMNG_NOMAT SWDL_COMMIT_FAIL
CH
SWDL_NEPKGCHECK TEMP_OVER SWDL_ROLLBACK_FAIL
SYNC_FAIL BIOS_STATUS WRG_BD_TYPE
CFCARD_FULL PATCH_DEACT_TIMEOUT NP1_MANUAL_STOP
PATCH_ACT_TIMEOU STORM_CUR_QUENUM_O LCS_DAYS_OF_GRACE
T VER
LCS_EXPIRED LCS_FILE_NOT_EXIST SYSLOG_COMM_FAIL
SEC_RADIUS_FAIL NE_CFG_CONFLICT
1.1.12.1.27 Q1SL4
ALM_ALS AU_AIS AU_CMM
AU_LOP B1_EXC B1_SD
B2_EXC B2_SD B3_EXC
B3_SD BD_STATUS C2_VCAIS
BIP8_ECC C2_PDI FPGA_ABN
CHIP_FAIL COMMUN_FAIL HP_RDI
FSELECT_STG HP_LOM HP_TIM
HP_REI HP_SLM J0_MM
HP_UNEQ IN_PWR_ABN LOOP_ALM
LASER_MOD_ERR LASER_SHUT LSR_WILL_DIE
LSR_COOL_ALM LSR_NO_FITED MS_REI
MS_AIS MS_RDI OH_LOOP
NO_BD_SOFT R_LOF POWER_ABNORMAL
OUT_PWR_ABN SLAVE_WORKING R_LOS
R_LOC TEM_HA SPARE_PATH_ALM
R_OOF TF TEM_LA
T_LOSEX PS TR_LOC
TEST_STATUS W_R_FAIL MOD_TYPE_MISMATCH
1.1.12.2 Q3CXL4
1.1.12.2.28 ECXL
APS_FAIL APS_INDI BD_STATUS
CHIP_FAIL BUS_ERR CHIP_ABN
EXT_SYNC_LOS CLK_NO_TRACE_MODE COMMUN_FAIL
HSC_UNAVAIL FPGA_ABN HARD_BAD
LPS_UNI_BI_M K1_K2_M K2_M
NO_BD_SOFT LTI MS_APS_INDI_EX
OTH_HARD_FAIL OOL OTH_BD_STATUS
SWITCH_DISABLE POWER_ABNORMAL S1_SYN_CHANGE
SYNC_F_M_SWITCH SYN_BAD SYNC_C_LOS
TEST_STATUS SYNC_LOCKOFF TEMP_OVER
W_OFFLINE W_R_FAIL TIME_NOT_SUPPORT
TIME_NO_TRACE_MOD TIME_LOS TIME_FORCE_SWITCH
E
EXT_TIME_LOC NP1_SW_INDI NP1_SW_FAIL
RPS_INDI
1.1.12.2.29 GSCC
APS_MANUAL_STOP BD_AT_LOWPOWER BD_NOT_INSTALLED
BD_STATUS BOOTROM_BAD CFCARD_FAILED
CFCARD_OFFLINE CFCARD_W_R_DISABLED COMMUN_FAIL
DBMS_ERROR DBMS_PROTECT_MODE DCC_CHAN_LACK
FPGA_ABN HARD_BAD HSC_UNAVAIL
MSSW_DIFFERENT NE_POWER_OVER NESF_LOST
NESTATE_INSTALL LAN_LOC PATCH_ERR
PATCH_PKGERR PATCH_NOT_CONFIRM PATCHFILE_NOTEXIST
POWER_ABNORMAL POWER_FAIL REG_MM
RINGMAPM_MM RTC_FAIL SECU_ALM
SQUTABM_MM SWDL_ACTIVATED_TIME SWDL_AUTOMATCH_IN
OUT H
SWDL_INPROCESS SWDL_CHGMNG_NOMAT SWDL_COMMIT_FAIL
CH
SWDL_NEPKGCHECK TEMP_OVER SWDL_ROLLBACK_FAIL
SYNC_FAIL BIOS_STATUS WRG_BD_TYPE
CFCARD_FULL PATCH_DEACT_TIMEOUT NP1_MANUAL_STOP
PATCH_ACT_TIMEOU STORM_CUR_QUENUM_O LCS_DAYS_OF_GRACE
T VER
LCS_EXPIRED LCS_FILE_NOT_EXIST SYSLOG_COMM_FAIL
SEC_RADIUS_FAIL NE_CFG_CONFLICT
1.1.12.2.30 Q1SL4
ALM_ALS AU_AIS AU_CMM
AU_LOP B1_EXC B1_SD
B2_EXC B2_SD B3_EXC
B3_SD BD_STATUS C2_VCAIS
BIP8_ECC C2_PDI FPGA_ABN
CHIP_FAIL COMMUN_FAIL HP_RDI
FSELECT_STG HP_LOM HP_TIM
HP_REI HP_SLM J0_MM
HP_UNEQ IN_PWR_ABN LOOP_ALM
LASER_MOD_ERR LASER_SHUT LSR_WILL_DIE
LSR_COOL_ALM LSR_NO_FITED MS_REI
MS_AIS MS_RDI OH_LOOP
NO_BD_SOFT R_LOF POWER_ABNORMAL
OUT_PWR_ABN SLAVE_WORKING R_LOS
R_LOC TEM_HA SPARE_PATH_ALM
R_OOF TF TEM_LA
T_LOSEX PS TR_LOC
TEST_STATUS W_R_FAIL MOD_TYPE_MISMATCH
1.1.13.3.31 GSCC
XCSTMPMAX XCSTMPMIN XCSTMPCUR
CPUUSAGEMAX CPUUSAGEMIN CPUUSAGECUR
MEMUSAGEMAX MEMUSAGEMIN MEMUSAGECUR
1.1.13.3.32 Q1SL4
AUPJCHIGH AUPJCLOW AUPJCNEW
HPBBE HPCSES HPES
HPFEBBE HPFECSES HPFEES
HPFESES HPFEUAS HPSES
HPUAS MSBBE MSCSES
MSES MSFEBBE MSFECSES
MSFEES MSFESES MSFEUAS
MSSES MSUAS OSPICCVCUR
OSPICCVMAX OSPICCVMIN OSPITMPCUR
OSPITMPMAX OSPITMPMIN RPLCUR
RPLMAX RPLMIN RSBBE
RSCSES RSES RSOFS
RSSES RSUAS TLBCUR
TLBMAX TLBMIN TPLCUR
TPLMAX TPLMIN
1.1.13.4 Q3CXL4
1.1.13.4.33 GSCC
XCSTMPMAX XCSTMPMIN XCSTMPCUR
CPUUSAGEMAX CPUUSAGEMIN CPUUSAGECUR
MEMUSAGEMAX MEMUSAGEMIN MEMUSAGECUR
1.1.13.4.34 Q1SL4
AUPJCHIGH AUPJCLOW AUPJCNEW
HPBBE HPCSES HPES
HPFEBBE HPFECSES HPFEES
HPFESES HPFEUAS HPSES
HPUAS MSBBE MSCSES
MSES MSFEBBE MSFECSES
MSFEES MSFESES MSFEUAS
MSSES MSUAS OSPICCVCUR
OSPICCVMAX OSPICCVMIN OSPITMPCUR
OSPITMPMAX OSPITMPMIN RPLCUR
RPLMAX RPLMIN RSBBE
RSCSES RSES RSOFS
RSSES RSUAS TLBCUR
TLBMAX TLBMIN TPLCUR
TPLMAX TPLMIN
Table 1-13 Parameters specified for the optical interfaces of the CXL4
Parameter Value
Transmission 0 to 2 2 to 15 20 to 40 50 to 80 80 to 100
distance (km)
Minimum -8 -8 -8 -8 -13
overload (dBm)
Maximum -20 dB – – 1 1 1
spectral width
(nm)
Minimum side – – 30 30 30
mode suppression
ratio (dB)