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JFET Switching 2N5555
JFET Switching 2N5555
1 DRAIN
JFET Switching
N–Channel — Depletion
3
GATE
2N5555
OFF CHARACTERISTICS
Gate–Source Breakdown Voltage (IG = 10 µAdc, VDS = 0) V(BR)GSS 25 — Vdc
Gate Reverse Current (VGS = 15 Vdc, VDS = 0) IGSS — 1.0 nAdc
Drain Cutoff Current (VDS = 12 Vdc, VGS = –10 V) ID(off) — 10 nAdc
Drain Cutoff Current (VDS = 12 Vdc, VGS = –10 V, TA = 100°C) — 2.0 µAdc
ON CHARACTERISTICS
Zero–Gate–Voltage Drain Current(1) IDSS 15 — mAdc
(VDS = 15 Vdc, VGS = 0)
Gate–Source Forward Voltage VGS(f) — 1.0 Vdc
(IG(f) = 1.0 mAdc, VDS = 0)
Drain–Source On–Voltage VDS(on) — 1.5 Vdc
(ID = 7.0 mAdc, VGS = 0)
Static Drain–Source On Resistance rDS(on) — 150 Ohms
(ID = 0.1 mAdc, VGS = 0)
1. Pulse Test: Pulse Width < 300 µs, Duty Cycle < 3.0%.
SMALL–SIGNAL CHARACTERISTICS
Small–Signal Drain–Source “ON” Resistance rds(on) — 150 Ohms
(VGS = 0, ID = 0, f = 1.0 kHz)
Input Capacitance Ciss — 5.0 pF
(VDS = 15 Vdc, VGS = 0, f = 1.0 MHz)
Reverse Transfer Capacitance Crss — 1.2 pF
(VDS = 0, VGS = 10 Vdc, f = 1.0 MHz)
SWITCHING CHARACTERISTICS
Turn–On Delay Time (V
( DD = 10 Vdc,, ID(on) = 7.0 mAdc,, td(on) — 5.0 ns
0 VGS(off) = –10
VGS(on) = 0, 10 Vdc)
Vd ) (See
(S Figure
Fi 1)
Rise Time tr — 5.0 ns
Turn–Off Delay Time ( DD = 10 Vdc,, ID(on) = 7.0 mAdc,,
(V td(off) — 15 ns
VGS(on) = 0,
0 VGS(off) = –1010 Vdc)
Vd ) (See
(S Figure
Fi 1)
Fall Time tf — 10 ns
PULSE WIDTH
VGS(on)
VDD 90% 90%
50 OHM TEKTRONIX 50% 50%
COAXIAL 567 10% 10%
1.0 k INPUT VGS(off)
CABLE SAMPLING
10 k SCOPE
INPUT PULSE INPUT PULSE
PULSE 50 OHM COAXIAL CABLE
RISE TIME FALL TIME
GENERATOR
(50 OHMS) 1.0 k 50 Rin =
50 OHMS
td(on) td(off)
OUTPUT 10% 10%
INPUT PULSE
RISE TIME < 1.0 ns
90% 90%
FALL TIME < 1.0 ns
NOMINAL VALUE OF ON" PULSE WIDTH = 400 ns tr tf
DUTY CYCLE ≤ 1.0%
GENERATOR SOURCE IMPEDANCE = 50 OHMS
Figure 1. Switching Times Test Circuit
30 5.0
grs , REVERSE TRANSADMITTANCE (mmhos)
brs , REVERSE SUSCEPTANCE (mmhos)
20 3.0
bis, INPUT SUSCEPTANCE (mmhos)
gis, INPUT CONDUCTANCE (mmhos)
2.0
10 bis @ IDSS
brs @ IDSS
7.0 1.0
5.0
0.7
0.25 IDSS
3.0 gis @ IDSS 0.5
2.0 0.3
gis @ 0.25 IDSS
0.2
1.0
0.7
0.1
0.5 grs @ IDSS, 0.25 IDSS
bis @ 0.25 IDSS 0.07
0.3 0.05
10 20 30 50 70 100 200 300 500 700 1000 10 20 30 50 70 100 200 300 500 700 100
f, FREQUENCY (MHz) f, FREQUENCY (MHz)
20 10
gfs, FORWARD TRANSCONDUCTANCE (mmhos)
|b fs|, FORWARD SUSCEPTANCE (mmhos)
5.0
bos, OUTPUT SUSCEPTANCE (mhos)
gos, OUTPUT ADMITTANCE (mhos)
10
7.0 gfs @ IDSS 2.0 bos @ IDSS and 0.25 IDSS
5.0
1.0
3.0 gfs @ 0.25 IDSS
0.5
2.0
0.2 gos @ IDSS
1.0 |bfs| @ IDSS 0.1
0.7
0.5 0.05
|bfs| @ 0.25 IDSS
gos @ 0.25 IDSS
0.3 0.02
0.2 0.01
10 20 30 50 70 100 200 300 500 700 1000 10 20 30 50 70 100 200 300 500 700 100
f, FREQUENCY (MHz) f, FREQUENCY (MHz)
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2N5555
150° 160° 170° 180° 190° 200° 210° 150° 160° 170° 180° 190° 200° 210°
150° 160° 170° 180° 190° 200° 210° 150° 160° 170° 180° 190° 200° 210°
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2N5555
20 0.5
10
0.2 brg @ IDSS
7.0 gig @ IDSS
5.0
0.1
3.0 grg @ 0.25 IDSS 0.07
2.0 0.05
0.03 0.25 IDSS
1.0
0.02
0.7
0.5 big @ IDSS
big @ 0.25 IDSS 0.01 gig @ IDSS, 0.25 IDSS
0.3 0.007
0.2 0.005
10 20 30 50 70 100 200 300 500 700 1000 10 20 30 50 70 100 200 300 500 700 1000
f, FREQUENCY (MHz) f, FREQUENCY (MHz)
Figure 10. Input Admittance (yig) Figure 11. Reverse Transfer Admittance (yrg)
gfg , FORWARD TRANSCONDUCTANCE (mmhos)
10 1.0
gfg @ IDSS
bfg , FORWARD SUSCEPTANCE (mmhos)
5.0 0.5
3.0 gfg @ 0.25 IDSS 0.3
2.0 0.2
1.0 0.1
0.7 0.07
0.5 0.05 gog @ IDSS
bfg @ IDSS
0.3 0.03
0.2 brg @ 0.25 IDSS 0.02
gog @ 0.25 IDSS
0.1 0.01
10 20 30 50 70 100 200 300 500 700 1000 10 20 30 50 70 100 200 300 500 700 1000
f, FREQUENCY (MHz) f, FREQUENCY (MHz)
Figure 12. Forward Transfer Admittance (yfg) Figure 13. Output Admittance (yog)
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2N5555
150° 160° 170° 180° 190° 200° 210° 150° 160° 170° 180° 190° 200° 210°
30° 20° 10° 0° 350° 340° 330° 30° 20° 10° 0° 350° 340° 330°
1.5 300
40° 0.5 320° 40° 1.0 500 320°
200
400 700
100 600
100
0.4 0.9 800 900
50° ID = IDSS 310° 50° 310°
100 ID = IDSS, 0.25 IDSS
0.3 0.8
60° 300° 60° 300°
0.2 0.7
70° ID = 0.25 IDSS 290° 70° 290°
150° 160° 170° 180° 190° 200° 210° 150° 160° 170° 180° 190° 200° 210°
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2N5555
PACKAGE DIMENSIONS
TO–92 (TO–226AA)
CASE 29–11
ISSUE AL
NOTES:
A B 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
R IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
P BEYOND DIMENSION K MINIMUM.
L
SEATING INCHES MILLIMETERS
PLANE K DIM MIN MAX MIN MAX
A 0.175 0.205 4.45 5.20
B 0.170 0.210 4.32 5.33
C 0.125 0.165 3.18 4.19
D 0.016 0.021 0.407 0.533
X X D G 0.045 0.055 1.15 1.39
G H 0.095 0.105 2.42 2.66
J 0.015 0.020 0.39 0.50
H J K 0.500 --- 12.70 ---
L 0.250 --- 6.35 ---
V C N 0.080 0.105 2.04 2.66
P --- 0.100 --- 2.54
SECTION X–X R 0.115 --- 2.93 ---
1 N V 0.135 --- 3.43 ---
N
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
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2N5555
Notes
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2N5555
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
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alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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