Verilog for

Digital Design
Chapter 1:
Introduction

Verilog for Digital Design

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 Digital Systems

Verilog for Digital Design

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 Digital Systems
• Digital systems surround us
– Electronic system operating on 0s and 1s
– Typically implemented on an Integrated Circuit (IC) –
"chip"
• Desktop/laptop computers ("PCs") are the most
popular examples
• Other increasingly common examples
– Consumer electronics: Cell phones, portable music
players, cameras, video game consoles, electronic
music instruments, ...
– Medical equipment: Hearing aids, pacemakers, life
support systems, ...
– Automotive electronics: Engine control, brakes, ...
– Military equipment
– Networking components: Routers, switches, ...
– Many, many more...
Verilog for Digital Design
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 Hardware Description Languages (HDLs)

Verilog for Digital Design

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 Transistors per IC (millions)
100,000

Digital Systems and HDLs 10,000

1,000

• Typical digital components per IC 100

10
– 1960s/1970s: 10-1,000
–

2003
1997

2000

2006

2009

2012

2015

2018
1980s: 1,000-100,000
– 1990s: Millions Inputs: b; Outputs: x
– 2000s: Billions x=0
diagrams Off b’
• 1970s b
x=1 x=1 x=1
– IC behavior documented using On1 On2 On3
combination of schematics, schematics
natural
diagrams, and natural language language Combinational Logic
(e.g., English) b x

outputs
inputs
FSM

FSM
b x
"The system has four states.
• 1980s Combinational n1
When in state Off, the logic n1
– Simulating circuits becoming more system outputs 0 and stays s1 s0
n0

important in state Off until the input clk State register

• Schematics commonplace becomes 1. In that case, the n0

system enters state On1,

• Simulating schematic helped
followed by On2, and then
ensure circuit was correct before s1 s0
On3, in which the system
costly implementation clk State register
outputs 1. The system then
returns to state Off."
Verilog for Digital Design
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 HDLs for Simulation

• Hardware description
languages (HDLs) –
Machine-readable textual FSM outputs
languages for describing // CombLogic
always @(State, B) begin
hardware case (State)
S_Off: begin
– Text language could be X <= 0;
if (B == 0)
more efficient means of StateNext <= S_Off;
Clk_s
else
circuit entry than graphical StateNext <= S_On1; Rst_s
end
language S_On1: begin
X <= 1; Simulation B_s
StateNext <= S_On2; X_s
end
S_On2: begin 10 20 30 40 50 60 70 80 90 100110
X <= 1;
StateNext <= S_On3;
end
S_On3: begin
X <= 1;
StateNext <= S_Off;
end
endcase
Verilog for Digital Design end
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 module DoorOpener(C,H,P,F);
input C, H, P;
output F;
Verilog reg F;

always @(C,H,P)
begin
• Verilog F = (~C) & (H | P);
end
– Defined in 1985 at Gateway Design Automation Inc., endmodule
which was then acquired by Cadence Design
Systems ENTITY DoorOpener IS
– C-like syntax PORT (c, h, p: IN std_logic;
f: OUT std_logic);
– Initially a proprietary language, but became open END DoorOpener;
standard in early 1990s, then IEEE standard ("1364")
in 1995, revised in 2002, and again in 2005. ARCHITECTURE Beh OF DoorOpener IS
BEGIN
• Other HDLs PROCESS(c, h, p)
– VHDL BEGIN
f <= NOT(c) AND (h OR p);
• VHSIC Hardware Description Language / defined in END PROCESS;
1980s / U.S. Dept. of Defense project / Ada-like syntax / END Beh;
IEEE standard ("1076") in 1987
• VHDL & Verilog very similar in capabilities, differ mostly #include "systemc.h"
in syntax SC_MODULE(DoorOpener)
{
– SystemC sc_in<sc_logic> c, h, p;
sc_out<sc_logic> f;
• Defined in 2000s by several companies / C++ libraries
and macro routines / IEEE standard ("1666") in 2005 SC_CTOR(DoorOpener)
{
• Excels for system-level; cumbersome for logic level SC_METHOD(comblogic);
– SystemVerilog }
sensitive << c << h << p;

• System-level modeling extensions to Verilog / IEEE

Standard ("1800") in 2005 void comblogic()
{
f.write((~c.read()) & (h.read() | p.read()));
}
Verilog for Digital Design };
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 HDLs for Design and Synthesis

Verilog for Digital Design

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 HDLs for Design and Synthesis
HDL
• HDLs became increasingly used for
designing ICs using top-down design
process
– Design: Converting a higher-level
HDL FSM outputs
description into a lower-level one Clk_s
– Describe circuit in HDL, simulate Rst_s

• Physical design tools automatically HDL behavior b_s

convert to low-level IC design
x_s
– Describe behavior in HDL, simulate
10 20 30 40 50 60 70 80 90100110
• e.g., Describe addition as A = B + C, Synthesis
rather than as circuit of hundreds of logic Clk_s
gates Rst_s
– Compact description, designers get HDL circuit
b_s
function right first
• Design circuit x_s

– Manually, or Physical design 10 20 30 40 50 60 70 8090100110

– Using synthesis tools, which
automatically convert HDL behavior to
HDL circuit
– Simulate circuit, should match
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 HDLs for Synthesis
• Use of HDLs for synthesis is growing
– Circuits are more complex
– Synthesis tools are maturing
• But HDLs originally defined for Clk_s

simulation Simulate Rst_s

HDL behavior
– General language b_s

x_s
– Many constructs not suitable for
10 20 30 40 50 60 70 80 90100110
synthesis Synthesis
• e.g., delays
– Behavior description may simulate, but HDL circuit
not synthesize, or may synthesize to
incorrect or inefficient circuit
• Not necessarily synthesis tool's fault!

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 HDLs for Synthesis
• Consider the English language
– General and complex; many uses
– But use for cooking recipes is greatly restricted
• Chef understands: stir, blend, eggs, bowl, ...
• Chef may not understand: bludgeon, harmonic,
forthright, castigate, ..., even if English grammar Clk_s
is correct Simulate Rst_s
– If the meal turns out bad, don't blame the chef!
HDL behavior b_s
• Likewise, consider HDL language x_s
– General and complex; many uses
10 20 30 40 50 60 70 80 90100110
– But use for synthesizing circuits is greatly Synthesis
restricted
• Synthesis tool understands: sensitivity lists, if
statements, ... HDL circuit
• Synthesis tool may not understand: wait
statements, while loops, ..., even if the HDL
simulates correctly
– If the circuit is bad, don't blame the synthesis tool!
– This book emphasizes use of Verilog HDL for
design and synthesis

Verilog for Digital Design

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 Verilog for Digital Design
• This book introduces use of Verilog for design and synthesis
– In contrast to books that introduce the general language first, and then (maybe)
describe synthesis subset
– No need to learn entire French language if your goal is just to write recipes in
French
• Shows use of Verilog for increasingly complex digital systems
– Combinational logic design
– Sequential logic design
– Datapath components
– Register transfer level (RTL) design
– Emphasizes a very disciplined use of the language for specific purposes
• Book can be used as supplement to digital design textbook
– Specifically follows structure and examples of "Digital Design" by Frank Vahid,
John Wiley and Sons, 2011
• But can be used with other books too
– Can also be used as standalone introduction to Verilog

Verilog for Digital Design

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