A31s Datasheet V1.0
A31s Datasheet V1.0
A31s Datasheet V1.0
Datasheet
Revision 1.0
Declaration
THIS A31s DATASHEET IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER
TECHNOLOGY (“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE
WRITTEN APPROVAL OF ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT
OWNER.
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 2
Revision History
Revision History
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 3
Table of Contents
Table of Contents
Declaration ........................................................................................................................................................ 2
Revision History ............................................................................................................................................... 3
Table of Contents ............................................................................................................................................. 4
1 OVERVIEW ................................................................................................................................................. 5
2 FEATURES ................................................................................................................................................. 6
3 BLOCK DIAGRAM ................................................................................................................................... 10
4 PIN DESCRIPTION................................................................................................................................... 11
4.1. Pin Characteristics ............................................................................................................................. 11
4.2. GPIO Multiplexing Functions ............................................................................................................. 18
4.3. Detailed Pin/Signal Description ......................................................................................................... 22
4.4. Power/GND Signal Description ......................................................................................................... 27
5 ELECTRICAL CHARACTERISTICS ........................................................................................................ 29
5.1. Absolute Maximum Ratings ............................................................................................................... 29
5.2. Recommended Operating Conditions ............................................................................................... 29
5.3. DC Electrical Characteristics ............................................................................................................. 30
5.4. Oscillator Electrical Characteristics ................................................................................................... 30
5.5. Power up AND Power Down Sequence ............................................................................................ 32
6 PIN ASSIGNMENT ................................................................................................................................... 33
6.1. Ball map ............................................................................................................................................. 33
6.2. Pin Dimension .................................................................................................................................... 34
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 4
OVERVIEW
1 OVERVIEW
The Allwinner A31s processor is a quad-core phablet processor designed for the phablet market. The phablet
is a product category that combines the functionalities of a smartphone with that of a tablet, and its size
usually falls somewhere in between a smartphone and a tablet.
The A31s processor is based on quad-core Cortex-A7 CPU, which is the most power efficient processor
developed by ARM. It also comes with SGX544MP2 GPU with eight logic core to enable powerful 3D
computing capability as well as excellent UI experience, especially when it comes to the smoothness of
screens with large size.
More importantly, A31s processor integrates a robust Audio Codec that includes two sets of I2S/PCM
interface for Baseband and Bluetooth, two integrated differential analog MIC for headset and phone, as well
as a digital MIC. It is capable of 3G, 2G, LTE, WiFi, Bluetooth, FM, GPS, AGPS, NFC and other voice and
data wireless transmission technology with a minimum of external components.
Additionally, A31s processor provides a wide range of peripheral interfaces. For example, it integrates display
interfaces such as HDMI, RGB LCD and LVDS, image input interfaces such as CSI, and data interfaces such
as USB OTG, USB EHCI/OHCI, SDC, SPI, UART, etc.
When it comes to power efficiency, AXP221s is specially designed for the power optimization of A31s. A31s
processor also supports a smart Power Consumption Management System to dynamically adjust CPU
frequency and voltage, supports DRAM Dynamic Frequency Scaling technology to dynamically adjust DRAM
frequency based on bandwidth requirements, and also supports Super Standby Mode to lower the system
power consumption during system standby.
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 5
FEATURES
2 FEATURES
DMA
2D RTC
- Support BLT and ROP2/3/4, scaling function with - Real time registers for second, minute, hour, day,
4x4 taps and 32 phases month and year
- Support 90/180/270 degree rotation - Two alarms based on seconds and weeks
- Support mirror/alpha (plane and pixel alpha)/ - 16 general purpose registers
color key
- Format conversion: ARGB 8888/4444/1555, CCU
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 6
FEATURES
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 7
FEATURES
SPI
CONNECTIVITY - Master/Slave configurable
USB2.0 OTG - Up to 4 independent SPI controllers, SPI0 with
- Support High-Speed (HS, 480-Mbps), Full-Speed only one CS signal for system boot, and SPI1/2/3
(FS, 12-Mbps), and Low-Speed (LS, 1.5-Mbps) with two CS signals
in Host mode
- Support dual input and dual output operation
- Support High-Speed (HS, 480-Mbps), Full-Speed
(FS, 12-Mbps) in Device mode TWI
- Support up to 10 user-configurable endpoints for - Up to 5 TWIs compliant with I2C protocol
bulk , isochronous, control and interrupt - Support SCCB protocol
bi-directional transfers
P2WI (Push-Pull TWI)
USB EHCI/OHCI
- Two EHCI/OHCI-compliant Hosts - Support speed up to 12MHz
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 8
FEATURES
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 9
BLOCK DIAGRAM
3 BLOCK DIAGRAM
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PIN DESCRIPTION
4 PIN DESCRIPTION
Notes
1) Pin Name defines the names of pins. Note that a group of pins with similar meaning may be expressed in the form of [x:0];
2) Default Function defines the default function of each pin;
3) Type defines the signal direction: I (Input), O (Output), I/O(Input / Output), A (Analog), P (Power), G (Ground);
4) Default IO State defines the default IO state of each pin: DIS means disable;
5) Default Pull Up/Down defines the presence of an internal pull up or pull down resister. Unless otherwise specified, the pin
is default to be floating, and can be configured as pull up or pull down; Note that the NMI and RESET pins require no
additional pull-up resistors;
6) Buffer Strength defines drive strength of the associated output buffer. It is tested in the condition that VCC= 3.3V,
strength=MAX;
7) P[A:M] in Table 5-1 stands for GPIO [A:M]. For detailed auxiliary functions of each GPIO, please go to Section 5.2 GPIO
Multiplexing Functions section.
DRAM
Y9,Y6,AA8,AA6,AA9,Y7
,AB8,AB6,AA4,AA1,AB5
,AA2,AA5,AB1,Y5,AB2,
SDQ[31:0] DRAM I/O DIS Z -
T2,N2,P3,P1,R3,N3,U1,
P2,M1,J2,L3,K2,M2,J1,
M3,K3
AA7,AA3,R1,L1, SDQS[3:0] DRAM I/O DIS Z -
K4 SZQ DRAM A - - -
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 11
PIN DESCRIPTION
W5 SVREF DRAM P - - -
P6,R6,T6,T7,U6,U7,U8, VCC-DRAM
DRAM P - - -
V6,V7,W7, (10)
U9 VDD-DLL DRAM P - - -
7
GPIO A
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 12
PIN DESCRIPTION
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 13
PIN DESCRIPTION
E7 VCC-PF POWER P - - -
7
GPIO G
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 14
PIN DESCRIPTION
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 15
PIN DESCRIPTION
7
GPIO L
7
GPIO M
System Control
HDMI
AA12 HTX0P - A - - -
AB12 HTX0N - A - - -
AA13 HTX1P - A - - -
Y12 HTX1N - A - - -
AA14 HTX2P - A - - -
Y14 HTX2N - A - - -
VCC-HDMI
AB11 HTXCP - A - - -
AA11 HTXCN - A - - -
U17 VCC-HDMI - P - - -
AB14 HSCL - A - - -
Y13 HSDA - A - - -
Y11 HHPD - A - - -
USB
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 16
PIN DESCRIPTION
Y22 DP0 - A - - -
AA21 DM1 - A - - -
AA22 DP1 - A - - -
T17 VCC-USB - P - - -
AB21 DM2 - A - - -
AB22 DP2 - A - - -
Audio Codec
P18 PHOUTN - A - - -
P19 PHOUTP - A - - -
L21 PHINP - A - - -
L22 PHINN - A - - -
P20 HBIAS - A - - -
N20 MBIAS - A - - -
M22 MIC2N - A - - -
M21 MIC2P - A - - -
M20 MIC1N - A - - -
L20 MIC1P - A - - -
K19 VRA1 - A - - -
K20 VRA2 - A - - -
K18 VRP - P - - -
P21 LINEOUTR - A - - -
P22 LINEOUTL - A - - -
N19 LINEINR - A - - -
M19 LINEINL - A - - -
N16 AGND - G - - -
K21 HPOUTR - A - - -
L19 HPOUTL - A - - -
M18 HPCOMFB - A - - -
N18 HPCOM - A - - -
N21 HPBP - A - - -
P17 VCC-HP - A - - -
LRADC
RTC
AA10 X24MI - A - - -
Y10 X24MO - A - - -
VCC-RTC
AA20 VIO-RTC - P - - -
V19 VCC-RTC - P - - -
Clock
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 17
PIN DESCRIPTION
V21 X32KO - A - - -
Power
L16,L17 VDD-CPUS - P - - - -
F11,F12,F13,F14,F15,F
16,G11,G12,G13,G14,G
VDD-CPU
15,G16,G17,H12,H13,H - P - - - -
(23)
14,H15,H16,H17,J16,J1
7,K16,K17
F17 CPU-VDDFB - - - - -
J6,J7,K5,K6,K7,L6,L7,M VDD-GPU
- P - - - -
6,M7,N6,N7,P5 (12)
T12,T13,T14,T15,T16,U
VDD-SYS
10,U11,U12,U13,U14,U - P - - - -
(12)
15,U16
W10,G8,H8,H9,H10,H1
1,J8,J9,J10,J11,J12,J13
,J14,J15,K8,K9,K10,K11
,K12,K13,K14,K15,L8,L
9,L10,L11,L12,L13,L14,
L15,M8,M9,M10,M11,M
12,M13,M14,M15,M16, GND(69) - G - - - -
N8,N9,N10,N11,N12,N1
3,N14,N15,P7,P8,P9,P1
0,P11,P12,P13,P14,P15
,R7,R8,R9,R10,R11,R1
2,R13,R14,R15,T8,T9,T
10,T11
Others
A1,A2,A3,B1,B2,B3,B4,
C1,C4,D2,E1,E3,F6,F7, NC - - - - - -
G6,G7,H7,C10.D10
Table 5-1 Pin Characteristics
Default
Pin Default IO Default
Pull-up/ Function2 Function 3 Function 4 Function 5 Function 6
Name Function Type IO State
down
Z PA_EINT0
PA0 I/O DIS - - UART1_DTR -
Z PA_EINT1
PA1 I/O DIS - - UART1_DSR -
Z PA_EINT2
PA2 I/O DIS - - UART1_DCD -
Z PA_EINT3
PA3 I/O DIS - - UART1_RING -
Z PA_EINT4
PA4 I/O DIS - - UART1_TX -
Z PA_EINT5
PA5 I/O DIS - - UART1_RX -
Z PA_EINT6
PA6 I/O DIS - - UART1_RTS -
GPIO
Z PA_EINT7
PA7 I/O DIS - - UART1_CTS -
Z PA_EINT8
PA8 I/O DIS - - ECLK_IN0 -
Z PA_EINT9
PA9 I/O DIS - - SDC3_CMD SDC2_CMD
PA10 I/O Z SDC3_CLK SDC2_CLK PA_EINT10
DIS - -
Z PA_EINT11
PA11 I/O DIS - - SDC3_D0 SDC2_D0
Z PA_EINT12
PA12 I/O DIS - - SDC3_D1 SDC2_D1
Z PA_EINT13
PA13 I/O DIS - - SDC3_D2 SDC2_D2
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 18
PIN DESCRIPTION
Default
Pin Default IO Default
Pull-up/ Function2 Function 3 Function 4 Function 5 Function 6
Name Function Type IO State
down
Z PA_EINT14
PA14 I/O DIS - - SDC3_D3 SDC2_D3
Z - PA_EINT15
PA15 I/O DIS - - CLKA_OUT
Z - PA_EINT16
PA16 I/O DIS - - DMIC_CLK
Z - PA_EINT17
PA17 I/O DIS - - DMIC_DIN
Z - PA_EINT18
PA18 I/O DIS - - CLKB_OUT
Z - PA_EINT19
PA19 I/O DIS - - PWM3_P
Z - PA_EINT20
PA20 I/O DIS - - PWM3_N
Z SPI3_CS0 - PA_EINT21
PA21 I/O DIS - -
Z - PA_EINT22
PA22 I/O DIS - - SPI3_CLK
Z - PA_EINT23
PA23 I/O DIS - - SPI3_MOSI
Z - PA_EINT24
PA24 I/O DIS - - SPI3_MISO
Z SPI3_CS1 - PA_EINT25
PA25 I/O DIS - -
Z - PA_EINT26
PA26 I/O DIS - - CLKC_OUT
Z - PA_EINT27
PA27 I/O DIS - - ECLK_IN1
PB0 I/O Z I2S0_MCLK UART3_CTS - PB_EINT0
DIS -
PB1 I/O Z I2S0_BCLK - - PB_EINT1
DIS -
PB2 I/O Z I2S0_LRCK - - PB_EINT2
DIS -
PB3 I/O Z I2S0_DO0 - - PB_EINT3
DIS -
GPIO
PB4 I/O Z I2S0_DO1 UART3_RTS - PB_EINT4
DIS TWI3-SCK
PB5 I/O Z I2S0_DO2 UART3_TX - PB_EINT5
DIS TWI3-SDA
PB6 I/O Z I2S0_DO3 UART3_RX - PB_EINT6
DIS -
PB7 I/O Z I2S0_DI - - - PB_EINT7
DIS
PC0 I/O Z NAND_WE SPI0_MOSI - - -
DIS
PC1 I/O Z NAND_ALE SPI0_MISO - - -
DIS
PC2 I/O Z NAND_CLE SPI0_CLK - - -
DIS
PC3 I/O Pull-up NAND_CE1 - - - -
DIS
PC4 I/O Pull-up NAND_CE0 - - - -
DIS
PC5 I/O Z NAND_RE - - - -
DIS
PC6 I/O Pull-up NAND_RB0 SDC2_CMD SDC3_CMD - -
DIS
PC7 I/O Pull-up NAND_RB1 SDC2_CLK SDC3_CLK - -
DIS
PC8 I/O Z NAND_DQ0 SDC2_D0 SDC3_D0 - -
DIS
PC9 GPIO I/O Z NAND_DQ1 SDC2_D1 SDC3_D1 - -
DIS
PC10 I/O Z NAND_DQ2 SDC2_D2 SDC3_D2 - -
DIS
PC11 I/O Z NAND_DQ3 SDC2_D3 SDC3_D3 - -
DIS
PC12 I/O Z NAND_DQ4 SDC2_D4 SDC3_D4 - -
DIS
PC13 I/O Z NAND_DQ5 SDC2_D5 SDC3_D5 - -
DIS
PC14 I/O Z NAND_DQ6 SDC2_D6 SDC3_D6 - -
DIS
PC15 I/O Z NAND_DQ7 SDC2_D7 SDC3_D7 - -
DIS
PC24 I/O Z NAND_DQS SDC2_RST SDC3_RST - -
DIS
PC25 I/O Pull-up NAND_CE2 - - - -
DIS
PC26 I/O Pull-up NAND_CE3 - - - -
DIS
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 19
PIN DESCRIPTION
Default
Pin Default IO Default
Pull-up/ Function2 Function 3 Function 4 Function 5 Function 6
Name Function Type IO State
down
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 20
PIN DESCRIPTION
Default
Pin Default IO Default
Pull-up/ Function2 Function 3 Function 4 Function 5 Function 6
Name Function Type IO State
down
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 21
PIN DESCRIPTION
Default
Pin Default IO Default
Pull-up/ Function2 Function 3 Function 4 Function 5 Function 6
Name Function Type IO State
down
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 22
PIN DESCRIPTION
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 23
PIN DESCRIPTION
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 24
PIN DESCRIPTION
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 25
PIN DESCRIPTION
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 26
PIN DESCRIPTION
Note
1) VRP/VRA1/VRA2 are output type, and are not for third party development use.
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 27
PIN DESCRIPTION
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 28
ELECTRICAL CHARACTERISTICS
5 ELECTRICAL CHARACTERISTICS
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 29
ELECTRICAL CHARACTERISTICS
The A31s clock control module includes 11PLLs, a main oscillator, an on-chip RC oscillator of 466.9KHz
~867.1KHz, and a 32768Hz low power oscillator.
The 24.000MHz frequency is used to generate the main source clock for PLL and the main digital blocks, and
the 32768Hz oscillator is used only to provide a low power accurate reference for RTC.
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 30
ELECTRICAL CHARACTERISTICS
A31s Datasheet (Revision 1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 31
ELECTRICAL CHARACTERISTICS
PS
VCC-RTC
PWRIN delay
VCC-3V3
VDD-CPU
VDD-GPU
VDD-SYS
PWROK delay
VCC-DRAM
AVCC
VCC-CPUS
OFF delay
AP-RESET#
PMU-SCK
PMU-SDA
Timer
PWRON Debounce
A31s Datasheet (Revision1.0) Copyright © 2013 Allwinner Technology. All Rights Reserved. Page 32
PIN ASSIGNMENT
6 PIN ASSIGNMENT
A NC NC NC PH11 PH16 PH20 PH24 PE1 PE8 PE13 PG0 PG5 PG14 PB2 PB4 PB6 A
B NC NC NC NC PH10 PH15 PH17 PH21 PH25 PE0 PE3 PE9 PE11 PE14 PG1 PG3 PG10 PG15 PB0 PB3 PB5 PB7 B
C NC PC26 PC27 NC PH9 PH14 PH18 PH22 PH26 NC PE2 PE10 PE12 PE15 PG2 PG4 PG11 PG16 PB1 PA7 PA8 PA9 C
D NC PC11 PC24 PF0 PH13 PH19 PH27 PH28 NC JTAGSEL1 PE4 PE6 PE7 PG6 PG8 PG12 PG17 VCC-PB PA4 PA13 D
E NC PC10 NC PC15 PC14 PH12 VCC-PF VCC-PC PH23 UBOOT JTAGSEL0 PE5 VCC-PE VCC-PG PG7 PG9 PG13 PG18 PA1 PA14 PA17 PA18 E
F PC4 PC8 PC9 PC12 PC13 NC NC VCC-PC VCC-PH VCC-PH VDD-CPU VDD-CPU VDD-CPU VDD-CPU VDD-CPU VDD-CPU CPU-VDDFB PA0 PA3 PA16 PA19 PA20 F
G PC0 PC5 PC6 PC7 NC NC GND BOOTSEL1 BOOTSEL0 VDD-CPU VDD-CPU VDD-CPU VDD-CPU VDD-CPU VDD-CPU VDD-CPU PA2 PA12 PA15 PA22 G
H PF4 PF5 PC1 PC2 PC3 PC25 NC GND GND GND GND VDD-CPU VDD-CPU VDD-CPU VDD-CPU VDD-CPU VDD-CPU PA5 PA11 PA21 PA23 PA26 H
J SDQ2 SDQ6 PF1 PF2 PF3 VDD-GPU VDD-GPU GND GND GND GND GND GND GND GND VDD-CPU VDD-CPU PA6 PA10 PA25 PA24 PA27 J
K SDQ4 SDQ0 SZQ VDD-GPU VDD-GPU VDD-GPU GND GND GND GND GND GND GND GND VDD-CPU VDD-CPU VRP VRA1 VRA2 HPOUTR K
L SDQS0 SDQS0B SDQ5 SDQM0 SRAS VDD-GPU VDD-GPU GND GND GND GND GND GND GND GND VDD-CPUS VDD-CPUS AVCC HPOUTL MIC1P PHINP PHINN L
M SDQ7 SDQ3 SDQ1 SODT SODT1 VDD-GPU VDD-GPU GND GND GND GND GND GND GND GND GND VCC-PA HPCOMFB LINEINL MIC1N MIC2P MIC2N M
N SDQ14 SDQ10 SCS1 SCAS VDD-GPU VDD-GPU GND GND GND GND GND GND GND GND AGND VCC-PA HPCOM LINEINR MBIAS HPBP N
P SDQ12 SDQ8 SDQ13 SDQM1 VDD-GPU VCC-DRAM GND GND GND GND GND GND GND GND GND VCC-PD VCC-HP PHOUTN PHOUTP HBIAS LINEOUTR LINEOUTL P
R SDQS1 SDQS1B SDQ11 SCS SA2 VCC-DRAM GND GND GND GND GND GND GND GND GND VCC-PD VCC-PD PM1 PM0 PM2 PM4 LRADC0 R
T SDQ15 SA3 SBA2 SCKE VCC-DRAM VCC-DRAM GND GND GND GND VDD-SYS VDD-SYS VDD-SYS VDD-SYS VDD-SYS VCC-USB PM3 PM6 PM5 PM7 T
U SDQ9 SBA0 SA0 SRST SA10 VCC-DRAM VCC-DRAM VCC-DRAM VDD-DLL VDD-SYS VDD-SYS VDD-SYS VDD-SYS VDD-SYS VDD-SYS VDD-SYS VCC-HDMI VCC-PM PL5 PL3 PL0 RESET U
V SWE SA5 SCK SA15 SBA1 VCC-DRAM VCC-DRAM SA8 SA6 SA11 PD27 PD25 PD23 PD9 PD7 PD5 PD3 PD1 VCC-RTC PL8 X32KO X32KI V
W SA7 SCKB SA1 SVREF SA12 VCC-DRAM SA14 SA4 GND PD26 PD24 PD22 PD8 PD6 PD4 PD2 PD0 NMI PL7 PL2 W
Y SA9 SA13 SCKE1 SDQM2 SDQ17 SDQ30 SDQ26 SDQS3B SDQ31 X24MO HHPD HTX1N HSDA HTX2N PD20 PD19 PD21 PD10 PL6 PL4 DM0 DP0 Y
AA SDQ22 SDQ20 SDQS2 SDQ23 SDQ19 SDQ28 SDQS3 SDQ29 SDQ27 X24MI HTXCN HTX0P HTX1P HTX2P PD16 PD18 PD15 PD13 PD11 VIO-RTC DM1 DP1 AA
AB SDQ18 SDQ16 SDQS2B SDQ21 SDQ24 SDQ25 SDQM3 HTXCP HTX0N HSCL PD17 PD14 PD12 PL1 DM2 DP2 AB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
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PIN ASSIGNMENT
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