38-08032 Cy7c68013a Cy7c68014a Cy7c68015a Cy7c68016a Ez-Usb Fx2lp Usb Microcontroller High Speed Usb Peripheral Controller
38-08032 Cy7c68013a Cy7c68014a Cy7c68015a Cy7c68016a Ez-Usb Fx2lp Usb Microcontroller High Speed Usb Peripheral Controller
CY7C68015A/CY7C68016A
EZ-USB® FX2LP™ USB Microcontroller
High-Speed USB Peripheral Controller
EZ-USB® FX2LP™ USB Microcontroller High-Speed USB Peripheral Controller
Errata: For information on silicon errata, see “Errata” on page 68. Details include trigger conditions, devices affected, and proposed workaround.
Note
1. The actual I2C clock frequency will be different. The measured I2C clock frequency when set for 100 kHz and 400 kHz is around 85 kHz and 300 kHz respectively.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-08032 Rev. AB Revised December 6, 2018
CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly
and effectively integrate the device into your design. For a comprehensive list of resources, see the application note AN65209 - Getting
Started with FX2LP.
■ Overview: USB Portfolio, USB Roadmap EZ-USB FX2LP Development Kit
■ USB 2.0 Product Selectors: FX2LP, AT2LP, NX2LP-Flex, SX2 The CY3684 EZ-USB FX2LP Development Kit is a complete
development resource for FX2LP. It provides a platform to
■ Application notes: Cypress offers a large number of USB appli- develop and test custom projects using FX2LP. The
cation notes covering a broad range of topics, from basic to development kit contains collateral materials for the firmware,
advanced level. Recommended application notes for getting hardware, and software aspects of a design using FX2LP.
started with FX2LP are:
❐ AN65209 - Getting Started with FX2LP GPIF™ Designer
®
❐ AN15456 - Guide to Successful EZ-USB FX2LP™ and FX2LP™ General Programmable Interface (GPIF) provides an
EZ-USB FX1™ Hardware Design and Debug independent hardware unit, which creates the data and control
®
❐ AN50963 - EZ-USB FX1™/FX2LP™ Boot Options signals required by an external interface. FX2LP GPIF Designer
®
❐ AN66806 - EZ-USB FX2LP™ GPIF Design Guide allows users to create and modify GPIF waveform descriptors for
❐ AN61345 - Implementing an FX2LP™- FPGA Interface EZ-USB FX2/ FX2LP family of chips using a graphical user
❐ AN57322 - Interfacing SRAM with FX2LP over GPIF interface. Extensive discussion of general GPIF discussion and
❐ AN4053 - Streaming Data through Isochronous/Bulk End- programming using GPIF Designer is included in FX2LP
points on EZ-USB® FX2 and EZUSB FX2LP Technical Reference Manual and GPIF Designer User Guide,
®
❐ AN63787 - EZ-USB FX2LP™ GPIF and Slave FIFO Con- distributed with GPIF Designer. AN66806 - Getting Started with
figuration Examples using 8-bit Asynchronous Interface EZ-USB® FX2LP™ GPIF can be a good starting point.
For complete list of Application notes, click here.
■ Code Examples:
❐ USB Hi-Speed
■ Reference Designs:
❐ CY4661 - External USB Hard Disk Drives (HDD) with Finger-
print Authentication Security
❐ FX2LP DMB-T/H TV Dongle reference design
■ Models: IBIS
FX2LP
Address (16)
Data (8)
/0.5 I2C
x20 8051 Core Master
VCC /1.0
PLL 12/24/48 MHz,
Cypress’s EZ-USB® FX2LP™ (CY7C68013A/14A) is a With EZ-USB FX2LP, the Cypress Smart SIE handles most of
low-power version of the EZ-USB FX2™(CY7C68013), which is the USB 1.1 and 2.0 protocol in hardware, freeing the embedded
a highly integrated, low-power USB 2.0 microcontroller. By microcontroller for application-specific functions and decreasing
integrating the USB 2.0 transceiver, serial interface engine (SIE), the development time to ensure USB compatibility.
enhanced 8051 microcontroller, and a programmable peripheral The general programmable interface (GPIF) and Master/Slave
interface in a single chip, Cypress has created a cost-effective Endpoint FIFO (8-bit or 16-bit data bus) provide an easy and
solution that provides superior time-to-market advantages with glueless interface to popular interfaces such as ATA, UTOPIA,
low power to enable bus-powered applications. EPP, PCMCIA, and most DSP/processors.
The ingenious architecture of FX2LP results in data transfer The FX2LP draws less current than the FX2 (CY7C68013), has
rates of over 53 Mbytes per second (the maximum allowable double the on-chip code/data RAM, and is fit, form, and function
USB 2.0 bandwidth), while still using a low-cost 8051 compatible with the 56-, 100-, and 128-pin FX2.
microcontroller in a package as small as a 56 VFBGA (5 mm x
5 mm). Because it incorporates the USB 2.0 transceiver, the Five packages are defined for the family: 56-ball VFBGA, 56-pin
FX2LP is more economical, providing a smaller-footprint solution SSOP, 56-pin QFN, 100-pin TQFP, and 128-pin TQFP.
than a USB 2.0 SIE or external transceiver implementations.
Contents
Applications ...................................................................... 5 Data Memory Write[32] ............................................... 45
Functional Overview ........................................................ 5 PORTC Strobe Feature Timings ............................... 46
USB Signaling Speed .................................................. 5 GPIF Synchronous Signals ....................................... 47
8051 Microprocessor ................................................... 5 Slave FIFO Synchronous Read ................................. 48
I2C Bus ........................................................................ 5 Slave FIFO Asynchronous Read ............................... 49
Buses .......................................................................... 5 Slave FIFO Synchronous Write ................................. 50
USB Boot Methods ...................................................... 6 Slave FIFO Asynchronous Write ............................... 51
ReNumeration ............................................................. 6 Slave FIFO Synchronous Packet End Strobe ........... 52
Bus-Powered Applications .......................................... 6 Slave FIFO Asynchronous Packet End Strobe ......... 54
Interrupt System .......................................................... 6 Slave FIFO Output Enable ........................................ 54
Reset and Wakeup ...................................................... 9 Slave FIFO Address to Flags/Data ............................ 54
Program/Data RAM ................................................... 10 Slave FIFO Synchronous Address ............................ 55
Register Addresses ................................................... 12 Slave FIFO Asynchronous Address .......................... 55
Endpoint RAM ........................................................... 13 Sequence Diagram .................................................... 56
External FIFO Interface ............................................. 15 Ordering Information ...................................................... 60
GPIF .......................................................................... 15 Ordering Code Definitions ......................................... 60
ECC Generation[10] ................................................... 16 Package Diagrams .......................................................... 61
USB Uploads and Downloads ................................... 16 PCB Layout Recommendations .................................... 65
Autopointer Access ................................................... 16 Quad Flat Package No Leads (QFN)
I2C Controller ............................................................. 16 Package Design Notes ................................................... 66
Compatible with Previous Generation Acronyms ........................................................................ 67
EZ-USB FX2 ..................................................................... 17 Document Conventions ................................................. 67
CY7C68013A/14A and CY7C68015A/16A Units of Measure ....................................................... 67
Differences ....................................................................... 17 Errata ............................................................................... 68
Pin Assignments ............................................................ 18 Part Numbers Affected .............................................. 68
CY7C68013A/15A Pin Descriptions .......................... 25 CY7C68013A/14A/15A/16A Qualification Status ...... 68
Register Summary .......................................................... 34 CY7C68013A/14A/15A/16A Errata Summary ........... 68
Absolute Maximum Ratings .......................................... 41 Document History Page ................................................. 69
Operating Conditions ..................................................... 41 Sales, Solutions, and Legal Information ...................... 73
Thermal Characteristics ................................................. 41 Worldwide Sales and Design Support ....................... 73
DC Characteristics ......................................................... 42 Products .................................................................... 73
USB Transceiver ....................................................... 42 PSoC® Solutions ...................................................... 73
AC Electrical Characteristics ........................................ 43 Cypress Developer Community ................................. 73
USB Transceiver ....................................................... 43 Technical Support ..................................................... 73
Program Memory Read ............................................. 43
Data Memory Read[30] ............................................... 44
Applications
Figure 1. Crystal Configuration
■ Portable video recorder
C1 24 MHz C2
■ MPEG/TV conversion
■ DSL modems 12 pF 12 pF
■ ATA interface
■ Memory card readers 20 × PLL
■ Legacy conversion devices
■ Cameras 12-pF capacitor values assume a trace capacitance
of 3 pF per side on a four-layer FR4 PCA
■ Scanners
The CLKOUT pin, which can be three-stated and inverted using
■ Wireless LAN
internal control bits, outputs the 50% duty cycle 8051 clock, at
■ MP3 players the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.
■ Networking USARTs
The “Reference Designs” section of the Cypress web site FX2LP contains two standard 8051 USARTs, addressed through
provides additional tools for typical USB 2.0 applications. Each Special Function Register (SFR) bits. The USART interface pins
reference design comes complete with firmware source and are available on separate I/O pins, and are not multiplexed with
object code, schematics, and documentation. Visit port pins.
www.cypress.com for more information.
UART0 and UART1 can operate using an internal clock at
230 KBaud with no more than 1% baud rate error. 230 KBaud
Functional Overview operation is achieved by an internally derived clock source that
USB Signaling Speed generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and
FX2LP operates at two of the three rates defined in the USB 12 MHz) such that it always presents the correct frequency for
Specification Revision 2.0, dated April 27, 2000: the 230-KBaud operation[2].
■ Full speed, with a signaling bit rate of 12 Mbps Special Function Registers
■ High speed, with a signaling bit rate of 480 Mbps Certain 8051 SFR addresses are populated to provide fast
FX2LP does not support the Low Speed signaling mode of access to critical FX2LP functions. These SFR additions are
1.5 Mbps. shown in Table 1 on page 6. Bold type indicates nonstandard,
enhanced 8051 registers. The two SFR rows that end with “0”
8051 Microprocessor and “8” contain bit-addressable registers. The four I/O ports A to
D use the SFR addresses used in the standard 8051 for ports 0
The 8051 microprocessor embedded in the FX2LP family has to 3, which are not implemented in FX2LP. Because of the faster
256 bytes of register RAM, an expanded interrupt system, three
and more efficient SFR addressing, the FX2LP I/O ports are not
timer/counters, and two USARTs. addressable in external RAM space (using the MOVX
8051 Clock Frequency instruction).
FX2LP has an on-chip oscillator circuit that uses an external I2C Bus
24-MHz (±100 ppm) crystal with the following characteristics:
FX2LP supports the I2C bus as a master only at 100/400 kHz[3].
■ Parallel resonant SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3 V, even if no I2C
■ Fundamental mode device is connected.
■ 500-W drive level
Buses
■ 12-pF (5% tolerance) load capacitors All packages, 8-bit or 16-bit “FIFO” bidirectional data bus,
An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, multiplexed on I/O ports B and D. 128-pin package: adds 16-bit
as required by the transceiver/PHY; internal counters divide it output-only 8051 address bus, 8-bit bidirectional data bus.
down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically.
Notes
2. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.
3. The actual I2C clock frequency will be different.The measured I2C clock frequency when set for 100 kHz and 400 kHz is around 85 kHz and 300 kHz respectively.
USB Boot Methods Two control bits in the USBCS (USB Control and Status) register
control the ReNumeration process: DISCON and RENUM. To
During the power-up sequence, internal logic checks the I2C port
simulate a USB disconnect, the firmware sets DISCON to 1. To
for the connection of an EEPROM whose first byte is either 0xC0
reconnect, the firmware clears DISCON to 0.
or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
in place of the internally stored values (0xC0), or it boot-loads the Before reconnecting, the firmware sets or clears the RENUM bit
EEPROM contents into internal RAM (0xC2). If no EEPROM is to indicate whether the firmware or the Default USB Device
detected, FX2LP enumerates using internally stored descriptors. handles device requests over endpoint zero: if RENUM = 0, the
The default ID values for FX2LP are VID/PID/DID (0x04B4, Default USB Device handles device requests; if RENUM = 1, the
0x8613, 0xAxxx where xxx = Chip revision)[4]. firmware services the requests.
Note
4. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high
byte (“page”) of a jump table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs
the jump to the correct address out of the 27 addresses within the page.
Note
5. Errata: In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT Endpoint (EP) in the first
transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than one word in the first transaction. For more information, see
the “Errata” on page 68.
RESET# RESET#
VIL VIL
3.3V 3.3V
3.0V
VCC VCC
0V 0V
TRESET TRESET
Wakeup Pins
Table 5. Reset Timing Values
The 8051 puts itself and the rest of the chip into a power-down
Condition TRESET mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
Power-on reset with crystal 5 ms restarts after the PLL stabilizes, and the 8051 receives a wakeup
Power-on reset with external interrupt. This applies irrespective of whether FX2LP is
200 s + clock stability time connected to the USB.
clock
Powered reset 200 s The FX2LP exits the power-down (USB suspend) state by using
one of the following methods:
■ USB bus activity (if D+/D– lines are left floating, noise on these
lines may indicate activity to the FX2LP and initiate a wakeup)
■ External logic asserts the WAKEUP pin
■ External logic asserts the PA3/WU2 pin
The second wakeup pin, WU2, can also be configured as a
general-purpose I/O pin. This enables a simple external R-C
network to be used as a periodic wakeup source. WAKEUP is by
default active LOW.
Program/Data RAM
Size enables the user to connect a 64 KB memory without requiring
The FX2LP has 16 KB of internal program/data RAM, where address decodes to keep clear of internal memory spaces.
PSEN#/RD# signals are internally ORed to enable the 8051 to Only the internal 16 KB and scratch pad 0.5 KB RAM spaces
access it as both program and data memory. No USB control have the following access:
registers appears in this space.
■ USB download
Two memory maps are shown in the following diagrams:
■ USB upload
Figure 3 shows the Internal Code Memory, EA = 0.
Figure 4 on page 11 shows the External Code Memory, EA = 1. ■ Setup data pointer
■ I2C interface boot load
Internal Code Memory, EA = 0
This mode implements the internal 16 KB block of RAM (starting External Code Memory, EA = 1
at 0) as combined code and data memory. When external RAM The bottom 16 KB of program memory is external and therefore
or ROM is added, the external read and write strobes are the bottom 16 KB of internal RAM is accessible only as a data
suppressed for memory spaces that exist inside the chip. This memory.
3FFF
0000
Data Code
Note
6. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 s.
40 KB
External
Data 64 KB
Memory External
(RD#,WR#) Code
Memory
(PSEN#)
3FFF
16 KB (Ok to populate
RAM data memory
Data here—RD#/WR#
(RD#,WR#)* strobes are not
active)
0000
Data Code
Register Addresses
FFFF
4 KB EP2-EP8
buffers
(8 x 512)
F000
EFFF
2 KB RESERVED
E800
E7FF
64 BEP1IN
E7C0
E7BF
64 Bytes EP1OUT
E780
E77F
E740 64 Bytes EP0 IN/OUT
E73F
64 Bytes RESERVED
E700
E6FF
8051 Addressable Registers
(512)
E500
E4FF
Reserved (128)
E480
E47F
128 Bytes GPIF Waveforms
E400
E3FF Reserved (512)
E200
E1FF
512 Bytes
8051 xdata RAM
E000
Endpoint RAM
Size Setup Data Buffer
■ 3 × 64 bytes (Endpoints 0 and 1) A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data
from a CONTROL transfer.
■ 8 × 512 bytes (Endpoints 2, 4, 6, 8)
Endpoint Configurations (Hi-Speed Mode)
Organization
Endpoints 0 and 1 are the same for every configuration.
■ EP0 Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT.
■ Bidirectional endpoint zero, 64-byte buffer
The endpoint buffers can be configured in any 1 of the 12
■ EP1IN, EP1OUT configurations shown in the vertical columns. When operating in
■ 64 byte buffers, bulk or interrupt the Full-Speed BULK mode, only the first 64 bytes of each buffer
are used. For example, in Hi-Speed mode, the max packet size
■ EP2, 4, 6, 8 is 512 bytes, but in Full-Speed mode, it is 64 bytes. Even though
a buffer is configured to a 512-byte buffer, in Full-Speed mode,
■ Eight 512-byte buffers, bulk, interrupt, or isochronous. EP4 and only the first 64 bytes are used. The unused endpoint buffer
EP8 can be double buffered; EP2 and 6 can be either double, space is not available for other operations. An example endpoint
triple, or quad buffered. For Hi-Speed endpoint configuration configuration is the EP2–1024 double-buffered; EP6–512
options, see Figure 5. quad-buffered (column 8).
EP0 IN&OUT 64 64 64 64 64 64 64 64 64 64 64 64
EP1 IN 64 64 64 64 64 64 64 64 64 64 64 64
EP1 OUT 64 64 64 64 64 64 64 64 64 64 64 64
EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2 EP2
512 512 512 512 512 512 512
1024 1024 1024
512 512 512 512 1024
512 512 512 1024
512
EP4 EP4 EP4
512 512 512 512 512 512
1024 1024 1024
EP6 1024
1024
512 512 512 512 512 512 512
EP6 EP6 EP6 EP6 EP6 EP6 EP6 EP6 EP6 512
1024
512 512 512 512 512 512 1024 1024
1024 1024 1024 512
512 512 512 512 512 512
1 2 3 4 5 6 7 8 9 10 11 12
Notes
7. “0” means “not implemented.”
8. “2×” means “double buffered.”
9. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
ECC Generation[10] under the control of a mode bit (AUTOPTRSET-UP.0). Using the
external FX2LP autopointer access (at 0xE67B–0xE67C)
The EZ-USB can calculate ECCs (Error Correcting Codes) on
enables the autopointer to access all internal and external RAM
data that passes across its GPIF or Slave FIFO interfaces. There
to the part.
are two ECC configurations: Two ECCs, each calculated over
256 bytes (SmartMedia Standard); and one ECC calculated over Also, autopointers can point to any FX2LP register or endpoint
512 bytes. buffer space. When the autopointer access to external memory
is enabled, locations 0xE67B and 0xE67C in XDATA and code
The ECC can correct any one-bit error or detect any two-bit error.
space cannot be used.
ECC Implementation
I2C Controller
The two ECC configurations are selected by the ECCM bit:
FX2LP has one I2C port that is driven by two internal controllers,
ECCM = 0 the one that automatically operates at boot time to load
Two 3-byte ECCs, each calculated over a 256-byte block of data. VID/PID/DID and configuration information, and another that the
This configuration conforms to the SmartMedia Standard. 8051 uses when running to control external I2C devices. The I2C
port operates in master mode only.
Write any value to ECCRESET, then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 256 bytes of data I2C Port Pins
is calculated and stored in ECC1. The ECC for the next 256 bytes
is stored in ECC2. After the second ECC is calculated, the values The I2C pins SCL and SDA must have external 2.2-k pull-up
in the ECCx registers do not change until ECCRESET is written resistors even if no EEPROM is connected to the FX2LP.
again, even if more data is subsequently passed across the External EEPROM device address pins must be configured
interface. properly. See Table 8 for configuring the device address pins.
ECCM = 1 Table 8. Strap Boot EEPROM Address Lines to These Values
One 3-byte ECC calculated over a 512-byte block of data. Bytes Example EEPROM A2 A1 A0
Write any value to ECCRESET then pass data across the GPIF 16 24LC00[12] N/A N/A N/A
or Slave FIFO interface. The ECC for the first 512 bytes of data
is calculated and stored in ECC1; ECC2 is unused. After the 128 24LC01 0 0 0
ECC is calculated, the values in ECC1 do not change even if 256 24LC02 0 0 0
more data is subsequently passed across the interface, till 4K 24LC32 0 0 1
ECCRESET is written again.
8K 24LC64 0 0 1
USB Uploads and Downloads 16K 24LC128 0 0 1
The core has the ability to directly edit the data contents of the
internal 16-KB RAM and of the internal 512-byte scratch pad I2C Interface Boot Load Access
RAM via a vendor-specific command. This capability is normally
used when soft downloading the user code and is available only At power-on reset, the I2C interface boot loader loads the
to and from the internal RAM, only when the 8051 is held in reset. VID/PID/DID configuration bytes and up to 16 KB of
The available RAM spaces are 16 KB from 0x0000–0x3FFF program/data. The available RAM spaces are 16 KB from
(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad 0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051
data RAM)[11]. is in reset. I2C interface boot loads only occur after power-on
reset.
Autopointer Access
I2C Interface General-Purpose Access
FX2LP provides two identical autopointers. They are similar to
The 8051 can control peripherals connected to the I2C bus using
the internal 8051 data pointers but with an additional feature:
the I2CTL and I2DAT registers. FX2LP provides I2C master
they can optionally increment after every memory access. This
control only; it is never an I2C slave.
capability is available to and from both internal and external
RAM. Autopointers are available in external FX2LP registers
Notes
10. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
11. After the data is downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory.
12. This EEPROM does not have address pins.
Compatible with Previous Generation EZ-USB FX2 CY7C68013A/14A and CY7C68015A/16A Differences
The EZ-USB FX2LP is form-, fit-, and with minor exceptions, CY7C68013A is identical to CY7C68014A in form, fit, and
functionally-compatible with its predecessor, the EZ-USB FX2. functionality. CY7C68015A is identical to CY7C68016A in form,
This makes for an easy transition for designers wanting to fit, and functionality. CY7C68014A and CY7C68016A have a
upgrade their systems from the FX2 to the FX2LP. The pinout lower suspend current than CY7C68013A and CY7C68015A
and package selection are identical and a vast majority of respectively and are ideal for power-sensitive battery
firmware previously developed for the FX2 functions in the applications.
FX2LP. CY7C68015A and CY7C68016A are available in 56-pin QFN
For designers migrating from the FX2 to the FX2LP, a change in package only. Two additional GPIO signals are available on the
the bill of material and review of the memory allocation (due to CY7C68015A and CY7C68016A to provide more flexibility when
increased internal memory) is required. For more information neither IFCLK or CLKOUT are needed in the 56-pin package.
about migrating from EZ-USB FX2 to EZ-USB FX2LP, see the USB developers wanting to convert their FX2 56-pin application
application note titled Migrating from EZ-USB FX2 to EZ-USB to a bus-powered system directly benefit from these additional
FX2LP available in the Cypress web site. signals. The two GPIOs give developers the signals they need
for the power-control circuitry of their bus-powered application
Table 9. Part Number Conversion Table without pushing them to a high-pincount version of FX2LP.
EZ-USB FX2 EZ-USB FX2LP Package The CY7C68015A is only available in the 56-pin QFN package
Part Number Part Number Description
CY7C68013A-56PVXC or 56-pin Table 10. CY7C68013A/14A and CY7C68015A/16A
CY7C68013-56PVC Pin Differences
CY7C68014A-56PVXC SSOP
56-pin CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A
CY7C68013A-56PVXCT or SSOP – IFCLK PE0
CY7C68013-56PVCT
CY7C68014A-56PVXCT Tape and
Reel CLKOUT PE1
CY7C68013A-56LFXC or
CY7C68013-56LFC 56-pin QFN
CY7C68014A-56LFXC
CY7C68013A-100AXC or 100-pin
CY7C68013-100AC
CY7C68014A-100AXC TQFP
CY7C68013A-128AXC or 128-pin
CY7C68013-128AC
CY7C68014A-128AXC TQFP
Pin Assignments
Figure 6 on page 19 identifies all signals for the five package The 100-pin package adds functionality to the 56-pin package by
types. The following pages illustrate the individual pin diagrams, adding these pins:
plus a combination diagram showing which of the full set of
signals are available in the 128-pin, 100-pin, and 56-pin ■ PORTC or alternate GPIFADR[7:0] address signals
packages. ■ PORTE or alternate GPIFADR[8] address signal and seven
The signals on the left edge of the 56-pin package in Figure 6 additional 8051 signals
on page 19 are common to all versions in the FX2LP family with ■ Three GPIF Control signals
the noted differences between the CY7C68013A/14A and the
CY7C68015A/16A. ■ Four GPIF Ready signals
Three modes are available in all package versions: Port, GPIF ■ Nine 8051 signals (two USARTs, three timer inputs, INT4, and
master, and Slave FIFO. These modes define the signals on the INT5#)
right edge of the diagram. The 8051 selects the interface mode
using the IFCONFIG[1:0] register bits. Port mode is the power on ■ BKPT, RD#, WR#.
default configuration. The 128-pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100-pin version.
In the 100-pin and 128-pin versions, an 8051 control bit can be
set to pulse the RD# and WR# pins when the 8051 reads
from/writes to PORTC. This feature is enabled by setting the
PORTCSTB bit in the CPUCS register.
PORTC Strobe Feature Timings on page 46 displays the timing
diagram of the read and write strobing function on accessing
PORTC.
Figure 6. Signal
Port GPIF Master Slave FIFO
PD7 FD[15] FD[15]
PD6 FD[14] FD[14]
PD5 FD[13] FD[13]
PD4 FD[12] FD[12]
PD3 FD[11] FD[11]
PD2 FD[10] FD[10]
PD1 FD[9] FD[9]
PD0 FD[8] FD[8]
PB7 FD[7] FD[7]
PB6 FD[6] FD[6]
PB5 FD[5] FD[5]
XTALIN PB4 FD[4] FD[4]
XTALOUT PB3 FD[3] FD[3]
RESET# PB2 FD[2] FD[2]
WAKEUP# FD[1] FD[1]
PB1
PB0 FD[0] FD[0]
SCL 56
SDA
RDY0 SLRD
RDY1 SLWR
**PE0 replaces IFCLK
& PE1 replaces CLKOUT CTL0 FLAGA
on CY7C68015A/16A CTL1 FLAGB
**PE0 CTL2 FLAGC
**PE1
INT0#/PA0 INT0#/PA0 INT0#/ PA0
IFCLK INT1#/PA1 INT1#/PA1 INT1#/ PA1
CLKOUT PA2 PA2 SLOE
WU2/PA3 WU2/PA3 WU2/PA3
DPLUS PA4 PA4 FIFOADR0
DMINUS PA5 PA5 FIFOADR1
PA6 PA6 PKTEND
PA7 PA7 PA7/FLAGD/SLCS#
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
100 RDY5
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4 RxD0
PORTC3/GPIFADR3 TxD0
PORTC2/GPIFADR2 RxD1
PORTC1/GPIFADR1 TxD1
PORTC0/GPIFADR0 INT4
PE7/GPIFADR8 INT5#
PE6/T2EX T2
PE5/INT6 T1
PE4/RxD1OUT T0
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT RD#
PE0/T0OUT WR#
D7 CS#
D6 OE#
D5 PSEN#
D4
D3 A15
D2 A14
D1 A13
D0
A12
A11
A10
128 A9
A8
A7
A6
A5
A4
EA A3
A2
A1
A0
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
PSEN#
RXD0
RXD1
TXD0
TXD1
WR#
GND
GND
VCC
VCC
VCC
RD#
CS#
D0
D1
D2
D3
D4
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CLKOUT
GND
PD7/FD15
PD6/FD14
PD5/FD13
PD4/FD12
GND
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RXD1OUT
PE3/RXD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
VCC
INT5#
PD3/FD11
PD2/FD10
PD1/FD9
1 VCC PD0/FD8 80
2 GND *WAKEUP 79
3 RDY0/*SLRD VCC 78
4 RDY1/*SLWR RESET# 77
5 RDY2 CTL5 76
6 RDY3 GND 75
7 RDY4 PA7/*FLAGD/SLCS# 74
8 RDY5 PA6/*PKTEND 73
9 AVCC PA5/FIFOADR1 72
10 XTALOUT PA4/FIFOADR0 71
11 XTALIN PA3/*WU2 70
12 AGND PA2/*SLOE 69
13 NC PA1/INT1# 68
14 NC PA0/INT0# 67
15 NC CY7C68013A/CY7C68014A VCC 66
16 AVCC 100-pin TQFP GND 65
17 DPLUS PC7/GPIFADR7 64
18 DMINUS PC6/GPIFADR6 63
19 AGND PC5/GPIFADR5 62
20 VCC PC4/GPIFADR4 61
21 GND PC3/GPIFADR3 60
22 INT4 PC2/GPIFADR2 59
23 T0 PC1/GPIFADR1 58
24 T1 PC0/GPIFADR0 57
25 T2 CTL2/*FLAGC 56
26 *IFCLK CTL1/*FLAGB 55
27 RESERVED CTL0/*FLAGA 54
28 BKPT VCC 53
29 SCL CTL4 52
30 SDA CTL3 51
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
RXD0
RXD1
TXD0
TXD1
WR#
GND
GND
GND
VCC
VCC
VCC
31 RD#
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CY7C68013A/CY7C68014A
56-pin SSOP
1 PD5/FD13 PD4/FD12 56
2 PD6/FD14 PD3/FD11 55
3 PD7/FD15 PD2/FD10 54
4 GND PD1/FD9 53
5 CLKOUT PD0/FD8 52
6 VCC *WAKEUP 51
7 GND VCC 50
8 RDY0/*SLRD RESET# 49
9 RDY1/*SLWR GND 48
10 AVCC PA7/*FLAGD/SLCS# 47
11 XTALOUT PA6/PKTEND 46
12 XTALIN PA5/FIFOADR1 45
13 AGND PA4/FIFOADR0 44
14 AVCC PA3/*WU2 43
15 DPLUS PA2/*SLOE 42
16 DMINUS PA1/INT1# 41
17 AGND PA0/INT0# 40
18 VCC VCC 39
19 GND CTL2/*FLAGC 38
20 *IFCLK CTL1/*FLAGB 37
21 RESERVED CTL0/*FLAGA 36
22 SCL GND 35
23 SDA VCC 34
24 VCC GND 33
25 PB0/FD0 PB7/FD7 32
26 PB1/FD1 PB6/FD6 31
27 PB2/FD2 PB5/FD5 30
28 PB3/FD3 PB4/FD4 29
CLKOUT/**PE1
*WAKEUP
PD7/FD15
PD6/FD14
PD5/FD13
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
GND
GND
VCC
VCC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
RDY0/*SLRD 1 42 RESET#
RDY1/*SLWR 2 41 GND
AVCC 3 40 PA7/*FLAGD/SLCS#
XTALOUT 4 39 PA6/*PKTEND
XTALIN 5 CY7C68013A/CY7C68014A 38 PA5/FIFOADR1
&
AGND 6 CY7C68015A/CY7C68016A 37 PA4/FIFOADR0
AVCC 7 36 PA3/*WU2
56-pin QFN
DPLUS 8 35 PA2/*SLOE
DMINUS 9 34 PA1/INT1#
AGND 10 33 PA0/INT0#
VCC 11 32 VCC
GND 12 31 CTL2/*FLAGC
*IFCLK/**PE0 13 30 CTL1/*FLAGB
RESERVED 14 29 CTL0/*FLAGA
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
GND
VCC
GND
1 2 3 4 5 6 7 8
A 1A 2A 3A 4A 5A 6A 7A 8A
B 1B 2B 3B 4B 5B 6B 7B 8B
C 1C 2C 3C 4C 5C 6C 7C 8C
D 1D 2D 7D 8D
E 1E 2E 7E 8E
F 1F 2F 3F 4F 5F 6F 7F 8F
G 1G 2G 3G 4G 5G 6G 7G 8G
H 1H 2H 3H 4H 5H 6H 7H 8H
2 1 6 55 5A VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
26 20 18 11 1G VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
43 33 24 17 7E VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
48 38 – – – VCC Power N/A N/A VCC. Connect to 3.3-V power source.
64 49 34 27 8E VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
68 53 – – – VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
81 66 39 32 5C VCC Power N/A N/A VCC. Connect to the 3.3-V power source.
Register Summary
FX2LP register bit definitions are described in the FX2LP TRM in greater detail.
Table 12. FX2LP Register Summary
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
GPIF Waveform Memories
E400 128 WAVEDATA GPIF Waveform D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
Descriptor 0, 1, 2, 3 data
E480 128 reserved
GENERAL CONFIGURATION
E50D GPCR2 General Purpose Configu- reserved reserved reserved FULL_SPEE reserved reserved reserved reserved 00000000 R
ration Register 2 D_ONLY
E600 1 CPUCS CPU Control & Status 0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr
E601 1 IFCONFIG Interface Configuration IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW
(Ports, GPIF, slave FIFOs)
E602 1 PINFLAGSAB [15] Slave FIFO FLAGA and FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000 RW
FLAGB Pin Configuration
E603 1 PINFLAGSCD[15] Slave FIFO FLAGC and FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0 00000000 RW
FLAGD Pin Configuration
E604 1 FIFORESET [15] Restore FIFOS to default NAKALL 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
state
E605 1 BREAKPT Breakpoint Control 0 0 0 0 BREAK BPPULSE BPEN 0 00000000 rrrrbbbr
E606 1 BPADDRH Breakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
E607 1 BPADDRL Breakpoint Address L A7 A6 A5 A4 A3 A2 A1 A0 xxxxxxxx RW
E608 1 UART230 230 Kbaud internally 0 0 0 0 0 0 230UART1 230UART0 00000000 rrrrrrbb
generated ref. clock
E609 1 FIFOPINPOLAR [15] Slave FIFO Interface pins 0 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb
polarity
E60A 1 REVID Chip Revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 RevA R
00000001
E60B 1 REVCTL[15] Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb
UDMA
E60C 1 GPIFHOLDAMOUNT MSTB Hold Time 0 0 0 0 0 0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
(for UDMA)
3 reserved
ENDPOINT CONFIGURATION
E610 1 EP1OUTCFG Endpoint 1-OUT VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
Configuration
E611 1 EP1INCFG Endpoint 1-IN VALID 0 TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
Configuration
E612 1 EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 10100010 bbbbbrbb
E613 1 EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 10100000 bbbbrrrr
E614 1 EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 11100010 bbbbbrbb
E615 1 EP8CFG Endpoint 8 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 11100000 bbbbrrrr
2 reserved
E618 1 EP2FIFOCFG[15] Endpoint 2 / slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
configuration
E619 1 EP4FIFOCFG[15] Endpoint 4 / slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
configuration
E61A 1 EP6FIFOCFG [15] Endpoint 6 / slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
configuration
E61B 1 EP8FIFOCFG [15] Endpoint 8 / slave FIFO 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE 00000101 rbbbbbrb
configuration
E61C 4 reserved
E620 1 EP2AUTOINLENH[15 Endpoint 2 AUTOIN 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
Packet Length H
E621 1 EP2AUTOINLENL[15] Endpoint 2 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
Packet Length L
E622 1 EP4AUTOINLENH[15] Endpoint 4 AUTOIN 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
Packet Length H
E623 1 EP4AUTOINLENL[15] Endpoint 4 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
Packet Length L
E624 1 EP6AUTOINLENH[15] Endpoint 6 AUTOIN 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
Packet Length H
E625 1 EP6AUTOINLENL[15] Endpoint 6 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
Packet Length L
E626 1 EP8AUTOINLENH[15] Endpoint 8 AUTOIN 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
Packet Length H
E627 1 EP8AUTOINLENL[15] Endpoint 8 AUTOIN PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
Packet Length L
E628 1 ECCCFG ECC Configuration 0 0 0 0 0 0 0 ECCM 00000000 rrrrrrrb
E629 1 ECCRESET ECC Reset x x x x x x x x 00000000 W
E62A 1 ECC1B0 ECC1 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 00000000 R
Note
15. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay.”
Notes
16. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay.”
17. The register can only be reset; it cannot be set.
ENDPOINTS
E68A 1 EP0BCH[19] Endpoint 0 Byte Count H (BC15) (BC14) (BC13) (BC12) (BC11) (BC10) (BC9) (BC8) xxxxxxxx RW
E68B 1 EP0BCL[19] Endpoint 0 Byte Count L (BC7) BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E68C 1 reserved
E68D 1 EP1OUTBC Endpoint 1 OUT Byte 0 BC6 BC5 BC4 BC3 BC2 BC1 BC0 0xxxxxxx RW
Count
E68E 1 reserved
E68F 1 EP1INBC Endpoint 1 IN Byte Count 0 BC6 BC5 BC4 BC3 BC2 BC1 BC0 0xxxxxxx RW
E690 1 EP2BCH[19] Endpoint 2 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 00000xxx RW
E691 1 EP2BCL[19] Endpoint 2 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E692 2 reserved
E694 1 EP4BCH[19] Endpoint 4 Byte Count H 0 0 0 0 0 0 BC9 BC8 000000xx RW
E695 1 EP4BCL[19] Endpoint 4 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E696 2 reserved
E698 1 EP6BCH[19] Endpoint 6 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 00000xxx RW
E699 1 EP6BCL[19] Endpoint 6 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
Notes
18. The register can only be reset; it cannot be set.
19. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay.”
Note
20. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay.”
E6F4 1 GPIFREADYSTAT GPIF Ready Status 0 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 00xxxxxx R
E6F5 1 GPIFABORT Abort GPIF Waveforms x x x x x x x x xxxxxxxx W
E6F6 2 reserved
ENDPOINT BUFFERS
E740 64 EP0BUF EP0-IN/-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E780 64 EP10UTBUF EP1-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E7C0 64 EP1INBUF EP1-IN buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E800 2048 reserved RW
F000 1024 EP2FIFOBUF 512/1024 byte EP 2 / slave D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
FIFO buffer (IN or OUT)
F400 512 EP4FIFOBUF 512 byte EP 4 / slave FIFO D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
buffer (IN or OUT)
F600 512 reserved
Note
21. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay.”
Notes
22. If no EEPROM is detected by the SIE then the default is 00000000.
23. SFRs not part of the standard 8051 architecture.
Notes
24. SFRs not part of the standard 8051 architecture.
25. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for “Synchronization Delay.”
Thermal Characteristics
Maximum junction temperature ................................. 125 °C
The following table displays the thermal characteristics of various packages:
Table 13. Thermal Characteristics
Jc Ja
Package Ambient Temperature (°C) Junction to Case Junction to Ambient Thermal
Thermal Resistance (°C/W) Resistance (°C/W)
56 SSOP 70 24.4 47.7
100 TQFP 70 11.9 45.9
128 TQFP 70 15.5 43.2
56 QFN 70 10.6 25.2
56 VFBGA 70 30.9 58.6
The junction temperature j, can be calculated using the following equation: j = P*Ja + a
Where,
P = Power
Ja = Junction to ambient temperature (Jc + Ca)
a = Ambient temperature (70 °C)
The case temperature c, can be calculated using the following equation: c = P*Ca + a
where,
P = Power
Ca = Case to ambient temperature
a = Ambient temperature (70 °C)
Note
26. Do not power I/O with the chip power OFF.
DC Characteristics
Table 14. DC Characteristics
Parameter Description Conditions Min Typ Max Unit
VCC Supply voltage – 3.00 3.3 3.60 V
VCC Ramp Up 0 to 3.3 V – 200 – – s
VIH Input HIGH voltage – 2 – 5.25 V
VIL Input LOW voltage – –0.5 – 0.8 V
VIH_X Crystal input HIGH voltage – 2 – 5.25 V
VIL_X Crystal input LOW voltage – –0.5 – 0.8 V
II Input leakage current 0< VIN < VCC – – ±10 A
VOH Output voltage HIGH IOUT = 4 mA 2.4 – – V
VOL Output LOW voltage IOUT = –4 mA – – 0.4 V
IOH Output current HIGH – – – 4 mA
IOL Output current LOW – – – 4 mA
Except D+/D– – – 10 pF
CIN Input pin capacitance
D+/D– – – 15 pF
Suspend current Connected – 300 380[27] A
CY7C68014/CY7C68016 Disconnected – 100 150[27] A
ISUSP
Suspend current Connected – 0.5 1.2[27] mA
CY7C68013/CY7C68015 Disconnected – 0.3 1.0[27] mA
8051 running, connected to USB HS – 50 85 mA
ICC Supply current
8051 running, connected to USB FS – 35 65 mA
Reset time after valid power 5.0 – – ms
TRESET VCC min = 3.0 V
Pin reset after powered on 200 – – s
USB Transceiver
USB 2.0 compliant in Full Speed and Hi-Speed modes.
Note
27. Measured at Max VCC, 25 °C.
AC Electrical Characteristics
USB Transceiver
USB 2.0 compliant in Full-Speed and Hi-Speed modes.
tCL
CLKOUT[28]
tAV tAV
A[15..0]
tSTBL tSTBH
PSEN#
tDH
tACC1[29]
D[7..0]
data in
tSOEL
OE#
tSCSL
CS#
Notes
28. CLKOUT is shown with positive polarity.
29. tACC1 is computed from these parameters as follows:
tACC1(24 MHz) = 3*tCL – tAV – tDSU = 106 ns.
tACC1(48 MHz) = 3*tCL – tAV – tDSU = 43 ns.
CLKOUT[28]
tAV tAV
A[15..0]
tSTBL tSTBH
RD#
tSCSL
CS#
tSOEL
OE#
tDSU
[31] tDH
tACC2
D[7..0]
data in
tCL Stretch = 1
CLKOUT[28]
tAV
A[15..0]
RD#
CS#
tDSU
tDH
tACC3 [31]
D[7..0]
data in
Notes
30. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including typical
strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual. The address cycle width can be interpreted from these.
31. tACC2 and tACC3 are computed from these parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 MHz) = 3*tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 190 ns
tACC3(48 MHz) = 5*tCL – tAV – tDSU = 86 ns.
tCL
CLKOUT
tAV
tSTBL tSTBH tAV
A[15..0]
WR#
tSCSL
CS#
tON1
tOFF1
D[7..0] data out
tCL Stretch = 1
CLKOUT
tAV
A[15..0]
WR#
CS#
tON1
tOFF1
D[7..0] data out
Note
32. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including
typical strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual. The address cycle width can be interpreted from these.
As for read, the value of PORTC three clock cycles before the Following is the timing diagram of the read and write strobing
assertion of RD# is the value that the 8051 reads in. The RD# is function on accessing PORTC. Refer to Data Memory Read[30]
pulsed for two clock cycles after three clock cycles from the point on page 44 and Data Memory Write[32] on page 45 for details on
when the 8051 has performed a read function on PORTC. propagation delay of RD# and WR# signals.
tCLKOUT
CLKOUT
PORTC IS UPDATED
tSTBL tSTBH
WR#
tCLKOUT
CLKOUT
8051 READS PORTC DATA MUST BE HELD FOR 3 CLK CYLCES DATA CAN BE UPDATED BY EXTERNAL LOGIC
tSTBL tSTBH
RD#
IFCLK
tSGA
GPIFADR[8:0]
RDYX
tSRY
tRYH
DATA(input) valid
tSGD tDAH
CTLX
tXCTL
DATA(output) N N+1
tXGD
Table 18. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[33, 34]
Typ
Parameter Description Min Max Unit
Min Max
tIFCLK IFCLK Period 20.83 – – – ns
tSRY RDYX to clock setup time 8.9 – – – ns
tRYH RDYX Hold Time 0 – – – ns
tSGD GPIF data to clock setup time 9.2 – – – ns
tDAH GPIF data hold time 0 – – – ns
tSGA Clock to GPIF address propagation delay – 7.5 – – ns
tXGD Clock to GPIF data output propagation delay – 10 – – ns
tXCTL Clock to CTLX output propagation delay – 6.7 – – ns
tIFCLKR IFCLK rise time – – – 900 ps
tIFCLKF IFCLK fall time – – – 900 ps
tIFCLKOD IFCLK output duty cycle – – 49 51 %
tIFCLKJ IFCLK jitter peak to peak – – – 300 ps
Table 19. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[34]
Parameter Description Min Max Unit
tIFCLK IFCLK period[35] 20.83 200 ns
tSRY RDYX to clock setup time 2.9 – ns
tRYH RDYX Hold Time 3.7 – ns
tSGD GPIF data to clock setup time 3.2 – ns
tDAH GPIF data hold time 4.5 – ns
tSGA Clock to GPIF address propagation delay – 11.5 ns
tXGD Clock to GPIF data output propagation delay – 15 ns
tXCTL Clock to CTLX output propagation delay – 10.7 ns
Notes
33. Dashed lines denote signals with programmable polarity.
34. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
35. IFCLK must not exceed 48 MHz.
IFCLK
tSRD tRDH
SLRD
tXFLG
FLAGS
DATA N N+1
tOEon tXFD tOEoff
SLOE
Table 20. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[37]
Typ
Parameter Description Min Max Unit
Min Max
tIFCLK IFCLK period 20.83 – – – ns
tSRD SLRD to clock setup time 18.7 – – – ns
tRDH Clock to SLRD hold time 0 – – – ns
tOEon SLOE turn on to FIFO data valid – 10.5 – – ns
tOEoff SLOE turn off to FIFO data hold – 10.5 – – ns
tXFLG Clock to FLAGS output propagation delay – 9.5 – – ns
tXFD Clock to FIFO data output propagation delay – 11 – – ns
tIFCLKR IFCLK rise time – – – 900 ps
tIFCLKF IFCLK fall time – – – 900 ps
tIFCLKOD IFCLK output duty cycle – – 49 51 %
tIFCLKJ IFCLK jitter peak to peak – – – 300 ps
Table 21. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[37]
Parameter Description Min Max Unit
tIFCLK IFCLK period 20.83 200 ns
tSRD SLRD to clock setup time 12.7 – ns
tRDH Clock to SLRD hold time 3.7 – ns
tOEon SLOE turn on to FIFO data valid – 10.5 ns
tOEoff SLOE turn off to FIFO data hold – 10.5 ns
tXFLG Clock to FLAGS output propagation delay – 13.5 ns
tXFD Clock to FIFO data output propagation delay – 15 ns
Notes
36. Dashed lines denote signals with programmable polarity.
37. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
SLRD tRDpwl
tXFLG
FLAGS tXFD
DATA N N+1
tOEon tOEoff
SLOE
Notes
38. Dashed lines denote signals with programmable polarity.
39. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
IFCLK
SLWR tWRH
tSWR
DATA Z N Z
tSFD tFDH
FLAGS
tXFLG
Table 23. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[41]
Parameter Description Min Max Unit
tIFCLK IFCLK period 20.83 – ns
tSWR SLWR to clock setup time 10.4 – ns
tWRH Clock to SLWR hold time 0 – ns
tSFD FIFO data to clock setup time 9.2 – ns
tFDH Clock to FIFO data hold time 0 – ns
tXFLG Clock to FLAGS output propagation time – 9.5 ns
Table 24. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[41]
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 200 ns
tSWR SLWR to clock setup time 12.1 – ns
tWRH Clock to SLWR hold time 3.6 – ns
tSFD FIFO data to clock setup time 3.2 – ns
tFDH Clock to FIFO data hold time 4.5 – ns
tXFLG Clock to FLAGS output propagation time – 13.5 ns
Notes
40. Dashed lines denote signals with programmable polarity.
41. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
tSFD tFDH
DATA
FLAGS tXFD
Table 25. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK[43]
Parameter Description Min Max Unit
tWRpwl SLWR pulse LOW 50 – ns
tWRpwh SLWR pulse HIGH 70 – ns
tSFD SLWR to FIFO DATA setup time 10 – ns
tFDH FIFO DATA to SLWR hold time 10 – ns
tXFD SLWR to FLAGS output propagation delay – 70 ns
Notes
42. Dashed lines denote signals with programmable polarity.
43. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Figure 23. Slave FIFO Synchronous Packet End Strobe Timing Diagram [44]
IFCLK
tPEH
PKTEND tSPE
FLAGS
tXFLG
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[45]
Parameter Description Min Max Unit
tIFCLK IFCLK period 20.83 – ns
tSPE PKTEND to clock setup time 14.6 – ns
tPEH Clock to PKTEND hold time 0 – ns
tXFLG Clock to FLAGS output propagation delay – 9.5 ns
Table 27. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[45]
Parameter Description Min Max Unit
tIFCLK IFCLK period 20.83 200 ns
tSPE PKTEND to clock setup time 8.6 – ns
tPEH Clock to PKTEND hold time 2.5 – ns
tXFLG Clock to FLAGS output propagation delay – 13.5 ns
Notes
44. Dashed lines denote signals with programmable polarity.
45. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
There is no specific timing requirement that should be met for caused the last byte or word to be clocked into the previous auto
asserting the PKTEND pin to asserting SLWR. PKTEND can be committed packet. Figure 24 shows this scenario. X is the value
asserted with the last data value clocked into the FIFOs or the AUTOINLEN register is set to when the IN endpoint is
thereafter. The setup time tSPE and the hold time tPEH must be configured to be in auto mode.
met. Figure 24 shows a scenario where two packets are committed.
Although there are no specific timing requirements for PKTEND The first packet gets committed automatically when the number
assertion, there is a specific corner-case condition that needs of bytes in the FIFO reaches X (value set in AUTOINLEN
attention while using the PKTEND pin to commit a one byte or register) and the second one byte/word short packet being
word packet. There is an additional timing requirement that committed manually using PKTEND.
needs to be met when the FIFO is configured to operate in auto Note that there is at least one IFCLK cycle timing between the
mode and it is required to send two packets back to back: a full assertion of PKTEND and clocking of the last byte of the previous
packet (full defined as the number of bytes in the FIFO meeting packet (causing the packet to be committed automatically).
the level set in AUTOINLEN register) committed automatically Failing to adhere to this timing results in the FX2 failing to send
followed by a short one byte or word packet committed manually the one byte or word short packet.
using the PKTEND pin. In this scenario, the user must ensure to
assert PKTEND, at least one clock cycle after the rising edge that
Figure 24. Slave FIFO Synchronous Write Sequence and Timing Diagram[46]
tIFCLK
IFCLK
tSFA tFAH
FIFOADR
SLWR
tSFD tFDH tSFD tFDH tSFD tFDH tSFD tFDH tSFD tFDH tSFD tFDH
PKTEND
Note
46. Dashed lines denote signals with programmable polarity.
Figure 25. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[47]
tPEpwh
PKTEND tPEpwl
FLAGS
tXFLG
tOEoff
tOEon
DATA
FIFOADR [1.0]
tXFLG
FLAGS
tXFD
DATA N N+1
Notes
47. Dashed lines denote signals with programmable polarity.
48. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
IFCLK
SLCS/FIFOADR [1:0]
tSFA tFAH
SLCS/FIFOADR [1:0]
tFAH
tSFA
SLRD/SLWR/PKTEND
Notes
49. Dashed lines denote signals with programmable polarity.
50. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
51. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Sequence Diagram
Single and Burst Synchronous Read Example
Figure 30. Slave FIFO Synchronous Read Sequence and Timing Diagram[52]
tIFCLK
IFCLK
tSFA tSFA
tFAH tFAH
FIFOADR
t=0 T=0
tSRD tRDH >= tSRD >= tRDH
SLRD
SLCS
tXFLG
FLAGS
SLOE
t=4 T=1 T=4
t=1
Figure 30 shows the timing relationship of the SLAVE FIFO asserted (The SLCS and SLRD signals must both be asserted
signals during a synchronous FIFO read using IFCLK as the to start a valid read condition).
synchronizing clock. The diagram illustrates a single read
followed by a burst read. ■ The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
■ At t = 0, the FIFO address is stable and the signal SLCS is from the newly addressed location to the data bus. After a
asserted (SLCS may be tied LOW in some applications). Note propagation delay of tXFD (measured from the rising edge of
that tSFA has a minimum of 25 ns. This means that when IFCLK IFCLK) the new data value is present. N is the first data value
is running at 48 MHz, the FIFO address setup time is more than read from the FIFO. To have data on the FIFO data bus, SLOE
one IFCLK cycle. MUST also be asserted.
■ At t = 1, SLOE is asserted. SLOE is an output enable only, The same sequence of events are shown for a burst read and
whose sole function is to drive the data bus. The data that is are marked with the time indicators of T = 0 through 5.
driven on the bus is the data that the internal FIFO pointer is Note For the burst mode, the SLRD and SLOE are left asserted
currently pointing to. In this example it is the first data value in during the entire duration of the read. In the burst read mode,
the FIFO. Note: the data is prefetched and is driven on the bus when SLOE is asserted, data indexed by the FIFO pointer is on
when SLOE is asserted. the data bus. During the first read cycle, on the rising edge of the
■ At t = 2, SLRD is asserted. SLRD must meet the setup time of clock, the FIFO pointer is updated and incremented to point to
tSRD (time from asserting the SLRD signal to the rising edge of address N+1. For each subsequent rising edge of IFCLK, while
the IFCLK) and maintain a minimum hold time of tRDH (time the SLRD is asserted, the FIFO pointer is incremented and the
from the IFCLK edge to the deassertion of the SLRD signal). next data value is placed on the data bus.
If the SLCS signal is used, it must be asserted before SLRD is
Note
52. Dashed lines denote signals with programmable polarity.
IFCLK
FIFOADR
SLWR
SLCS
tXFLG
tXFLG
FLAGS
PKTEND
Figure 32 shows the timing relationship of the SLAVE FIFO FIFO data bus is written to the FIFO on every rising edge of
signals during a synchronous write using IFCLK as the IFCLK. The FIFO pointer is updated on each rising edge of
synchronizing clock. The diagram illustrates a single write IFCLK. In Figure 32, after the four bytes are written to the FIFO,
followed by burst write of three bytes and committing all four SLWR is deasserted. The short 4 byte packet can be committed
bytes as a short packet using the PKTEND pin. to the host by asserting the PKTEND signal.
■ At t = 0 the FIFO address is stable and the signal SLCS is There is no specific timing requirement that should be met for
asserted. (SLCS may be tied LOW in some applications) Note asserting PKTEND signal with regards to asserting the SLWR
that tSFA has a minimum of 25 ns. This means when IFCLK is signal. PKTEND can be asserted with the last data value or
running at 48 MHz, the FIFO address setup time is more than thereafter. The only requirement is that the setup time tSPE and
one IFCLK cycle. the hold time tPEH must be met. In the scenario of Figure 32, the
number of data values committed includes the last value written
■ At t = 1, the external master/peripheral must outputs the data to the FIFO. In this example, both the data value and the
value onto the data bus with a minimum set up time of tSFD PKTEND signal are clocked on the same rising edge of IFCLK.
before the rising edge of IFCLK. PKTEND can also be asserted in subsequent clock cycles. The
■ At t = 2, SLWR is asserted. The SLWR must meet the setup FIFOADDR lines should be held constant during the PKTEND
time of tSWR (time from asserting the SLWR signal to the rising assertion.
edge of IFCLK) and maintain a minimum hold time of tWRH (time Although there are no specific timing requirement for the
from the IFCLK edge to the deassertion of the SLWR signal). PKTEND assertion, there is a specific corner-case condition that
If the SLCS signal is used, it must be asserted with SLWR or needs attention while using the PKTEND to commit a one
before SLWR is asserted (The SLCS and SLWR signals must byte/word packet. Additional timing requirements exist when the
both be asserted to start a valid write condition). FIFO is configured to operate in auto mode and it is desired to
send two packets: a full packet (‘full’ defined as the number of
■ While the SLWR is asserted, data is written to the FIFO and on bytes in the FIFO meeting the level set in the AUTOINLEN
the rising edge of the IFCLK, the FIFO pointer is incremented. register) committed automatically followed by a short one byte or
The FIFO flag is also updated after a delay of tXFLG from the word packet committed manually using the PKTEND pin.
rising edge of the clock.
In this case, the external master must ensure to assert the
The same sequence of events are also shown for a burst write PKTEND pin at least one clock cycle after the rising edge that
and are marked with the time indicators of T = 0 through 5. caused the last byte or word that needs to be clocked into the
Note For the burst mode, SLWR and SLCS are left asserted for previous auto committed packet (the packet with the number of
the entire duration of writing all the required data values. In this bytes equal to what is set in the AUTOINLEN register). Refer to
burst write mode, after the SLWR is asserted, the data on the Figure 24 on page 53 for further details on this timing.
Note
53. Dashed lines denote signals with programmable polarity.
Figure 33. Slave FIFO Asynchronous Read Sequence and Timing Diagram[54]
FIFOADR
t=0
tRDpwl tRDpwh T=0 tRDpwl tRDpwh tRDpwl tRDpwh tRDpwl tRDpwh
SLRD
SLCS
tXFLG
tXFLG
FLAGS
SLOE
SLOE SLRD SLRD SLOE SLOE SLRD SLRD SLRD SLRD SLOE
FIFO POINTER N N N N+1 N+1 N+1 N+1 N+2 N+2 N+3 N+3
FIFO DATA BUS Not Driven Driven: X N N Not Driven N N+1 N+1 N+2 N+2 Not Driven
Figure 33 shows the timing relationship of the SLAVE FIFO ■ The data that is driven, after asserting SLRD, is the updated
signals during an asynchronous FIFO read. It shows a single data from the FIFO. This data is valid after a propagation delay
read followed by a burst read. of tXFD from the activating edge of SLRD. In Figure 33, data N
is the first valid data read from the FIFO. For data to appear on
■ At t = 0, the FIFO address is stable and the SLCS signal is the data bus during the read cycle (SLRD is asserted), SLOE
asserted. must be in an asserted state. SLRD and SLOE can also be tied
■ At t = 1, SLOE is asserted. This results in the data bus being together.
driven. The data that is driven on to the bus is the previous The same sequence of events is also shown for a burst read
data, the data that was in the FIFO from an earlier read cycle. marked with T = 0 through 5.
■ At t = 2, SLRD is asserted. The SLRD must meet the minimum Note In the burst read mode, during SLOE is asserted, the data
active pulse of tRDpwl and minimum de-active pulse width of bus is in a driven state and outputs the previous data. After SLRD
tRDpwh. If SLCS is used, then SLCS must be asserted before is asserted, the data from the FIFO is driven on the data bus
SLRD is asserted (The SLCS and SLRD signals must both be (SLOE must also be asserted) and then the FIFO pointer is
asserted to start a valid read condition.) incremented.
Note
54. Dashed lines denote signals with programmable polarity.
Figure 35. Slave FIFO Asynchronous Write Sequence and Timing Diagram[55]
tSFA tFAH tSFA tFAH
FIFOADR
t=0 T=0
tWRpwl tWRpwh tWRpwl tWRpwh tWRpwl tWRpwh tWRpwl tWRpwh
SLWR
SLCS
tXFLG
tXFLG
FLAGS
PKTEND
Figure 35 shows the timing relationship of the SLAVE FIFO write The FIFO flag is also updated after tXFLG from the deasserting
in an asynchronous mode. The diagram shows a single write edge of SLWR.
followed by a burst write of 3 bytes and committing the 4byte The same sequence of events is shown for a burst write and is
short packet using PKTEND. indicated by the timing marks of T = 0 through 5.
■ At t = 0 the FIFO address is applied, ensuring that it meets the Note In the burst write mode, after SLWR is deasserted, the data
setup time of tSFA. If SLCS is used, it must also be asserted is written to the FIFO and then the FIFO pointer is incremented
(SLCS may be tied LOW in some applications). to the next byte in the FIFO. The FIFO pointer is post
■ At t = 1 SLWR is asserted. SLWR must meet the minimum incremented.
active pulse of tWRpwl and minimum de-active pulse width of In Figure 35, after the four bytes are written to the FIFO and
tWRpwh. If the SLCS is used, it must be asserted with SLWR or SLWR is deasserted, the short 4-byte packet can be committed
before SLWR is asserted. to the host using PKTEND. The external device should be
designed to not assert SLWR and the PKTEND signal at the
■ At t = 2, data must be present on the bus tSFD before the same time. It should be designed to assert the PKTEND after
deasserting edge of SLWR. SLWR is deasserted and met the minimum deasserted pulse
■ At t = 3, deasserting SLWR causes the data to be written from width. The FIFOADDR lines have to held constant during the
the data bus to the FIFO and then increments the FIFO pointer. PKTEND assertion.
Note
55. Dashed lines denote signals with programmable polarity.
Ordering Information
Table 33. Ordering Information
Note
56. As UART is not available in the 56-pin package of CY7C68013A, serial port debugging using Keil Monitor is not possible.
Package Diagrams
The FX2LP is available in five packages:
■ 56-pin SSOP
■ 56-pin QFN
■ 100-pin TQFP
■ 128-pin TQFP
■ 56-ball VFBGA
51-85062 *F
Figure 37. 56-pin QFN (8 × 8 × 1 mm) 4.5 × 5.2 E-Pad (Sawn) Package Outline, 001-53450
001-53450 *E
Figure 38. 100-pin TQFP (14 × 20 × 1.4 mm) Package Outline, 51-85050
ș2
ș1
DIMENSIONS NOTE:
SYMBOL
MIN. NOM. MAX.
1. ALL DIMENSIONS ARE IN MILLIMETERS.
A 1.60
2. BODY LENGTH DIMENSION DOES NOT
A1 0.05 0.15
INCLUDE MOLD PROTRUSION/END FLASH.
A2 1.35 1.40 1.45
D 15.80 16.00 16.20 MOLD PROTRUSION/END FLASH SHALL
D1 13.90 14.00 14.10 NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
E 21.80 22.00 22.20 BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1 19.90 20.00 20.10 BODY SIZE INCLUDING MOLD MISMATCH.
R1 0.08 0.20 3. JEDEC SPECIFICATION NO. REF: MS-026.
R2 0.08 0.20
ș 0° 7°
ș1 0°
ș2 11° 12° 13°
c 0.20
b 0.22 0.30 0.38
L 0.45 0.60 0.75
L1 1.00 REF
L2 0.25 BSC
L3 0.20
e 0.65 TYP
51-85050 *G
Figure 39. 128-pin TQFP (14 × 20 × 1.4 mm) Package Outline, 51-85101
51-85101 *F
Figure 40. 56-ball VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 Ball Package Outline, 001-03901
001-03901 *F
Note
57. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com and High Speed USB Platform Design Guidelines,
http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
Solder Mask
Cu Fill Cu Fill
0.013” dia
PCB Material PCB Material
Via hole for thermally connecting the This figure only shows the top three layers of the
QFN to the circuit board ground plane. circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
Errata
This section describes the errata for the EZ-USB® FX2LP™ CY7C68013A/14A/15A/16A Rev. B silicon. Details include errata trigger
conditions, scope of impact, available workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
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