LatticeXP2FamilyDataSheet PDF
LatticeXP2FamilyDataSheet PDF
LatticeXP2FamilyDataSheet PDF
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Introduction
LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with non-volatile Flash cells in an architec-
ture referred to as flexiFLASH.
The flexiFLASH approach provides benefits including instant-on, infinite reconfigurability, on chip storage with
FlashBAK embedded block memory and Serial TAG memory and design security. The parts also support Live
Update technology with TransFR, 128-bit AES Encryption and Dual-boot technologies.
The LatticeXP2 FPGA fabric was optimized for the new technology from the outset with high performance and low
cost in mind. LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked
Loops (PLLs), pre-engineered source synchronous I/O support and enhanced sysDSP blocks.
Lattice Diamond® design software allows large and complex designs to be efficiently implemented using the
LatticeXP2 family of FPGA devices. Synthesis library support for LatticeXP2 is available for popular logic synthesis
tools. The Diamond software uses the synthesis tool output along with the constraints from its floor planning tools
to place and route the design in the LatticeXP2 device. The Diamond tool extracts the timing from the routing and
back-annotates it into the design for timing verification.
Lattice provides many pre-designed Intellectual Property (IP) LatticeCORE™ modules for the LatticeXP2 family. By
using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
1-2
LatticeXP2 Family Data Sheet
Architecture
August 2014 Data Sheet DS1009
Architecture Overview
Each LatticeXP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and a row of sys-
DSP™ Digital Signal Processing blocks as shown in Figure 2-1.
On the left and right sides of the Programmable Functional Unit (PFU) array, there are Non-volatile Memory Blocks.
In configuration mode the nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™
peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the con-
figuration SRAM. With this technology, expensive external configuration memory is not required, and designs are
secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via
wide busses happens in microseconds, providing an “instant-on” capability that allows easy interfacing in many
applications. LatticeXP2 devices can also transfer data from the sysMEM EBR blocks to the Non-volatile Memory
Blocks at user request.
There are two kinds of logic blocks, the PFU and the PFU without RAM (PFF). The PFU contains the building
blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic
and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be imple-
mented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used
per row.
LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18Kbit
memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addi-
tion, LatticeXP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumu-
lators, which are the building blocks for complex signal processing capabilities.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the
LatticeXP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards.
PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic
also includes pre-engineered support to aid in the implementation of high speed source synchronous standards
such as 7:1 LVDS interfaces, found in many display applications, and memory interfaces including DDR and DDR2.
The LatticeXP2 registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is
configured, the device enters into user mode with these registers SET/RESET according to the configuration set-
ting, allowing device entering to a known state for predictable system function.
Other blocks provided include PLLs and configuration functions. The LatticeXP2 architecture provides up to four
General Purpose PLLs (GPLL) per device. The GPLL blocks are located in the corners of the device.
The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates
and dual boot support is located between banks two and three. Every device in the LatticeXP2 family supports a
sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. A JTAG port is provided
between banks two and three.
This family also provides an on-chip oscillator. LatticeXP2 devices use 1.2V as their core voltage.
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
On-chip
Oscillator
Programmable
Function Units
(PFUs)
SPI Port
DSP Blocks
Flash
PFU Blocks
The core of the LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be pro-
grammed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be pro-
grammed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data
sheet will use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered Slice 0 through Slice 3, as shown in Figure 2-2.
All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated
with each PFU block.
2-2
Architecture
LatticeXP2 Family Data Sheet
From
Routing
LUT4 & LUT4 & LUT4 & LUT4 & LUT4 & LUT4 &
CARRY CARRY CARRY CARRY CARRY CARRY LUT4 LUT4
D D D D D D
FF FF FF FF FF FF
To
Routing
Slice
Slice 0 through Slice 2 contain two 4-input combinatorial Look-Up Tables (LUT4), which feed two registers. Slice 3
contains two LUT4s and no registers. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory,
a capability not available in PFF blocks. Table 2-1 shows the capability of the slices in both PFF and PFU blocks
along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be com-
bined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset func-
tions (programmable as synchronous/asynchronous), clock select, chip-select and wider RAM/ROM functions.
Figure 2-3 shows an overview of the internal logic of the slice. The registers in the slice can be configured as posi-
tive/negative edge triggered or level sensitive clocks.
Slice 0 through Slice 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adja-
cent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has
13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice
2.
2-3
Architecture
LatticeXP2 Family Data Sheet
SLICE
FXB OFX1
FXA
A1 CO F1
B1 F/SUM
C1
D1 LUT4 & D Q1
CARRY* FF*
CI To
Routing
M1
M0 LUT5
From Mux
Routing OFX0
A0 CO
B0
C0 F0
D0 LUT4 &
CARRY* F/SUM Q0
D
FF*
CI
CE
CLK
LSR
2-4
Architecture
LatticeXP2 Family Data Sheet
Modes of Operation
Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.
Logic Mode
In this mode, the LUTs in each slice are configured as LUT4s. A LUT4 has 16 possible input combinations. Four-
input logic functions are generated by programming the LUT4. Since there are two LUT4s per slice, a LUT5 can be
constructed within one slice. Larger LUTs such as LUT6, LUT7 and LUT8, can be constructed by concatenating
two or more slices. Note that a LUT8 requires more than four slices.
Ripple Mode
Ripple mode allows efficient implementation of small arithmetic functions. In ripple mode, the following functions
can be implemented by each slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/Subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Up/Down counter with async clear
• Up/Down counter with preload (sync)
• Ripple mode multiplier building block
• Multiplier support
• Comparator functions of A and B inputs
– A greater-than-or-equal-to B
– A not-equal-to B
– A less-than-or-equal-to B
Two carry signals, FCI and FCO, are generated per slice in this mode, allowing fast arithmetic functions to be con-
structed by concatenating slices.
RAM Mode
In this mode, a 16x4-bit distributed Single Port RAM (SPR) can be constructed using each LUT block in Slice 0 and
Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit Pseudo
Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice
as the read-only port.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of slices required to implement different distributed RAM primitives. For more information on
using RAM in LatticeXP2 devices, please see TN1137, LatticeXP2 Memory Usage Guide.
ROM Mode
ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in the ROM mode. Preloading is accom-
plished through the programming interface during PFU configuration.
2-5
Architecture
LatticeXP2 Family Data Sheet
Routing
There are many resources provided in the LatticeXP2 devices to route signals individually or as busses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) or x6 (spans seven PFU)
connections. The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions.
The x2 and x6 resources are buffered to allow both short and long connections routing between PFUs.
The LatticeXP2 family has an enhanced routing architecture to produce a compact design. The Diamond design
tool takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is
completely automatic, although an interactive routing editor is available to optimize the design.
CLKI, the PLL reference frequency, is provided either from the pin or from routing; it feeds into the Input Clock
Divider block. CLKFB, the feedback signal, is generated from CLKOP (the primary clock output) or from a user
clock pin/logic. CLKFB feeds into the Feedback Divider and is used to multiply the reference frequency.
Both the input path and feedback signals enter the Voltage Controlled Oscillator (VCO) block. The phase and fre-
quency of the VCO are determined from the input path and feedback signals. A LOCK signal is generated by the
VCO to indicate that the VCO is locked with the input clock signal.
The output of the VCO feeds into the CLKOP Divider, a post-scalar divider. The duty cycle of the CLKOP Divider
output can be fine tuned using the Duty Trim block, which creates the CLKOP signal. By allowing the VCO to oper-
ate at higher frequencies than CLKOP, the frequency range of the GPLL is expanded. The output of the CLKOP
Divider is passed through the CLKOK Divider, a secondary clock divider, to generate lower frequencies for the
CLKOK output. For applications that require even lower frequencies, the CLKOP signal is passed through a divide-
by-three divider to produce the CLKOK2 output. The CLKOK2 output is provided for applications that use source
synchronous logic. The Phase/Duty Cycle/Duty Trim block is used to adjust the phase and duty cycle of the CLKOP
Divider output to generate the CLKOS signal. The phase/duty cycle setting can be pre-programmed or dynamically
adjusted.
The clock outputs from the GPLL; CLKOP, CLKOK, CLKOK2 and CLKOS, are fed to the clock distribution network.
For further information on the GPLL please see TN1126, LatticeXP2 sysCLOCK PLL Design and Usage Guide.
2-6
Architecture
LatticeXP2 Family Data Sheet
WRDEL
DDUTY
DPHASE CLKOK2
3
Phase/ CLKOS
CLKI Duty Cycle/
CLKI
Divider Duty Trim
Clock Dividers
LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These are
intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or
÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock
based on the release of its reset signal. The clock dividers can be fed from the CLKOP output from the GPLLs or
from the Edge Clocks (ECLK). The clock divider outputs serve as primary clock sources and feed into the clock dis-
tribution network. The Reset (RST) control signal resets the input and forces all outputs to low. The RELEASE sig-
nal releases outputs to the input clock. For further information on clock dividers, please see TN1126, LatticeXP2
sysCLOCK PLL Design and Usage Guide. Figure 2-5 shows the clock divider connections.
2-7
Architecture
LatticeXP2 Family Data Sheet
ECLK
÷1
CLKOP (GPLL)
÷2
CLKDIV
÷4
RST
RELEASE ÷8
2-8
Architecture
LatticeXP2 Family Data Sheet
From Routing
CLK CLK
DIV DIV
Clock Clock
Input Input
From Routing
Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs.
2-9
Architecture
LatticeXP2 Family Data Sheet
2-10
Architecture
LatticeXP2 Family Data Sheet
CLKOP CLKOP
PLL PLL
GPLL CLKOS CLKOS GPLL
Input Input
Clock Clock
Input Input
Eight Edge Clocks (ECLK)
Clock Two Clocks per Edge Clock
Input Input
CLKOP CLKOP
PLL GPLL
PLL
CLKOS CLKOS GPLL
Input Input
Sources for left edge clocks Sources for right edge clocks
Sources for
bottom edge
clocks
From From
Routing Routing
Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs.
2-11
Architecture
LatticeXP2 Family Data Sheet
30:1 30:1 30:1 30:1 30:1 30:1 29:1 29:1 29:1 29:1
DCS DCS
Figure 2-10 shows the timing waveforms of the default DCS operating mode. The DCS block can be programmed
to other modes. For more information on the DCS, please see TN1126, LatticeXP2 sysCLOCK PLL Design and
Usage Guide.
CLK1
SEL
DCSOUT
2-12
Architecture
LatticeXP2 Family Data Sheet
LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have four
secondary clocks (SC0 to SC3) which are distributed to every region.
The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for
high fan-out signals.
Vertical Routing
Channel Regional
Boundary
I/O Bank 2
Region 1
Regional
Boundary
2-13
Architecture
LatticeXP2 Family Data Sheet
Clock/Control
If none of the signals are selected for both clock and control, then the default value of the mux output is 1. Slice 3
does not have any registers; therefore it does not have the clock or control muxes.
Primary Clock
8
Secondary Clock
4 Clock to Slice
25:1
Routing
12
Vcc
1
2-14
Architecture
LatticeXP2 Family Data Sheet
Secondary Clock
3
Slice Control
Routing 16:1
12
Vcc
1
(Both Muxes)
Routing
2-15
Architecture
LatticeXP2 Family Data Sheet
sysMEM Memory
LatticeXP2 devices contains a number of sysMEM Embedded Block RAM (EBR). The EBR consists of 18 Kbit
RAM with dedicated input and output registers.
2-16
Architecture
LatticeXP2 Family Data Sheet
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
EBR memory supports two forms of write behavior for single port or dual port operation:
1. Normal – Data on the output appears only during a read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through – A copy of the input data appears at the output of the same port during a write cycle. This
mode is supported for all data widths.
SET
Memory Core D Q Port A[17:0]
LCLR
Output Data
Latches
D
SET
Q Port B[17:0]
LCLR
RSTA
RSTB
GSRN
Programmable Disable
2-17
Architecture
LatticeXP2 Family Data Sheet
For further information on the sysMEM EBR block, please see TN1137, LatticeXP2 Memory Usage Guide.
Reset
Clock
Clock
Enable
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
sysDSP™ Block
The LatticeXP2 family provides a sysDSP block making it ideally suited for low cost, high performance Digital Sig-
nal Processing (DSP) applications. Typical functions used in these applications include Bit Correlators, Fast Fourier
Transform (FFT) functions, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/
Decoder and Convolutional Encoder/Decoder. These complex signal processing functions use similar building
blocks such as multiply-adders and multiply-accumulators.
2-18
Architecture
LatticeXP2 Family Data Sheet
Operand Operand
A B
x Multiplier 0
Multiplier 1
x x m/k
loops
Single
Multiplier
x M loops Multiplier k
Accumulator
Function implemented in
(k adds)
+
General purpose DSP
m/k
accumulate
Output
Function implemented
in LatticeXP2
The resources in each sysDSP block can be configured to support the following four elements:
• MULT (Multiply)
• MAC (Multiply, Accumulate)
• MULTADDSUB (Multiply, Addition/Subtraction)
• MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available in each block depends on the width selected from the three available options: x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-6 shows the capabilities of the block.
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift register from previous operand registers. By selecting ‘dynamic operation’ the following operations
are possible:
2-19
Architecture
LatticeXP2 Family Data Sheet
• In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle.
• In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle.
• The loading of operands can switch between parallel and serial operations.
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-20 shows the MULT sysDSP element.
Multiplicand m m
Multiplier n m
n
Input Data m Multiplier
m+n
Register
Register A
Output
(default) m+n
n
Input Data n
x Output
Register B Pipeline
m Register
n
Signed A Input To
Register Multiplier
Signed B Input To CLK (CLK0,CLK1,CLK2,CLK3)
Register Multiplier
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
2-20
Architecture
LatticeXP2 Family Data Sheet
Multiplicand m m
Accumulator
n m
Multiplier n m+n+16
Register
Output
Input Data m Multiplier (default)
x
Register A
n Output
m+n m+n+16
Input Data n (default) (default)
Register B Pipeline
n Register
Register
Output
n
Signed A Input Pipeline Overflow
To Accumulator
Register Register
signal
Signed B Input Pipeline
Register Register To Accumulator
Input Pipeline
Addn To Accumulator
Register Register
CLK (CLK0,CLK1,CLK2,CLK3)
Accumsload Input Pipeline
To Accumulator CE (CE0,CE1,CE2,CE3)
Register Register
RST(RST0,RST1,RST2,RST3)
SROB SROA
2-21
Architecture
LatticeXP2 Family Data Sheet
CLK (CLK0,CLK1,CLK2,CLK3)
Multiplicand A0 m m
CE (CE0,CE1,CE2,CE3)
n m RST (RST0,RST1,RST2,RST3)
Multiplier B0 n
Input Data m Multiplier
Register A
n
Input Data n
x m+n
(default)
Register B Pipeline
m Register Add/Sub
n
Register
Multiplicand A1 m
Output
Output
m+n+1 m+n+1
m (default) (default)
Multiplier B1 n
Input Data m Multiplier m+n
Register A (default)
n
Input Data n
x
Register B Pipeline
m Register
n
Signed A Input Pipeline
Pipe
Register Register
Reg To Add/Sub
Signed B Input Pipeline
Pipe
Register Register
Reg To Add/Sub
Addn Input Pipeline
Pipe
Register Register
To Add/Sub
Reg
2-22
Architecture
LatticeXP2 Family Data Sheet
Multiplicand A0 m m
CLK (CLK0,CLK1,CLK2,CLK3)
n m CE (CE0,CE1,CE2,CE3)
Multiplier B0 n
Input Data m Multiplier RST(RST0,RST1,RST2,RST3)
m+n
Register A
n
Input Data n
x (default)
Register B Pipeline
m Register Add/Sub0
n
Multiplicand A1 m
m+n
(default)
m
Multiplier B1 n
Input Data n Multiplier
Register A m+n+1
n
Input Data n
x
Register B Pipeline SUM
Register
Register
Output
Multiplicand A2 Output
m m
m+n+2 m+n+2
n m
Multiplier B2 n
Input Data m Multiplier
m+n
Register A
n
Input Data n
x (default)
m+n+1
Register B Pipeline
m Register Add/Sub1
n
Multiplicand A3 m
m+n
(default)
m
Multiplier B3 n
Input Data m Multiplier
Register A
n
Input Data n
x
Register B Pipeline
m Register
Signed A n
Input Pipeline
Register Register To Add/Sub0, Add/Sub1
Signed B
Input Pipeline
Register Register To Add/Sub0, Add/Sub1
Addn0 Input Pipeline
Register Register To Add/Sub0
Addn1 Input Pipeline
Register Register
To Add/Sub1
2-23
Architecture
LatticeXP2 Family Data Sheet
register. Similarly, CE and RST are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0,
RST1, RST2, RST3) at each input register, pipeline register and output register.
Unsigned Operation
Signed Operation
2-24
Architecture
LatticeXP2 Family Data Sheet
IPexpress™
The user can access the sysDSP block via the Lattice IPexpress tool, which provides the option to configure each
DSP module (or group of modules), or by direct HDL instantiation. In addition, Lattice has partnered with The Math-
Works® to support instantiation in the Simulink® tool, a graphical simulation environment. Simulink works with Dia-
mond to dramatically shorten the DSP design cycle in Lattice FPGAs.
For further information on the sysDSP block, please see TN1140, LatticeXP2 sysDSP Usage Guide.
2-25
Architecture
LatticeXP2 Family Data Sheet
PIOA
TD
OPOS1
IOLT0
ONEG1
Tristate
Register
Block
OPOS0 PADA
OPOS21 “T”
ONEG0
ONEG21 IOLD0
Output
Register
Block sysIO
Buffer
QNEG01
QNEG11
QPOS01
QPOS11
INCK2
INDD
INFF
IPOS0 DI
IPOS1 Input
Control Register
CLK Muxes Block
CE CLK1
LSR CEO
GSRN LSR
ECLK1 GSR
ECLK2 CLK0
DDRCLKPOL1 CEI
DQSXFER1
DQS
DEL
PADB
“C”
PIOB
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25.
The PAD Labels “T” and “C” distinguish the two PIOs. Approximately 50% of the PIO pairs on the left and right
edges of the device can be configured as true LVDS outputs. All I/O pairs can operate as inputs.
2-26
Architecture
LatticeXP2 Family Data Sheet
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for operating in a variety of modes along with necessary clock and selection
logic.
Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired, the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and,
in selected blocks, the input to the DQS delay block. If an input delay is desired, designers can select either a fixed
delay or a dynamic delay DEL[3:0]. The delay, if selected, reduces input register hold time requirements when
using a global clock.
The input block allows three modes of operation. In the Single Data Rate (SDR) mode, the data is registered, by
one of the registers in the SDR Sync register block, with the system clock. In DDR mode two registers are used to
sample the data on the positive and negative edges of the DQS signal which creates two data streams, D0 and D2.
D0 and D2 are synchronized with the system clock before entering the core. Further information on this topic can
be found in the DDR Memory Support section of this data sheet.
By combining input blocks of the complementary PIOs and sharing registers from output blocks, a gearbox function
can be implemented, that takes a double data rate signal applied to PIOA and converts it as four data streams,
IPOS0A, IPOS1A, IPOS0B and IPOS1B. Figure 2-26 shows the diagram using this gearbox function. For more
information on this topic, please see TN1138, LatticeXP2 High Speed I/O Interface.
2-27
Architecture
LatticeXP2 Family Data Sheet
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic,
see the DDR Memory section of this data sheet.
DDRCLKPOL
CLKA
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
INCK2
DI DDRSRC To DQS Delay Block 2
(From sysIO INDD
Buffer) DDR Registers SDR & Sync
Fixed Delay 0 Clock Transfer Registers
0
Registers IPOS0B
D0
Dynamic Delay 1 0
D Q
1 D Q D Q QPOS0B
1 D-Type
DEL [3:0] D-Type /LATCH D-Type1
From IPOS1B
Routing D1 0
D Q D Q D Q D Q QPOS1B
D2 1
D-Type D-Type D-Type D-Type1
Delayed 0 /LATCH
DQS 1
To
Routing
CLK0 (of PIO B)
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-
type or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. At the next
clock cycle the registered OPOS0 is latched. A multiplexer running off the same clock cycle selects the correct reg-
ister to feed the output (D0).
By combining output blocks of the complementary PIOs and sharing some registers from input blocks, a gearbox
function can be implemented, to take four data streams ONEG0A, ONEG1A, ONEG1B and ONEG1B. Figure 2-27
2-28
Architecture
LatticeXP2 Family Data Sheet
shows the diagram using this gearbox function. For more information on this topic, see TN1138, LatticeXP2 High
Speed I/O Interface.
1
OPOS1 D Q D Q
D-Type Latch
To sysIO Buffer
From Routing
0
Q D Q DDR Output
ONEG0 D 0
1 D-Type Registers
D-Type* 1 /LATCH DO
0
1
OPOS0 0
0
Q 1
D Q D D Q D Q
0 1
D-Type* Latch D-Type Latch
1
CLKA
Clock Transfer
Registers
ECLK1 0 Programmable
ECLK2 0 Control
CLK1 1
1
(CLKA)
DQSXFER Output Logic
True PIO (A) in LVDS I/O Pair
Comp PIO (B) in LVDS I/O Pair
TD
Tristate Logic
ONEG1 D Q 0
D-Type
1
/LATCH
0 TO
1
0
Q D Q 1
OPOS1 D
D-Type Latch
To sysIO Buffer
From Routing
ONEG0 D Q D Q
D-Type DDR Output
D-Type* /LATCH Registers
DO
0
1
OPOS0 0
1
D Q D Q D Q D Q
D-Type* Latch D-Type Latch
CLKB
Clock Transfer
Registers
ECLK1 Programmable
ECLK2 0
CLK1 1
0 Control
(CLKB) 1
DQSXFER
Output Logic
* Shared with input register Note: Simplified version does not show CE and SET/RESET details
2-29
Architecture
LatticeXP2 Family Data Sheet
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as D-
type or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in
the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct
register for feeding to the output (D0).
PICs have registered elements that support DDR memory interfaces. Interfaces on the left and right edges are
designed for DDR memories that support 16 bits of data, whereas interfaces on the top and bottom are designed
for memories that support 18 bits of data. One of every 16 PIOs on the left and right and one of every 18 PIOs on
the top and bottom contain delay elements to facilitate the generation of DQS signals. The DQS signals feed the
DQS buses which span the set of 16 or 18 PIOs. Figure 2-28 and Figure 2-29 show the DQS pin assignments in
each set of PIOs.
The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-
tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR
data from the memory into input register blocks. For additional information on using DDR memory support please
see TN1138, LatticeXP2 High Speed I/O Interface.
2-30
Architecture
LatticeXP2 Family Data Sheet
PADA "T"
PIO A
LVDS Pair
PIO B PADB "C"
2-31
Architecture
LatticeXP2 Family Data Sheet
The DQS signal (selected PIOs only, as shown in Figure 2-30) feeds from the PAD through a DQS delay element to
a dedicated DQS routing resource. The DQS signal also feeds polarity control logic which controls the polarity of
the clock to the sync registers in the input register blocks. Figure 2-30 and Figure 2-31 show how the DQS transi-
tion signals are routed to the PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of 6-bit bus cal-
ibration signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates
DQS delays in its half of the device as shown in Figure 2-30. The DLL loop is compensated for temperature, volt-
age and process variations by the system clock and feedback loop.
Figure 2-30. Edge Clock, DLL Calibration and DQS Local Bus Distribution
ECLK1
ECLK2
I/O Bank 2
I/O Bank 7
DQS Input
Delayed
DDR_DLL DDR_DLL DQS
(Left) (Right)
Polarity Control
I/O Bank 3
DQSXFER
I/O Bank 6
DQS Delay
Control Bus
Spans 18 PIOs
Top & Bottom
Sides
2-32
Architecture
LatticeXP2 Family Data Sheet
ECLK2
ECLK1
CLK1
Polarity control
DCNTL[6:0]
DQSXFER
DQS
PIO
Output
DQSXFER Register Block DDR
sysIO Datain
Input Buffer PAD
Register Block
GSR To Sync DI
CEI Reg.
DQS CLK1
DQS To DDR
Reg.
DQS
sysIO Strobe
PIO Buffer PAD
Polarity Control
Logic
DI
DQS
DQSDEL
Calibration bus
from DLL
DCNTL[6:0]
ECLK1
DQSXFER
DQSXFERDEL*
DCNTL[6:0]
*DQSXFERDEL shifts ECLK1 by 90% and is not associated with a particular PIO.
Prior to the READ operation in DDR memories, DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
2-33
Architecture
LatticeXP2 Family Data Sheet
DQSXFER
LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories
that require DQS strobe be shifted 90o. This shifted DQS strobe is generated by the DQSDEL block. The
DQSXFER signal runs the span of the data bus.
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
In LatticeXP2 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-
ered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs inde-
pendent of VCCIO.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2, that set the threshold for the refer-
enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.
Each I/O is individually configurable based on the bank’s supply and reference voltages.
V
CCIO0
REF1(0)
REF2(0)
CCIO1
REF1(1)
REF2(1)
GND
GND
Bank 0 Bank 1
V V CCIO2
CCIO7
V REF1(7) V REF1(2)
Bank 7
Bank 2
V REF2(7) V REF2(2)
GND GND
RIGHT
LEFT
V CCIO6 V CCIO3
V REF1(6) V REF1(3)
Bank 6
Bank 3
V REF2(6) V REF2(3)
GND GND
Bank 5 Bank 4
VREF1(5)
REF2(5)
REF1(4)
REF2(4)
GND
GND
CCIO5
CCIO4
V
V
V
BOTTOM
2-34
Architecture
LatticeXP2 Family Data Sheet
1. Top and Bottom (Banks 0, 1, 4 and 5) sysIO Buffer Pairs (Single-Ended Outputs Only)
The sysIO buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of
single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also be con-
figured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have programmable PCI clamps.
2. Left and Right (Banks 2, 3, 6 and 7) sysIO Buffer Pairs (50% Differential and 100% Single-Ended Outputs)
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the ref-
erenced input buffers can also be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential I/O, and the comp pad is associated with the negative side of the differential I/O.
LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks.
The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buf-
fers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or
together with the VCC and VCCAUX supplies.
2-35
Architecture
LatticeXP2 Family Data Sheet
2-36
Architecture
LatticeXP2 Family Data Sheet
Hot Socketing
LatticeXP2 devices have been carefully designed to ensure predictable behavior during power-up and power-
down. Power supplies can be sequenced in any order. During power-up and power-down sequences, the I/Os
remain in tri-state until the power supply voltage is high enough to ensure reliable operation. In addition, leakage
into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system.
These capabilities make the LatticeXP2 ideal for many multiple power supply and hot-swap applications.
2-37
Architecture
LatticeXP2 Family Data Sheet
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can
operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more information, please see TN1141, LatticeXP2
sysCONFIG Usage Guide.
Figure 2-33. Overview of Flash and SRAM Configuration Cells Within LatticeXP2 Devices
Massively Parallel
Data Transfer
EBR Blocks Instant-ON
Flash for
Flash Memory
Single-Chip
SRAM Solution
Configuration
Bits
FlashBAK
for EBR
Storage
EBR Blocks
Device Lock
for Design
Decryption TAG Security
and Device Memory
Lock
At power-up, or on user command, data is transferred from the on-chip Flash memory to the SRAM configuration
cells that control the operation of the device. This is done with massively parallel buses enabling the parts to oper-
ate within microseconds of the power supplies reaching valid levels; this capability is referred to as Instant-On.
The on-chip Flash enables a single-chip solution eliminating the need for external boot memory. This Flash can be
programmed through either the JTAG or Slave SPI ports of the device. The SRAM configuration space can also be
infinitely reconfigured through the JTAG and Master SPI ports. The JTAG port is IEEE 1149.1 and IEEE 1532 com-
pliant.
As described in the EBR section of the data sheet, the FlashBAK capability of the parts enables the contents of the
EBR blocks to be written back into the Flash storage area without erasing or reprogramming other aspects of the
device configuration. Serial TAG memory is also available to allow the storage of small amounts of data such as
calibration coefficients and error codes.
For applications where security is important, the lack of an external bitstream provides a solution that is inherently
more secure than SRAM only FPGAs. This is further enhanced by device locking. The device can be in one of
three modes:
2-38
Architecture
LatticeXP2 Family Data Sheet
1. Unlocked
2. Key Locked – Presenting the key through the programming interface allows the device to be unlocked.
To further complement the security of the device a One Time Programmable (OTP) mode is available. Once the
device is set in this mode it is not possible to erase or re-program the Flash portion of the device.
Flash
Sequential
Address Flash Memory Array
Counter
1. Decryption Support
LatticeXP2 devices provide on-chip, non-volatile key storage to support decryption of a 128-bit AES encrypted
bitstream, securing designs and deterring design piracy.
2-39
Architecture
LatticeXP2 Family Data Sheet
original backup configuration and try again. This all can be done without power cycling the system. For more
information please see TN1220, LatticeXP2 Dual Boot Feature.
For more information on device configuration, please see TN1141, LatticeXP2 sysCONFIG Usage Guide.
For further information on SED support, please see TN1130, LatticeXP2 Soft Error Detection (SED) Usage Guide.
On-Chip Oscillator
Every LatticeXP2 device has an internal CMOS oscillator that is used to derive a Master Clock (CCLK) for configu-
ration. The oscillator and CCLK run continuously and are available to user logic after configuration is complete. The
available CCLK frequencies are listed in Table 2-14. When a different CCLK frequency is selected during the
design process, the following sequence takes place:
3. CCLK frequency changes to the selected frequency after clock configuration bits are received.
This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further
information on the use of this oscillator for configuration or user mode, please see TN1141, LatticeXP2 sysCON-
FIG Usage Guide.
Table 2-14. Selectable CCLKs and Oscillator Frequencies During Configuration and User Mode
CCLK/Oscillator (MHz)
2.51
3.12
4.3
5.4
6.9
8.1
9.2
10
13
15
20
26
32
40
54
803
1633
1. Software default oscillator frequency.
2. Software default CCLK frequency.
3. Frequency not valid for CCLK.
2-40
Architecture
LatticeXP2 Family Data Sheet
Density Shifting
The LatticeXP2 family is designed to ensure that different density devices in the same family and in the same pack-
age have the same pinout. Furthermore, the architecture ensures a high success rate when performing design
migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower uti-
lization design targeted for a high-density device to a lower density device. However, the exact details of the final
resource utilization will impact the likely success in each case.
2-41
LatticeXP2 Family Data Sheet
DC and Switching Characteristics
September 2014 Data Sheet DS1009
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
ESD Performance
Please refer to the LatticeXP2 Product Family Qualification Summary for complete qualification data, including
ESD performance.
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol Parameter Condition Min. Typ. Max. Units
0 VIN VCCIO — — 10 µA
IIL, IIH1 Input or I/O Low Leakage
VCCIO VIN VIH (MAX) — — 150 µA
IPU I/O Active Pull-up Current 0 VIN 0.7 VCCIO -30 — -150 µA
IPD I/O Active Pull-down Current VIL (MAX) VIN VCCIO 30 — 210 µA
IBHLS Bus Hold Low Sustaining Current VIN = VIL (MAX) 30 — — µA
IBHHS Bus Hold High Sustaining Current VIN = 0.7 VCCIO -30 — — µA
IBHLO Bus Hold Low Overdrive Current 0 VIN VCCIO — — 210 µA
IBHHO Bus Hold High Overdrive Current 0 VIN VCCIO — — -150 µA
VBHT Bus Hold Trip Points VIL (MAX) — VIH (MIN) V
VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
C1 I/O Capacitance2 — 8 — pf
VCC = 1.2V, VIO = 0 to VIH (MAX)
VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
C2 Dedicated Input Capacitance — 6 — pf
VCC = 1.2V, VIO = 0 to VIH (MAX)
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. TA 25oC, f = 1.0 MHz.
3-2
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-3
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-4
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-5
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-6
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-7
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
For further information on LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see details in
additional technical notes listed at the end of this data sheet.
LVDS25E
The top and bottom sides of LatticeXP2 devices support LVDS outputs via emulated complementary LVCMOS out-
puts in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possi-
ble solution for point-to-point signals.
3-8
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
LVCMOS33D
All I/O banks support emulated differential I/O using the LVCMOS33D I/O type. This option, along with the external
resistor network, provides the system designer the flexibility to place differential outputs on an I/O bank with 3.3V
VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to
4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D.
3-9
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
BLVDS
The LatticeXP2 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS
outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when
multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one
possible solution for bi-directional multi-point differential signals.
45-90 45-90
ohms RTL ohms RTR
2.5V 2.5V
16mA 16mA
RS = 90 ohms RS = RS =
RS = RS = 90 ohms
RS = 90 ohms
90 ohms ... 90 ohms
90 ohms
+ +
- -
- -
+
+
2.5V 2.5V 2.5V 2.5V
16mA 16mA 16mA 16mA
3-10
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
LVPECL
The LatticeXP2 devices support the differential LVPECL standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is
supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-
to-point signals.
+
VCCIO = 3.3V RP = 196 ohms RT = 100 ohms
(+/-5%) (+/-1%) (+/-1%) -
RS = 93.1 ohms
(+/-1%)
16mA
Transmission line,
Zo = 100 ohm differential
On-chip Off-chip Off-chip On-chip
3-11
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
RSDS
The LatticeXP2 devices support differential RSDS standard. This standard is emulated using complementary LVC-
MOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-
ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS
standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors.
VCCIO = 2.5V +
RP = 121 ohms RT = 100 ohms
(+/-5%) (+/-1%) (+/-1%) -
RS = 294 ohms
(+/-1%)
8mA
Transmission line,
Zo = 100 ohm differential
On-chip Off-chip Off-chip On-chip
3-12
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
MLVDS
The LatticeXP2 devices support the differential MLVDS standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is
supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for
MLVDS standard implementation. Resistor values in Figure 3-5 are industry standard values for 1% resistors.
16mA 16mA
RS = RS =
35ohms 35ohms
+ RS = RS = RS = RS = +
- 35ohms 35ohms 35ohms 35ohms
-
...
+
-
-
For further information on LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see details of
additional technical information at the end of this data sheet.
3-13
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
Register-to-Register Performance
Function -7 Timing Units
Basic Functions
16-bit Decoder 521 MHz
32-bit Decoder 537 MHz
64-bit Decoder 484 MHz
4:1 MUX 744 MHz
8:1 MUX 678 MHz
16:1 MUX 616 MHz
32:1 MUX 529 MHz
8-bit Adder 570 MHz
16-bit Adder 507 MHz
64-bit Adder 293 MHz
16-bit Counter 541 MHz
32-bit Counter 440 MHz
64-bit Counter 321 MHz
64-bit Accumulator 261 MHz
Embedded Memory Functions
512x36 Single Port RAM, EBR Output Registers 315 MHz
1024x18 True-Dual Port RAM (Write Through or Normal, EBR Output Registers) 315 MHz
1024x18 True-Dual Port RAM (Write Through or Normal, PLC Output Registers) 231 MHz
Distributed Memory Functions
16x4 Pseudo-Dual Port RAM (One PFU) 760 MHz
32x2 Pseudo-Dual Port RAM 455 MHz
64x1 Pseudo-Dual Port RAM 351 MHz
DSP Functions
18x18 Multiplier (All Registers) 342 MHz
9x9 Multiplier (All Registers) 342 MHz
36x36 Multiply (All Registers) 330 MHz
18x18 Multiply/Accumulate (Input and Output Registers) 218 MHz
18x18 Multiply-Add/Sub-Sum (All Registers) 292 MHz
3-14
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-15
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-16
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-17
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-18
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-19
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-20
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-21
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
CLKA
CSA
WEA
ADA A0 A1 A0 A1 A0
tSU tH
DIA D0 D1
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
CLKA
CSA
WEA
ADA A0 A1 A0 A1 A0
tSU tH
DIA D0 D1
tCOO_EBR tCOO_EBR
3-22
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
Figure 3-8. Write Through (SP Read/Write on Port A, Input Registers Only)
CLKA
CSA
WEA
ADA A0 A1 A0
tSU tH
DIA D0 D1 D2 D3 D4
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
3-23
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-24
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-25
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-26
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-27
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-28
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
VCC
PROGRAMN
DONE
INITN
CSSPIN
0 1 2 3 … 7 8 9 10 … 31 32 33 34 … 127 128
CCLK
3-29
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-30
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
3-31
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
TMS
TDI
tBTS tBTH
TCK
tBTCRH
tBTCRS
Data to be
captured Data Captured
from I/O
Data to be
driven out Valid Data Valid Data
to I/O
3-32
DC and Switching Characteristics
LatticeXP2 Family Data Sheet
VT
R1
DUT Test Poi nt
R2 CL*
3-33
LatticeXP2 Family Data Sheet
Pinout Information
February 2012 Data Sheet DS1009
Signal Descriptions
Signal Name I/O Description
General Purpose
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-
ify Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
P[Edge] [Row/Column Number*]_[A/B] I/O
[A/B] indicates the PIO within the PIC to which the pad is connected. Some of
these user-programmable pins are shared with special function pins. These
pins, when not used as special purpose pins, can be programmed as I/Os for
user logic. During configuration the user-programmable I/Os are tri-stated
with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled
after configuration.
GSRN I Global RESET signal (active low). Any I/O pin can be GSRN.
NC — No connect.
GND — Ground. Dedicated pins.
VCC — Power supply pins for core logic. Dedicated pins.
Auxiliary power supply pin. This dedicated pin powers all the differential and
VCCAUX —
referenced input buffers.
VCCPLL — PLL supply pins. csBGA, PQFP and TQFP packages only.
VCCIOx — Dedicated power supply pins for I/O bank x.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
VREF1_x, VREF2_x —
assigned as VREF inputs. When not used, they may be used as I/O pins.
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_VCCPLL — Power supply pin for PLL: LLC, LRC, URC, ULC, num = row from center.
General Purpose PLL (GPLL) input pads: LLC, LRC, URC, ULC, num = row
[LOC][num]_GPLL[T, C]_IN_A I
from center, T = true and C = complement, index A,B,C...at each side.
Optional feedback GPLL input pads: LLC, LRC, URC, ULC, num = row from
[LOC][num]_GPLL[T, C]_FB_A I
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
PCLK[T, C]_[n:0]_[3:0] I
bank and 0,1,2,3 within bank.
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
[LOC]DQS[num] I
function number. Any pad can be configured to be output.
Test and Programming (Dedicated Pins)
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
TMS I
enabled during configuration.
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
TCK I
enabled.
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
TDI I appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4-2
Pinout Information
LatticeXP2 Family Data Sheet
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated with DDR Strobe (DQS) and
DQS Strobe PIO Within PIC Data (DQ) Pins
For Left and Right Edges of the Device
A DQ
P[Edge] [n-4]
B DQ
A DQ
P[Edge] [n-3]
B DQ
A DQ
P[Edge] [n-2]
B DQ
A DQ
P[Edge] [n-1]
B DQ
A [Edge]DQSn
P[Edge] [n]
B DQ
A DQ
P[Edge] [n+1]
B DQ
A DQ
P[Edge] [n+2]
B DQ
A DQ
P[Edge] [n+3]
B DQ
For Top and Bottom Edges of the Device
A DQ
P[Edge] [n-4]
B DQ
A DQ
P[Edge] [n-3]
B DQ
A DQ
P[Edge] [n-2]
B DQ
A DQ
P[Edge] [n-1]
B DQ
A [Edge]DQSn
P[Edge] [n]
B DQ
A DQ
P[Edge] [n+1]
B DQ
A DQ
P[Edge] [n+2]
B DQ
A DQ
P[Edge] [n+3]
B DQ
A DQ
P[Edge] [n+4]
B DQ
Notes:
1. “n” is a row PIC number.
2. The DDR interface is designed for memories that support one DQS strobe up to 16 bits
of data for the left and right edges and up to 18 bits of data for the top and bottom
edges. In some packages, all the potential DDR data (DQ) pins may not be available.
PIC numbering definitions are provided in the “Signal Names” column of the Signal
Descriptions table.
4-3
Pinout Information
LatticeXP2 Family Data Sheet
4-4
Pinout Information
LatticeXP2 Family Data Sheet
Thermal Management
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal
characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.
Designers must complete a thermal analysis of their specific design to ensure that the device and package do not
exceed the junction temperature limits. Refer to the Lattice Thermal Management document to find the device/
package specific thermal values.
4-5
LatticeXP2 Family Data Sheet
Ordering Information
February 2012 Data Sheet DS1009
Ordering Information
The LatticeXP2 devices are marked with a single temperature grade, either Commercial or Industrial, as shown
below.
LFXP2-17E LFXP2-17E
7FT256C 6FT256I
Datecode Datecode
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Lead-Free Packaging
Commercial
Part Number Voltage Grade Package Pins Temp. LUTs (k)
LFXP2-5E-5MN132C 1.2V -5 Lead-Free csBGA 132 COM 5
LFXP2-5E-6MN132C 1.2V -6 Lead-Free csBGA 132 COM 5
LFXP2-5E-7MN132C 1.2V -7 Lead-Free csBGA 132 COM 5
LFXP2-5E-5TN144C 1.2V -5 Lead-Free TQFP 144 COM 5
LFXP2-5E-6TN144C 1.2V -6 Lead-Free TQFP 144 COM 5
LFXP2-5E-7TN144C 1.2V -7 Lead-Free TQFP 144 COM 5
LFXP2-5E-5QN208C 1.2V -5 Lead-Free PQFP 208 COM 5
LFXP2-5E-6QN208C 1.2V -6 Lead-Free PQFP 208 COM 5
LFXP2-5E-7QN208C 1.2V -7 Lead-Free PQFP 208 COM 5
LFXP2-5E-5FTN256C 1.2V -5 Lead-Free ftBGA 256 COM 5
LFXP2-5E-6FTN256C 1.2V -6 Lead-Free ftBGA 256 COM 5
LFXP2-5E-7FTN256C 1.2V -7 Lead-Free ftBGA 256 COM 5
5-2
Ordering Information
LatticeXP2 Family Data Sheet
Industrial
Part Number Voltage Grade Package Pins Temp. LUTs (k)
LFXP2-5E-5MN132I 1.2V -5 Lead-Free csBGA 132 IND 5
LFXP2-5E-6MN132I 1.2V -6 Lead-Free csBGA 132 IND 5
LFXP2-5E-5TN144I 1.2V -5 Lead-Free TQFP 144 IND 5
LFXP2-5E-6TN144I 1.2V -6 Lead-Free TQFP 144 IND 5
LFXP2-5E-5QN208I 1.2V -5 Lead-Free PQFP 208 IND 5
LFXP2-5E-6QN208I 1.2V -6 Lead-Free PQFP 208 IND 5
LFXP2-5E-5FTN256I 1.2V -5 Lead-Free ftBGA 256 IND 5
LFXP2-5E-6FTN256I 1.2V -6 Lead-Free ftBGA 256 IND 5
5-3
Ordering Information
LatticeXP2 Family Data Sheet
5-4
Ordering Information
LatticeXP2 Family Data Sheet
Conventional Packaging
Commercial
Part Number Voltage Grade Package Pins Temp. LUTs (k)
LFXP2-5E-5M132C 1.2V -5 csBGA 132 COM 5
LFXP2-5E-6M132C 1.2V -6 csBGA 132 COM 5
LFXP2-5E-7M132C 1.2V -7 csBGA 132 COM 5
LFXP2-5E-5FT256C 1.2V -5 ftBGA 256 COM 5
LFXP2-5E-6FT256C 1.2V -6 ftBGA 256 COM 5
LFXP2-5E-7FT256C 1.2V -7 ftBGA 256 COM 5
5-5
Ordering Information
LatticeXP2 Family Data Sheet
Industrial
Part Number Voltage Grade Package Pins Temp. LUTs (k)
LFXP2-5E-5M132I 1.2V -5 csBGA 132 IND 5
LFXP2-5E-6M132I 1.2V -6 csBGA 132 IND 5
LFXP2-5E-6FT256I 1.2V -6 ftBGA 256 IND 5
5-6
Ordering Information
LatticeXP2 Family Data Sheet
5-7
LatticeXP2 Family Data Sheet
Supplemental Information
February 2012 Data Sheet DS1009
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Revision History
Date Version Section Change Summary
May 2007 01.1 — Initial release.
September 2007 01.2 DC and Switching Added JTAG Port Timing Waveforms diagram.
Characteristics
Updated sysCLOCK PLL Timing table.
Pinout Information Added Thermal Management text section.
February 2008 01.3 Architecture Added LVCMOS33D to Supported Output Standards table.
Clarified: “This Flash can be programmed through either the JTAG or
Slave SPI ports of the device. The SRAM configuration space can also
be infinitely reconfigured through the JTAG and Master SPI ports.”
Added External Slave SPI Port to Serial TAG Memory section. Updated
Serial TAG Memory diagram.
DC and Switching Updated Flash Programming Specifications table.
Characteristics
Added “8W” specification to Hot Socketing Specifications table.
Updated Timing Tables
Clarifications for IIH in DC Electrical Characteristics table.
Added LVCMOS33D section
Updated DOA and DOA (Regs) to EBR Timing diagrams.
Removed Master Clock Frequency and Duty Cycle sections from the
LatticeXP2 sysCONFIG Port Timing Specifications table. These are
listed on the On-chip Oscillator and Configuration Master Clock Charac-
teristics table.
Changed CSSPIN to CSSPISN in description of tSCS, tSCSS, and tSCSH
parameters. Removed tSOE parameter.
Clarified On-chip Oscillator documentation
Added Switching Test Conditions
Pinout Information Added “True LVDS Pairs Bonding Out per Bank,” “DDR Banks Bonding
Out per I/O Bank,” and “PCI capable I/Os Bonding Out per Bank” to Pin
Information Summary in place of previous blank table “PCI and DDR
Capabilities of the Device-Package Combinations”
Removed pinout listing. This information is available on the LatticeXP2
product web pages
Ordering Information Added XP2-17 “8W” and all other family OPNs.
April 2008 01.4 DC and Switching Updated Absolute Maximum Ratings footnotes.
Characteristics Updated Recommended Operating Conditions Table footnotes.
Updated Supply Current (Standby) Table
Updated Initialization Supply Current Table
Updated Programming and Erase Flash Supply Current Table
Updated Register to Register Performance Table
Updated LatticeXP2 External Switching Characteristics Table
Updated LatticeXP2 Internal Switching Characteristics Table
Updated sysCLOCK PLL Timing Table
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com 7-1
Revision History
LatticeXP2 Family Data Sheet
7-2