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AND8346/D A519Hrt Hart Modem: Application Note
AND8346/D A519Hrt Hart Modem: Application Note
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APPLICATION NOTE
Introduction Physical Layer Specification2. The A5191HRT is intended
This application note describes a demonstration circuit to replace the 20C15 for all existing and future HART
that permits a user to implement a HART slave or master applications with no circuit topology changes. Only the
interface between a microprocessor and a process loop using values of four external resistors in the receive filter need to
the ON Semiconductor A5191HRT HART modem be adapted.
integrated circuit. The information in this Application Note
is correct to the best of our knowledge. Development of a Features
circuit suitable to the user’s particular system and • Same modem design as 20C15 from LSI Logic
application environment is the responsibility of the user. (formerly NCR and Symbios)
The HART (Highway Addressable Remote Transmitter) • Transmits a trapezoidal signal
communication protocol provides digital communication • Internal oscillator cell
for microprocessor−based process control instruments.
• Internal receive filter
HART uses the Bell−202 forward channel signaling
frequencies and bit rate (1200 bits/second) as making it a • Carrier detect
subset of the Bell−202 standard. HART−speaking devices • Available in 28−pin PLCC, 32−pin QFN and
can use virtually any Bell−202 standard modem. However, 32−pin LQFP Packages
the ON Semiconductor A5191HRT single−chip modem has • These Devices are Pb−Free and are RoHS Compliant
been designed to meet the low power requirements of This application note shows how to interface the
2−wire process instruments. A5191HRT modem to the HART network, as well as other
The ON Semiconductor A5191HRT modem is designed general advice on using the modem and on designing HART
to allow the user to easily implement a HART compliant devices. A block diagram showing a typical application of
Physical Layer design conforming to the HART FSK the A5191HRT in a HART Slave is shown in Figure 1.
PC20101210.4
RxD
RxA
TxD
+
UART
A5191HRT
RTS
4 − 20 mA
+
TxA Loop
CD
Current
mP
4 − 20 mA
DAC OUT
DAC −
Process Variable
24 V
4 − 20 mA
ADC Loop Current
Current
Sense Receive
Resistor
Amplifier
Receive
Amplifier
Tx Current
Modem
PC20101207.1
Tx Voltage
Figure 2. Current Loop with HART Signal Sources. Analog Signaling is Marked in Black. Digital Signaling is
Marked in Blue.
6 mA 1 mA
Data t BIT
833 ms
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HART Slave Device HART network can only have one Primary and one
HART Slaves transmit by modulating the process Secondary Master connected a time.
4−20 mA DC loop current with a 1 mA p−p AC current
signal as shown in Figure 3. Since the average value of the Multiplexing a HART Master
HART signal is zero, the DC value of the process loop To reduce the design complexity of a multiple loop HART
remains unchanged. Receive circuits in a HART Slave Master, the physical layer can be multiplexed to two or more
device amplify, filter, and demodulate the current signal. process loops. This is usually done with analog switches that
allow signals as high as 6 Vp−p to pass and exhibit an
HART Multi−dropped Slave Devices extremely low ‘on resistance’. The added impedance of the
Some current loops (called networks in HART switch directly affects the output impedance of the Master
documents) use only digital signaling. The field instrument device.
current is fixed at 4 mA or some other convenient value, and The multiplexer can switch only the HART signal or it can
only digital communication occurs. Up to 15 such field switch both the HART signal and the associated signal
instruments with unique addresses of 1 through 15 may be return. Switching the signal return insures the physical layer
connected in parallel. More address space is available for interface will be non−intrusive to the HART network if a
devices compliant with HART specification rev. 5 or higher failure were to occur. Typically, the analog switches connect
(up to 38 bits). A device that is not multi−dropped will to each process loop through a coupling capacitor (about
usually have its address set to 0. 2.2 mF).
The greatest disadvantage of multiplexing HART signals
HART Master Device
is the reduction in communication throughput to each Slave
HART Masters transmit by driving the loop with a low
device.
impedance voltage source as shown in Figure 2. Regardless
whether a master or field device is transmitting, a signal HART Cabling
voltage of about 500 mVp−p is developed across the Because of the relatively low HART frequencies, there is
conductors of the current loop (assuming a 500 W current little cable attenuation and delay distortion. This results in
sense resistor), and is seen by both devices. Receive circuits very few restrictions on constructing networks. The
in each device filter and demodulate the signal voltage. complete topology requirements and electrical requirements
for HART devices are given in the HART Physical Layer
HART Primary Master
Specification2.
In general, a HART Primary Master is the device that In most applications, HART communications can be
provides the communications between the control system performed up to a distance of 1500 meter using existing field
(DCS) and the remote process instruments with the intent to wiring for a 2−wire process instrument.
receive process information and perform maintenance
operations. A HART network that has a HART Master HART Data Link Layer
interface integrated into the DCS will usually be configured Normally, one HART device talks while others listen.
as a Primary Master. Talking means that the device applies the modulated carrier
to the network cable. A given device applies the carrier in
HART Secondary Master
one unbroken segment called a frame. Between frames the
In general, a second HART interface connected to a network is silent. Field instrument frames are usually
network that contains a Master will be a Secondary Master. responses to commands by a Master. Further information on
An example of a Secondary Master is a hand−held network protocol is found in the HART Data Link Layer
communicator that would be connected directly across a Specification1.
HART. Such a network may have a Primary Master. A
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AND8346/D
RESET
Demodulator RxA
RxD Logic
FSK_IN
Rx Comp Rx HP Filter
AREF
Carrier Detect
CD Counter
CDREF
Carrier Comp DEMODULATOR
RTS MODULATOR
Numeric
Sine
TxA
TxD Controlled
Shaper
FSK_OUT
Oscillator
Clock
Oscillator
BIAS
A5191HRT
HART MODEM
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FSK_IN
RxD
PC20101207.4 “0” “1” “0” “1” “0” “0” “1” “0” “1” “0”
t
tBIT 8 data bits BIT
Modulator TxA output. RTSB must be a logic low for the modulator
The modulator accepts digital data in NRZ form at its TxD to be active.
input and generates the FSK modulated signal at its
RTS
IDLE (mark)
TxD
tBIT
“0” “1” “0” “1” “0” “0” “1” “0” “1” “0”
TxA
0.5 V
PC20101208.3
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VTxA VTxA
“1” = Mark; fm =1.2 kHz “0” = Space; fs =2.2 kHz
0 1 2 0 1 2
PC20101209.4
Clock Oscillator
The A5191HRT requires a 460.8 kHz clock. This
frequency is generated in the internal clock oscillator block,
designed to use either a quartz crystal, ceramic resonator, or
Figure 8. Demodulator Carrier and Signal an external clock.
Comparator
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XIN PC20101208.5
XOUT
R1
Xtal
Clock
Oscillator
C1 C2
PC20101118.6
XOUT XIN
Figure 10. Oscillator Connection for Ceramic
Resonator or Quartz Crystal 460.8 kHz
When using a crystal or resonator the accuracy should be
at least 1%. The oscillator requires two external capacitors Figure 11. External Clock
and one external resistor, which values varies depending on
the used type. The specifications are listed in Table 4. Care NOTE: Output XOUT is driven by an external source
should be taken to keep the circuit board traces between the
A5191HRT and the external oscillator components as short
as possible. Table 2. COMMONLY AVAILABLE FREQUENCY
MULTIPLES
Ceramic Resonator Sources Frequency Multiple
Ceramic resonators are less expensive than quartz
1.8432 MHz x4
crystals, but are not as accurate. Unfortunately, ceramic
resonators at the needed frequency require special ordering 3.6864 MHz x8
in very large quantities. Ceramic resonators that oscillate at 7.3728 MHz x16
460.8 kHz are available from: 14.7456 MHz x32
http://www.ecsxtal.com/store/dc-4-ecs-resonators.aspx
www.raltron.com/products/resonators/default.asp 29.4912 MHz x64
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performance. These UARTs may not be satisfactory, Even if your own time base is perfect, you still must plan
depending on how close the samples are to each other, and on a possible 35% shift in a bit boundary, since you don’t
how samples are interpreted. A UART that takes a majority have control over time bases in other HART devices.
vote of 3 samples is acceptable.
tBIT
Transmitter tBIT
tBIT@ 99% nominal CLK
2
t
PC20101209.1
UART mid bit sample moment ±12% jitter
Receive High−pass Filter The interfering analog signal should be reduced to at least
To remove the interfering analog signal, a high−pass filter ten times smaller than the smallest HART signal, or under
is required in the HART signal receive path. The filter about 7.5 mV. Therefore, the high−pass filter should have an
requirements are found as follows. From section 7.1 of the attenuation of 63 dB at 25 Hz. The HART signal band covers
HART Physical Layer Specification2, the interfering signal approximately 950 Hz to 2500 Hz, which means that the
can be as high as 16 V p−p at 25 Hz. high−pass filter should begin rolling off somewhere below
NOTE: This is directly related to limits on analog 950 Hz and be 63 dB down at 25 Hz. This is illustrated in
signaling. The difference in specifications for analog Figure 13.
interference as output versus analog interference as input is
the result of the loads being different.
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The A5191HRT has an internal active filter to attenuate Table 3. RECEIVE FILTER VALUES FOR A5191HRT
the frequencies outside the HART band. In addition to the AND 20C15
internal active filter, an external passive filter is necessary to
Symbol A5191HRT 20C15 Tolerance Unit
complete the filtering requirements. The external capacitors
and resistor were too large in size to cost effectively integrate R1 215 402 1% kW
into the A5191HRT silicon. R2 215 453 1% kW
The external components required for the receive filter is R3 499 825 1% kW
shown in Figure 14. All the external capacitors are ±5% and
R4 787 787 1% kW
the resistors are ±1% components (except the 3 MW which
is ±5%). R5 422 732 1% kW
The external components on the receiver create a third R6 215 215 1% kW
order high pass filter with a pole at 624 Hz and a first order
R7 3 3 5% MW
low pass filter with a pole at 2500 Hz. Internally, the
A5191HRT has a high pass pole at 35 Hz and a low pass pole C1 470 470 5% pF
at 90 kHz, each of which can vary by as much as ±30 %. The C2 1 1 5% nF
input impedance to the entire filter is greater than 150 kW at C3 1 1 5% nF
frequencies less than 50 kHz.
C4 220 220 5% pF
A5191HRT is a pin to pin replacement for 20C15. Only
the values of four resistors in the receiver need to be The values shown for all external components in
changed. (See Table 5 values marked in italic).The different Figures 14 and Table 6 and all other circuits in this
resistor values change the shape of the lower pass band for application note are those used in the circuitry which was
the receive filter. It creates a more robust and noise immune used to pass the HART physical layer conformance test for
receiver and as a results provides more margin in passing the the A5191HRT.
out−of−band noise interference tests.
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C4 R6 R5
300 pF
R3 C3 C2 C1
RxA
15 MW
R4 R2 R1
Rx Comp 214 kW
40 pF
R7
44 kW
CDREF
AREF − 80 mV
DEMODULATOR
Voltage References The bias current controls the operating parameters of the
The A5191HRT requires two voltage references, AREF internal operational amplifiers and comparators and should
and CDREF. AREF sets the DC operating point of the be set to 2.5 mA.
internal operational amplifiers and is the reference for the The value of the bias current resistor is determined by the
Rx comparator. reference voltage AREF and the following formula:
If A5191HRT operates at VDD = 3.3 V the AREF
ON Semiconductor LM285D−1.2 1.235 V reference is R BIAS +
2.5 mA
recommended. In the case VDD = 5 V, AREF is typically
2.5 VDC. LM285D−2.5 is recommended. The recommended bias current resistor is 499 kW when
The level at which CD (Carrier Detect) becomes active is AREF is equal to 1.235 V or 100 kW when AREF is 2.5 V.
determined by the DC voltage difference (CDREF − AREF). Supply Current Budget and Transmitter Lift−Off
Selecting a voltage difference of 80 mV will set the carrier Voltage
detect to a nominal 100 mVp−p. Current consumption of internal circuits is important in
Analog Bias Resistor
any 2−wire field instrument. It becomes critically important
The A5191HRT requires a bias current resistor RBIAS to in a microprocessor− based field instrument featuring both
be connected between CBIAS and VSS. analog and digital signaling. The available current is derived
here and some techniques are examined for reducing current
consumption.
The nominal HART signal transmitted by a field
BIAS instrument is 0.5 mA peak. When this is superimposed upon
2.5 mA
AREF
a 4 mA analog signal, the terminal current must vary
between 3.5 mA and 4.5 mA. During the peak of the HART
OPA waveform, the instrument has 4.5 mA available, but during
the valley it has only 3.5 mA. Energy storage techniques can
be used to allow the internal circuits to draw a steady 4 mA
at all times. However, to be effective at HART frequencies,
the storage capacitor should be quite large. A large capacitor
PC20101118.4 CBIAS (or any form of energy storage device) complicates the
RBIAS
circuit design if intrinsic safety is required.
Therefore, the circuit is normally designed to run
everything on 3.5 mA. Another 200 to 400 mA is often
subtracted from this to allow some margin and to satisfy
Figure 15. Bias Circuit
other conditions. Assuming a guard value of 200 mA, the
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AND8346/D
internal circuits of the 2−wire field instrument have to live temperature. One way of reducing the A5191HRT current
on a diet of 3.3 mA during transmit. While receiving 3.8 mA consumption is to operate it at reduced voltage. Since the
is available. A5191HRT is a CMOS part, current consumption is roughly
proportional to supply voltage. Operation at VDD = 3.3 V is
Loop Current (mA) common.
In applying the A5191HRT be careful not to let inputs
float. The nRTS pin of the A5191HRT will often be driven
4
1 mA by an I/O pin of a microprocessor. During power−up or after
HART signal
reset an I/O pin may be tri−stated, allowing it to float. This
3.5
3.3
can cause the A5191HRT to draw excess current. In some
200 mA guardband
3.3 mA
cases the current may be large enough to prevent the field
Supply Current Budget instrument from starting up properly. There should be a
1 MW pull−up resistor on RTSB.
t
The transmitter lift−off voltage is the minimum terminal
PC20101212.1
voltage at which it is guaranteed to operate. When only
Figure 16. Supply Current Budget analog signaling is involved, lift−off voltage is an
unambiguous quantity. But when HART digital signaling is
A characteristic of the A5191HRT is that its current added, the available voltage can swing by as much as 0.75 V
consumption is approximately 350 to 450 mA. This leads to above and below the DC level. The minimum applied
the fortunate circumstance that the remaining (non−modem) voltage is the DC level minus 0.75 volt. You should either
circuits always have at least 2.85 mA available. Margins design the field instrument to accommodate the dips in
may be needed to cover current consumption over voltage, or else specify the lift−off voltage to include them.
Receive
Amplifier +
A5191HRT
RxA
TxA
Loop Loop
Amplifier Current
Vref
D/A
Converter
−
PC20101125.2
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AND8346/D
Receive
Amplifier +
RxA
A5191HRT
RTS Loop
Current
TxA
PC20101125.3
Loop
Amplifier
Vref
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PC20101209.1
Loop
illustrated in Figure 24. This means, for example, that a
2.2 mF
Current sinusoidal output at 25 Hz must have an amplitude into a
HART 500 W test load of less than 8 Vp−p. It also means that a
+
Modem 25 Hz square wave of 8 Vp−p would not be acceptable, since
Current its harmonics do not decrease at a −40 dB rate.
Sense
Resistor The required roll−off of the 4 – 20 mA analog signal can
HART be achieved by various means, including:
Field
Device • Analog filters.
• Digital filters (software).
• Inherent filtering in the instrument sensor.
In this case the Field Device will have a direct Often it is a combination of these. Any convenient method
short across it. may be used to insure that changes in instrument output
Figure 22. Single Capacitor Coupled DC Ground current fall within the specification. If the field instrument
Loop uses a D/A converter (DAC) to generate its analog output,
If the Master has a ground connection that is not at the the output steps of the DAC must be sufficiently small or else
ground potential as the analog ground from the process loop, the high−frequency content of the steps must be removed by
it is possible to create AC ground loops. A noisy 240 VAC filtering. When large changes in the DAC output occur due
ground signal could be coupled directly unto the process to calibration operations, caution must be used not to have
loop ground (single capacitive coupling) or coupled unto the these DAC changes active during a HART command or
process loop (dual capacitive coupling) ground through the response. Any large and fast current changes that fall outside
connection. The AC noise potentially could impede HART the HART specifications can cause unreliable
communications and corrupt the accuracy of the DCS communications with the HART Master or Slave.
measuring the analog current as shown in Figure 23. The analog signaling of typical field instruments is
usually band−limited to the range of 1 to 10 Hz, so that the
PC20101209.2 roll−off starts well below the 25 Hz point of Figure 24. This
Loop can lead to simpler low− pass filtering. For example, a
HART
Current
single−pole filter that begins rolling off at 1 Hz falls below
Modem
+ the curve of Figure 24.
The dashed line illustrated the use of a simple first order
Current
Sense filter with a pole at 1 Hz.
Resistor
Digital Analog
Ground Ground
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APPENDIX
HART Slave only. For detailed information on the Hart Physical Layer
The schematic in Figure 25 is a possible implementation specification and requirements see the HART Physical
of the HART Slave physical layer. The Loop Current Layer Specification1.
Regulator Circuit build around the op amp is for information
3.3 V
C4 R6 R5
R4 R2 R1
R7
VDDA
RxD
25 LM285
AREF R9
A5191HRT
CD 8
26 Z1
3.3 V
R11 C5
mC R13 9
R10
+
CDREF
RTS
22
C9 Opamp
TxD TxA R15 Q1
23 7
17 18 1 3 4 5 11 28 6, 20 12,19 10
R18
R20 R16
4 ć 20 mA
DAC OUT
−
**
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3.3 V
C4 R6 R5
R4 R2 R1
R7
VDDA
RxD
25 LM285
AREF R9
A5191HRT
CD 8
26
Z1
3.3 V
R11 C5
mC R13 9
R10
CDREF
RTS
22
Opamp
TxD TxA MC74VHC1GT66
23 7 C9
17 18 1 3 4 5 11 28 6, 20 12,19 10 Loop
PC20101210.1 XIN VSS VSSA CBIAS Current
XOUT IC2
X1
R15
R12 RTS
C7 C8
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REFERENCES
1. HART Communication Foundation Document Layer Specification, Revision 8.1; 9390 Research
Number HCF_SPEC−13, HART FSK Blvd., Suite I−350, Austin Texas, 78759.
Communication Protocol Specification, Revision 3. HART Communication Foundation Document
7.3; 9390 Research Blvd., Suite I−350, Austin Number HCF_TEST_2, HART FSK Physical
Texas, 78759. Layer Test Specification, Revision 2.1; 9390
2. HART Communication Foundation Document Research Blvd., Suite I−350, Austin Texas, 78759.
Number HCF_SPEC−54, HART FSK Physical
HART is a registered trademark of the HART Communication Foundation of Austin, Texas, USA. Any time that the term ‘HART’ is used in
this document or in any document referenced by this document, that term implies the registered trademark.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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