Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 1

10. Chapter: A/D and D/A converter principles

Time of study: 6 hours

Goals: the student should be able to

• define basic principles of D/A converters
• define basic principles of A/D converters
• describe aliasing
• use a multiply D/A converter for a control of circuit properties

Text

Basic considerations - ADC

The devices which perform the interfacing function between analog and digital worlds are
analog-to-digital (A/D or ADC) and digital-to-analog (D/A or DAC) converters, which
together are known as data converters.

The input to the system is a physical parameter such as temperature, pressure, flow,
acceleration, and position, which are analog quantities. The parameter is first converted into
an electrical signal by means of a transducer, once in electrical form, all further processing is
done by electronic circuits – xIN(t) – Fig.1.

An Analog to Digital converter is an electronic circuit which accepts an analog input signal
(usually a voltage V(t)) and produces a corresponding digital number at the output – see
Fig.1. The resultant digital word goes to a computer data bus or to the input of a digital
circuit.

The analog-to-digital converter requires a small amount of time to perform the quantizing and
coding operations. The time required to make the conversion depends on: the converter
resolution, the conversion technique, and the speed of the components employed in the
converter. The conversion speed required for a particular application depends on the time
variation of the signal to be converted and on the accuracy desired.

Aperture time - refers to the time uncertainty (or time window) in making a measurement and
results in an amplitude uncertainty (or error) in the measurement if the signal is changing
during this time – Fig. 2.
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 2

xIN(t) xLP(t)
Antialiasing
filtr – LP

Sampling xs(t) Quantizing xq(t)

Coding
(number)

A/D converter (ADC)

x(n) Digital signal y(n) y(t) Output filter –

processing DAC LP

Fig. 1: Possible block diagram of digital signal processing

Fig. 2: Aperture time TA and amplitude uncertainty

For the specific case of a sinusoidal input signal, the maximum rate of change occurs at the
zero crossing of the waveform, and the amplitude error is
∆V = T A ⋅
d
(V m sin ω t ) = T A ⋅ (V m ω cos ω t ) = ω = 0 = T AV m ω
dt

The resultant error as a fraction of the peak to peak full scale value is

∆V TAVmω T AVm 2π ⋅ f
ε= = = = π ⋅ f ⋅ TA
2Vm 2Vm 2Vm

From this result the aperture time required to digitize a 1 kHz signal to 10 bits resolution can
be found. The resolution required is one part in 210 or approximately 0.001, thus
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 3

ε 0,001
TA = = ≅ 302 ⋅ 10 −9
π ⋅ f 3,14 ⋅ 10 3

The result is a required aperture time of just 320ns! It is evident that it is hard to find a 10-bit
A/D converter to perform this conversion at any price! Fortunately, there is a simple and
inexpensive way around this dilemma by using a sample-hold circuit – Fig. 4. The aperture
time of the A/D converter is therefore greatly reduced by the much shorter aperture time of
the sample-hold circuit. In turn, the aperture time of the sample-hold is a function of its
bandwidth and switching time. All “signal sampling” we can see in Fig. 3.

SIGNAL

SAMLING
PULSES

SAMLED
SIGNAL

SAMLED AND
HELD SIGNAL

Fig. 3: Signal sampling

LP filter Sample and Hold Quantizing Coding

• The electrical signal is sampled (a sample-hold circuit acquires the signal
voltage and then holds its value while an analog-to-digital
2
2
n
B converter converts the
value into digital form) Encoder x(n)
x(t)
• 1
Quantizing is the process of transforming an analog signal into a set of discrete
output states - there are 2n -1 analog decision
1 points (or threshold levels) in the
transfer function ( n – number of the quantizer bits)
• Each threshold level corresponds to the number (code).
Fig. 4:
3: Once more ADC

• The electrical signal is sampled (a sample-hold circuit acquires the signal

voltage and then holds its value while an analog-to-digital converter converts the
value into digital form)
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 4

• Quantizing is the process of transforming an analog signal into a set of discrete

output states - there are 2n -1 analog decision points (or threshold levels) in the
transfer function ( n – number of quantizer bits)
• Each threshold level corresponds to the number (code).

LP filter - a low pass active filter which reduces high frequency signal components,
unwanted electrical interference noise, or electronic noise from the signal; so-called
antialiasing filter; its characteristics frequency must be ½ of sampling frequency fs.

Sampling – (sampling theorem, Nyquist theorem):

If a continuous bandwidth-limited signal contains no frequency components higher than fc,
then the original signal can be recovered without distortion if it is sampled at a rate of at least
2 fc samples per second, thus

fs ≥ 2·fc

Aliasing in the time domain – Fig. 5

False signal – alias frequency

fc

0 T 2T 3T 4T 5T 6T 7T
Fig. 5: Aliasing – in the time domain; f s < fc
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 5

Aliasing – spectrum – Fig. 6

fs -fc
(a)

-2fs - fs 0 fc fs 2fs
FREQUENCY FOLDING
(b)

- fs 0 fc fs 2fs

Fig. 6: a) right sampling – fs > 2fc; practically at least 5x higher

b) bad sampling – fs < 2fc

From the figure 6, if the sampling rate is increased such that fS - fC > fC, then the two spectra
are separated and the original signal can be recovered without distortion. This demonstrates
the result of the Sampling Theorem that fS >2fC. Frequency folding (aliasing) can be
eliminated in two ways: first by using a high enough sampling rate, and second by filtering
the signal before sampling to limit its bandwidth to fS/2 – antialiasing filter.

Quantizer, coding

At any part of the input range of the quantizer, there is a small range of analog values within
which the same output code word is produced. This small range is the voltage difference
between any two adjacent decision points and is known as the analog quantization size, or
quantum, q – it is found in general by dividing the full scale analog range (FSR) by the
number of output states. FSR is defined by the applied reference voltage VREF. Q is the
smallest analog difference which can be resolved, or distinguished, by the quantizer (the
quantization step; quantum - analog).

VREF V
q= ≈ REF
2 −1
n
2n

For a given analog input value to the quantizer, the output error will vary anywhere from 0 to
±q/2; the error is zero only at analog values corresponding to the code center points. This
error is also frequently called quantization uncertainty or quantization noise.

The quantizer output can be thought of as the analog input with quantization noise added to it.
The noise has a peak-to-peak value of q but, as with other types of noise, the average value is
zero. Its RMS value, however, is useful in analysis and can be computed from the triangular
waveshape to be q/(2.√3).

The most popular code is natural binary, or straight binary, which is used in its fractional
form to represent a number
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 6

N = a1 ⋅ 2 −1 + a 2 ⋅ 2 −2 + L a n ⋅ 2 − n

where each coefficient “ai” assumes a value of zero or one and N has a value between zero
and one.

The binary code word 110101 therefore represents the decimal fraction

(1x0.5) + (1x0.25) + (0x0.125) + (1x0.0625) + (0x0.03125) + (1x0.015625) = 0.828125

or 82.8125% of full scale for the converter. If full scale (VREF) is +10V, then the code word
represents +8.28125V.

The leftmost bit has the most weight, 0.5 of full scale, and is called the most significant bit,
or MSB; the rightmost bit has the least weight, 2-n of full scale, and is therefore called the
least significant bit, or LSB. The bits in a code word are numbered from left to right from 1
to n.

The LSB has the same analog equivalent value as q discussed previously, namely

VREF V
LSB(analogvalue) = q = ≈ REF
2 −1
n
2n

Table 1 and Table 2 are useful summaries of the resolution, number of states, and LSB
weights.

Table 1:
VREF n LSB (q)
1.00V 8 3.9062 mV
1.00V 12 244.14 µV
2.00V 8 7.8125 mV
2.00V 10 1.9531 mV
2.00V 12 488.28 µV
2.048V 10 2.0000 mV
2.048V 12 500.00 µV
4.00V 8 15.625 mV
4.00V 10 3.9062 mV
4.00V 12 976.56 µV
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 7

Table 2:

Resolution = 2n -1 [n = number of bites] error (FSR)

n 2n 1bit ppm [1x10-6]

8bits 256 3906
10bits 1 024 976
12bits 4 096 244
14bits 16 384 61
16bits 65 536 15
18bits 262 144 3.8
20bits 1 048 576 0.95
22bits 4 194 304 0.24
24bits 16 777 216 0.06

The dynamic range DR(dB) of a data converter in dB is found as follows:

DR(dB) = 20 log 2 n = 20n log 2 = 20n(0,3010) = 6,02 ⋅ n

A 12-bit converter, for example, has a dynamic range of 72.2dB.

Basic considerations - DAC

A Digital to Analog converter is an electronic circuit which accepts a digital number at its
input and produces a corresponding analog signal (usually a voltage) at the output.

There are different DACs realizations.

1) Summation of binary weighted currents – Fig. 7

MSB

VREF

LSB

Fig. 7: DAC – summation of weighted currents

Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 8

- It is a summing connection (inverting) of an operational amplifier.

- For given ratios is output voltage VDAC:

 1000 1000 1000 1000 

VDAC = −10 ⋅ 1 ⋅ + 1⋅ + 1⋅ +0⋅  = −8,75 V
 2000 4000 8000 16000 

- For example, in a 12-bit converter you would need a range of resistor values of 2000:1, with
corresponding precision of the small resistor values – an elegant solution is R – 2R ladder.
- The switch resistance must be smaller than 1/2n of the smallest resistor.
- This principle is used only in fast, low-precision DACs.

2) R – 2R ladder – Fig. 8

VIRTUAL
GROUND
C B A IVG

LSB

MSB

Fig. 8: DAC – R – 2R ladder

- Only two resistor values are needed (R and 2R).

- The resistor must be precisely matched, though the actual resistor values are not critical.
- Electronic switches connect resistors to either ground or the VREF line. The result is binary
weighted current IVG flowing down VIRTUAL GROUND (The Thevenin resistance of an
R/2R ladder is always R – regardless of the number of bits in the ladder. Since an R/2R ladder
is a linear circuit, we can apply the principle of superposition to calculate IVG.).
- Operational amplifier – current – to – voltage converter (inverting).
- The circuit shown generates an output of zero to – 10 V (the maximum input count is 15,
with output voltage -10x15/16).
- The operational amplifier tends to be the slowest part of the DAC – we can use a converter
with current output.
 Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 9

3) DAC with current output (current switched DAC) –Fig. 9

UREF IREF
RREF

VIRT. GROUND
4AE – for example
TREF T1 T2 T3 T4
OZ
16AE 8AE 4AE 2AE 1AE
IREF I1 I2 I3

R 2R 2R 2R 2R
R R R

IREF/2 IREF/4 IREF/8

Fig. 9: DAC – R – 2R ladder; current output

- The current sources are ON all the time, and their output current is switched to the output
terminal or to ground (very fast and cheap).
- The transistor areas are scaled (16AE : 8AE : 4AE : 2AE :1AE), thereby ensuring equal current
densities in all the transistors for optimum VBE matching (the emitter areas of the BJT devices
must be proportional to the emitter current).
- OZ + TREF – create current IREF = UREF/RREF (TREF is an inverting structure, thus feedback is
negative, virtual ground).
- I 1 = (( I REF ⋅ R + U BE ) − U BE ) / 2 R = I REF / 2
- I 2 = (( I REF ⋅ R + U BE ) − U BE − R ⋅ I REF / 2 ) / 2 R = I REF / 4
- I 3 = (( I REF ⋅ R + U BE ) − U BE − R ⋅ I REF / 2 − R ⋅ I REF / 4) / 2 R = I REF / 8
- etc.

There are a few ways to generate an output voltage from a current DAC. To generate large
swings, or to buffer into small load resistances, a current to voltage amplifier (with an op-
amp) can be used.

4) Multiplying DACs (MDAC) - can be made from DACs that have no internal reference by
using the reference input for the analog input signal. A DAC with good multiplying properties
(wide analog input range, high speed, etc.) will be called a “multiplying DAC”.

When used like this, MDAC behaves as a digitally controlled audio attenuator because the
output V0 is a fraction of the voltage representing the input digital code and the attenuator
setting can be controlled by digital logic. If followed by an op-amp integrator, the MDAC
provides digitally programmable integration which can be used in the design of digitally
programmable oscillators, filters.
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 10

5) Generally, the output voltage

(
VDAC = ±VREF ⋅ N = ±VREF ⋅ a1 ⋅ 2 −1 + a 2 ⋅ 2 −2 + L a n ⋅ 2 − n )
Sign + means a noninverting DAC.
Sign - means an inverting DAC.
a1 – MSB; an – LSB.

Basic principles of ADCs

There are different ADCs realizations.

1) Flash conversion (parallel encoder)

Of all conversion techniques, one of the fastest is direct conversion, better known as
"flash" conversion. ADCs based on this architecture are extremely fast and perform their
multibit conversion directly, but they require intensive analog design to manage the large

Fig. 10: ADCs based on the direct-conversion architecture (better known as

flash converters) include 2N-1 comparator banks and a reference
resistor-divider network
number of comparators and reference voltages required. As shown in Fig. 10, a converter with
N-bit resolution has 2N-1 comparators connected in parallel, with reference voltages set by a
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 11

resistor network and spaced VREF/2N (~1 least significant bit, or LSB) apart. Input voltage
offset of operational amplifiers must be less than the "LSB / 2".

A change of input voltage usually causes a change of state in more than one comparator
output. These output changes are combined in a decoder-logic unit that produces a parallel N-
bit output from the converter.

2) Dual slope ADCs

The dual-slope ADC architecture was truly a breakthrough in ADCs for high resolution
applications such as digital voltmeters (DVMs), etc. A simplified diagram is shown in Fig. 11,
and the integrator output waveforms are shown in Fig. 12.

Fig. 11: Dual slope ADC

Fig. 12: Dual slope ADC – output waveforms

Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 12

The input signal is applied to an integrator; at the same time a counter is started, counting
clock pulses. After a predetermined amount of time (T), a reference voltage having opposite
polarity is applied to the integrator. At that instant, the accumulated charge on the integrating
capacitor is proportional to the average value of the input over the interval T. By choosing
that time interval to be a multiple of the power-line period, the converter becomes insensitive
to 50 Hz “hum” (and its harmonics) – Fig. 13. The integral of the reference is an opposite-
going ramp having a slope of VREF/RC. At the same time, the counter is again counting from
zero. When the integrator output reaches zero, the count is stopped, and the analog circuitry is
reset. Since the charge gained is proportional to VIN · T, and the equal amount of charge lost is
proportional to VREF · tx, then the number of counts relative to the full scale count is
proportional to tx/T, or VIN/VREF. If the output of the counter is a binary number, it will
therefore be a binary representation of the input voltage.

Fig. 13: Frequency response of integrating ADC

Dual-slope integration has many advantages. Conversion accuracy is independent of both

the capacitance and the clock frequency, because they affect both the up-slope and the down-
slope by the same ratio.

3) SAR ADCs

Although there are many variations in the implementation of a SAR (successive

approximation register) ADC, the basic architecture is quite simple (see Fig. 14). The analog
input voltage (VIN) is held on a track/hold. To implement the binary search algorithm, the N-
bit register is first set to midscale (that is, 100... .00, where the MSB is set to '1'). This forces
the DAC output (VDAC) to be VREF/2, where VREF is the reference voltage provided to the
ADC. A comparison is then performed to determine if VIN is less than or greater than VDAC.
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 13

If VIN is greater than VDAC, the comparator output is a logic high or '1' and the MSB of the
N-bit register remains at '1'. Conversely, if VIN is less than VDAC, the comparator output is a
logic low and the MSB of the register is cleared to logic '0'. The SAR control logic then
moves to the next bit down, forces that bit high, and does another comparison. The sequence
continues all the way down to the LSB. Once this is done, the conversion is complete, and the
N-bit digital word is available in the register.

Fig. 14: Simplified N-bit SAR architecture

Fig. 15: SAR operation – 4 –bit example

Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 14

Fig. 15 shows an example of a 4-bit conversion. The y-axis (and the bold line in the figure)
represents the DAC output voltage. In the example, the first comparison shows that VIN <
VDAC. Thus, bit 3 is set to '0'. The DAC is then set to 01002 and the second comparison is
performed. As VIN > VDAC, bit 2 remains at '1'. The DAC is then set to 01102, and the third
comparison is performed. Bit 1 is set to '0', and the DAC is then set to 01012 for the final
comparison. Finally, bit 0 remains at '1' because VIN > VDAC.

Notice that four comparison periods are required for a 4-bit ADC. Generally speaking, an
N-bit SAR ADC will require N comparison periods and will not be ready for the next
conversion until the current one is complete. This explains why these types of ADCs are
power- and space-efficient, yet are rarely seen in speed-and resolution combinations beyond a
few Msps at 14 to 16 bits. The two critical components are the comparator and the DAC.

4) Voltage – to – frequency ADC

Voltage-to-frequency ADCs convert the analog input voltage to a pulse train with the
frequency proportional to the amplitude of the input (see Fig. 16). This can be done simply by
charging a capacitor with a current proportional to the input level and discharging it when the
ramp reaches a preset threshold. The pulses are counted over a fixed period to determine the
frequency, and the pulse counter output, in turn, represents the digital voltage.

Fig. 16: Principle of voltage – to – frequency DACs

Voltage-to-frequency converters inherently have a high noise rejection characteristic,

because the input signal is effectively integrated over the counting interval. Voltage-to-
frequency conversion is commonly used to convert slow and noisy signals. Voltage-to-
frequency ADCs are also widely used for remote sensing in noisy environments. The input
voltage is converted to a frequency at the remote location and the digital pulse train is
transmitted over a pair of wires to the counter. This eliminates noise that can be introduced in
the transmission lines of an analog signal over a relatively long distance.

5) Delta sigma converter – see the 9. Chapter

Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 15

6) Pipelined analog-to-digital converters

The pipelined analog-to-digital converter (ADC) has become the most popular ADC
architecture for sampling rates from a few megasamples per second (Msps) up to 100Msps.
Resolutions range from eight bits at the faster sample rates up to 16 bits at the lower rates.
These resolutions and sampling rates cover a wide range of applications, including CCD
imaging, ultrasonic medical imaging, digital receivers, base stations, digital video, etc.

Fig. 17: Pipelined ADC with four 3-bit stages (each stage resolves two bits)

Fig. 17 shows a block diagram of a 12-bit pipelined ADC. In this schematic, the analog
input, VIN, is first sampled and held steady by a sample-and-hold (S&H), while the flash ADC
in stage one quantizes it to three bits. The 3-bit output is then fed to a 3-bit DAC (accurate to
about 12 bits), and the analog output is subtracted from the input. This "residue" is then
gained up by a factor of four and fed to the next stage (Stage 2). This gained-up residue
continues through the pipeline, providing three bits per stage until it reaches the 4-bit flash
ADC, which resolves the last 4LSB bits. Because the bits from each stage are determined at
different points in time, all the bits corresponding to the same sample are time-aligned with
shift registers before being fed to the digital-error-correction logic. Note when a stage finishes
processing a sample, determining the bits, and passing the residue to the next stage, it can then
start processing the next sample received from the sample-and-hold embedded within each
stage. This pipelining action is the reason for the high throughput.

Although each stage generates three raw bits in the Figure 1 example, because the
interstage gain is only 4, each stage (Stages 1 to 4) effectively resolves only two bits. The
extra bit is simply to reduce the size of the residue by one half, allowing extra range in the
next 3-bit ADC for digital error correction, as mentioned above. This process is called "1-bit
overlap" between adjacent stages. The effective number of bits of the entire ADC is therefore
2 + 2 + 2 + 2 + 4 = 12 bits.
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 16

7) Comparison of ADCs

As ADCs can consume a large percentage of power in a device, it is of vital interest to

minimize ADC power consumption. Optimal power consumption for different sampling rates,
and resolutions we can see in Fig. 18 (qualitative description only).

Fig. 18: A/D Converter technologies, resolution and bandwidth

When selecting an ADC, some of the factors to consider are

- Precision
- Speed
- Accuracy (external trimming required? monotonicity?)
- Required supply voltages and power dissipation
- Reference (internal or external? if internal, is it accessible externally?)
- Input impedance and analog voltage range (unipolar, bipolar, or both?)
- etc.
Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 17

Basic texts

[1]
[2]

Other text
[3] Horowitz, P-Hill, W.: The art of electronics. Cambridge University press 2001,
str.612 až 636

Questions

' Answers you find in this text

1. Explain basic operating principles of DACs.
2. Explain basic operating principles of ADCs.
3. Can we use DAC as a variable controlled attenuator?
4. Explain the operating principle of an ADC, usually referred as a SAR.
5. Explain what aliasing is, how it happens, and what may be done to prevent it from
happening to an ADC circuit.

Problems

1. Determine the required sampling frequency fs if the maximum signal frequency is 16 kHz.

2. Suppose an analog-digital converter inputs a voltage ranging from 0 to 5 volts DC and

converts the magnitude of that voltage into an 8-bit binary number. How many discrete
"steps" are there in the output as the converter circuit resolves the input voltage from one end
of its range (0 volts) to the other (5 volts)? How much voltage does each of these steps
represent?

3. Determine the output voltage of a multiplying DAC (inverting), who’s VREF = 10 V, a

binary word is 10001001.

4. Determine the maximum input voltage offset of comparators in parallel converter according
to problem 3.

Problems key

Ad1) Use the equation fs ≥ 2·fc.

Punčochář, Mohylová: TELO, Chapter 10: A/D and D/A converter principles 18

Ad2) This ADC (Analog-to-Digital Converter) circuit has 256 steps in its output range, each
step representing 19.61 mV.

( )
Ad3) Use the equation VDAC = ±VREF ⋅ N = ±VREF ⋅ a1 ⋅ 2 −1 + a 2 ⋅ 2 −2 + L a n ⋅ 2 − n ; n = 8.

VREF V
Ad4) We know n = 8, LSB(analog value) = q = ≈ REF ; thus comparators input
2 −1
n
2n
voltage offset must be less than q/2.

Recommendation

If you can solve and answer more than circa 60 % of the problems and questions, you
may continue your study.