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Low Power UPF and VP
Low Power UPF and VP
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Institute of Digital and Computer Systems / TKT-9636 Advanced Power Modeling Support in today‟s EDA Flows 23.1.2009
2
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Institute of Digital and Computer Systems / TKT-9636 Advanced Power Modeling Support in today‟s EDA Flows 23.1.2009
What is a Virtual Platform?
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Board-level
Fast Instruction- M em
Accurate Simulator
System-on-Chip
Functional
Peripherals
Simulation Infrastructure
Transaction-level Graphical
Interfaces Peripheral Models
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Mem
CPU(s) TLM Bus P(f,V,mode) Ctrl
Mem
Instruction Device Energy
Add Clock
P(f,V,mode)
Set Simulator
P(f,V,mode)
Distribution I$ D$ Slave
Power
Periph Power time
Mgmt Mgmt
TLM Bus
Clock Module IC
Distribution Slave
Periph Power Events
P(f,V,mode)
Voltage
Clocks
Flash
Add Power States
Memory
SRAM
Management
Add Power Complete Device Model
Estimation Schemes
Equations
Optimize System
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Clock
Controller
Master1 Master2
Periph Periph
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Voltage Domains
VDD USB
I2C
I2C
Voltage
Distribution
PM
Sequencer
Power parameters
Components are characterized by a set of representative power parameters
(„kernels‟)
Used in power equations to calculate power
Flexible to support specific component characteristics
Interactively changeable by user
Source
Power consumption numbers are delivered by semiconductor company
Based on (1) budget planning, (2) estimations, (3) measurements
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ARM1136 (OMAP2420)
ARM MPU Power
Estimation Component
MPU Voltage (Volt) Power
update request
PRCM
Power update
response
MPU Clock
(frequency (MHz))
I/O I/O
Energy(t)
Penalty when CPU(s) TLM Bus
Mem Mem
Ctrl
Cache miss Instr uction time
I$ D$ Slave
Penalty for each bus Power Events
Periph
APLL
TLM Bus
transaction Voltage
Clocks
Slave DPLL (D sys memory (length))
Periph States
System-on-Chip
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Power Dashboard
Clock Dashboard
Voltage Monitor
SoC Voltage Dashboard
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Institute of Digital and Computer Systems / TKT-9636 Advanced Power Modeling Support in today‟s EDA Flows 23.1.2009
UPF Targets Design Styles using
Advanced Power Management Techniques
Mainstream Techniques
Clock Gating Multi-Threshold
Leakage Current
Din
Register
Low VTH
Enable Bank Dout Nominal VTH
Latch
High VTH
Clock Delay
• Advanced Techniques
OFF OFF
PWR
0.7 – 0.9V
CTRL
0.9V 0.9V 0.9V
OFF
0.7V 0.9V 0.9V 0.9V 0.7V 0.9V 0.7V
0.9V
Power Domain 1
Power Domain 3
Power Domain 2
PS_3
PS_1
PS_2
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PrimeTime
Gate PrimeTime PX
Ref
UPF’
Formality
Impl
IC Compiler
PrimeTime
Gate PrimeTime PX
Ref
UPF”
VCS+MVSIM Formality
MVRC PG Netlist Impl
PrimeRail
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MVRC:
Design Compiler RTL Checks
Power Compiler
Gate
UPF’
MVRC:
Netlist Checks
IC Compiler
PG
Gate
Netlist
UPF’’
MVRC:
Final Signoff
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RTC
(Battery)
Power Domain1 Domain 2 Domain 3 Domain 4
Management
Mode1 1.2V 1.2V 1.2V 1.2V
ISO_Control
Mode2 Off 1.2V 1.2V 1.2V
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ON/OFF
Block
• Structurally correct, but may lead to
functional problems
Can be caught with test vectors, but
ISO_Control
MVRC can catch without vectors
CLK
Gen
Isolation gate
on clock path
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UPF RTL/Netlist
Testbench MVCMP
APDB
MVDBGEN
VCS + MVSIM
Multi-Voltage
VCD/FSDB
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Restore signal
GPRS wake up Register values
asserted
restored
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Standard scan
Includes AutoFix, observe point insertion, user-defined test point
insertion
Multiplexed flip-flop scan style only
Adaptive scan
Default and High X-tolerance
Multiplexed flip-flop scan style only
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route_opt
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P1
Scoped and mapped power net
G1
UPF objects
• Tie-off nets are also hooked up to
correct PG net
• Checks for any PG connection
VSS violations
derive_pg_connection •connect_pg_nets is
check_mv_design –power_nets
recommended for physical only
cells
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add_header_footer_cell_array
-lib_cell "mult_sw“
-voltage_area MULT
-design Multiplier
-x_increment 63
-y_increment 8
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VSS
external-VDD external-VDD
GATE GATE GATE
switch switch
VDDG
VDDG
VSS
VSS
VDDGS
switch switch
GATE GATE GATE
external-VDD external-VDD
VSS
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Designer
chooses best
option
Implementation
automatically
optimized
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MemX,
MemY
Multiplier
S1: Top, Mult @ HV
Low Volt
OFF
High Volt
OFF
GENPP GPRS, RAMs @ LV
High Volt
MemX
MemY
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place_opt
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create_power_domain create_power_switch
create_supply_port set_retention
create_supply_net set_retention_control
connect_supply_net map_retention
set_domain_supply_net set_isolation
connect_supply_net set_isolation_control
add_port_state set_level_shifter
create_pst
add_pst_state
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Institute of Digital and Computer Systems / TKT-9636 Advanced Power Modeling Support in today‟s EDA Flows 23.1.2009
create_power_domain
create_power_domain <domain_name>
[-elements <list of hierarchical
instances>]
[-scope <instance_name>]
Creates a power domain at the current scope, level of hierarchy
-elements to define specific instances to include in power domain
-scope to create the power domain in another scope, level of
hierarchy
• To define a power domain for a child design at the child‟s level of hierarchy
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ChipTop
VDDG VDDB • UPF can specify a complete
1.0 V power supply network
• Supply ports
VDDG • Supply nets
Sleep Sleepout • Power switches
VDDB
gprs_sw • Implicit connections based
VDDGS
on PD
GPRS • Explicit supply
VDDGS connections
1.2 V
VDDB
• UPF commands
•create_supply_ports
R •create_supply_nets
VSS •create_power_switch
•connect_supply_net
•set_domain_supply_net
VSS
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create_supply_port <port_name>
[-domain <domain name>]
port_name needs to be unique at the level of hierarchy it is defined
-domain is used to specify supply ports inside another power
domain
For designs with multiple power domains at the same scope/ level of
hierarchy, supply ports are available to all power domains defined at
that scope
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create_supply_net <supply_net_name>
-domain <domain_name>
[-reuse]
supply_net_name must be a unique identifier
-domain specifies the power domain in which the supply net is to be
created
-reuse specifies that the listed supply net name is to be re-used as
a supply net inside the power domain specified by the -domain
option
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To make supply net VDD available to PD2, the -reuse option
needs to be used when defining the supply net VDD in PD2
>create_power_domain PD1 -elements {A B}
>create_power_domain PD2 -elements {C D}
>create_supply_net VDD -domain PD1
>create_supply_net VDD -domain PD2 -reuse
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set_domain_supply_net <domain_name> \
-primary_supply_net <power_supply_net> \
-primary_ground_net <ground_supply_net>
Tells tools what are the default power and ground connections for cells in a
power domain
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create_power_switch <switch_name>
-domain <domain_name>
-output_supply_port <port_name
supply_net_name>
{-input_supply_port <port_name
supply_net_name>}
{-control_port <port_name net_name>}
[-ack_port <port_name net_name>]
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set_isolation <isolation_strategy>
-domain power_domain
-isolation_power_net <isolation_power_net>
-isolation_ground_net <isolation_ground_net>
[-clamp_value 0 | 1 | latch]
[-applies_to inputs | outputs | both]
[-elements objects]
[-no_isolation]
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set_isolation_control <isolation_strategy>
-domain power_domain
-isolation_signal <isolation_signal>
[-isolation_sense 0 | 1]
[-location self | parent]
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1.2V/OFF ELS
set_isolation_control
gprs_iso_out –domain GPRS
-isolation_signal
PwrCtrl/isolate_ctrl
-isolation_sense low
-location parent
sleep restore retn isolate_ctrl
PwrCtrl
VSS
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set_retention_control <retention_strategy>
-domain power_domain
-save_signal {{net_name <high | low >}}
-restore_signal {{net_name <high | low >}}
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map_retention_cell <retention_strategy>
-domain power_domain
[-lib_cells lib_cells]
[-lib_cell_type lib_cell_type]
[-elements objects]
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map_retention_cell
sleep restore retn isolate_ctrl gprs_ret -domain GPRS
PwrCtrl -lib_cell_type RSDFCD1
VSS
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set_level_shifter <level_shifter_name>
-domain <domain_name>
[-elements list]
[-applies_to <inputs | outputs | both>]
[-threshold value]
[-rule <low_to_high | high_to_low | both>]
[-location <self | parent | fanout | automatic>]
[-no_shift]
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