Low Power UPF and VP

1
Low Power System-on-Chip Design
Advanced Power Modeling Support

in today‟s EDA Flows
Petri Solanti, CAE

Synopsys Finland Oy
This material is property of Synopsys Inc. Using this presentation or individual slides without permission from Synopsys is prohibited
Institute of Digital and Computer Systems / TKT-9636 Advanced Power Modeling Support in today‟s EDA Flows 23.1.2009
2
Part 1 : Power Analysis with Virtual Platforms
What is a Virtual Platform

Power Modeling & Estimation goals
Power Modeling Support
Clock Modeling
Voltage Modeling
Power Estimation
Dashboards
What is a Virtual Platform?
• Fully functional software model of

complete systems
• SoC, board, I/O, user interface
• Executes unmodified production
code
• Drivers, OS, and applications
• Runs close to real time
• Boots OS in seconds
• Highest debugging efficiency
through full system visibility and
control
• Supports multi-core SoCs debug
Institute of Digital and Computer Systems / TKT-9636

Virtual Platform – Closer Look
Virtual I/O User Interface High-Level, High-speed
Emulation C/C++/SystemC
Models
Virtual I/ O & User Interface
System IO
Board-level
Fast Instruction- M em
Accurate Simulator
System-on-Chip
CPU Func TLM Bus Func TLM Bus
Functional
Peripherals
Simulation Infrastructure
Transaction-level Graphical
Interfaces Peripheral Models

Power Modeling & Estimation Goals
Increase visibility into global system state & individual power/clock

domains
Architectural power trade-offs
 Explore performance vs. power trade-offs
 Test drive new power scheme with “system software” load
Power-related software development
1. Perform software power optimizations by providing (relative) power consumption
estimations
2. Enable development of power management software
3. Provide insight into system power consumption, when running actual system
software

Power Modeling Support
 The following power support is added to a TLM platform:

1. Power management modeling
1. Clock modeling – gating, scaling freq(t), …
2. Voltage distribution - power domains, scaling V(t) , …
3. Power state control – power state sequencing (power down,
retention, …)
2. Power estimation equations – evaluated at run-time
3. Dashboards – clocks, state, voltage, power
 Applies both to PV & PVT level modeling
 PV
• Instantaneous power consumption, at each point in time
 PVT
• Supports trade-off of performance vs. power
• Graphs: Power(t) & Energy(t)
• Improved accuracy for accounting for (memory) transactions power
contribution

System-level Power Exploration
SW-Driven Power Analysis & Optimization
Start with functional-

Run System Software
accurate TLM System
Model
Analyze Power Results
Camera USB
DesignWare® Specify
Virtual Platform
Voltage Domain Power Consumptions
System-on-Chip
Domains
System System
I/O I/O
P(f,V,mode)
time
Mem
CPU(s) TLM Bus P(f,V,mode) Ctrl
Mem
Instruction Device Energy
Add Clock
P(f,V,mode)
Set Simulator
P(f,V,mode)
Distribution I$ D$ Slave
Power
Periph Power time
Mgmt Mgmt
TLM Bus
Clock Module IC
Distribution Slave
Periph Power Events
P(f,V,mode)
Voltage
Clocks
Flash
Add Power States
Memory
SRAM
Management
Add Power Complete Device Model
Estimation Schemes
Equations
Optimize System

Clock Modeling
Clock
Controller
Master1 Master2
Signal is used to transmit value of clock

CPU(s) frequency from controller to peripheral;
TLM Bus
Instr uction
Set Simulator does not model actual clock waveform
Periph Periph
Functional clock modeling

 Models functional operation of the clock controller, including:
• Clock distribution
• Control over peripheral clock gating
• Registers, to model software control over clock frequencies

Voltage & Power State Control Modeling
Functional models of:

 On-chip Power Manager (SoC)
• Control of (internal) voltage  Power management chip (PMIC)
distribution & domains • Voltage scaling of SoC
• State control & sequencing • SoC I2C control interface,
power sequencing, LDO regulators
control, DC/DC convertors, …
VDD (SoC voltage scaling)
Voltage Domains
VDD USB
PRCM LDOs VDD RF
I2C
I2C
Voltage
Distribution
PM
Sequencer
System-on-Chip (SoC) Power Management Chip


Power Estimation - Concepts
Parametrizable power model, consisting of:

1. Component power characteristics
2. Component power calc. equations
3. Power accumulator
Power
Manager
Master1 Master2
PV / PVT
Model
CPU(s)
TLM Bus
Instr uction
Set Simulator
Voltage Power Estimation
Frequency
Power State Equation
Power
Accumulator
Power request /
response APIs
Power event
Logging (file)
Power
Power Dashboard
Accumulator

Power Estimation – Component Characterization
Power parameters
 Components are characterized by a set of representative power parameters
(„kernels‟)
 Used in power equations to calculate power
 Flexible to support specific component characteristics
 Interactively changeable by user
Source
 Power consumption numbers are delivered by semiconductor company
 Based on (1) budget planning, (2) estimations, (3) measurements

Power Estimation – Component Characterization
Examples: OMAP2420 (PV model)

Example – PRCM (OMAP2420)
1.CPU
• Power active (mA / MHz)
• Power dormant (mA)
• Power inactive (mA)
• Power shutdown (mA)
2.Peripherals:
• Power clock off (mA)
• Power idle (mA / MHz)
• Power typical (mA / MHz)
• Power maximum (mA / MHz)
3.On-chip Memories (RAM / ROM)
• Power clock off (mA)
• Power idle (mA / MHz)
• Power read transaction (mA / MHz)
• Power write transaction (mA / MHz)

Power Estimation
 System power estimations expressions, contain:

1. Component power characteristics
2. Power state of APLLs & DPLLs { off, on }
3. Power state of domain { off, ret, on }
4. Voltage applied (to domain)
 At run-time power estimation expressions are

evaluated on the fly, as triggered by user requests
 Complements functional component model
 Leverage power state & frequency modeling of func. component
model
 Expressed in C code (Magic-C or C++)

Power Estimation (cont‟d)
 Expressions can be linear, or more complex,

depending on:
• Component type
• Data / charatistics which can be measured / estimated
 Fixed modeling APIs for voltage, frequency & power

state updates, and reporting to accumulator

Power Estimation - Example
ARM1136 (OMAP2420)
ARM MPU Power
Estimation Component
MPU Voltage (Volt) Power
update request
PRCM
Power update
response
MPU Clock
(frequency (MHz))
MPU Power State Power Parameters

(on, off, …)
Magic-C Power Model


Power Estimation – PVT Platform Example
– 1st order power model
Penalty for each bus
transaction
Fixed power (D transaction (length))
f(V,f,st)
Penalty for each busPower(t)
Camera USB transaction
Fixed power (D transaction (length))
f(V,f,st) System System
time
I/O I/O
Energy(t)
Penalty when CPU(s) TLM Bus
Mem Mem
Ctrl
Cache miss Instr uction time
(Dcache iss) Set Simulator
I$ D$ Slave
Penalty for each bus Power Events
Periph
APLL
TLM Bus
transaction Voltage
Clocks
Slave DPLL (D sys memory (length))
Periph States
System-on-Chip
Fixed power Platform Analyzer *

Flash
Memory
PMIC f(freq,St)
System/ Device
* Under development

Dashboards Overview
On-chip Power Reset Controller
Power Dashboard
Clock Dashboard
Voltage Monitor
SoC Voltage Dashboard

Power Analysis View Example

19
Part 2 : UPF Language in Design Flows
UPF Target Design Styles

UPF Conceptual model
Synopsys UPF Flows
Multi-Voltage Rule Checks
Multi-Voltage Simulation Flow
Logic Synthesis
Design for Testing Flow
Multi-Voltage Place & Route Flow
UPF Targets Design Styles using
Advanced Power Management Techniques
Mainstream Techniques
Clock Gating Multi-Threshold
Leakage Current
Din
Register
Low VTH
Enable Bank Dout Nominal VTH
Latch
High VTH
Clock Delay
• Advanced Techniques
OFF OFF
PWR
0.7 – 0.9V
CTRL
0.9V 0.9V 0.9V
OFF
0.7V 0.9V 0.9V 0.9V 0.7V 0.9V 0.7V
0.9V
Multi-Voltage (MV) MTCMOS power MV with power Dynamic Voltage

gating (shut down) gating Frequency Scaling
(DVFS)

UPF Conceptual Model
Overlay power information on top of the design
Power Domain 1
Power Domain 3
Power Domain 2
PS_3
PS_1
PS_2

Synopsys UPF Flow
Functional Implementation Equivalence Timing/Power
Verification Checking Signoff
RTL
Ref
UPF
Formality
Impl
VCS+MVSIM Design Compiler

MVRC Power Compiler
PrimeTime
Gate PrimeTime PX
Ref
UPF’
Formality
Impl
IC Compiler
PrimeTime
Gate PrimeTime PX
Ref
UPF”
VCS+MVSIM Formality
MVRC PG Netlist Impl
PrimeRail

Multi-Voltage Rule Checking using MVRC
Implementation Static
Functional
Verification
RTL
UPF
MVRC:
Design Compiler RTL Checks
Power Compiler
Gate
UPF’
MVRC:
Netlist Checks
IC Compiler
PG
Gate
Netlist
UPF’’
MVRC:
Final Signoff

MVRC
Structural Checks
PMIC/PMU
ISO-Enable Checks protection
logic against
Domain 1
• Missing cell
ON(1.2V)/OFF Domain 3 • Redundant cell
Isolation • Incorrect cell type
• Incorrect power domain
Domain 2 ON (1.2V)
• Incorrect isolation polarity
• Incorrect iso-enable
0.9-1.2
Level Shifters
Domain1 Domain2 Domain3

Mode1 1.2V 1.2V 1.2V Structural checks performed using
Mode2 Oｆｆ 1.2V 1.2V supplied MV state table
Mode3 Off 0.9V 1.2V

MVRC
Architectural Checks
• Architecture checks verify that

isolation / sleep control signals are
generated from the proper domain
Processor
Control Memory
• ISO_Control is driven during Mode2,
but in Mode3 it becomes HighZ
IO Control
RTC
(Battery)
Power Domain1 Domain 2 Domain 3 Domain 4
Management
Mode1 1.2V 1.2V 1.2V 1.2V
ISO_Control
Mode2 Oｆｆ 1.2V 1.2V 1.2V
Mode3 Off 0.9V Off 1.2V

MVRC
Architectural Checks (2)
• Non-MV aware DFT and CTS tools can

Always-ON Block place buffers into an incorrect domain
ON/OFF
Block
• Structurally correct, but may lead to
functional problems
 Can be caught with test vectors, but
ISO_Control
MVRC can catch without vectors
CLK
Gen
Isolation gate
on clock path

MVSIM Flow
UPF RTL/Netlist
Testbench MVCMP
APDB
MVDBGEN
VCS + MVSIM
Multi-Voltage
VCD/FSDB

Multi-voltage Simulation Steps
> mvcmp -f simulation_file_list

> mvcmp -upf tb_ChipTop+.upf
> mvdbgen -top tb
> /usr/bin/gmake -f Makefile.ev all TOOL=vcs
simulation_file_list consists of RTL verilog files

and testbench files
The testbench needs to be made power aware. This is
done by creating a power domain for the testbench. Also
the power supply nets defined in the design need to be
propagated up into the testbench, so that the testbench
can control them. This is done with a testbench level UPF
– tb_ChipTop+.upf
mvdbgen is run in testbench module

Power-down and Power-up Sequence
simulation Example
GPRS register Save asserted ISO signal GPRS output GPRS shutdown
loaded for retention asserted DATA clamped signal asserted
to 1
Restore signal
GPRS wake up Register values
asserted
restored

Logic Synthesis
compile(_ultra) recognizes multiple operating

voltages and automatically synthesizes logic
compile(_ultra) works with special cells
 Maps isolation cells and retention registers based on directives
 Hooks up control signals of retention registers
 Performs always on synthesis
 Optimizes level shifters
• Automatic insertion of level shifter cells
• Sizing of level shifters and isolation cells
• remapping from ISO/LS to ELS
All multi-voltage features are available in Design
Compiler Topographical mode as well

Always-on Synthesis
ChipTop VDD VDDG VDD Library cell

VDDB marked as
1.0V
Always-On
AO
gprs_sw
NSleep
Mark lib cells to be used as AO

VDDGS
AO anchor pins (ISO, ELS,
GPRs Switch, Ret control pins) are
1.2V/OFF VDDGS VDDG ELS
automatically inferred from PG-
pin library
RR
Use get_always_on_logic
to retrieve AO nets and cells
To enable AO synthesis
sleep restore retn isolate_ctrl set enable_ao_synthesis
PwrCtrl
VSS true
compile/place_opt

Overview of DFT support in UPF mode
All DFT MV features in non-UPF mode are available in

UPF mode
DFT MAX in UPF mode is easier to use vs. non-UPF

mode
 Automatic isolation and enable-level-shifter cell insertion as part of
insert_dft
 Correct handling of MV cell location

DFT flows supported in UPF mode
Standard scan
 Includes AutoFix, observe point insertion, user-defined test point
insertion
 Multiplexed flip-flop scan style only
Adaptive scan
 Default and High X-tolerance
 Multiplexed flip-flop scan style only

Multi-Voltage-Aware DFT
By default, scan stitching does not mix scan cells between power domains
To allow mixing of scan-chains
set_scan_configuration –power_domain_mixing true
set_scan_configuration –voltage_mixing true
1.1V 0.9V 0.7V 0.7V

1.1V 0.9V
PD top PD top
PD2 PD2
PD1 PD1
voltage_mixing false voltage_mixing true

power_domain_mixing false power_domain_mixing true

IC Compiler UPF flow
Read ddc from DC/DCT

Design Setup Read TDF IO/pin constraints
Timing constraints are passed through
ddc
Design Planning UPF power intent is passed through
ddc
Same UPF subset is supported in DC
place_opt and ICC
Most of special cells (LS, ISO, ELS,
RR) are inserted in DC and
clock_opt
maintained/optimized in ICC
route_opt

Design Planning
Voltage Area Creation
• Create Voltage area for each

power domain
• Rectilinear shapes are allowed
• Physically nested voltage areas
supported
## CREATE VA FOR EACH PD

create_voltage_area \
-power_domain MULT \
-coord { 40 40 60 60 }

Design Planning
PG Pin Hookup
PN1 (switch input)
• PG pins of standard cells hooked
PN2 up to PG nets automatically
(switch output,primary) • PG connections are derived from
 PG pin syntax in the library
P1
 Scoped and mapped power net
G1
UPF objects
• Tie-off nets are also hooked up to
correct PG net
• Checks for any PG connection
VSS violations
derive_pg_connection •connect_pg_nets is
check_mv_design –power_nets
recommended for physical only
cells

Switch Cell Placement
add_header_footer_cell_array
-lib_cell "mult_sw“
-voltage_area MULT
-design Multiplier
-x_increment 63
-y_increment 8

Switch Cell Power Planning
VSS
external-VDD external-VDD
GATE GATE GATE
switch switch
VDDG
VDDG
VSS
VSS
VDDGS
switch switch
GATE GATE GATE
external-VDD external-VDD
VSS

Automated Power Switch Handling
Rapid Analysis of Power Network Configuration
Automatically generate various options…
Problem: How many power switches? map MAX VD(mV) Area(%) Res(Ω) Total N X pitch Y pitch
Where do you put them?
A 284.092 9.03 10 338 0 0
Too few switches cause IR drop issues
B 280.707 6.09 10 228 40 25
Too many switches take valuable chip area
C 259.819 8.02 10 300 40 20
Option A Option B Option C
Designer
chooses best
option
Implementation
automatically
optimized

MV + MCMM
 By using MCCM for a MV design,

 “Dynamic voltage scaling” designs can be implemented
 i.e. the design/blocks can operate at different voltages at different
points of time
ChipTop
GPRs
High Volt
Low Volt S0: Design @ HV,
High Volt
PwrCtrl RAMs @ LV
OFF
MemX,
MemY
Multiplier
S1: Top, Mult @ HV
Low Volt
OFF
High Volt
OFF
GENPP GPRS, RAMs @ LV
High Volt
MemX
MemY

MV Aware Placement
LS cells ISO cells
MV aware placement and

optimization
Multi-site row support
Special Level Shifter and
Isolation Cells handling
High Fanout Net Synthesis
(HFNS)
Routing estimation detours
around VA
place_opt

MV Aware Clock Tree Synthesis
• Register clusters are

created respecting
voltage areas
• Clock routing is confined

to voltage area
• Tracing through level

shifters and enable level
shifters

44
Part 3 : UPF Language Syntax
create_power_domain create_power_switch
create_supply_port set_retention
create_supply_net set_retention_control
connect_supply_net map_retention
set_domain_supply_net set_isolation
connect_supply_net set_isolation_control
add_port_state set_level_shifter
create_pst
add_pst_state
create_power_domain
create_power_domain <domain_name>
[-elements <list of hierarchical
instances>]
[-scope <instance_name>]
 Creates a power domain at the current scope, level of hierarchy
 -elements to define specific instances to include in power domain
 -scope to create the power domain in another scope, level of
hierarchy
• To define a power domain for a child design at the child‟s level of hierarchy

Scope of a Power Domain
ChipTop VDDG Power domain created at top

1.0V level scope
create_power_domain Top
create_power_domain
GPRS -elements GPRs
Power domain created as
GPRs GPRS
1.2V/OFF Subsequently all UPF
components for power domain
GPRS will be created at top
level
create_supply_port VDDG
sleep restore retn isolate_ctrl
-domain GPRS
PwrCtrl

Scope of a Power Domain
ChipTop
1.0V Power domain created at
lower level scope
VDDG create_power_domain
GPRS -elements GPRs
-scope GPRs
Power domain created as
GPRs GPRs/GPRS
1.2V/OFF
Subsequently all UPF
components for power
domain GPRS will be created
at GPRs level
create_supply_port
VDDG –domain GPRS
PwrCtrl

Supply Network
ChipTop
VDDG VDDB • UPF can specify a complete
1.0 V power supply network
• Supply ports
VDDG • Supply nets
Sleep Sleepout • Power switches
VDDB
gprs_sw • Implicit connections based
VDDGS
on PD
GPRS • Explicit supply
VDDGS connections
1.2 V
VDDB
• UPF commands
•create_supply_ports
R •create_supply_nets
VSS •create_power_switch
•connect_supply_net
•set_domain_supply_net
VSS

create_supply_port
create_supply_port <port_name>
[-domain <domain name>]
 port_name needs to be unique at the level of hierarchy it is defined
 -domain is used to specify supply ports inside another power
domain
 For designs with multiple power domains at the same scope/ level of
hierarchy, supply ports are available to all power domains defined at
that scope
>create_supply_port VDD -domain child

create_supply_net
create_supply_net <supply_net_name>
-domain <domain_name>
[-reuse]
 supply_net_name must be a unique identifier
 -domain specifies the power domain in which the supply net is to be
created
 -reuse specifies that the listed supply net name is to be re-used as
a supply net inside the power domain specified by the -domain
option

Re-use of supply nets
To make supply net VDD available to PD2, the -reuse option
needs to be used when defining the supply net VDD in PD2
>create_power_domain PD1 -elements {A B}
>create_power_domain PD2 -elements {C D}
>create_supply_net VDD -domain PD1
>create_supply_net VDD -domain PD2 -reuse
Supply net VDD is now available in both PD1 and PD2

connect_supply_net
connect_supply_net <supply_net> [-ports list]

To connect a supply net to a supply port at current level of
hierarchy, self
connect_supply_net VDD -ports VDD
To connect a supply net to a child‟s supply port

connect_supply_net VDD -ports child/VDD
To connect a supply net to both self and child

connect_supply_net VDD -ports {VDD child/VDD}

set_domain_supply_net
set_domain_supply_net <domain_name> \
-primary_supply_net <power_supply_net> \
-primary_ground_net <ground_supply_net>
 Tells tools what are the default power and ground connections for cells in a
power domain

Dynamic Voltage and Frequency Scaling
(DVFS): Power State Tables
0.8 • Capture dynamic voltage

0.9 scaling (DVS/DVFS) and
0.8
Vdd2 shutdown scenarios with
Vdd1 Power State Table (PST)
Vdd3 • UPF Commands
• add_port_state
U1 a
U2 U3 • create_pst
MACRO b
• add_pst_state
PD2 PDT
Vdd1 Vdd2 Vdd3

-------------------
PwrState1 0.8V 0.8V 0.8V
PwrState2 0.8V 0.9V off

Power State Table
PST defines all possible power states for a design

Should be defined at the top level of a design
Only one PST can be defined for a design
add_port_state <port_name> {-state {name
<nom>|<min nom max>|<off>}}
 Defines all possible state information to a supply port
create_pst <table_name> -supplies {list}
 Creates a PST using a specific order of supply nets
add_pst_state <state_name> -pst <table_name>
-state <supply_states>
 Defines states of each of the supply nets for one possible state of the design

create_power_switch
create_power_switch <switch_name>
-output_supply_port <port_name
supply_net_name>
{-input_supply_port <port_name
supply_net_name>}
{-control_port <port_name net_name>}
[-ack_port <port_name net_name>]
Multiple control and acknowledge signals may be given to

the power switch defined
ICC will expand this into a power switch network

Power Switch
ChipTop VDD VDDG Create power switch for

1.0V GPRS
create_power_switch gprs_sw
gprs_sw
NSleep
-domain GPRS
-input_supply_port {in
VDDGS
VDDG} -output_supply_port
GPRs
{out VDDGS} -control_port
1.2V/OFF
{sleep PwrCtrl/sleep}
-on_state {state2002 in
{!sleep}}

PwrCtrl
VSS

Isolation Cells
set_isolation
set_isolation <isolation_strategy>
-domain power_domain
-isolation_power_net <isolation_power_net>
-isolation_ground_net <isolation_ground_net>
[-clamp_value 0 | 1 | latch]
[-applies_to inputs | outputs | both]
[-elements objects]
[-no_isolation]
The power net given to isolation_power_net and

isolation_ground_net needs to be more always_on than the
domain’s primary power or ground net

Isolation Cells
set_isolation_control
set_isolation_control <isolation_strategy>
-isolation_signal <isolation_signal>
[-isolation_sense 0 | 1]
[-location self | parent]
 The isolation_signal needs to exist in

the scope in which the isolation strategy
is defined

Isolation Strategy
ChipTop VDD VDDG Isolation strategy for GPRS

1.0V
set_isolation
gprs_iso_out -domain GPRS
gprs_sw -isolation_power_net VDD
NSleep
-isolation_ground_net VSS
VDDGS
-clamp_value 1 -
applies_to outputs
GPRs
1.2V/OFF ELS
set_isolation_control
gprs_iso_out –domain GPRS
-isolation_signal
PwrCtrl/isolate_ctrl
-isolation_sense low
-location parent
PwrCtrl
VSS

set_retention
set_retention <retention_strategy> -domain

<power_domain> -retention_power_net
<retention_power_net> -retention_ground_net
<retention_ground_net> [-elements objects]
The power net used must be more always on that the

power domain‟s primary power
Unless elements are specified, this constraint will apply to
all registers in the power domain

set_retention_control
set_retention_control <retention_strategy>
-save_signal {{net_name <high | low >}}
-restore_signal {{net_name <high | low >}}
The save and restore signals will be stitched up to the

scope the set_retention_control command was
defined at
 If set_retention_control was defined at the top scope, save
and restore will be stitched up to the top of the design

map_retention_cell
map_retention_cell <retention_strategy>
[-lib_cells lib_cells]
[-lib_cell_type lib_cell_type]
[-elements objects]
Directs DC to map the specified sequential cells to a

specific retention cell during compile(_ultra)

Retention Register Strategy
ChipTop VDD VDDG Retention strategy for GPRS

1.0V
set_retention gprs_ret
-domain GPRS
gprs_sw
NSleep -retention_power_net VDDG
-retention_ground_net VSS
VDDGS
set_retention_control
GPRs gprs_ret -domain GPRS
VDDGS ELS
-save_signal
1.2V/OFF VDDG
{PwrCtrl/retn high} -
RR restore_signal
{PwrCtrl/restore high}
map_retention_cell
sleep restore retn isolate_ctrl gprs_ret -domain GPRS
PwrCtrl -lib_cell_type RSDFCD1
VSS

Level Shifters
set_level_shifter <level_shifter_name>
[-elements list]
[-applies_to <inputs | outputs | both>]
[-threshold value]
[-rule <low_to_high | high_to_low | both>]
[-location <self | parent | fanout | automatic>]
[-no_shift]
The default for level shifters is ‘-rule both’ and ‘-

location automatic’
‘-location automatic’ allows the tool is determine what is
the best location for level shifter insertion

Predictable Success
Thank you for your attention!

Low Power UPF and VP

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1

Low Power System-on-Chip Design

Advanced Power Modeling Support

Petri Solanti, CAE

Part 1 : Power Analysis with Virtual Platforms

What is a Virtual Platform

• Fully functional software model of

Institute of Digital and Computer Systems / TKT-9636

CPU Func TLM Bus Func TLM Bus

Institute of Digital and Computer Systems / TKT-9636

Increase visibility into global system state & individual power/clock

Institute of Digital and Computer Systems / TKT-9636

 The following power support is added to a TLM platform:

Institute of Digital and Computer Systems / TKT-9636

Start with functional-

Institute of Digital and Computer Systems / TKT-9636

Signal is used to transmit value of clock

Functional clock modeling

Institute of Digital and Computer Systems / TKT-9636

Functional models of:

PRCM LDOs VDD RF

System-on-Chip (SoC) Power Management Chip

Institute of Digital and Computer Systems / TKT-9636

Parametrizable power model, consisting of:

Institute of Digital and Computer Systems / TKT-9636

Institute of Digital and Computer Systems / TKT-9636

Examples: OMAP2420 (PV model)

Institute of Digital and Computer Systems / TKT-9636

 System power estimations expressions, contain:

 At run-time power estimation expressions are

Institute of Digital and Computer Systems / TKT-9636

 Expressions can be linear, or more complex,

 Fixed modeling APIs for voltage, frequency & power

Institute of Digital and Computer Systems / TKT-9636

MPU Power State Power Parameters

Magic-C Power Model

Institute of Digital and Computer Systems / TKT-9636

(Dcache iss) Set Simulator

Fixed power Platform Analyzer *

Institute of Digital and Computer Systems / TKT-9636

Institute of Digital and Computer Systems / TKT-9636

Institute of Digital and Computer Systems / TKT-9636

Part 2 : UPF Language in Design Flows

UPF Target Design Styles

Multi-Voltage (MV) MTCMOS power MV with power Dynamic Voltage

Institute of Digital and Computer Systems / TKT-9636

Institute of Digital and Computer Systems / TKT-9636

VCS+MVSIM Design Compiler

Institute of Digital and Computer Systems / TKT-9636

Institute of Digital and Computer Systems / TKT-9636

Domain1 Domain2 Domain3

Institute of Digital and Computer Systems / TKT-9636

• Architecture checks verify that

Mode3 Off 0.9V Off 1.2V

Institute of Digital and Computer Systems / TKT-9636

• Non-MV aware DFT and CTS tools can

Institute of Digital and Computer Systems / TKT-9636

Institute of Digital and Computer Systems / TKT-9636

> mvcmp -f simulation_file_list

simulation_file_list consists of RTL verilog files

Institute of Digital and Computer Systems / TKT-9636

Institute of Digital and Computer Systems / TKT-9636

compile(_ultra) recognizes multiple operating