Computer Organization - Functional Units of A Computer
Computer Organization - Functional Units of A Computer
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11. The I/O interface required to connect the I/O device to the bus consists of ______
a) Address decoder and registers
b) Control circuits
c) Address decoder, registers and Control circuits
d) Only Control circuits
Answer: c
Explanation: The I/O devices are connected to the CPU via BUS and to interact with the BUS
they have an interface.
12. To reduce the memory access time we generally make use of ______
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
Answer: d
Explanation: The time required to access a part of the memory for data retrieval
13. ______ is generally used to increase the apparent size of physical memory.
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
Answer: b
Explanation: Virtual memory is like an extension to the existing memory.
9. The registers, ALU and the interconnection between them are collectively called as _____
a) process route
b) information trail
c) information path
d) data path
Answer: d
Explanation: The Operational and processing part of the CPU are collectively called as a data
path.
2. ______ are used to overcome the difference in data transfer speeds of various devices.
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
Answer: d
Explanation: By using Buffer registers, the processor sends the data to the I/O device at the
processor speed and the data gets stored in the buffer. After that the data gets sent to or
from the buffer to the devices at the device speed.
4. IBM developed a bus standard for their line of computers ‘PC AT’ called _____
a) IB bus
b) M-bus
c) ISA
d) None of the mentioned
Answer: c
5. The bus used to connect the monitor to the CPU is ______
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
Answer: b
Explanation: SCSI BUS is usually used to connect the video devices to the processor.
6. ANSI stands for __________
a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
Answer: a
7. _____ register Connected to the Processor bus is a single-way transfer capable.
a) PC
b) IR
c) Temp
d) Z
View Answer
Answer: d
Explanation: The Z register is a special register which can interact with the processor BUS
only.
8. In multiple Bus organisation, the registers are collectively placed and referred as ______
a) Set registers
b) Register file
c) Register Block
d) Map registers
Answer: b
9. The main advantage of multiple bus organisation over a single bus is _____
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of the mentioned
Answer: a
Performance of a System
1. During the execution of the instructions, a copy of the instructions is placed in the ______
a) Register
b) RAM
c) System heap
d) Cache
Answer: d
2. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose
A can execute an instruction with an average of 3 steps and B can execute with an average of 5
steps. For the execution of the same instruction which processor is faster?
a) A
b) B
c) Both take the same time
d) Insufficient information
Answer: a
Explanation: The performance of a system can be found out using the Basic performance
formula.
3. A processor performing fetch or decoding of different instruction during the execution of another
instruction is called ______
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
d) None of the mentioned
Answer: b
Explanation: Pipe-lining is the process of improving the performance of the system by
processing different instructions at the same time, with only one instruction performing one
specific operation.
4. For a given FINITE number of instructions to be executed, which architecture of the processor
provides for a faster execution?
a) ISA
b) ANSA
c) Super-scalar
d) All of the mentioned
Answer: c
Explanation: In super-scalar architecture, the instructions are set in groups and they’re
decoded and executed together reducing the amount of time required to process them.
10. When Performing a looping operation, the instruction gets stored in the ______
a) Registers
b) Cache
c) System Heap
d) System stack
Answer: b
Explanation: When a looping or branching operation is carried out the offset value is stored
in the cache along with the data.
11. The average number of steps taken to execute the set of instructions can be made to be less
than one by following _______
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
Answer: c
Explanation: The number of steps required to execute a given set of instructions is
sufficiently reduced by using super-scaling. In this method, a set of instructions are grouped
together and are processed.
12. If a processor clock is rated as 1250 million cycles per second, then its clock period is ________
a) 1.9 * 10-10 sec
b) 1.6 * 10-9 sec
c) 1.25 * 10-10 sec
d) 8 * 10-10 sec
Answer: d
13. If the instruction, Add R1, R2, R3 is executed in a system which is pipe-lined, then the value of S
is (Where S is a term of the Basic performance equation)
a) 3
b) ~2
c) ~1
d) 6
Answer: c
Explanation: S is the number of steps required to execute the instructions.
15. As of 2000, the reference system to find the SPEC rating are built with _____ Processor.
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
Answer: b
Addressing Modes
1. The instruction, Add #45,R1 does _______
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned
Answer: b
Explanation: The instruction is using immediate addressing mode hence the value is stored
in the location 45 is added.
2. In the case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
Answer: c
Explanation: In this case, the operands are implicitly loaded onto the ALU.
3. Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
d) None of the mentioned
Answer: b
4. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
Answer: a
Explanation: In this addressing mode, the value of the register serves as another memory
location and hence we use pointers to get the data.
5. In the following indexed addressing mode instruction, MOV 5(R1),LOC the effective address is
______
a) EA = 5+R1
b) EA = R1
c) EA = [R1].
d) EA = 5+[R1].
Answer: d
Explanation: This instruction is in Base with offset addressing mode.
6. The addressing mode/s, which uses the PC instead of a general purpose register is ______
a) Indexed with offset
b) Relative
c) direct
d) both Indexed with offset and direct
Answer: b
Explanation: In this, the contents of the PC are directly incremented.
7. When we use auto increment or auto decrements, which of the following is/are true?
1) In both, the address is used to retrieve the operand and then the address gets altered
2) In auto increment, the operand is retrieved first and then the address altered
3) Both of them can be used on general purpose registers as well as memory locations
a) 1, 2, 3
b) 2
c) 1, 3
d) 2, 3
Answer: d
Explanation: In the case of, auto increment the increment is done afterward and in auto
decrement the decrement is done first.
8. The addressing mode, where you directly specify the operand value is _______
a) Immediate
b) Direct
c) Definite
d) Relative
Answer: a
9. The effective address of the following instruction is MUL 5(R1,R2).
a) 5+R1+R2
b) 5+(R1*R2)
c) 5+[R1]+[R2].
d) 5*([R1]+[R2])
Answer: c
Explanation: The addressing mode used is base with offset and index.
10. _____ addressing mode is most suitable to change the normal sequence of execution of
instructions.
a) Relative
b) Indirect
c) Index with Offset
d) Immediate
Answer: a
Explanation: The relative addressing mode is used for this since it directly updates the PC.
Numbers and Arithmetic Operations
1. Which method/s of representation of numbers occupies a large amount of memory than others?
a) Sign-magnitude
b) 1’s complement
c) 2’s complement
d) 1’s & 2’s compliment
Answer: a
Explanation: It takes more memory as one bit used up to store the sign.
4. When we perform subtraction on -7 and 1 the answer in 2’s complement form is _________
a) 1010
b) 1110
c) 0110
d) 1000
Answer: d
Explanation: First the 2’s complement is found and that is added to the number and the
overflow is ignored.
5. When we perform subtraction on -7 and -5 the answer in 2’s complement form is ________
a) 11110
b) 1110
c) 1010
d) 0010
Answer: b
Explanation: First the 2’s complement is found and that is added to the number and the
overflow is ignored.
6. When we subtract -3 from 2 , the answer in 2’s complement form is _________
a) 0001
b) 1101
c) 0101
d) 1001
Answer: c
Explanation: First the 2’s complement is found and that is added to the number and the
overflow is ignored.
7. The processor keeps track of the results of its operations using a flags called ________
a) Conditional code flags
b) Test output flags
c) Type flags
d) None of the mentioned
Answer: a
Explanation: These flags are used to indicate if there is an overflow or carry or zero result
occurrence.
10. In some pipelined systems, a different instruction is used to add to numbers which can affect the
flags upon execution. That instruction is _______
a) AddSetCC
b) AddCC
c) Add++
d) SumSetCC
Answer: a
Explanation: By using this instruction the condition flags won’t be affected at all.
11. The most efficient method followed by computers to multiply two unsigned numbers is _______
a) Booth algorithm
b) Bit pair recording of multipliers
c) Restoring algorithm
d) Non restoring algorithm
Answer: b
12. For the addition of large integers, most of the systems make use of ______
a) Fast adders
b) Full adders
c) Carry look-ahead adders
d) None of the mentioned
Answer: c
Explanation: In this method the carries for each step are generated first.
13. In a normal n-bit adder, to find out if an overflow as occurred we make use of ________
a) And gate
b) Nand gate
c) Nor gate
d) Xor gate
Answer: d
14. In the implementation of a Multiplier circuit in the system we make use of _______
a) Counter
b) Flip flop
c) Shift register
d) Push down stack
Answer: c
Explanation: The shift registers are used to store the multiplied answer.
2. The collection of the above mentioned entities where data is stored is called ______
a) Block
b) Set
c) Word
d) Byte
Answer: c
Explanation: Each readable part of data is called as blocks.
4. If a system is 64 bit machine, then the length of each word will be _______
a) 4 bytes
b) 8 bytes
c) 16 bytes
d) 12 bytes
Answer: b
Explanation: A 64 bit system means, that at a time 64 bit instruction can be executed.
6. When using the Big Endian assignment to store a number, the sign bit of the number is stored in
_____
a) The higher order byte of the word
b) The lower order byte of the word
c) Can’t say
d) None of the mentioned
Answer: a
7. To get the physical address from the logical address generated by CPU we use ____
a) MAR
b) MMU
c) Overlays
d) TLB
Answer: b
Explanation: Memory Management Unit, is used to add the offset to the logical address
generated by the CPU to get the physical address.
8. _____ method is used to map logical addresses of variable length onto physical memory.
a) Paging
b) Overlays
c) Segmentation
d) Paging with segmentation
Answer: c
Explanation: Segmentation is a process in which memory is divided into groups of variable
length called segments.
9. During the transfer of data between the processor and memory we use ______
a) Cache
b) TLB
c) Buffers
d) Registers
Answer: d
10. Physical memory is divided into sets of finite size called as ______
a) Frames
b) Pages
c) Blocks
d) Vectors
Answer: a
4. The technique used to store programs larger than the memory is ______
a) Overlays
b) Extension registers
c) Buffers
d) Both Extension registers and Buffers
Answer: a
Explanation: In this, only a part of the program getting executed is stored on the memory and
later swapped in for the other part.
5. The unit which acts as an intermediate agent between memory and backing store to reduce
process time is _____
a) TLB’s
b) Registers
c) Page tables
d) Cache
Answer: d
Explanation: The cache’s help in data transfers by storing most recently used memory pages.
7. Complete the following analogy:- Registers are to RAM’s as Cache’s are to _____
a) System stacks
b) Overlays
c) Page Table
d) TLB
Answer: d
8. The BOOT sector files of the system are stored in _____
a) Harddisk
b) ROM
c) RAM
d) Fast solid state chips in the motherboard
Answer: b
Explanation: The files which are required for the starting up of a system are stored on the
ROM.
9. The transfer of large chunks of data with the involvement of the processor is done by _______
a) DMA controller
b) Arbitrator
c) User system programs
d) None of the mentioned
Answer: a
Explanation: This mode of transfer involves the transfer of a large block of data from the
memory.
10. Which of the following technique/s used to effectively utilize main memory?
a) Address binding
b) Dynamic linking
c) Dynamic loading
d) Both Dynamic linking and loading
Answer: c
Explanation: In this method only when the routine is required is loaded and hence saves
memory.
8. While using the iterative construct (Branching) in execution ____ instruction is used to check the
condition.
a) TestAndSet
b) Branch
c) TestCondn
d) None of the mentioned
Answer:b
Explanation: Branch instruction is used to check the test condition and to perform the
memory jump with help of offset.
9. When using Branching, the usual sequencing of the PC is altered. A new instruction is loaded
which is called as ______
a) Branch target
b) Loop target
c) Forward target
d) Jump instruction
Answer:a
10. The condition flag Z is set to 1 to indicate _______
a) The operation has resulted in an error
b) The operation requires an interrupt call
c) The result is zero
d) There is no empty register available
Answer:c
Explanation: This condition flag is used to check if the arithmetic operation yields a zero
output.
Assembly Language
1. ____ converts the programs written in assembly language into machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
Answer: c
Explanation: An assembler is a software used to convert the programs into machine
instructions.
2. The instructions like MOV or ADD are called as ______
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
Answer: a
Explanation: This OP – codes tell the system what operation to perform on the operands.
4. Instructions which won’t appear in the object program are called as _____
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
Answer: d
Explanation: The directives help the program in getting compiled and hence wont be there in
the object code.
5. The assembler directive EQU, when used in the instruction: Sum EQU 200 does ________
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
Answer: b
Explanation: This basically is used to replace the variable with a constant value.
7. The directive used to perform initialization before the execution of the code is ______
a) Reserve
b) Store
c) Dataword
d) EQU
Answer: c
8. _____ directive is used to specify and assign the memory required for the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
Answer: d
Explanation: This instruction is used to allocate a block of memory and to store the object
code of the program there.
11. When dealing with the branching code the assembler ___________
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
Answer: c
Explanation: When the assembler comes across the branch code, it immediately finds the
branch offset and replaces it with it.
12. The assembler stores all the names and their corresponding values in ______
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
Answer: b
Explanation: The table where the assembler stores the variable names along with their
corresponding memory locations and values.
14. The utility program used to bring the object code into memory for execution is ______
a) Loader
b) Fetcher
c) Extractor
d) Linker
Answer: a
Explanation: The program which is used to load the program into memory.
15. To overcome the problems of the assembler in dealing with branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
Answer: d
Explanation: This creates entries into the symbol table first and then creates the object code.
6. The appropriate return addresses are obtained with the help of ____ in case of nested routines.
a) MAR
b) MDR
c) Buffers
d) Stack-pointers
Answer: d
Explanation: The pointers are used to point to the location on the stack where the address is
stored.
7. When parameters are being passed on to the subroutines they are stored in ________
a) Registers
b) Memory locations
c) Processor stacks
d) All of the mentioned
Answer: d
Explanation: In the case of, parameter passing the data can be stored on any of the storage
space.
8. The most efficient way of handling parameter passing is by using ______
a) General purpose registers
b) Stacks
c) Memory locations
d) None of the mentioned
Answer: a
Explanation: By using general purpose registers for the parameter passing we make the
process more efficient.
9. The most Flexible way of logging the return addresses of the subroutines is by using _______
a) Registers
b) Stacks
c) Memory locations
d) None of the mentioned
Answer: b
Explanation: The stacks are used as Logs for return addresses of the subroutines.
10. The wrong statement/s regarding interrupts and subroutines among the following is/are ______
i) The sub-routine and interrupts have a return statement
ii) Both of them alter the content of the PC
iii) Both are software oriented
iv) Both can be initiated by the user
a) i, ii and iv
b) ii and iii
c) iv
d) iii and iv
Answer: d
2. If the subroutine exceeds the private space allocated to it then the values are pushed onto
_________
a) Stack
b) System heap
c) Reserve Space
d) Stack frame
Answer: a
Explanation: If the allocated work space is exceeded then the data is pushed onto the system
stack.
3. ______ pointer is used to point to parameters passed or local parameters of the subroutine.
a) Stack pointer
b) Frame pointer
c) Parameter register
d) Log register
Answer: b
Explanation: This pointer is used to track the current position of the stack being used.
4. The reserved memory or private space of the subroutine gets deallocated when _______
a) The stop instruction is executed by the routine
b) The pointer reaches the end of the space
c) When the routine’s return statement is executed
d) None of the mentioned
Answer: c
Explanation: The work space allocated to a subroutine gets deallocated when the routine is
completed.
6. _____ the most suitable data structure used to store the return addresses in the case of nested
subroutines.
a) Heap
b) Stack
c) Queue
d) List
Answer: b
7. In case of nested subroutines, the stack top is always _________
a) The saved contents of the called sub routine
b) The saved contents of the calling sub routine
c) The return addresses of the called sub routine
d) None of the mentioned Answer: a
8. The stack frame for each subroutine is present in ______
a) Main memory
b) System Heap
c) Processor Stack
d) None of the mentioned
Answer: c
Explanation: The memory for the work space is allocated from the processor stack.
10. The sub-routine service procedure is similar to that of the interrupt service routine in ________
a) Method of context switch
b) Returning
c) Process execution
d) Method of context switch & Process execution
Answer: d
Explanation: The Subroutine service procedure is the same as the interrupt service routine in
all aspects, except the fact that interrupt might not be related to the process being executed.
2. The usual BUS structure used to connect the I/O devices is ___________
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
Answer: c
Explanation: BUS is a collection of address, control and data lines used to connect the
various devices of the computer.
3. In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices?
a) False
b) True
Answer: b
Explanation: This type of access is called as I/O mapped devices.
6. To overcome the lag in the operating speeds of the I/O device and the processor we use
___________
a) BUffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
Answer: b
Explanation: The processor operating is much faster than that of the I/O devices, so by using
the status flags the processor need not wait till the I/O operation is done. It can continue with
its work until the status flag is set.
7. The method of accessing the I/O devices by repeatedly checking the status flags is ___________
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None of the mentioned
Answer: a
Explanation: In this method, the processor constantly checks the status flags, and when it
finds that the flag is set it performs the appropriate operation.
8. The method of synchronising the processor with the I/O device in which the device sends a signal
when it is ready is
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
Answer: c
Explanation: This is a method of accessing the I/O devices which gives the complete power
to the devices, enabling them to intimate the processor when they’re ready for transfer.
10. The process wherein the processor constantly checks the status flags is called as
a) Polling
b) Inspection
c) Reviewing
d) Echoing
Answer: a
Interrupts – 1