Structural Lab
Structural Lab
AIM:
AIM To simulate the design of 4bit subtractor using structural modeling style
Apparatus: Pc installed with xilinx tool
Circuit diagram:
VHDL Code :
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M.TECH-ECE-VLSI & EMBEDDED SYSTEMS STRUCTURAL DIGITAL SYSTEM DESIGN LAB
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity subtractor_4bit is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : in STD_LOGIC_VECTOR(3 downto 0);
borrow : out STD_LOGIC;
diff : out STD_LOGIC_VECTOR(3 downto 0)
);
end subtractor_4bit;
Component fa is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end component;
begin
l <= not b;
u0 : fa port map (a(0),l(0),'1',diff(0),s(0));
u1 : fa port map (a(1),l(1),s(0),diff(1),s(1));
u2 : fa port map (a(2),l(2),s(1),diff(2),s(2));
ue : fa port map (a(3),l(3),s(2),diff(3),borrow);
entity fa is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end fa;
architecture fa_arc of fa is
begin
sum <= a xor b xor c;
carry <= (a and b) or (b and c) or (c and a);
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end fa_arc;
OUTPUT WAVEFORM:
Circuit diagram:
VHDL CODE:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity booths is
GENERIC(k : POSITIVE := 7); --input number word length less one
Port ( a,b : in STD_LOGIC_VECTOR (k downto 0);
mul : out STD_LOGIC_VECTOR (2*k+1 downto 0));
end booths;
architecture Behavioral of booths is
begin
process(a,b)
variable m: std_logic_vector (2*k+1 downto 0);
variable s: std_logic;
begin
m:="00000000"&b;
s:='0';
for i in 0 to k loop
if(m(0)='0' and s='1') then
m(k downto k-3):= m(k downto k-3)+a;
s:=m(0);
m(k-1 downto 0):=m(k downto 1);
elsif(m(0)='1' and s='0') then
m(k downto k-3):= m(k downto k-3)-a;
s:=m(0);
m(k-1 downto 0):=m(k downto 1);
else
s:=m(0);
m(k-1 downto 0):=m(k downto 1);
end if;
end loop;
mul<=m;
end process;
end Behavioral;
B)library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Testbench_di_Booth is
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end Testbench_di_Booth;
architecture behavior of Testbench_di_Booth is
component booths
GENERIC(k : POSITIVE := 7); --input number word length less one
Port( a,b : in STD_LOGIC_VECTOR (k downto 0);
mul : out STD_LOGIC_VECTOR (2*k+1 downto 0));
end component;
--Inputs
signal A : STD_LOGIC_VECTOR (7 downto 0):= "00000011";
signal B : STD_LOGIC_VECTOR (7 downto 0):= "00000100";
--Outputs
signal MUL : STD_LOGIC_VECTOR(15 downto 0);
begin
--Instantiate the UnitUnder Test (UUT)
uut: booths PORT MAP
(a => A,
b => B,
mul => MUL);
--Stimulus process
stim_proc: process
begin
--insert stimulus here
A<="00000011"; B<="00000100"; wait for 500 fs;
A<="00000110"; B<="00000111"; wait for 500 fs;
A<="00001011"; B<="00000100"; wait for 500 fs;
wait;
end process;
end;
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M.TECH-ECE-VLSI & EMBEDDED SYSTEMS STRUCTURAL DIGITAL SYSTEM DESIGN LAB
OUTPUT WAVEFORM:
VHDL CODE:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
Port ( inp_a : in signed(3 downto 0);
inp_b : in signed(3 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
out_alu : out signed(3 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(inp_a, inp_b, sel)
begin
case sel is
when "000" =>
out_alu<= inp_a + inp_b; --addition
when "001" =>
out_alu<= inp_a - inp_b; --subtraction
when "010" =>
out_alu<= inp_a - 1; --sub 1
when "011" =>
out_alu<= inp_a + 1; --add 1
when "100" =>
out_alu<= inp_a and inp_b; --AND gate
when "101" =>
out_alu<= inp_a or inp_b; --OR gate
when "110" =>
out_alu<= not inp_a ; --NOT gate
when "111" =>
out_alu<= inp_a xor inp_b; --XOR gate
when others =>
NULL;
end case;
end process;
end Behavioral;
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OUTPUT WAVEFORM:
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Circuit diagram:
VHDL Code-
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity siso_behavior is
port(
din : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end siso_behavior;
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begin
end siso_behavior_arc;
Output waveform:
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Aim: To simulate and design of 4bit serial in- parallel out shift register
using behavior modeling style
VHDL Code -
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity sipo_behavior is
port(
din : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end sipo_behavior;
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begin
if (reset='1') then
s := "0000";
elsif (rising_edge (clk)) then
s := (din & s(3 downto 1));
end if;
dout <= s;
end process sipo;
end sipo_behavior_arc;
Output waveform:
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Circuit diagram:
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VHDL Code-
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity parallel_in_serial_out is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
load : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC
);
end parallel_in_serial_out;
end piso_arc;
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Output waveform:
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VHDL Code.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity pipo_behavior is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
din : in STD_LOGIC_VECTOR(3 downto 0);
dout : out STD_LOGIC_VECTOR(3 downto 0)
);
end pipo_behavior;
end pipo_behavior_arc;
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Output waveform:
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Circuit diagram:
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ring_counter is
Port ( CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Ring_counter;
architecture Behavioral of Ring_counter is
signal q_tmp: std_logic_vector(3 downto 0):= "0000";
begin
process(CLOCK,RESET)
begin
if RESET = '1' then
q_tmp <= "0001";
elsif Rising_edge(CLOCK) then
q_tmp(1) <= q_tmp(0);
q_tmp(2) <= q_tmp(1);
q_tmp(3) <= q_tmp(2);
q_tmp(0) <= q_tmp(3);
end if;
end process;
Q <= q_tmp;
end Behavioral;
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Output waveform:
Circuit diagram:
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench
-- VHDL project: VHDL code for up counter
entity UP_COUNTER is
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end UP_COUNTER;
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if(rising_edge(clk)) then
if(reset='1') then
counter_up <= x"0";
else
counter_up <= counter_up + x"1";
end if;
end if;
end process;
counter <= counter_up;
end Behavioral;
Testbench VHDL code for the up-counter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench
-- VHDL project: Testbench VHDL code for up counter
entity tb_counters is
end tb_counters;
component UP_COUNTER
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end component;
signal reset,clk: std_logic;
signal counter:std_logic_vector(3 downto 0);
begin
dut: UP_COUNTER port map (clk => clk, reset=>reset, counter => counter);
-- Clock process definitions
clock_process :process
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begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process;
end Behavioral;
Output waveform:
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VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench
-- VHDL project: VHDL code for down counter
entity DOWN_COUNTER is
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit
counter
);
end DOWN_COUNTER;
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end Behavioral;
Output waveform:
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VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ring_counter is
Port ( CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Ring_counter;
architecture Behavioral of Ring_counter is
signal q_tmp: std_logic_vector(3 downto 0):= "0000";
begin
process(CLOCK,RESET)
begin
if RESET = '1' then
q_tmp <= "0001";
elsif Rising_edge(CLOCK) then
q_tmp(1) <= q_tmp(0);
q_tmp(2) <= q_tmp(1);
q_tmp(3) <= q_tmp(2);
q_tmp(0) <= q_tmp(3);
end if;
end process;
Q <= q_tmp;
end Behavioral;
Output waveform:
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Aim: To simulate and design a 4 bit johnson counter using D flip flop
Apparatus: Pc linked with xilinx tool
Circuit diagram:
VHDL Code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Johnson_counter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Johnson_counter;
architecture Behavioral of Johnson_counter is
signal temp: std_logic_vector(3 downto 0):= "0000";
begin
process(clk,rst)
begin
if rst = '1' then
temp <= "0000";
elsif Rising_edge(clk) then
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Output waveform:
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Aim : To write vhdl code for data memory of the MIPS processor
Apparatus: Pc linked with xilinx tool
Architecture:
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VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.all;
-- VHDL code for the data Memory of the MIPS Processor
entity Data_Memory_VHDL is
port (
clk: in std_logic;
mem_access_addr: in std_logic_Vector(15 downto 0);
mem_write_data: in std_logic_Vector(15 downto 0);
mem_write_en,mem_read:in std_logic;
mem_read_data: out std_logic_Vector(15 downto 0)
);
end Data_Memory_VHDL;
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end Behavioral;
Output waveform:
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VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_signed.all;
-- VHDL code for ALU of the MIPS Processor
entity ALU_VHDL is
port(
a,b : in std_logic_vector(15 downto 0); -- src1, src2
alu_control : in std_logic_vector(2 downto 0); -- function select
alu_result: out std_logic_vector(15 downto 0); -- ALU Output Result
zero: out std_logic -- Zero Flag
);
end ALU_VHDL;
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Aim: To write the vhdl code for alu control unit of the MIPS processor
Apparatus: Pc linked with xilinx tool
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VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- VHDL code for ALU Control Unit of the MIPS Processor
entity ALU_Control_VHDL is
port(
ALU_Control: out std_logic_vector(2 downto 0);
ALUOp : in std_logic_vector(1 downto 0);
ALU_Funct : in std_logic_vector(2 downto 0)
);
end ALU_Control_VHDL;
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Output waveform:
Aim: To write the vhdl code for register file of the MIPS processor
Apparatus: Pc linked with xilinx tool
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.all;
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end Behavioral;
Output waveform:
Aim: To write the vhdl code for control unit of the MIPS SOFTWARE
Apparatus: Pc linked with xilinx tool
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VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- VHDL code for Control Unit of the MIPS Processor
entity control_unit_VHDL is
port (
opcode: in std_logic_vector(2 downto 0);
reset: in std_logic;
reg_dst,mem_to_reg,alu_op: out std_logic_vector(1 downto 0);
jump,branch,mem_read,mem_write,alu_src,reg_write,sign_or_zero: out std_logic
);
end control_unit_VHDL;
begin
process(reset,opcode)
begin
if(reset = '1') then
reg_dst <= "00";
mem_to_reg <= "00";
alu_op <= "00";
jump <= '0';
branch <= '0';
mem_read <= '0';
mem_write <= '0';
alu_src <= '0';
reg_write <= '0';
sign_or_zero <= '1';
else
case opcode is
when "000" => -- add
reg_dst <= "01";
mem_to_reg <= "00";
alu_op <= "00";
jump <= '0';
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end Behavioral;
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Output waveform:
Aim: To write the vhdl code for instruction memory for the MIPS
PROCESSOR
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end Behavioral;
Output waveform:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_signed.all;
entity MIPS_VHDL is
port (
clk,reset: in std_logic;
pc_out, alu_result: out std_logic_vector(15 downto 0)
);
end MIPS_VHDL;
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end Behavioral;
Output waveform:
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Circuit diagram:
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Traffic ligh system for a intersection between
highway and farm way
-- There is a sensor on the farm way side, when there
are vehicles,
-- Traffic light turns to YELLOW, then GREEN to let the
vehicles cross the highway
-- Otherwise, always green light on Highway and Red
light on farm way
entity traffic_light_controller is
port ( sensor : in STD_LOGIC; -- Sensor
clk : in STD_LOGIC; -- clock
rst_n: in STD_LOGIC; -- reset active low
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begin
case current_state is
when HGRE_FRED => -- When Green light on Highway and
Red light on Farm way
RED_LIGHT_ENABLE <= '0';-- disable RED light delay
counting
YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light
Highway delay counting
YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light
Farmway delay counting
light_highway <= "001"; -- Green light on Highway
light_farm <= "100"; -- Red light on Farm way
if(sensor = '1') then -- if vehicle is detected on
farm way by sensors
next_state <= HYEL_FRED;
-- High way turns to Yellow light
else
next_state <= HGRE_FRED;
-- Otherwise, remains GREEN ON highway and RED on
Farm way
end if;
when HYEL_FRED => -- When Yellow light on Highway and
Red light on Farm way
light_highway <= "010";-- Yellow light on Highway
light_farm <= "100";-- Red light on Farm way
RED_LIGHT_ENABLE <= '0';-- disable RED light delay
counting
YELLOW_LIGHT1_ENABLE <= '1';-- enable YELLOW light
Highway delay counting
YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light
Farmway delay counting
if(delay_3s_H='1') then
-- if Yellow light delay counts to 3s,
-- turn Highway to RED,
-- Farm way to green light
next_state <= HRED_FGRE;
else
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end if;
end if;
end if;
end if;
end process;
-- create delay 1s
process(clk)
begin
if(rising_edge(clk)) then
counter_1s <= counter_1s + x"0000001";
if(counter_1s >= x"0000003") then -- x"0004" is for
simulation
-- change to x"2FAF080" for 50 MHz clock running real
FPGA
counter_1s <= x"0000000";
end if;
end if;
end process;
clk_1s_enable <= '1' when counter_1s = x"0003" else
'0'; -- x"0002" is for simulation
-- x"2FAF080" for 50Mhz clock on FPGA
end traffic_light;
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);
END COMPONENT;
signal sensor : std_logic := '0';
signal clk : std_logic := '0';
signal rst_n : std_logic := '0';
--Outputs
signal light_highway : std_logic_vector(2 downto 0);
signal light_farm : std_logic_vector(2 downto 0);
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the traffic light controller
trafficlightcontroller : traffic_light_controller PORT MAP (
sensor => sensor,
clk => clk,
rst_n => rst_n,
light_highway => light_highway,
light_farm => light_farm
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
rst_n <= '0';
sensor <= '0';
wait for clk_period*10;
rst_n <= '1';
wait for clk_period*20;
sensor <= '1';
wait for clk_period*100;
sensor <= '0';
wait;
end process;
END;
Output waveform:
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MINI PROJECT
ABSTRACT
Technology advancements have made possible the implementation of
embedded systems within home appliances. This has added new capabilities
and features, however, most of the time, the implementations are proprietary
and networking is not always possible. Yet there is an increasing demand for
smart homes, where appliances react automatically to changing
environmental conditions and can be easily controlled through one common
device. This paper presents a possible solution whereby the user controls
devices by employing a central Field Programmable Gate Array (FPGA)
controller to which the devices and sensors are interfaced. Control is
communicated to the FPGA from a mobile phone through
its Bluetooth interface. This results in a simple, cost effective, and flexible
system, making it a good candidate for future smart home solutions.
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Demonstration Video
BLOCK DIAGRAM
Home Section
Introduction
The Bluetooth wireless technology is set to revolutionize the way people
perceive digital devices in our homes and office environment. Now they are
no longer just the individual devices; instead, with the embedded Bluetooth
technology, they form a network in which appliances can communicate with
each other. This wireless technology is especially useful in home
environment, where there exists hardly any infrastructure to interconnect
intelligent appliances. It could be suitably used for home automation in a
cost-effective manner. Operating over unlicensed, universally available
frequency of 2.4 GHz, it can link digital devices within a range of 10 m
(expandable to 100 m, by increasing the transmitted power) at the speed of 1
Mbps. Building upon this theme; we propose a home automation system
based on Bluetooth . technology There are certain issues involved in the
design of a home automation system. The system should be scalable, so that
new device can easily be integrated into it. It should provide a user-friendly
interface on the host side, so that the devices can be setup, monitored and
controlled. The interface should also provide some diagnostic services so
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those problems with the system, if any, can be tracked down. The overall
system should be fast enough to realize the true power of wireless
technology. It should also be cost effective in order to justify its application
in home automation.
The system developed consists of android mobile phone and a FPGA based
Door Lock open/close system and relay on/off to control electrical Appliance,
that is able to communicate with the host through the Bluetooth link.
Device Registration
Device Control
Hardware design and development
A Door Lock open/close system and relay on/off to control electrical
Appliance circuitry has been developed to demonstrate the feasibility and
effectiveness of the application. The hardware interface component of
the Bluetooth based home automation system consists of a FPGA with
stepper motor, relay interface and an RS232 link between the FPGA and
the Bluetooth .
Tool required
Software: Xilinx ISE 10.1i or above
Language: VHDL
Hardware:
1.Spartan3an FPGA kit
2. Bluetooth Module
3.JTAG Cable
4. Serial Cable
5.Stepper Motor
6.Relay
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Source Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity uart_stepper is
din : in std_logic;
);
end uart_stepper;
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begin
process(clk)
variable i : integer := 0 ;
begin
if ps = ready then
end if;
ps <= b0;
ps <= ready;
end if;
------------------------------------------1
if ps = b0 then
i := i + 1;
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if i = 2600 then
end if;
if i = 7800 then
end if;
if i = 13000 then
end if;
if i = 18200 then
end if;
if i = 23400 then
end if;
if i = 28600 then
end if;
if i = 33800 then
end if;
if i = 39000 then
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end if;
if i = 44200 then
end if;
if i = 49400 then
end if;
if i = 54600 then
i := 0 ;
ps <= ready ;
end if;
end if;
end if;
end process;
process(clk,store)
variable j,k,l,m:integer:=0;
begin
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if(ps1=a0)then
j:=j+1;
if(j=500000)then
s_count<="1000";
end if;
if(j=1000000)then
s_count<="0100";
end if;
if(j=1500000)then
s_count<="0010";
end if;
if(j=2000000)then
s_count<="0001";
j:=0;
if k
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Conclusion
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