Ade7880 PDF
Ade7880 PDF
Ade7880 PDF
1
Protected by U.S. Patent 8,010,304 B2. Other patents pending.
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ADE7880 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Power Quality Measurements................................................... 32
Applications ....................................................................................... 1 Phase Compensation ................................................................. 37
General Description ......................................................................... 1 Reference Circuit ........................................................................ 39
Revision History ............................................................................... 3 Digital Signal Processor............................................................. 39
Functional Block Diagram .............................................................. 4 Root Mean Square Measurement ............................................. 41
Specifications..................................................................................... 5 Active Power Calculation .......................................................... 45
Timing Characteristics ................................................................ 8 Fundamental Reactive Power Calculation .............................. 51
Absolute Maximum Ratings .......................................................... 11 Apparent Power Calculation ..................................................... 55
Thermal Resistance .................................................................... 11 Power Factor Calculation .......................................................... 58
ESD Caution ................................................................................ 11 Harmonics Calculations ............................................................ 58
Pin Configuration and Function Descriptions ........................... 12 Waveform Sampling Mode ....................................................... 66
Typical Performance Characteristics ........................................... 14 Energy-to-Frequency Conversion............................................ 66
Test Circuit ...................................................................................... 19 No Load Condition .................................................................... 71
Terminology .................................................................................... 20 Checksum Register..................................................................... 73
Power Management ........................................................................ 21 Interrupts ..................................................................................... 74
PSM0—Normal Power Mode (All Parts) ................................ 21 Serial Interfaces .......................................................................... 75
PSM1—Reduced Power Mode.................................................. 21 ADE7880 Quick Setup As Energy Meter ................................ 82
PSM2—Low Power Mode ......................................................... 21 Layout Guidelines....................................................................... 83
PSM3—Sleep Mode (All Parts) ................................................ 22 Crystal Circuit ............................................................................ 84
Power-Up Procedure .................................................................. 24 ADE7880 Evaluation Board ...................................................... 84
Hardware Reset ........................................................................... 25 Die Version .................................................................................. 84
Software Reset Functionality .................................................... 25 Silicon Anomaly ............................................................................. 85
Theory of Operation ...................................................................... 26 ADE7880 Functionality Issues ................................................. 85
Analog Inputs .............................................................................. 26 Functionality Issues.................................................................... 85
Analog-to-Digital Conversion .................................................. 26 Section 1. ADE7880 Functionality Issues ............................... 86
Current Channel ADC............................................................... 27 Registers List ................................................................................... 87
di/dt Current Sensor and Digital Integrator ............................... 29 Outline Dimensions ..................................................................... 107
Voltage Channel ADC ............................................................... 30 Ordering Guide ........................................................................ 107
Changing Phase Voltage Data Path .......................................... 31
AIRMSOS
27 CF1DEN
IAP 7
PGA1 ADC
HPF
IAN 8 AVRMSOS DFC : 33 CF1
HPFEN OF APGAIN AWATTOS
APHCAL CONFIG3 AVGAIN
CF2DEN
COMPUTATIONAL 29 IRQ0
BLOCK FOR
ICP 13
HARMONIC SPI/I2C
INFORMATION ON 32 IRQ1
PGA1 ADC TOTAL/FUNDAMENTAL ACTIVE ENERGIES PHASE A CURRENT
FUNDAMENTAL REACTIVE ENERGY
ICN 14 APPARENT ENERGY AND VOLTAGE
VOLTAGE/CURRENT RMS 36 SCLK/SCL
HARMONIC INFORMATION CALCULATION
VCP 19 FOR PHASE C
ADC
(SEE PHASE A FOR DETAILED DATA PATH) 38 MOSI/SDA
PGA3
VN 18
I2C
37 MISO/HSD
COMPUTATIONAL BLOCK FOR HARMONIC
INFORMATION ON NEUTRAL CURRENT
39 SS/HSA
HPFEN OF DIGITAL HSDC
CONFIG3 INTEGRATOR NIGAIN NIRMSOS
INP 15
DIGITAL SIGNAL
PGA2 ADC X2 NIRMS PROCESSOR
HPF LPF
10193-001
INN 16
SPECIFICATIONS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C, TTYP = 25°C.
Table 1.
Parameter 1, 2 Min Typ Max Unit Test Conditions/Comments
ACTIVE ENERGY MEASUREMENT
Active Energy Measurement Error
(per Phase)
Total Active Energy 0.1 % Over a dynamic range of 1000 to 1,
PGA = 1, 2, 4; integrator off, pf = 1, gain
compensation only
0.2 % Over a dynamic range of 5000 to 1,
PGA = 1, 2, 4; integrator off, pf = 1
0.1 % Over a dynamic range of 500 to 1,
PGA = 8, 16; integrator on, pf = 1, gain
compensation only
0.2 % Over a dynamic range of 2000 to 1,
PGA = 8, 16; integrator on, pf = 1
Fundamental Active Energy 0.1 % Over a dynamic range of 1000 to 1,
PGA = 1, 2, 4; integrator off, pf = 1, gain
compensation only
0.2 % Over a dynamic range of 5000 to 1,
PGA = 1, 2, 4; integrator off, pf = 1
0.1 % Over a dynamic range of 500 to 1,
PGA = 8, 16; integrator on, pf = 1, gain
compensation only
0.2 % Over a dynamic range of 2000 to 1,
PGA = 8, 16; integrator on, pf = 1
AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz,
IPx = VPx = ±100 mV rms
Output Frequency Variation 0.01 %
DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc
Output Frequency Variation 0.01 %
Total Active Energy Measurement 3.3 kHz
Bandwidth (−3 dB)
REACTIVE ENERGY MEASUREMENT
Reactive Energy Measurement Error
(per Phase)
Fundamental Reactive Energy 0.1 % Over a dynamic range of 1000 to 1,
PGA = 1, 2, 4; integrator off, pf = 0, gain
compensation only
0.2 % Over a dynamic range of 5000 to 1,
PGA = 1, 2, 4; integrator off, pf = 0
0.1 % Over a dynamic range of 500 to 1,
PGA = 8, 16; integrator on, pf = 0, gain
compensation only
0.2 % Over a dynamic range of 2000 to 1,
PGA = 8, 16; integrator on, pf = 0
AC Power Supply Rejection VDD = 3.3 V + 120 mV rms/120 Hz,
IPx = VPx = ± 100 mV rms
Output Frequency Variation 0.01 %
DC Power Supply Rejection VDD = 3.3 V ± 330 mV dc
Output Frequency Variation 0.01 %
Fundamental Reactive Energy 3.3 kHz
Measurement Bandwidth (−3 dB)
TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Note that dual
function pin names are referenced by the relevant function only within the timing tables and diagrams (see the Pin Configuration and
Function Descriptions section for full pin mnemonics and descriptions).
SDA
tBUF
tF tSU;DAT tHD;STA tSP tF
tF tF
tLOW
SCL
tHD;STA
tHD;DAT tSU;STA tSU;STO
tHIGH
10193-002
SS
tSS
tSFS
SCLK
tSL
tSH tSF tSR
tDAV
tDIS
tDF tDR
INTERMEDIATE BITS
tDSU
10193-003
tDHD
HSA
tSS
tSFS
HSCLK
tSL
10193-004
tDF tDR
2mA IOL
TO OUTPUT 1.6V
PIN
CL
50pF
800µA IOH
10193-005
CF2/HREADY
CF3/HSCLK
SCLK/SCL
MOSI/SDA
MISO/HSD
SS/HSA
IRQ1
CF1
NC
NC
34
33
40
39
38
37
36
35
32
31
NC 1 30 NC
PM0 2 29 IRQ0
PM1 3 28 CLKOUT
RESET 4 ADE7880 27 CLKIN
DVDD 5 26 VDD
DGND 6 TOP VIEW 25 AGND
IAP 7 (Not to Scale) 24 AVDD
IAN 8 23 VAP
IBP 9 22 VBP
NC 10 21 NC
11
12
13
16
14
15
18
19
20
17 REFIN/OUT
IBN
INN
VN
ICN
ICP
INP
VCP
NC
NC
NOTES
1. NC = NO CONNECT.
2. CREATE A SIMILAR PAD ON THE PCB UNDER THE
EXPOSED PAD. SOLDER THE EXPOSED PAD TO
10193-006
THE PAD ON THE PCB TO CONFER MECHANICAL
STRENGTH TO THE PACKAGE. CONNECT THE
PADS TO AGND AND DGND.
0.1 0.1
ERROR (%)
ERROR (%)
–0.1 –0.1
–0.3 –0.3
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
–0.5 –0.5
10193-100
10193-103
0.01 0.1 1 10 100 0.01 0.1 1 10 100
PERCENTAGE OF FULL-SCALE CURRENT (%) PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 7. Total Active Energy Error as Percentage of Reading (Gain = +1, Figure 10. Total Active Energy Error as Percentage of Reading (Gain = +1)
Power Factor = 1) over Temperature with Internal Reference and over Power Supply with Internal Reference and Integrator Off
Integrator Off
0.5 0.5
GAIN = +1
GAIN = +2
GAIN = +4
GAIN = +8 0.3
0.3
GAIN = +16
0.1 0.1
ERROR (%)
ERROR (%)
–0.1 –0.1
–0.3 –0.3
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
–0.5 –0.5
10193-104
10193-101
Figure 8. Total Active Energy Error as Percentage of Reading over Gain with Figure 11. Total Active Energy Error as Percentage of Reading (Gain = +16)
Internal Reference and Integrator Off over Temperature with Internal Reference and Integrator On
0.5 0.5
PF = +1.0
PF = +0.5
PF = –0.5
0.3 0.3
0.1 0.1
ERROR (%)
ERROR (%)
–0.1 –0.1
–0.3 –0.3
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
–0.5 –0.5
10193-105
10193-102
Figure 9. Total Active Energy Error as Percentage of Reading (Gain = +1) over Figure 12. Fundamental Active Energy Error as Percentage of Reading
Frequency with Internal Reference and Integrator Off (Gain = +1, Power Factor = 1) over Temperature with Internal Reference and
Integrator Off
0.1 0.1
ERROR (%)
ERROR (%)
–0.1 –0.1
–0.3 –0.3
–0.5 –0.5
10193-109
10193-106
0.01 0.1 1 10 100 0.01 0.1 1 10 100
PERCENTAGE OF FULL-SCALE CURRENT (%) PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 13. Fundamental Active Energy Error as Percentage of Reading over Figure 16. Fundamental Reactive Energy Error as Percentage of Reading
Gain with Internal Reference and Integrator Off (Gain = +1, Power Factor = 0) over Temperature with Internal Reference and
Integrator Off
0.5 0.5
VDD = 2.97V GAIN = +1
VDD = 3.30V GAIN = +2
VDD = 3.63V GAIN = +4
0.3 GAIN = +8
0.3
GAIN = +16
0.1 0.1
ERROR (%)
ERROR (%)
–0.1 –0.1
–0.3 –0.3
–0.5 –0.5
10193-107
10193-110
0.01 0.1 1 10 100 0.01 0.1 1 10 100
PERCENTAGE OF FULL-SCALE CURRENT (%) PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 14. Fundamental Active Energy Error as Percentage of Reading Figure 17. Fundamental Reactive Energy Error as Percentage of Reading over
(Gain = +1) over Power Supply with Internal Reference and Integrator Off Gain with Internal Reference and Integrator Off
0.5 0.5
PF = 0
PF = +0.866
PF = –0.866
0.3 0.3
0.1 0.1
ERROR (%)
ERROR (%)
–0.1 –0.1
–0.3 –0.3
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0 –0.5
–0.5
10193-111
10193-108
Figure 15. Fundamental Active Energy Error as Percentage of Reading Figure 18. Fundamental Reactive Energy Error as Percentage of Reading
(Gain = +1) over Temperature with Internal Reference and Integrator On (Gain = +1) over Frequency with Internal Reference and Integrator Off
0.1 0.1
ERROR (%)
ERROR (%)
–0.1 –0.1
–0.3 –0.3
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
–0.5 –0.5
10193-112
10193-115
0.01 0.1 1 10 100 0.01 0.1 1 10 100
PERCENTAGE OF FULL-SCALE CURRENT (%) PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 19. Fundamental Reactive Energy Error as Percentage of Reading Figure 22. V RMS Error as a Percentage of Reading (Gain = +1) over
(Gain = +1) over Power Supply with Internal Reference and Integrator Off Temperature with Internal Reference
0.5 5
–10
0.1
GAIN ERROR
–15
ERROR (%)
–20
–0.1 –25
–30
–0.3 –35
+85°C, PF = 0
+25°C, PF = 0 –40
–40°C, PF = 0
–0.5 –45
10193-113
10193-116
0.01 0.1 1 10 100 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63
PERCENTAGE OF FULL-SCALE CURRENT (%) HARMONIC ORDER (55Hz FUNDAMENTAL)
Figure 20. Fundamental Reactive Energy Error as Percentage of Reading Figure 23. Harmonic I RMS Error as a Percentage of Reading over Harmonic
(Gain = +16) over Temperature with Internal Reference and Integrator On Order, 63 Harmonics, 55 Hz Fundamental, 30 Averages per Reading, 750 ms
Settling time, 125 µs Update Rate
0.5 6
MEASUREMENT ERROR (% of Reading)
4
0.3
2
0.1
ERROR (%)
–0.1
–2
–0.3
–4
+85°C, PF = 1.0
+25°C, PF = 1.0
–40°C, PF = 1.0
–0.5 –6
10193-114
10193-117
Figure 21. I RMS Error as Percentage of Reading (Gain = +1) over Figure 24. Harmonic I RMS Error as a Percentage of Reading (Gain = +1),
Temperature with Internal Reference and Integrator Off 51 Harmonics, 55 Hz Fundamental, Single Reading, 750 ms Settling Time;
125 µs Update Rate
2 2
0 0
–2 –2
–4 –4
–6 –6
10193-120
10193-118
0.01 0.1 1 10 100 0.01 0.1 1 10 100
PERCENTAGE OF FULL-SCALE CURRENT (%) PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 25. Harmonic I RMS Error as Percentage of Reading (Gain = +1), Figure 27. Harmonic Active Power Error as Percentage of Reading
51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading, 750 ms (Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading,
Settling Time, 125 µs Update Rate 750 ms Settling Time, 125 µs Update Rate
6 6
MEASUREMENT ERROR (% of Reading)
2 2
0 0
–2 –2
–4 –4
–6 –6
10193-121
10193-119
Figure 26. Harmonic Active Power Error as Percentage of Reading Figure 28. Harmonic Reactive Power Error as Percentage of Reading
(Gain = +1), 51 Harmonics, 55 Hz Fundamental, Single Reading, (Gain = +1), 51 Harmonics, 55 Hz Fundamental, Single Reading, 750 ms
750 ms Settling Time, 125 µs Update Rate Settling Time, 125 µs Update Rate
4 4
2 2
0 0
–2 –2
–4 –4
–6 –6
10193-124
10193-122
0.01 0.1 1 10 100 0.01 0.1 1 10 100
PERCENTAGE OF FULL-SCALE CURRENT (%) PERCENTAGE OF FULL-SCALE CURRENT (%)
Figure 29. Harmonic Reactive Power Error as Percentage of Reading Figure 31. Harmonic Apparent Power Error as Percentage of Reading
(Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading, (Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading,
750 ms Settling Time, 125 µs Update Rate 750 ms Settling Time, 125 µs Update Rate
6
MEASUREMENT ERROR (% of Reading)
–2
–4
–6
10193-123
TEST CIRCUIT
In Figure 32, the PM1 and PM0 pins are pulled up internally to VDD. Select the mode of operation by using a microcontroller to
programmatically change the pin values. See the Power Management section for details.
3.3V
+
10µF 0.1µF
+ +
4.7µF 0.22µF 4.7µF 0.22µF
24 26 5
VDD
AVDD
DVDD
3.3V 2 PM0
SS/HSA 39
3 PM1
10kΩ 1µF MOSI/SDA 38
3.3V
1kΩ 4 RESET MISO/HSD 37
2.2nF 7 IAP 1.5kΩ
SCLK/SCL 36
2.2nF 8 IAN
CF3/HSCLK 35
1kΩ 9 IBP
SAME AS CF2 34
IAP, IAN 12 IBN SAME AS
CF1 33
ADE7880 CF2
13 ICP
SAME AS IRQ1 32
IAP, IAN
14 ICN
1kΩ 2.2nF IRQ0 29
18 VN
REFIN/OUT 17
CL2 +
19 VCP 4.7µF 0.1µF
CLKOUT 28
1kΩ 2.2nF SAME AS
22 VBP
VCP 5MΩ 16.384MHz
AGND
DGND
SAME AS 23 VAP
VCP CLKIN 27
6 25 CL1
10193-007
Figure 32. Test Circuit
TERMINOLOGY
Measurement Error Maximum = max(Period0, Period1, Period2, Period3)
The error associated with the energy measurement made by the Minimum = min(Period0, Period1, Period2, Period3)
ADE7880 is defined by
Period0 Period1 Period 2 Period3
Measurement Error = Average =
4
Energy Registered by ADE 7880 True Energy
100% (1) The CF jitter is then computed as
True Energy
Maximum Minimum
Power Supply Rejection (PSR) CFJITTER 100% (2)
This quantifies the ADE7880 measurement error as a percen- Average
tage of reading when the power supplies are varied. For the ac Signal-to-Noise Ratio (SNR)
PSR measurement, a reading at nominal supplies (3.3 V) is SNR is the ratio of the rms value of the actual input signal to the
taken. A second reading is obtained with the same input signal rms sum of all other spectral components below 3.3 kHz, excluding
levels when an ac signal (120 mV rms at 100 Hz) is introduced harmonics and dc. The input signal contains only the fundamental
onto the supplies. Any error introduced by this ac signal is component. The spectral components are calculated over a 2 sec
expressed as a percentage of reading (see the Measurement window. The value for SNR is expressed in decibels.
Error definition).
Signal-to-Noise-and-Distortion (SINAD) Ratio
For the dc PSR measurement, a reading at nominal supplies SINAD is the ratio of the rms value of the actual input signal to the
(3.3 V) is taken. A second reading is obtained with the same rms sum of all other spectral components below 3.3 kHz,
input signal levels when the power supplies are varied ±10%. including harmonics but excluding dc. The input signal contains
Any error introduced is expressed as a percentage of the only the fundamental component. The spectral components are
reading. calculated over a 2 sec window. The value for SINAD is expressed
ADC Offset in decibels.
ADC offset refers to the dc offset associated with the analog Harmonic Power Measurement Error
inputs to the ADCs. It means that with the analog inputs To measure the error in the harmonic active and reactive power
connected to AGND, the ADCs still see a dc analog input calculations made by the ADE7880, the voltage channel is supplied
signal. The magnitude of the offset depends on the gain and with a signal comprising a fundamental and one harmonic
input range selection. The high-pass filter (HPF) removes the component with amplitudes equal to 250 mV. The current
offset from the current and voltage channels; therefore, the channel is supplied with a signal comprising a fundamental
power calculation remains unaffected by this offset. with amplitude of 50 mV and one harmonic component of the
Gain Error same index as the one in the voltage channel. The amplitude of
The gain error in the ADCs of the ADE7880 is defined as the the harmonic is varied from 250 mV, down to 250 μV, 2000 times
difference between the measured ADC output code (minus the lower than full scale.
offset) and the ideal output code (see the Current Channel ADC The error is defined by
section and the Voltage Channel ADC section). The difference
Measurement Error =
is expressed as a percentage of the ideal code.
Power Registered by ADE7880 True Power
CF Jitter 100% (3)
True Power
The period of pulses at one of the CF1, CF2, or CF3 pins is
continuously measured. The maximum, minimum, and average
values of four consecutive pulses are computed as follows:
POWER MANAGEMENT
The ADE7880 has four modes of operation, determined by the during PSM1 (see the Current Mean Absolute Value Calculation
state of the PM0 and PM1 pins (see Table 8). These pins provide section for more details on the xIMAV registers).
complete control of the ADE7880 operation and can easily be The 20-bit mean absolute value measurements done in PSM1,
connected to an external microprocessor I/O. The PM0 and although also available in PSM0, are different from the rms meas-
PM1 pins have internal pull-up resistors. See Table 10 and Table 11 urements of phase currents and voltages executed only in PSM0
for a list of actions that are recommended before and after setting and stored in the HxIRMS and HxVRMS 24-bit registers. See
a new power mode. the Current Mean Absolute Value Calculation section for details.
Table 8. Power Supply Modes If the ADE7880 is set in PSM1 mode after being in PSM0 mode,
Power Supply Modes PM1 PM0 the ADE7880 begins the mean absolute value calculations without
PSM0, Normal Power Mode 0 1 any delay. The xIMAV registers are accessible at any time; however,
PSM1, Reduced Power Mode 0 0 if the ADE7880 is set in PSM1 mode after being in PSM2 or
PSM2, Low Power Mode 1 0 PSM3 modes, the ADE7880 signals the start of the mean absolute
PSM3, Sleep Mode 1 1 value computations by triggering the IRQ1 pin low. The xIMAV
registers can be accessed only after this moment.
PSM0—NORMAL POWER MODE (ALL PARTS)
PSM2—LOW POWER MODE
In PSM0 mode, the ADE7880 is fully functional. For the ADE7880
to enter this mode, the PM0 pin is set to high, and the PM1 pin In the low power mode, PSM2, the ADE7880 compares all
is set to low. If the ADE7880 is in PSM1, PSM2, or PSM3 mode phase currents against a threshold for a period of 0.02 ×
and is switched into PSM0 mode, then all control registers take (LPLINE[4:0] + 1) seconds, independent of the line frequency.
the default values with the exception of the threshold register, LPLINE[4:0] are Bits[7:3] of the LPOILVL register (see Table 9).
LPOILVL, which is used in PSM2 mode, and the CONFIG2
Table 9. LPOILVL Register
register, both of which maintain their values.
Bit Mnemonic Default Description
The ADE7880 signals the end of the transition period by triggering [2:0] LPOIL[2:0] 111 Threshold is put at a value
the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in the corresponding to full scale
STATUS1 register to 1. This bit is 0 during the transition period multiplied by LPOIL/8
and becomes 1 when the transition is finished. The status bit is [7:3] LPLINE[4:0] 00000 The measurement period is
(LPLINE[4:0] + 1)/50 sec
cleared and the IRQ1 pin is set back to high by writing to the
STATUS1 register with the corresponding bit set to 1. Bit 15 The threshold is derived from Bits[2:0] (LPOIL[2:0]) of the
(RSTDONE) in the interrupt mask register does not have any LPOILVL register as LPOIL[2:0]/8 of full scale. Every time
functionality attached even if the IRQ1 pin goes low when Bit 15 one phase current becomes greater than the threshold, a
(RSTDONE) in the STATUS1 register is set to 1. This makes the counter is incremented. If every phase counter remains below
RSTDONE interrupt unmaskable. LPLINE[4:0] + 1 at the end of the measurement period, then
the IRQ0 pin is triggered low. If a single phase counter becomes
PSM1—REDUCED POWER MODE
greater or equal to LPLINE[4:0] + 1 at the end of the measurement
In the reduced power mode, PSM1, the ADE7880 measures the period, the IRQ1 pin is triggered low. Figure 33 illustrates how
mean absolute values (mav) of the 3-phase currents and stores the ADE7880 behaves in PSM2 mode when LPLINE[4:0] = 2
the results in the AIMAV, BIMAV, and CIMAV 20-bit registers. and LPOIL[2:0] = 3. The test period is three 50 Hz cycles (60 ms),
This mode is useful in missing neutral cases in which the voltage and the Phase A current rises above the LPOIL[2:0] threshold three
supply of the ADE7880 is provided by an external battery. The times. At the end of the test period, the IRQ1 pin is triggered low.
serial ports, I2C or SPI, are enabled in this mode; the active port
LPLINE[4:0] = 2
can be used to read the AIMAV, BIMAV, and CIMAV registers.
Do not read any of the other registers as their values are not LPOIL[2:0]
THRESHOLD
guaranteed in this mode. Similarly, the ADE7880 does not take a IA CURRENT
IRQ1
calibration process. The external microprocessor stores the gain
Figure 33. PSM2 Mode Triggering IRQ Pin for LPLINE[4:0] = 2 (50 Hz Systems)
values in connection with these measurements and uses them
Rev. C | Page 21 of 107
ADE7880 Data Sheet
+V p-p/2
+V p-p currents when there is no voltage input and the voltage supply
IxP
of the ADE7880 is provided by an external battery. If the IRQ0
pin is triggered low at the end of a measurement period, it signifies
IxP – IxN
–V p-p/2 all phase currents stayed below threshold and, therefore, there is
+V p-p/2
no current flowing through the system. At this point, the external
IxN
microprocessor sets the ADE7880 into sleep mode PSM3. If the
–V p-p
IRQ1 pin is triggered low at the end of the measurement period,
–V p-p/2 it signifies that at least one current input is above the defined
(a) threshold and current is flowing through the system, although
no voltage is present at the ADE7880 pins. This situation is often
IxP called missing neutral and is considered a tampering situation,
at which point the external microprocessor sets the ADE7880
PEAK DETECT CIRCUIT
TAMPER into PSM1 mode, measures the mean absolute values of phase
INDICATION
VREF
currents, and integrates the energy based on their values and the
nominal voltage.
10193-134
(b) It is recommended to use the ADE7880 in PSM2 mode when
Figure 34. PSM2 Low Power Mode Peak Detection Bits[2:0] (PGA1[2:0]) of the Gain register are equal to 1 or 2.
These bits represent the gain in the current channel data path. It
The PSM2 level threshold comparison works based on a peak
is not recommended to use the ADE7880 in PSM2 mode when
detection methodology. The peak detect circuit makes the
the PGA1[2:0] bits are equal to 4, 8, or 16.
comparison based on the positive terminal current channel
input, IAP, IBP, and ICP (see Figure 34). In case of differential PSM3—SLEEP MODE (ALL PARTS)
inputs being applied to the current channels, Figure 34 shows In sleep mode, the ADE7880 has most of its internal circuits
the differential antiphase signals at each of the current input turned off and the current consumption is at its lowest level.
terminals, IxP and IxN, and the net differential current, IxP − IxN. The I2C, HSDC, and SPI ports are not functional during this
The I2C or SPI port is not functional during this mode. The PSM2 mode, and the RESET, SCLK/SCL, MOSI/SDA, and SS/HSA pins
mode reduces the power consumption required to monitor the must be set high.
3.3V – 10%
0V
~26ms ~40ms
MICROPROCESSOR
MAKES THE
10193-009
MICROPROCESSOR POR TIMER ADE7880 RSTDONE CHOICE BETWEEN
SETS PM1 PIN TO 0; TURNED ON FULLY INTERRUPT I2C AND SPI
APPLY VDD TO CHIP POWERED UP TRIGGERED
The ADE7880 contains an on-chip power supply monitor that Immediately after entering PSM0 mode, all registers in the
supervises the power supply (VDD). At power-up, the device is ADE7880 are set to their default values, including the
inactive until VDD reaches 2.0 V ± 10%. When VDD crosses CONFIG2 and LPOILVL registers.
this threshold, the power supply monitor keeps the device in the The ADE7880 signals the end of the transition period by pulling
inactive state for an additional 26 ms to allow VDD to rise to the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in
3.3 V − 10%, the minimum recommended supply voltage.
the STATUS1 register to 1. This bit is cleared to 0 during the
The PM0 and PM1 pins have internal pull-up resistors, but it is transition period and is set to 1 when the transition ends.
necessary to set the PM1 pin to Logic 0, either through a micro- Writing the STATUS1 register with the RSTDONE bit set to 1
controller or by grounding the PM1 pin externally, before powering clears the status bit and returns the IRQ1 pin high. Because
up the chip. The PM0 pin can remain open as it is held high, due RSTDONE is an unmaskable interrupt, Bit 15 (RSTDONE) in
to the internal pull-up resistor. This ensures that the ADE7880 the STATUS1 register must be cancelled for the IRQ1 pin to
always powers up in PSM0 (normal) mode. The time from the chip return high. Wait until the IRQ1 pin goes low before accessing
being powered up completely to all functionality being enabled the STATUS1 register to test the state of the RSTDONE bit. At
is about 40 ms (see Figure 35). It is necessary to ensure that the this point, as a good programming practice, cancel all other
RESET pin is held high during the entire power-up procedure. status flags in the STATUS1 and STATUS0 registers by writing
If PSM0 mode is the only desired power mode, the PM1 pin can the corresponding bits with 1.
be tied to ground externally. When the ADE7880 enters PSM0 Initially, the DSP is in idle mode and, therefore, does not execute
mode, the I2C port is the active serial port. To use the SPI port, any instructions. This is the moment to initialize all registers in
toggle the SS/HSA pin three times from high to low. the ADE7880. See the Digital Signal Processor section for the
To lock I2C as the active serial port, set Bit 1 (I2C_LOCK) of the proper procedure to initialize all registers and start the metering.
CONFIG2 register to 1. From this moment, the device ignores If the supply voltage, VDD, falls lower than 2.0 V ± 10%, the
spurious toggling of the SS/HSA pin, and a switch to the SPI ADE7880 enters an inactive state, which means that no
port is no longer possible. measurements or computations are executed.
If SPI is the active serial port, any write to the CONFIG2 register If the RESET pin is held low while the IC powers up or if the
locks the port, and a switch to the I2C port is no longer possible. power-up sequence timing cannot be maintained as per
To use the I2C port, the ADE7880 must be powered down or the Figure 35, perform the following sequence of write operations
device must be reset by setting the RESET pin low. After the serial prior to starting the DSP (setting the RUN register to 0x01), to
port is locked, the serial port selection is maintained when the ensure that the modulators are reset properly.
device changes from one PSMx power mode to another.
1. 8-bit write: 0xAD is written at Address 0xE7FE.
2. 8-bit write: 0x14 is written at Address 0xE7E2.
3. Wait 200 μs.
4. 8-bit write: 0xAD is written at Address 0xE7FE.
5. 8-bit write: 0x04 is written at Address 0xE7E2.
THEORY OF OPERATION
DIFFERENTIAL INPUT
ANALOG INPUTS V1 + V2 = 500mV MAX PEAK
COMMON MODE
V1
The ADE7880 has seven analog inputs forming current and VCM = ±25mV MAX
voltage channels. The current channels consist of four pairs of +500mV VAP, VBP,
fully differential voltage inputs: IAP and IAN, IBP and IBN, ICP V1 OR VCP
and ICN, and INP and INN. These voltage input pairs have a VCM
maximum differential signal of ±0.5 V. VN
VCM
10193-011
–500mV
The maximum signal level on analog inputs for the IxP/IxN
pair is also ±0.5 V with respect to AGND. The maximum
Figure 38. PGA in Current and Voltage Channels
common-mode signal allowed on the inputs is ±25 mV. Figure 36
presents a schematic of the input for the current channels and ANALOG-TO-DIGITAL CONVERSION
their relation to the maximum common-mode voltage. The ADE7880 has seven sigma-delta (Σ-Δ) analog-to-digital
DIFFERENTIAL INPUT
V1 + V2 = 500mV MAX PEAK
converters (ADCs). In PSM0 mode, all ADCs are active. In
COMMON MODE PSM1 mode, only the ADCs that measure the Phase A, Phase B,
V1 + V2
VCM = ±25mV MAX
and Phase C currents are active. The ADCs that measure the
+500mV IAP, IBP, neutral current and the A, B, and C phase voltages are turned
V1 ICP, OR INP
off. In PSM2 and PSM3 modes, the ADCs are powered down to
VCM minimize power consumption.
VCM V2 IAN, IBN,
For simplicity, the block diagram in Figure 39 shows a first-order
10193-010
Gain register; thus, a different gain from the IA, IB, or IC inputs
is possible. See Table 43 for details on the Gain register.
.....10100101.....
10193-013
The voltage channel has three single-ended voltage inputs: VAP, 1-BIT DAC
VBP, and VCP. These single-ended voltage inputs have a maximum Figure 39. First-Order Σ-∆ ADC
input voltage of ±0.5 V with respect to VN. The maximum signal
level on analog inputs for VxP and VN is also ±0.5 V with respect A Σ-Δ modulator converts the input signal into a continuous
to AGND. The maximum common-mode signal allowed on the serial stream of 1s and 0s at a rate determined by the sampling
inputs is ±25 mV. Figure 37 presents a schematic of the voltage clock. In the ADE7880, the sampling clock is equal to 1.024 MHz
channels inputs and their relation to the maximum common- (CLKIN/16). The 1-bit DAC in the feedback loop is driven by
mode voltage. the serial data stream. The DAC output is subtracted from the
GAIN input signal. If the loop gain is high enough, the average value
SELECTION
of the DAC output (and, therefore, the bit stream) can approach
IxP, VyP that of the input signal level. For any given input value in a single
VIN K × VIN sampling interval, the data from the 1-bit ADC is virtually mean-
ingless. Only when a large number of samples are averaged is a
IxN, VN
meaningful result obtained. This averaging is carried out in the
NOTES second part of the ADC, the digital low-pass filter. By averaging
10193-012
1. x = A, B, C, N
y = A, B, C. a large number of bits from the modulator, the low-pass filter
Figure 37. Maximum Input Level, Voltage Channels, Gain = 1 can produce 24-bit data-words that are proportional to the
input signal level.
All inputs have a programmable gain with a possible gain
selection of 1, 2, 4, 8, or 16. To set the gain, use Bits[8:6]
(PGA3[2:0]) in the Gain register (see Table 43).
Figure 38 shows how the gain selection from the Gain register
works in both current and voltage channels.
10193-015
ANTIALIAS FILTER IMAGE
(RC) FREQUENCIES
DIGITAL FILTER
SIGNAL
SHAPED NOISE Figure 41. Aliasing Effects
SAMPLING
FREQUENCY
ADC Transfer Function
NOISE
All ADCs in the ADE7880 are designed to produce the same
24-bit signed output code for the same input signal level. With a
0 3.3 4 512 1024
FREQUENCY (kHz) full-scale input signal of 0.5 V and an internal reference of 1.2 V,
the ADC output code is nominally 5,326,737 (0x514791) and
HIGH RESOLUTION
OUTPUT FROM usually varies for each ADE7880 around this value. The code
DIGITAL LPF
SIGNAL from the ADC can vary between 0x800000 (−8,388,608) and
0x7FFFFF (+8,388,607); this is equivalent to an input signal
level of ±0.787 V. However, for specified performance, do not
NOISE exceed the nominal range of ±0.5 V; ADC performance is
guaranteed only for input signals lower than ±0.5 V.
10193-014
0V 0V
10193-016
–0.5V/GAIN 0xAEB86F =
–5,326,737
ANALOG INPUT RANGE
INWV WAVEFORM
VIN PGA2 ADC SAMPLE REGISTER
10193-017
HPF
IAN
10193-018
BITS[27:24] ARE BIT 23 IS A SIGN BIT
writing a corresponding twos complement number to the 24-bit EQUAL TO BIT 23
signed current waveform gain registers (AIGAIN, BIGAIN, Figure 44. 24-Bit xIGAIN Transmitted as 32-Bit Words
CIGAIN, and NIGAIN). For example, if 0x400000 is written to Current Channel HPF
those registers, the ADC output is scaled up by 50%. To scale
the input by −50%, write 0xC00000 to the registers. Equation 4 The ADC outputs can contain a dc offset. This offset can create
describes mathematically the function of the current waveform errors in power and rms calculations. High-pass filters (HPFs)
gain registers. are placed in the signal path of the phase and neutral currents
and of the phase voltages. If enabled, the HPF eliminates any dc
Current Waveform = offset on the current channel. All filters are implemented in the
Content of Current Gain Register DSP and, by default, they are all enabled: Bit 0 (HPFEN) of the
ADC Output × 1 + (4)
223 CONFIG3[7:0] register is set to 1. All filters are disabled by
setting Bit 0 (HPFEN) to 0.
Changing the content of the AIGAIN, BIGAIN, CIGAIN, or
INGAIN registers affects all calculations based on its current;
that is, it affects the corresponding phase active/reactive/
apparent energy and current rms calculation. In addition,
waveform samples scale accordingly.
Note that the serial ports of the ADE7880 work on 32-, 16-, or
8-bit words, and the DSP works on 28 bits. The 24-bit AIGAIN,
BIGAIN, CIGAIN, and NIGAIN registers are accessed as 32-bit
registers with the four most significant bits (MSBs) padded with
0s and sign extended to 28 bits. See Figure 44 for details.
Rev. C | Page 28 of 107
Data Sheet ADE7880
Current Channel Sampling allows for using a different current sensor to measure the neutral
The waveform samples of the current channel are taken at the current (for example a current transformer) from the current
output of HPF and stored in the 24-bit signed registers, IAWV, sensors used to measure the phase currents (for example di/dt
IBWV, ICWV, and INWV at a rate of 8 kSPS. All power and rms sensors). The digital integrators are managed by Bit 0 (INTEN) of
calculations remain uninterrupted during this process. Bit 17 the CONFIG register and by Bit 3 (ININTEN) of the CONFIG3
(DREADY) in the STATUS0 register is set when the IAWV, IBWV, register. Bit 0 (INTEN) of the CONFIG register manages the
ICWV, and INWV registers are available to be read using the I2C integrators in the phase current channels. Bit 3 (ININTEN) of the
or SPI serial port. Setting Bit 17 (DREADY) in the MASK0 CONFIG3 register manages the integrator in the neutral current
register enables an interrupt to be set when the DREADY flag is channel. When the INTEN bit is 0 (default), all integrators in the
set. See the Digital Signal Processor section for more details on phase current channels are disabled. When INTEN bit is 1, the
Bit DREADY. integrators in the phase currents data paths are enabled. When the
ININTEN bit is 0 (default), the integrator in the neutral current
As stated in the Current Waveform Gain Registers section, the
channel is disabled. When the ININTEN bit is 1, the integrator in
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words. the neutral current channel is enabled.
When the IAWV, IBWV, ICWV, and INWV 24-bit signed
registers are read from the ADE7880, they are transmitted sign Figure 47 and Figure 48 show the magnitude and phase
extended to 32 bits. See Figure 45 for details. response of the digital integrator.
31 24 23 22 0 Note that the integrator has a −20 dB/dec attenuation and
24-BIT SIGNED NUMBER approximately −90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response is a flat gain
10193-019
BITS[31:24] ARE BIT 23 IS A SIGN BIT over the frequency band of interest. However, the di/dt sensor
EQUAL TO BIT 23
has a 20 dB/dec gain associated with it and generates significant
Figure 45. 24-Bit IxWV Register Transmitted as 32-Bit Signed Word high frequency noise. At least a second order antialiasing filter
The ADE7880 contains a high speed data capture (HSDC) port is needed to avoid noise aliasing back in the band of interest
that is specially designed to provide fast access to the waveform when the ADC is sampling (see the Antialiasing Filter section).
sample registers. See the HSDC Interface section for more details. 50
MAGNITUDE (dB)
–50
10193-021
MAGNETIC FLUX DENSITY (di/dt) 0 500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
Figure 46. Principle of a di/dt Current Sensor
Figure 47. Combined Gain and Phase Response of the
The flux density of a magnetic field induced by a current is Digital Integrator
directly proportional to the magnitude of the current. The The DICOEFF 24-bit signed register is used in the digital
changes in the magnetic flux density passing through a conductor integrator algorithm. At power-up or after a reset, its value is
loop generate an electromotive force (EMF) between the two 0x000000. Before turning on the integrator, this register must be
ends of the loop. The EMF is a voltage signal that is propor- initialized with 0xFFF8000. DICOEFF is not used when the
tional to the di/dt of the current. The voltage output from the integrator is turned off and can remain at 0x000000 in that case.
di/dt current sensor is determined by the mutual inductance
between the current carrying conductor and the di/dt sensor.
Due to the di/dt sensor, the current signal needs to be filtered
before it can be used for power measurement. On each phase and
neutral current data path, there are built-in digital integrators to
recover the current signal from the di/dt sensor. The digital
integrators placed on the phase currents data paths are independent
of the digital integrator placed in the neutral current data path. This
Rev. C | Page 29 of 107
ADE7880 Data Sheet
–15
As stated in the Current Waveform Gain Registers section, the
MAGNITUDE (dB)
–20
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
Similar to the registers shown in Figure 44, the DICOEFF 24-bit
–25 signed register is accessed as a 32-bit register with four MSBs
padded with 0s and sign extended to 28 bits, which practically
–30
30 35 40 45 50 55 60 65 70 means it is transmitted equal to 0x0FFF8000.
FREQUENCY (Hz)
–89.96 When the digital integrator is switched off, the ADE7880 can
be used directly with a conventional current sensor, such as
PHASE (Degrees)
10193-022
30 35 40 45 50 55 60 65 70 Input VA in the voltage channel. The VB and VC channels
FREQUENCY (Hz)
have similar processing chains. The ADC outputs are signed
Figure 48. Combined Gain and Phase Response of the twos complement 24-bit words and are available at a rate of
Digital Integrator (30 Hz to 70 Hz) when DICOEFF is Set to 0x00000000
8 kSPS. With the specified full-scale analog input signal of
–15
±0.5 V, the ADC produces its maximum output code value.
MAGNITUDE (dB)
–20
Figure 50 shows a full-scale voltage signal being applied to the
differential inputs (VA and VN). The ADC output swings
–25 between −5,326,737 (0xAEB86F) and +5,326,737 (0x514791).
Note these are nominal values and every ADE7880 varies
–30
30 35 40 45 50 55 60 65 70 around these values.
FREQUENCY (Hz)
–80
PHASE (Degrees)
–82
–84
–86
10193-349
30 35 40 45 50 55 60 65 70
FREQUENCY (Hz)
TOTAL/FUNDAMENTAL
VIN PGA3 ADC ACTIVE AND REACTIVE
HPF
POWER CALCULATION
VN
VIN ZX DETECTION
LPF1
+0.5V/GAIN
0V 0x514791 = 0x514791 =
+5,326,737 +5,326,737
–0.5V/GAIN 0V 0V
ANALOG INPUT RANGE
10193-023
0xAEB86F = 0xAEB86F =
–5,326,737 –5,326,737
ZX
0V
ZX ZX ZX
IA, IB, IC VOLTAGE
10193-025
OR LPF1 OUTPUT OR
VA, VB, VC CURRENT 0V
SIGNAL
Figure 52. Zero-Crossing Detection on Voltage and Current Channels
10193-028
when the ADE7880 is connected in a 3-phase, 4-wire, three voltage ZX A ZX B ZX C
sensors configuration (Bits[5:4], CONSEL[1:0] in the ACCMODE Figure 55. Regular Succession of Phase A, Phase B, and Phase C
register, set to 00). In all other configurations, only two voltage
When the ANGLESEL[1:0] bits are set to 00, the default value,
sensors are used; therefore, it is not recommended to use the
the delays between voltages and currents on the same phase are
detection circuit. In these cases, use the time intervals between
measured. The delay between Phase A voltage and Phase A
phase voltages to analyze the phase sequence (see the Time
current is stored in the 16-bit unsigned ANGLE0 register (see
Interval Between Phases section for details).
Figure 56 for details). In a similar way, the delays between
Figure 54 presents the case in which Phase A voltage is not voltages and currents on Phase B and Phase C are stored in the
followed by Phase B voltage but by Phase C voltage. Every time ANGLE1 and ANGLE2 registers, respectively.
a negative-to-positive zero crossing occurs, Bit 19 (SEQERR) in
PHASE A
the STATUS1 register is set to 1 because such zero crossings on VOLTAGE
PHASE A
Phase C, Phase B, or Phase A cannot come after zero crossings CURRENT
10193-029
A, B, C PHASE ANGLE0
VOLTAGES AFTER
LPF1
Figure 56. Delay Between Phase A Voltage and Phase A Current Is
Stored in the ANGLE0 Register
ZX A ZX C ZX B When the ANGLESEL[1:0] bits are set to 01, the delays between
phase voltages are measured. The delay between Phase A voltage
and Phase C voltage is stored into the ANGLE0 register. The
BIT 19 (SEQERR) IN
STATUS1 REGISTER delay between Phase B voltage and Phase C voltage is stored in
the ANGLE1 register, and the delay between Phase A voltage
IRQ1 and Phase B voltage is stored in the ANGLE2 register (see
Figure 57 for details).
STATUS1[19] SET TO 1 STATUS1[19] CANCELLED
10193-027
BY A WRITE TO THE
STATUS1 REGISTER WITH When the ANGLESEL[1:0] bits are set to 10, the delays between
SEQERR BIT SET
phase currents are measured. Similar to delays between phase
Figure 54. SEQERR Bit Set to 1 When Phase A Voltage Is Followed by
voltages, the delay between Phase A and Phase C currents is
Phase C Voltage
stored into the ANGLE0 register, the delay between Phase B and
Once a phase sequence error is detected, the time measurement Phase C currents is stored in the ANGLE1 register, and the
between various phase voltages (see the Time Interval Between delay between Phase A and Phase B currents is stored into the
Phases section) can help to identify which phase to consider ANGLE2 register (see Figure 57 for details).
with another phase current in the computational data path.
Bits[9:8] (VTOIA[1:0]), Bits[11:10] (VTOIB[1:0]), and PHASE A PHASE B PHASE C
Period Measurement
The ADE7880 provides the period measurement of the line in
the voltage channel. The period of each phase voltage is SAGCYC[7:0] = 0x4
PHSTATUS[12] SET TO 1
for 60 Hz networks is approximately 4267 (256 kHz/60 Hz). The BECAUSE PHASE A
VOLTAGE WAS BELOW
length of the registers enables the measurement of line frequencies VSPHASE[0] =
SAGLVL FOR SAGCYC
HALF LINE CYCLES
as low as 3.9 Hz (256 kHz/216). The period registers are stable at PHSTATUS[12]
PHSTATUS[12] CLEARED
TO 0 BECAUSE PHASE A
±1 LSB when the line is established and the measurement does VOLTAGE WAS ABOVE
SAGLVL FOR SAGCYC
not change. VSPHASE[1] =
PHSTATUS[13]
HALF LINE CYCLES
10193-031
The following equations can be used to compute the line period PHSTATUS[13] SET TO 1
and frequency using the period registers: Figure 58. SAG Detection
10193-033
2. When a sag event happens, the IRQ1 interrupt pin goes PEAK DETECTED
ON PHASE B
low and Bit 16 (SAG) in the STATUS1 is set to 1.
Figure 60. Composition of IPEAK[31:0] and VPEAK[31:0] Registers
3. The STATUS1 register is read with Bit 16 (SAG) set to 1.
4. The PHSTATUS register is read, identifying on which PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF FIRST
phase or phases a sag event happened. PEAKCYC PERIOD
5. The STATUS1 register is written with Bit 16 (SAG) set to 1. END OF FIRST
PEAKCYC = 16 PERIOD
Immediately, the sag bit is erased.
END OF SECOND
Sag Level Set PEAKCYC = 16 PERIOD
31 24 23 0
0000 0000 24-BIT NUMBER
10193-034
MSBs padded with 0s. See Figure 59 for details. BIT 25 SECOND PEAKCYC PERIOD PEAKCYC PERIOD
OF IPEAK
Peak Detection
Figure 61. Peak Level Detection
The ADE7880 records the maximum absolute values reached by
the voltage and current channels over a certain number of half- Figure 61 shows how the ADE7880 records the peak value on the
line cycles and stores them into the less significant 24 bits of the current channel when measurements on Phase A and Phase B are
VPEAK and IPEAK 32-bit registers. enabled (Bit PEAKSEL[2:0] in the MMODE register are 011).
PEAKCYC is set to 16, meaning that the peak measurement
The PEAKCYC register contains the number of half-line cycles cycle is four line periods. The maximum absolute value of Phase A
used as a time base for the measurement. The circuit uses the is the greatest during the first four line periods (PEAKCYC = 16),
zero-crossing points identified by the zero-crossing detection so the maximum absolute value is written into the less signifi-
circuit. Bits[4:2] (PEAKSEL[2:0]) in the MMODE register select cant 24 bits of the IPEAK register, and Bit 24 (IPPHASE[0]) of
the phases upon which the peak measurement is performed. Bit 2 the IPEAK register is set to 1 at the end of the period. This bit
selects Phase A, Bit 3 selects Phase B, and Bit 4 selects Phase C. remains at 1 for the duration of the second PEAKCYC period of
Selecting more than one phase to monitor the peak values four line cycles. The maximum absolute value of Phase B is the
decreases proportionally the measurement period indicated in greatest during the second PEAKCYC period; therefore, the
the PEAKCYC register because zero crossings from more maximum absolute value is written into the less significant
phases are involved in the process. When a new peak value is 24 bits of the IPEAK register, and Bit 25 (IPPHASE[1]) in the
determined, one of Bits[26:24] (IPPHASE[2:0] or VPPHASE[2:0]) IPEAK register is set to 1 at the end of the period.
in the IPEAK and VPEAK registers is set to 1, identifying the
phase that triggered the peak detection event. For example, if a At the end of the peak detection period in the current channel,
peak value has been identified on Phase A current, Bit 24 Bit 23 (PKI) in the STATUS1 register is set to 1. If Bit 23 (PKI)
(IPPHASE[0]) in the IPEAK register is set to 1. If next time a in the MASK1 register is set, the IRQ1 interrupt pin is driven low
new peak value is measured on Phase B, Bit 24 (IPPHASE[0]) at the end of the PEAKCYC period, and Status Bit 23 (PKI) in
of the IPEAK register is cleared to 0, and Bit 25 (IPPHASE[1]) the STATUS1 register is set to 1. In a similar way, at the end of
of the IPEAK register is set to 1. Figure 60 shows the the peak detection period in the voltage channel, Bit 24 (PKV) in
composition of the IPEAK and VPEAK registers. the STATUS1 register is set to 1. If Bit 24 (PKV) in the MASK1
register is set, the IRQ1 interrupt pin is driven low at the end of
PEAKCYC period and Status Bit 24 (PKV) in the STATUS1
Rev. C | Page 35 of 107
ADE7880 Data Sheet
register is set to 1. To find the phase that triggered the interrupt, Whenever the absolute instantaneous value of the voltage goes
one of either the IPEAK or VPEAK registers is read immediately above the threshold from the OVLVL register, Bit 18 (OV) in
after reading the STATUS1 register. Next, the status bits are the STATUS1 register and Bit 9 (OVPHASE[0]) in the PHSTATUS
cleared, and the IRQ1 pin is set to high by writing to the register are set to 1. Bit 18 (OV) of the STATUS1 register and
STATUS1 register with the status bit set to 1. Bit 9 (OVPHASE[0]) in the PHSTATUS register are cancelled
when the STATUS1 register is written with Bit 18 (OV) set to 1.
Note that the internal zero-crossing counter is always active. By
setting Bits[4:2] (PEAKSEL[2:0]) in the MMODE register, the The recommended procedure to manage overvoltage events is
first peak detection result is, therefore, not executed across a full the following:
PEAKCYC period. Writing to the PEAKCYC register when the 1. Enable OV interrupts in the MASK1 register by setting
PEAKSEL[2:0] bits are set resets the zero-crossing counter, Bit 18 (OV) to 1.
thereby ensuring that the first peak detection result is obtained 2. When an overvoltage event happens, the IRQ1 interrupt
across a full PEAKCYC period. pin goes low.
Overvoltage and Overcurrent Detection 3. The STATUS1 register is read with Bit 18 (OV) set to 1.
The ADE7880 detects when the instantaneous absolute value 4. The PHSTATUS register is read, identifying on which
measured on the voltage and current channels becomes greater phase or phases an overvoltage event happened.
than the thresholds set in the OVLVL and OILVL 24-bit 5. The STATUS1 register is written with Bit 18 (OV) set to 1.
unsigned registers. If Bit 18 (OV) in the MASK1 register is set, In this moment, Bit OV is erased and also all Bits[11:9]
the IRQ1 interrupt pin is driven low in case of an overvoltage (OVPHASE[2:0]) of the PHSTATUS register.
event. There are two status flags set when the IRQ1 interrupt In case of an overcurrent event, if Bit 17 (OI) in the MASK1 register
pin is driven low: Bit 18 (OV) in the STATUS1 register and one is set, the IRQ1 interrupt pin is driven low. Immediately, Bit 17
of Bits[11:9] (OVPHASE[2:0]) in the PHSTATUS register to (OI) in the STATUS1 register and one of Bits[5:3] (OIPHASE[2:0])
identify the phase that generated the overvoltage. The Status in the PHSTATUS register, which identify the phase that generated
Bit 18 (OV) in the STATUS1 register and all Bits[11:9] the interrupt, are set. To find the phase that triggered the interrupt,
(OVPHASE[2:0]) in the PHSTATUS register are cleared, and the PHSTATUS register is read immediately after reading the
the IRQ1 pin is set to high by writing to the STATUS1 register STATUS1 register. Next, Status Bit 17 (OI) in the STATUS1
with the status bit set to 1. Figure 62 presents overvoltage register and Bits[5:3] (OIPHASE[2:0]) in the PHSTATUS
detection in the Phase A voltage. register are cleared and the IRQ1 pin is set to high by writing
PHASE A OVERVOLTAGE to the STATUS1 register with the status bit set to 1. The process
VOLTAGE CHANNEL DETECTED
is similar with overvoltage detection.
OVLVL[23:0]
Overvoltage and Overcurrent Level Set
The content of the overvoltage (OVLVL), and overcurrent,
(OILVL) 24-bit unsigned registers is compared to the absolute
value of the voltage and current channels. The maximum value of
these registers is the maximum value of the HPF outputs:
+5,326,737 (0x514791). When the OVLVL or OILVL register is
equal to this value, the overvoltage or overcurrent conditions
are never detected. Writing 0x0 to these registers signifies the
overvoltage or overcurrent conditions are continuously detected,
BIT 18 (OV) OF
STATUS1 and the corresponding interrupts are permanently triggered.
STATUS1[18] AND
As stated in the Current Waveform Gain Registers section, the
PHSTATUS[9] serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
CANCELLED BY A
WRITE OF STATUS1 Similar to the register presented in Figure 59, OILVL and
WITH OV BIT SET.
BIT 9 (OVPHASE)
OVLVL registers are accessed as 32-bit registers with the eight
10193-035
10193-036
ISUM[27:0]
I SUM (t ) = × I FS BIT 27 IS A SIGN BIT
ADC MAX Figure 63. The ISUM[27:0] Register is Transmitted As a 32-Bit Word
where: Similar to the registers presented in Figure 44, the ISUMLVL
ADCMAX = 5,326,737, the ADC output when the input is at register is accessed as a 32-bit register with four most significant
full scale. bits padded with 0s and sign extended to 28 bits.
IFS is the full-scale ADC phase current.
PHASE COMPENSATION
Note that the ADE7880 also computes the rms of ISUM and
stores it into NIRMS register when Bit 2 (INSEL) in CONFIG3 As described in the Current Channel ADC and Voltage Channel
register is set to 1 (see Current RMS Calculation section for ADC sections, the data path for both current and voltages is the
details). same. The phase error between current and voltage signals
introduced by the ADE7880 is negligible. However, the ADE7880
The ADE7880 computes the difference between the absolute must work with transducers that may have inherent phase
values of ISUM and the neutral current from the INWV errors. For example, a current transformer (CT) with a phase
register, take its absolute value and compare it against the error of 0.1° to 3° is not uncommon. These phase errors can
ISUMLVL threshold. vary from part to part, and they must be corrected to perform
If accurate power calculations.
ISUM − INWV ≤ ISUMLVL , The errors associated with phase mismatch are particularly
noticeable at low power factors. The ADE7880 provides a
then it is assumed that the neutral current is equal to the sum means of digitally calibrating these small phase errors. The
of the phase currents, and the system functions correctly. ADE7880 allows a small time delay or time advance to be
If introduced into the signal processing chain to compensate for
the small phase errors.
ISUM − INWV > ISUMLVL ,
The phase calibration registers (APHCAL, BPHCAL, and
a tamper situation may have occurred, and Bit 20 (MISMTCH) CPHCAL) are 10-bit registers that can vary the time advance
in the STATUS1 register is set to 1. An interrupt attached to the in the voltage channel signal path from −374.0 µs to +61.5 μs.
flag can be enabled by setting Bit 20 (MISMTCH) in the MASK1 Negative values written to the PHCAL registers represent a time
register. If enabled, the IRQ1 pin is set low when Status Bit advance whereas positive values represent a time delay. One LSB
MISMTCH is set to 1. The status bit is cleared and the IRQ1 pin is equivalent to 0.976 µs of time delay or time advance (clock
is set back to high by writing to the STATUS1 register with Bit 20 rate of 1.024 MHz). With a line frequency of 60 Hz, this gives
(MISMTCH) set to 1. a phase resolution of 0.0211° (360° × 60 Hz/1.024 MHz) at the
fundamental. This corresponds to a total correction range of
If ISUM − INWV ≤ ISUMLVL , then MISMTCH = 0
−8.079° to +1.329° at 60 Hz. At 50 Hz, the correction range is
If ISUM − INWV > ISUMLVL , then MISMTCH = 1 −6.732° to +1.107° and the resolution is 0.0176° (360° × 50 Hz/
1.024 MHz).
ISUMLVL, the positive threshold used in the process, is a 24-bit
signed register. Because it is used in a comparison with an absolute
Rev. C | Page 37 of 107
ADE7880 Data Sheet
Given a phase error of x degrees, measured using the phase current transducer (equivalent of 55.5 μs for 50 Hz systems). To
voltage as the reference, the corresponding LSBs are computed cancel the lead (1°) in the current channel of Phase A, a phase
dividing x by the phase resolution (0.0211°/LSB for 60 Hz and lead must be introduced into the corresponding voltage channel.
0.0176°/LSB for 50 Hz). Results between −383 and +63 only are Using Equation 8, APHCAL is 57 least significant bits, rounded
acceptable; numbers outside this range are not accepted. If the up from 56.8. The phase lead is achieved by introducing a time
current leads the voltage, the result is negative and the absolute delay of 55.73 μs into the Phase A current.
value is written into the PHCAL registers. If the current lags the As stated in the Current Waveform Gain Registers section, the
voltage, the result is positive and 512 is added to the result serial ports of the ADE7880 work on 32-, 16-, or 8-bit words. As
before writing it into xPHCAL. shown in Figure 64, APHCAL, BPHCAL, and CPHCAL 10-bit
APHCAL, BPHCAL, or CPHCAL registers are accessed as 16-bit registers with the six MSBs
x padded with 0s.
,x 0
10193-037
15 10 9 0
phase _ resolution
= (9) 0000 00 xPHCAL
x
512, x 0 Figure 64. xPHCAL Registers Communicated As 16-Bit Registers
phase _ resolution
IAP
IA PGA1 ADC
IAN
PHASE
CALIBRATION
APHCAL = 57
VAP
VA PGA3 ADC
VN
1°
IA IA
PHASE COMPENSATION
ACHIEVED DELAYING
VA IA BY 56µs
VA
10193-038
50Hz
AL C +25°C
Y PICpm/° pp LLY
m/°
T 0p C multiple temperatures.
+2 B
The ADE7880 use the internal voltage reference when Bit 0
A C
–40°C +85°C
(EXTREFEN) in the CONFIG2 register is cleared to 0 (the default
value); the external voltage reference is used when the bit is set to 1.
Set the CONFIG2 register during the PSM0 mode; its value is
10193-165
TEMPERATURE (°C)
maintained during the PSM1, PSM2, and PSM3 power modes.
Figure 66. Internal Voltage Reference Temperature Drift DIGITAL SIGNAL PROCESSOR
Figure 66 shows that independent consideration of two regions The ADE7880 contains a fixed function digital signal processor
is necessary for accurate analysis of the drift over temperature, (DSP) that computes all powers and rms values. It contains
as follows: program memory ROM and data memory RAM.
Considering the region between Point A and Point B, the The program used for the power and rms computations is stored
reference value increases with increase in temperature; in the program memory ROM and the processor executes it every
thus, the curve has a positive slope from A to B. This 8 kHz. The end of the computations is signaled by setting Bit 17
results in a positive temperature coefficient in this region. (DREADY) to 1 in the STATUS0 register. An interrupt attached
Considering the region between Point B and Point C, the to this flag can be enabled by setting Bit 17 (DREADY) in the
slope of the curve is negative because the voltage reference MASK0 register. If enabled, the IRQ0 pin is set low and Status
decreases with an increase in temperature; thus, this region Bit DREADY is set to 1 at the end of the computations. The status
of the curve has a negative temperature coefficient. bit is cleared and the IRQ0 pin is set to high by writing to the
STATUS0 register with Bit 17 (DREADY) set to 1.
The general relationship between the absolute value of the
voltage reference at a particular endpoint temperature and the The registers used by the DSP are located in the data memory
temperature coefficient for that region of the curve is explained RAM, at addresses between 0x4380 and 0x43BE. The width of
by the following two equations: this memory is 28 bits. A two-stage pipeline is used when write
operations to the data memory RAM are executed. This means
40C 25C
VREF (−40°C) = VREF (+25°C) × 1 c two things: when only one register needs to be initialized, write
106 it two more times to ensure the value has been written into RAM.
85C 25C When two or more registers need to be initialized, write the last
VREF (85°C) = VREF (25°C) × 1 h register in the queue two more times to ensure the value is
10 6
written into RAM.
where αc and αh are cold and hot temperature coefficients,
As explained in the Power-Up Procedure section, at power-up
respectively, calculated by:
or after a hardware or software reset, the DSP is in idle mode.
VREF ( 40C) VREF ( 25C) No instruction is executed. All the registers located in the data
VREF ( 25C) memory RAM are initialized at 0, their default values and they
c
40C 25C
× 106 ppm/°C
can be read/written without any restriction. The Run register,
used to start and stop the DSP, is cleared to 0x0000. The Run
VREF (85C) VREF (25C) register needs to be written with 0x0001 for the DSP to start
VREF (25C) code execution. It is recommended to first initialize all ADE7880
h × 106 ppm/°C
85C 25C registers located in the data memory RAM with their desired
values. Next, write the last register in the queue two additional
To find the typical, maximum, and minimum temperature
times to flush the pipeline and then write the Run register with
coefficients as listed in the Specifications section, data based on
the end-point method is collected on ICs spread out over
Rev. C | Page 39 of 107
ADE7880 Data Sheet
0x0001. In this way, the DSP starts the computations from a 7. Enable the data memory RAM protection by writing 0xAD
desired configuration. to an internal 8-bit register located at Address 0xE7FE
To protect the integrity of the data stored in the data memory RAM followed by a write of 0x80 to an internal 8-bit register
of the DSP (between Address 0x4380 and Address 0x43BE), a write located at Address 0xE7E3.
protection mechanism is available. By default, the protection is 8. Read back all data memory RAM registers to ensure that
disabled and registers placed between 0x4380 and 0x43BE can they initialized with the desired values. In the unlikely case
be written without restriction. When the protection is enabled, that one or more registers does not initialize correctly, disable
no writes to these registers are allowed. Registers can be always the protection by writing 0xAD to an internal 8-bit register
read, without restriction, independent of the write protection located at Address 0xE7FE, followed by a write of 0x00 to an
state. To enable the protection, write 0xAD to an internal 8-bit internal 8-bit register located at Address 0xE7E3. Reinitialize
register located at Address 0xE7FE, followed by a write of 0x80 the registers, and write the last register in the queue three
to an internal 8-bit register located at Address 0xE7E3. To disable times. Enable the write protection by writing 0xAD to an
the protection, write 0xAD to an internal 8-bit register located internal 8-bit register located at Address 0xE7FE, followed
at Address 0xE7FE, followed by a write of 0x00 to an internal 8-bit by a write of 0x80 to an internal 8-bit register located at
register located at Address 0xE7E3. It is recommended to enable Address 0xE7E3.
the write protection before starting the DSP. If any data memory 9. Start the DSP by setting Run = 1.
RAM based register needs to be changed, simply disable the 10. Read the energy registers xWATTHR, xVAHR, xFWATTHR,
protection, change the value and then enable back the protection. and xFVARHR to erase their content and start energy
There is no need to stop the DSP in order to change these registers. accumulation from a known state.
11. Enable the CF1, CF2 and CF3 frequency converter outputs
To disable the protection, write 0xAD to an internal 8-bit register by clearing bits 9, 10 and 11 (CF1DIS, CF2DIS, and
located at Address 0xE7FE, followed by a write of 0x00 to an CF3DIS) to 0 in CFMODE register.
internal 8-bit register located at Address 0xE7E3.
There is no obvious reason to stop the DSP if the ADE7880 is
Use the following procedure to initialize the ADE7880 registers
maintained in PSM0 normal mode. All ADE7880 registers,
at power-up:
including ones located in the data memory RAM, can be
1. Select the PGA gains in the phase currents, voltages, and modified without stopping the DSP. However, to stop the DSP,
neutral current channels: Bits [2:0] (PGA1), Bits [5:3] write 0x0000 into the Run register. To restart the DSP, follow
(PGA2) and Bits [8:6] (PGA3) in the Gain register. one of the following procedures:
2. If Rogowski coils are used, enable the digital integrators in
• If the ADE7880 registers located in the data memory RAM
the phase and neutral currents: Bit 0 (INTEN) set to 1 in
have not been modified, write 0x0001 into the Run register to
CONFIG register. Initialize DICOEFF register to 0xFF8000
start the DSP.
before setting the INTEN bit in the CONFIG register.
3. If fn is between 55 Hz and 66 Hz, set Bit 14 (SELFREQ) in • If the ADE7880 registers located in the data memory RAM
COMPMODE register. have to be modified, first execute a software or a hardware
4. Initialize all the other data memory RAM registers. Write reset, initialize all ADE7880 registers at desired values, enable
the last register in the queue three times to ensure that its the write protection and then write 0x0001 into the Run
value is written into the RAM. register to start the DSP.
5. Initialize WTHR, VARTHR, VATHR, VLEVEL and As mentioned in the Power Management section, when the
VNOM registers based on Equation 26, Equation 37, ADE7880 switch out of PSM0 power mode, it is recommended to
Equation 44, Equation 22, and Equation 42, respectively. stop the DSP by writing 0x0000 into the Run register (see Table 10
6. Initialize CF1DEN, CF2DEN, and CF3DEN based on and Table 11 for the recommended actions when changing
Equation 49. power modes).
10193-039
signal to be 99.5% settled. 0000 0000 24-BIT NUMBER
Figure 67. 24-Bit AIRMS, BIRMS, CIRMS and NIRMS Registers Transmitted as
32-Bit Words
xIRMSOS[23:0]
27
0x514791 =
5,326,737
0V
10193-040
0xAEB86F =
–5,326,737
exist in the rms calculation due to input noises that are integrated
LSB
209500
in the dc component of i2(t). The current rms offset register is 209000
multiplied by 128 and added to the squared current rms before the
208500
square root is executed. Assuming that the maximum value from
208000
the current rms calculation is 3,766,572 with full-scale ac inputs
(50 Hz), one LSB of the current rms offset represents 0.00045% 207500
207000
3767 2 + 128 / 3767 − 1 × 100
10193-042
45 50 55 60 65
FREQUENCY (Hz)
This section presents the second approach to estimate the rms As stated in the Current Waveform Gain Registers section, the
values of all phase currents using the mean absolute value (mav) serial ports of the ADE7880 work on 32-, 16-, or 8-bit words. As
method. This approach is used in PSM1 mode, to allow energy presented in Figure 71, the AIMAV, BIMAV, and CIMAV 20-bit
accumulation based on current rms values when the missing unsigned registers are accessed as 32-bit registers with the 12 MSBs
neutral case demonstrates to be a tamper attack. This data path padded with 0s.
31 20 19 0
10193-043
is active also in PSM0 mode to allow for its gain calibration.
0000 0000 0000 20-BIT UNSIGNED NUMBER
The gain is used in the external microprocessor during PSM1
mode. The mav value of the neutral current is not computed Figure 71. xIMAV Registers Transmitted as 32-Bit Registers
using this method. Figure 69 shows the details of the signal Current MAV Gain and Offset Compensation
processing chain for the mav calculation on one of the phases
The current rms values stored in the AIMAV, BIMAV, and CIMAV
of the current channel.
registers can be calibrated using gain and offset coefficients
10193-041
CURRENT SIGNAL
COMING FROM ADC
|X| xIMAV[23:0] corresponding to each phase. Calculate the gains in PSM0 mode
HPF LPF
by supplying the ADE7880 with nominal currents. The offsets
Figure 69. Current MAV Signal Processing for PSM1 Mode can be estimated by supplying the ADE7880 with low currents,
The current channel mav value is processed from the samples usually equal to the minimum value at which the accuracy is
used in the current channel waveform sampling mode. The required. Every time the external microcontroller reads the
samples are passed through a high-pass filter to eliminate the AIMAV, BIMAV, and CIMAV registers, it uses these coefficients
eventual dc offsets introduced by the ADCs and the absolute stored in its memory to correct them.
values are computed. The outputs of this block are then filtered
to obtain the average. The current mav values are unsigned 20-bit
values and they are stored in the AIMAV, BIMAV, and CIMAV
registers. The update rate of this mav measurement is 8 kHz.
27
VOLTAGE SIGNAL
FROM HPF x2 xVRMS[23:0]
LPF
0x14791 =
+5,326,737
0V
10193-044
0xAEB86F =
–5,326,737
ground of the system, and Phase A and Phase C voltages are (18)
measured relative to it. This configuration is chosen using The average power over an integral number of line cycles (n) is
CONSEL bits equal to 01 in ACCMODE register (see Table 15 given by the equation in Equation 19.
for all configurations where the ADE7880 may be used). In this
1 nT
situation, all Phase B active, reactive, and apparent powers are 0. P=
nT
pt dt Vk I k cos(φk – γk) (19)
0 k 1
In this configuration, the ADE7880 computes the rms value of the
line voltage between Phase A and Phase C and stores the result where:
into BVRMS register. BVGAIN and BVRMSOS registers may be T is the line cycle period.
used to calibrate BVRMS register computed in this configuration. P is referred to as the total active or total real power.
The apparent power computation, in 3-wire and 4-wire delta Note that the total active power is equal to the dc component of
configurations, will be incorrect, because the line to line the instantaneous power signal p(t) in Equation 18, that is,
voltages are treated as phase voltages by the IC. To get the
equivalent wye-configuration apparent power, a scaling factor
Vk I k cos(φk – γk)
k 1
needs to be applied. Refer to the Three Phase Configurations
This is the equation used to calculate the total active power in the
section of the AN-639 Application Note, Analog Devices Energy
ADE7880 for each phase. The equation of fundamental active
(ADE) Products: Frequently Asked Questions (FAQ), for details.
power is obtained from Equation 18 with k = 1, as follows:
ACTIVE POWER CALCULATION FP = V1I1 cos(φ1 – γ1) (20)
The ADE7880 computes the total active power on every phase.
Total active power considers in its calculation all fundamental
and harmonic components of the voltages and currents. In
addition, the ADE7880 computes the fundamental active power,
the power determined only by the fundamental components of
the voltages and currents.
MAGNITUDE (dB)
INSTANTANEOUS –10
ACTIVE POWER
SIGNAL: V rms × I rms
–20
0x000 0000
–25
10193-172
0.1 1 3 10
10193-046
Figure 74. Frequency Response of the LPF Used to Filter Instantaneous Power
Figure 73. Active Power Calculation in Each Phase When the LPFSEL Bit of CONFIG3 is 0 (Default)
Because LPF2 does not have an ideal brick wall frequency
response, the active power signal has some ripple due to the
instantaneous power signal. This ripple is sinusoidal and has a
0
frequency equal to twice the line frequency. Because the ripple
is sinusoidal in nature, it is removed when the active power
signal is integrated over time to calculate the energy. Bit 1 –10
MAGNITUDE (dB)
∞ Vk I 1 Figure 75. Frequency Response of the LPF Used to Filter Instantaneous Power
xWATT = ∑ × k × cos(φk – γk) × PMAX × 4 (21) in Each Phase when the LPFSEL Bit of CONFIG3 is 1
k =1 VFS I FS 2
IA APGAIN AWATTOS
HPF LPSEL BIT
CONFIG3[1]
HPFEN BIT
APHCAL CONFIG3[0] INSTANTANEOUS
AVGAIN PHASE A
LPF ACTIVE POWER
VA
: AWATT
HPF
10193-045
As stated in the Current Waveform Gain Registers section, the Interrupts attached to Bits[8:6] (REVAPC, REVAPB, and
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words REVAPA, respectively) in the STATUS0 register can be enabled
and the DSP works on 28 bits. Similar to registers presented in by setting Bits[8:6] in the MASK0 register. If enabled, the IRQ0
Figure 44, the AWATTOS, BWATTOS, CWATTOS, AFWATTOS, pin is set low, and the status bit is set to 1 whenever a change of
BFWATTOS, and CFWATTOS 24-bit signed registers are accessed sign occurs. To find the phase that triggered the interrupt, the
as 32-bit registers with the four MSBs padded with 0s and sign PHSIGN register is read immediately after reading the STATUS0
extended to 28 bits. register. Next, the status bit is cleared and the IRQ0 pin is returned
to high by writing to the STATUS0 register with the corresponding
Sign of Active Power Calculation
bit set to 1.
The average active power is a signed calculation. If the phase
difference between the current and voltage waveform is Active Energy Calculation
more than 90°, the average power becomes negative. Negative As previously stated, power is defined as the rate of energy flow.
power indicates that energy is being injected back on the grid. This relationship can be expressed mathematically as
The ADE7880 has sign detection circuitry for active power dEnergy
calculations. It can monitor the total active powers or the Power (24)
dt
fundamental active powers. As described in the Active Energy
Calculation section, the active energy accumulation is performed Conversely, energy is given as the integral of power, as follows:
in two stages. Every time a sign change is detected in the energy Energy p t dt (25)
accumulation at the end of the first stage, that is, after the energy
accumulated into the internal accumulator reaches the WTHR
register threshold, a dedicated interrupt is triggered. The sign of
each phase active power can be read in the PHSIGN register.
34 27 26 0
10193-049
WTHR 0
STAGE
1 PULSE = 1LSB OF WATTHR[31:0] Setting Bits[1:0] in the MASK0 register enable the FAEHF and
Figure 78. Active Power Accumulation Inside the DSP AEHF interrupts, respectively. If enabled, the IRQ0 pin is set
Figure 78 explains this process. The threshold is formed by low and the status bit is set to 1 whenever one of the energy
concatenating the WTHR 8-bit unsigned register to 27 bits registers, xWATTHR (for the AEHF interrupt) or xFWATTHR
equal to 0. It is introduced by the user and is common for total (for the FAEHF interrupt), become half full. The status bit is
and fundamental active powers on all phases. Its value depends cleared and the IRQ0 pin is set to logic high by writing to the
on how much energy is assigned to one LSB of watt-hour regis- STATUS0 register with the corresponding bit set to 1.
ters. Supposing a derivative of Wh [10n Wh], n as an integer, is Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a
desired as one LSB of the xWATTHR register, WTHR is read-with-reset for all watt-hour accumulation registers, that is,
computed using the following equation: the registers are reset to 0 after a read operation.
PMAX f S 3600 10n Integration Time Under Steady Load
WTHR (26)
U FS I FS 227 The discrete time sample period (T) for the accumulation register
where: is 976.5625 ns (1.024MHz frequency). With full-scale sinusoidal
PMAX = 27,059,678 = 0x19CE5DE as the instantaneous power signals on the analog inputs and the watt gain registers set to
computed when the ADC inputs are at full scale. 0x00000, the average word value from each LPF2 is PMAX =
fS = 1.024 MHz, the frequency at which every instantaneous 27,059,678 = 0x19CE5DE. If the WTHR register threshold is set
power computed by the DSP at 8 kHz is accumulated. at 3, its minimum recommended value, the first stage accumulator
UFS, IFS are the rms values of phase voltages and currents when generates a pulse that is added to watt-hour registers every
the ADC inputs are at full scale. 3 227
14.531 sec
WTHR register is an 8-bit unsigned number, so its maximum PMAX 1.024 106
value is 28 − 1. Its default value is 0x3. Avoid values lower than The maximum value that can be stored in the watt-hour
3, that is, 2 or 1, and never use 0 as the threshold must be a non- accumulation register before it overflows is 231 − 1 or
zero value. 0x7FFFFFFF. The integration time is calculated as
This discrete time accumulation or summation is equivalent to Time = 0x7FFF,FFFF × 14.531 μs = 8 hr 40 min 6 sec (28)
integration in continuous time following the description in
Equation 27.
Energy p t dt Lim p nT T (27)
T 0 n 0
Rev. C | Page 49 of 107
ADE7880 Data Sheet
Active Energy Accumulation Modes over an integer number of line cycles is that the sinusoidal compo-
The active power is accumulated in each watt-hour nent in the active energy is reduced to 0. This eliminates any
accumulation 32-bit register (AWATTHR, BWATTHR, ripple in the energy calculation and allows the energy to be
CWATTHR, AFWATTHR, BFWATTHR, and CFWATTHR) accumulated accurately over a shorter time. By using the line
according to the configuration of Bit 5 and Bit 4 (CONSEL bits) cycle energy accumulation mode, the energy calibration can be
in the ACCMODE register. The various configurations are greatly simplified, and the time required to calibrate the meter
described in Table 14. can be significantly reduced. In line cycle energy accumulation
mode, the ADE7880 transfers the active energy accumulated in the
Table 14. Inputs to Watt-Hour Accumulation Registers 32-bit internal accumulation registers into the xWATHHR or
CONSEL AWATTHR BWATTHR CWATTHR xFWATTHR registers after an integral number of line cycles, as
00 VA × IA VB × IB VC × IC shown in Figure 79. The number of half line cycles is specified
01 VA × IA VB × IB VC × IC in the LINECYC register.
VB = VA – VC1
The line cycle energy accumulation mode is activated by setting
10 VA × IA VB × IB VC × IC
Bit 0 (LWATT) in the LCYCMODE register. The energy accu-
VB = −VA − VC
mulation over an integer number of half line cycles is written to
11 VA × IA VB × IB VC × IC
the watt-hour accumulation registers after LINECYC number of
VB = −VA
half line cycles is detected. When using the line cycle accumulation
1
In a 3-phase three wire case (CONSEL[1:0] = 01), the ADE7880 computes the mode, the Bit 6 (RSTREAD) of the LCYCMODE register must
rms value of the line voltage between Phase A and Phase C and stores the
result into BVRMS register (see the Voltage RMS in 3-Phase, 3-Wire Delta be set to Logic 0 because the read with reset of watt-hour registers
Configurations section). Consequently, the ADE7880 computes powers is not available in this mode.
associated with Phase B that do not have physical meaning. To avoid any
errors in the frequency output pins (CF1, CF2, or CF3) related to the powers Phase A, Phase B, and Phase C zero crossings are, respectively,
associated with Phase B, disable the contribution of Phase B to the energy-to-
frequency converters by setting bits TERMSEL1[1] or TERMSEL2[1] or TERMSEL3[1]
included when counting the number of half line cycles by setting
to 0 in the COMPMODE register (see the Energy-to-Frequency Conversion Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-
section). nation of the zero crossings from all three phases can be used
Depending on the polyphase meter service, choose the appro- for counting the zero crossing. Select only one phase at a time
priate formula to calculate the active energy. The American for inclusion in the zero crossings count during calibration.
ANSI C12.10 standard defines the different configurations of ZXSEL[0] IN
LCYCMODE[7:0]
the meter. Table 15 describes which mode to choose in these
various configurations. ZERO-
CROSSING
DETECTION
(PHASE A)
Table 15. Meter Form Configuration
ZXSEL[1] IN LINECYC[15:0]
ANSI Meter Form Configuration CONSEL LCYCMODE[7:0]
capacitor) produces a phase difference between the applied ac This is the relationship used to calculate the total reactive power
voltage and the resulting current. The power associated with for each phase. The instantaneous reactive power signal, q(t), is
reactive elements is called reactive power, and its unit is VAR. generated by multiplying each harmonic of the voltage signals
Reactive power is defined as the product of the voltage and current by the 90° phase-shifted corresponding harmonic of the current
waveforms when all harmonic components of one of these in each phase.
signals are phase shifted by 90°.
The expression of fundamental reactive power is obtained from
Equation 31 is an example of the instantaneous reactive power Equation 33 with k = 1, as follows:
signal in an ac system when the phase of the current channel is
FQ = V1I1 sin(φ1 – γ1)
shifted by +90°.
∞
The ADE7880 computes the fundamental reactive power using
v(t ) = ∑Vk 2 sin(kωt + φk) (30) a proprietary algorithm that requires some initialization function
k =1 of the frequency of the network and its nominal voltage measured
∞ in the voltage channel. These initializations are introduced in
i(t ) = ∑ I k 2 sin(kωt + γ k ) (31)
k =1
the Active Power Calculation section and are common for both
fundamental active and reactive powers.
∞ π
i' (t ) = ∑ I k 2 sin kωt + γ k + The ADE7880 stores the instantaneous fundamental phase reactive
k =1 2
powers into the AFVAR, BFVAR, and CFVAR registers. Their
where i’(t) is the current waveform with all harmonic equation is
components phase shifted by 90°.
V1 I1 1
Next, the instantaneous reactive power, q(t), can be expressed as xFVAR = × × sin(φ1 – γ1) × PMAX × 4 (35)
VFS I FS 2
q(t) = v(t) × iʹ(t) (32)
where:
VFS, IFS are the rms values of the phase voltage and current when
the ADC inputs are at full scale.
Rev. C | Page 51 of 107
ADE7880 Data Sheet
PMAX = 27,059,678, the instantaneous power computed when Fundamental Reactive Power Gain Calibration
the ADC inputs are at full scale and in phase. The average fundamental reactive power in each phase can be
The xFVAR waveform registers are not mapped with an address scaled by ±100% by writing to one of the phase’s VAR gain 24-bit
in the register space and can be accessed only through HSDC register (APGAIN, BPGAIN, or CPGAIN). Note that these
port in the waveform sampling mode (see Waveform Sampling registers are the same gain registers used to compensate the other
Mode section for details). Fundamental reactive power powers computed by the ADE7880. See the Active Power Gain
information is also available through the harmonic calculations Calibration section for details on these registers.
of the ADE7880 (see Harmonics Calculations section for details). Fundamental Reactive Power Offset Calibration
Table 16 presents the settling time for the fundamental reactive The ADE7880 provides a fundamental reactive power offset
power measurement, which is the time it takes the power to register on each phase. The AFVAROS, BFVAROS, and CFVAROS
reflect the value at the input of the ADE7880. registers compensate the offsets in the fundamental reactive power
calculations. These are signed twos complement, 24-bit registers
Table 16. Settling Time for Fundamental Reactive Power
that are used to remove offsets in the fundamental reactive power
Input Signals
calculations. An offset can exist in the power calculation due to
63% PMAX 100% PMAX
crosstalk between channels on the PCB or in the chip itself. The
375 ms 875 ms
resolution of the registers is the same as for the active power
Bit 14 (SELFREQ) in the COMPMODE register must be set offset registers (see the Active Power Offset Calibration section).
according to the frequency of the network in which the ADE7880 As stated in the Current Waveform Gain Registers section, the
is connected. If the network frequency is between 45 Hz and 55 Hz, serial ports of the ADE7880 work on 32-, 16-, or 8-bit words
clear this bit to 0 (the default value). If the network frequency is and the DSP works on 28 bits. Similar to the registers presented
between 55 Hz and 66 Hz, set this bit to 1. In addition, initialize in Figure 44, the AFVAROS, BFVAROS, and CFVAROS 24-bit
the VLEVEL, 28-bit signed register based on Equation 22. signed registers are accessed as 32-bit registers with the four
Refer to the Managing Change in Fundamental Line Frequency MSBs padded with 0s and sign extended to 28 bits.
section for details on how to manage changes in line frequency.
34 27 26 0
10193-052
VARTHR 0
ZXSEL[1] IN
where:
LINECYC[15:0]
LCYCMODE[7:0]
S is the apparent power.
ZERO-
CROSSING
V rms and I rms are the rms voltage and current, respectively.
CALIBRATION
DETECTION CONTROL
(PHASE B) The ADE7880 computes the arithmetic apparent power on each
ZXSEL[2] IN
phase. Figure 82 illustrates the signal processing in each phase
LCYCMODE[7:0]
for the calculation of the apparent power in the ADE7880.
ZERO-
CROSSING
Because V rms and I rms contain all harmonic information, the
DETECTION
(PHASE C) apparent power computed by the ADE7880 is total apparent
power. The ADE7880 computes fundamental and harmonic
APGAIN AFVAROS
AFVARHR[31:0]
apparent powers determined by the fundamental and harmonic
components of the voltages and currents. See the Harmonics
INTERNAL
ACCUMULATOR
32-BIT
Calculations section for details.
REGISTER
OUTPUT FROM THRESHOLD
FUNDAMENTAL REACTIVE The ADE7880 stores the instantaneous phase apparent powers
POWER ALGORITHM
into the AVA, BVA, and CVA registers. Their equation is
34 27 26 0
10193-053
VARTHR 0 U I 1
xVA PMAX 4 (41)
Figure 81. Line Cycle Fundamental Reactive Energy Accumulation Mode U FS I FS 2
APGAIN
AIRMS
AVAHR[31:0]
INTERNAL
ACCUMULATOR
32-BIT REGISTER
AVRMS
: AVA
THRESHOLD
DIGITAL SIGNAL 24
PROCESSOR
34 27 26 0
10193-054
VATHR 0
Figure 82. Apparent Power Data Flow and Apparent Energy Accumulation
3 227 ZERO-
14.531 sec
CROSSING
xVAHR registers every DETECTION
PMAX 1.024 106 (PHASE A)
ZXSEL[1] IN LINECYC[15:0]
The maximum value that can be stored in the xVAHR LCYCMODE[7:0]
AVRMS
CONSEL[1:0] AVAHR BVAHR CVAHR THRESHOLD
00 AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS
01 AVRMS × AIRMS BVRMS × BIRMS CVRMS × CIRMS
10193-055
34 27 26 0
VB = VA – VC1 VATHR 0
10193-057
HREADY FLAG IN STATUS0 IS SET
IMMEDIATELY OF AFTER HSTIME
When the neutral current and the sum of the three phase the register for that harmonic to be monitored. If the second
currents represented by ISUM register are analyzed, the harmonic is monitored, write 2. If harmonic 51 is desired, write
following metering quantities are computed for both currents: 51. The fundamental components are always monitored, inde-
pendent of the values written into HX, HY, or HZ. Therefore, if
• RMS of fundamental and of up to 2 harmonics or rms of
one of these registers is made equal to 1, the ADE7880 monitors
up to three harmonics: Ix, Iy, Iz, x, y, z = 1,2, 3,…, N.
the fundamental components multiple times. The maximum
• Harmonic distortions of the analyzed harmonics.
index allowed in HX, HY, and HZ registers is 63. The no
Configuring the Harmonic Calculations attenuation pass band is 2.8 kHz, corresponding to a −3 dB
The ADE7880 requires a time base provided by a phase voltage. bandwidth of 3.3 kHz, thus all harmonics of frequency lower
Bit 9 and Bit 8 (ACTPHSEL) of HCONFIG[15:0]register select than 2800 Hz are supported without attenuation.
this phase voltage. If ACTPHSEL = 00, the phase A is used. If
The rms of the phase voltage and phase current fundamental
ACTPHSEL = 01, the Phase B is used and if ACTPHSEL = 10,
components are stored into FVRMS and FIRMS 24-bit signed
the Phase C is used. If the phase voltage used as time base is
registers. The associated data path is presented in Figure 86.
down, select another phase, and the harmonic engine continues
Similar to the rms current and voltage rms data paths presented
to work properly.
in the Root Mean Square Measurement section, the data path
The phase under analysis is selected by Bit 2 and Bit 1 (HPHASE) contains 24-bit signed offset compensation registers xIRMSOS,
of HCONFIG[15:0]register. If HPHASE = 00, the Phase A is xVRMSOS, x = A, B, C for each phase quantity. The rms of the
monitored. If HPHASE = 01, the Phase B is monitored and if phase current and phase voltage three harmonic components
HPHASE = 10, the Phase C is monitored. If HPHASE = 11, the are stored into HXVRMS, HXIRMS, HYVRMS, HYIRMS,
neutral current together with the sum of the phase currents HZVRMS, and HZIRMS 24-bit signed registers. The associated
represented by ISUM register are monitored. data path is presented in Figure 87 and contains the following
Harmonic Calculations When a Phase is Monitored 24-bit signed offset compensation registers: HXIRMSOS,
HYIRMSOS, HZIRMSOS, HXVRMSOS, HYVRMSOS, and
When a phase is monitored, fundamental information together
HZVRMSOS.
with information about up to three harmonics is computed. The
indexes of the three additional harmonics simultaneously It is recommended to leave the offset compensation registers at
monitored by the ADE7880 are provided by the 8-bit registers 0, the default value.
HX, HY, and HZ. Simply write the index of the harmonic into
Vy Iy HYVHD, HYIHD
HDV y = HDI y =
V1 , I1 ,y = 2, 3,…,N
Vz I HZVHD, HZIHD
HDV z = HDI z = z
V1 , I1 ,z = 2, 3,…,N
Table 21. Harmonic Engine Outputs when Neutral Current and ISUM are Analyzed and the Registers Where the Values are Stored
ADE7880
Quantity Definition Register
RMS of a Harmonic Component (Including the Fundamental) of the Neutral Current Ix, x = 1, 2, 3,…,N HXIRMS
Iy, y = 1, 2, 3,…,N HYIRMS
Iz, z = 1, 2, 3,…,N HZIRMS
RMS of a Harmonic Component (Including the Fundamental) of ISUM ISUMx, x = 1, 2, 3,…,N HXVRMS
ISUMy, y = 1, 2, 3,…,N HYVRMS
ISUMz, z = 1, 2, 3,…,N HZVRMS
Harmonic Distortion of a Harmonic Component (Including the Fundamental) of the Ix HXIHD
Neutral Current (Note that the HX Register Must be Set to 1 for These Calculations to be HDI x =
I1 ,
Executed)
x = 1, 2, 3,…,N
Iy HYIHD
HDI y =
I1 ,
y = 1, 2, 3,…,N
Iz HZIHD
HDI z =
I1 ,
z = 1, 2, 3,…,N
Harmonic Distortion of a Harmonic Component (Including the Fundamental) of ISUM. ISUM x HXVHD
(Note that the HX Register Must be Set to 1 for These Calculations to be Executed) HDISUM x =
ISUM 1 ,
x = 1, 2, 3,…,N
ISUM y HYVHD
HDISUM y =
ISUM 1 ,
y = 1, 2, 3,…,N
ISUM z HZVHD
HDISUM z =
ISUM 1 ,
z = 1, 2, 3,…,N
27
BFIRMSOS
27
27
APGAIN OR
BPGAIN OR
CPGAIN
CALCULATIONS
HPHASE BITS
FUNDAMENTAL
COMPONENTS
27 2–21
BFVRMSOS
27
FVRMS
CFVRMSOS
27
10193-058
The active, reactive, and apparent powers of the fundamental the active and reactive harmonic power data paths. Figure 89
component are stored into the FWATT, FVAR, and FVA 24-bit presents the associated data path.
signed registers. Figure 88 presents the associated data path. The power factor of the fundamental component is stored into
The active, reactive and apparent powers of the 3 harmonic FPF 24-bit signed register. The power factors of the three harmonic
components are stored into the HXWATT, HXVAR, HXVA, components are stored into the HXPF, HYPF, and HZPF 24-bit
HYWATT, HYVAR, HYVA, HZWATT, HZVAR, and HZVA signed registers.
24-bit signed registers. The HPGAIN register is a 24-bit signed
register used to scale the output of the harmonic active, reactive The total harmonic distortion ratios computed using the rms of
and apparent power components, as shown in Figure 89. The the fundamental components and the rms of the phase current
24-bit HPGAIN register is accessed as a 32-bit register with the and the phase voltage (see Root Mean Square Chapter for details
four most significant bits (MSBs) padded with 0s and sign about these measurements) are stored into the VTHD and ITHD
extended to 28 bits (See Figure 44 for details). HXWATTOS, 24-bit registers in 3.21 signed format. This means the ratios are
HYWATTOS, HZWATTOS, HXVAROS, HYVAROS and limited to +3.9999 and all greater results are clamped to it.
HZVAROS are 24-bit offset compensation registers located in
27
HXIRMS
HYIRMSOS
27
HYIRMS
HZIRMSOS
27
CALCULATIONS
COMPONENTS
HZIRMS
HARMONIC
HXVRMSOS
27
HXVRMS
HYVRMSOS
27
HYVRMS
HXVRMSOS
27
10193-059
HZVRMS
APGAIN AFWATTOS 22
÷
BPGAIN BFWATTOS 22
÷ FWATT
CPGAIN CFWATTOS 22
÷
CALCULATIONS
FUNDAMENTAL
COMPONENTS
HPHASE BITS
HCONFIG[2, 1] SELECT THE
PHASE BEING MONITORED
APGAIN AFVAROS 22
÷
BPGAIN BFVAROS 22
÷ FVAR
CPGAIN CFVAROS 22
10193-060
÷
Figure 88. Fundamental Active and Reactive Powers Signal Processing
Rev. C | Page 64 of 107
Data Sheet ADE7880
HPGAIN HXWATTOS 22
÷ HXWATT
HPGAIN HYWATTOS 22
÷ HYWATT
HPGAIN HZWATTOS 22
CALCULATIONS
COMPONENTS
÷
HARMONIC
HZWATT
HPGAIN HXVAROS 22
÷ HXVAR
HPGAIN HYVAROS 22
÷ HYVAR
HPGAIN HZVAROS 22
10193-061
÷ HZVAR
The harmonic distortions of the three harmonic components HYVHD, HYIHD, HZVHD, and HZIHD 24-bit registers. The
are stored into the HXVHD, HXIHD, HYVHD, HYIHD, distortions of the neutral current are saved into HYIHD and
HZVHD, and HZIHD 24-bit registers in 3.21 signed format. HZIHD registers and the distortions of the ISUM are stored
This means the ratios are limited to +3.9999 and all greater into the HYVHD and HZVHD registers. As HX is set to 1, the
results are clamped to it. HXIHD and HXVHD registers contain 0x1FFFFF, a number
As a reference, Table 20 presents the ADE7880 harmonic engine representing 1 in 3.21 signed format.
outputs when one phase is analyzed and the registers in which As a reference, Table 21 presents the ADE7880 harmonic engine
the outputs are stored. outputs when the neutral current and ISUM are analyzed and
Harmonic Calculations When the Neutral is Monitored the registers in which the outputs are stored.
When the neutral current and the sum of phase currents are Configuring Harmonic Calculations Update Rate
monitored, only the harmonic rms related registers are updated. The ADE7880 harmonic engine functions at 8 kHz rate. From
The registers HX, HY and HZ identify the index of the harmonic, the moment the HCONFIG register is initialized and the
including the fundamental. When a phase is analyzed, the harmonic indexes are set in the HX, HY and HZ index registers,
fundamental rms values are calculated continuously and the the ADE7880 calculations take typically 750 ms to settle within
results are stored in dedicated registers FIRMS and FVRMS. the specification parameters.
When the neutral is analyzed, the fundamental information is The update rate of the harmonic engine output registers is
calculated by setting one of the harmonic index registers HX, managed by Bits[7:5] (HRATE) in HCONFIG register and is
HY or HZ to 1 and the results are stored in harmonic registers. independent of the engine’s calculations rate of 8 kHz. The default
The maximum index allowed in HX, HY and HZ registers is 63. value of 000 means the registers are updated every 125 μs
The no attenuation pass band is 2.8 kHz, corresponding to a (8 kHz rate). Other update periods are: 250 μs (HRATE = 001),
−3 dB bandwidth of 3.3 kHz, thus all harmonics of frequency 1 ms (010), 16 ms (011), 128 ms (100), 512 ms (101), 1.024 sec
lower than 2800 Hz are supported without attenuation. (110). If HRATE bits are 111, then the harmonic calculations
HXIRMS, HYIRMS and HZIRMS registers contain the harmonic are disabled.
rms components of the neutral current and HXVRMS, HYVRMS The ADE7880 provides two ways to manage the harmonic
and HZVRMS registers contain the harmonic rms components computations. The first approach, enabled when Bit 0 (HRCFG)
of ISUM. Note that in this case, the rms of the fundamental of HCONFIG register is cleared to its default value of 0, sets Bit
component is not computed into FIRMS or FVRMS registers, 19 (HREADY) in STATUS0 register to 1 after a certain period
but it is computed if one of the index registers HX, HY and HZ of time and then every time the harmonic calculations are updated
is initialized with 1. at HRATE frequency. This allows an external microcontroller to
If the HX register is initialized to 1, the ADE7880 computes the access the harmonic calculations only after they have settled.
harmonic distortions of the other harmonics identified into HY The time period is determined by the state of Bits[4:3] (HSTIME)
and HZ registers and stores them in 3.21 signed format into the in the HCONFIG register. The default value of 01 sets the time
Rev. C | Page 65 of 107
ADE7880 Data Sheet
to 750 ms, the settling time of the harmonic calculations. Other • Initialize the gain registers used in the harmonic
possible values are 500 ms (HSTIME = 00), 1 sec (10) and calculations. Leave the offset registers to 0.
1250 ms (11).
• Read the registers in which the harmonic information is
The second approach, enabled when Bit 0 (HRCFG) of HCONFIG stored using the burst or regular reading mode at high to
register is set to 1, sets Bit 19 (HREADY) in STATUS0 register low transitions of CF2/HREADY pin.
to 1 every time the harmonic calculations are updated at the
update frequency determined by HRATE bits without waiting
WAVEFORM SAMPLING MODE
for the harmonic calculations to settle. This allows an external The waveform samples of the current and voltage waveform,
microcontroller to access the harmonic calculations immediately the active, reactive, and apparent power outputs are stored
after they have been started. If the corresponding mask bit in every 125 µs (8 kHz rate) into 24-bit signed registers that can be
the MASK0 interrupt mask register is enabled, the IRQ pin also accessed through various serial ports of the ADE7880. Table 22
goes active low. The status bit is cleared and the pin IRQ is set provides a list of registers and their descriptions.
to high again by writing to the STATUS0 register with the Table 22. Waveform Registers List
corresponding bit set to 1.
Register Description
Additionally, the ADE7880 provides a periodical output signal IAWV Phase A current
called HREADY at the CF2/HREADY pin synchronous to the VAWV Phase A voltage
moment the harmonic calculations are updated in the harmonic IBWV Phase B current
registers. This functionality is chosen if Bit 2 (CF2DIS) is set to VBWV Phase B voltage
1 in the CONFIG register. If CF2DIS is set to 0 (default value), ICWV Phase C current
the CF2 energy to frequency converter output is provided at VCWV Phase C voltage
CF2/HREADY pin. The default state of this signal is high. Every INWV Neutral current
time the harmonic registers are updated based on HRATE bits AVA Phase A apparent power
in HCONFIG register, the signal HREADY goes low for approx- BVA Phase B apparent power
imately 10 µs and then goes back high. If Bit 0 (HRCFG) in the CVA Phase C apparent power
HCONFIG register is set to 1, the HREADY bit in the STATUS0 AWATT Phase A active power
register is set to 1 every HRATE period right after the harmonic BWATT Phase B active power
calculations start, and the HREADY signal toggles high, low, and CWATT Phase C active power
back synchronously. If the HRCFG bit is set to 0, the HREADY
Bit 17 (DREADY) in the STATUS0 register can be used to
bit in the STATUS0 register is set to 1 after the HSTIME period,
signal when the registers listed in Table 22 can be read using
and the HREADY signal toggles high, low and back synchronously.
I2C or SPI serial ports. An interrupt attached to the flag can be
The HREADY signal allows fast access to the harmonic registers
enabled by setting Bit 17 (DREADY) in the MASK0 register. (see
without having to use HREADY interrupt in MASK0 register.
the Digital Signal Processor section for more details on
In order to facilitate the fast reading of the registers in which Bit DREADY).
the harmonic calculations are stored, a special burst registers
The ADE7880 contains a high speed data capture (HSDC) port
reading has been implemented in the serial interfaces. See the
that is specially designed to provide fast access to the waveform
I2C Read Operation of Harmonic Calculations Registers and the
sample registers. Read the HSDC Interface section for more
SPI Read Operation sections for details.
details.
Recommended Approach to Managing Harmonic
As stated in the Current Waveform Gain Registers section, the
Calculations
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
The recommended approach to managing the ADE7880 All registers listed in Table 22 are transmitted signed extended
harmonic calculations is the following: from 24 bits to 32 bits (see Figure 45).
• Set up Bit 2 (CF2DIS) in the CONFIG register. Set the ENERGY-TO-FREQUENCY CONVERSION
CF2DIS bit to 1 to use the CF2/HREADY pin to signal
when the harmonic calculations have settled and are The ADE7880 provides three frequency output pins: CF1, CF2,
updated. The high to low transition of HREADY signal and CF3. The CF2 pin is multiplexed with the HREADY pin of
indicates when to read the harmonic registers. Use the the harmonic calculations block. When HREADY is enabled, the
burst reading mode to read the harmonic registers as it is CF2 functionality is disabled at the pin. The CF3 pin is multiplexed
the most efficient way to read them. with the HSCLK pin of the HSDC interface. When HSDC is
enabled, the CF3 functionality is disabled at the pin. The CF1
• Choose the harmonics to be monitored by setting HX, HY pin and the CF2 pin are always available. After initial calibration
and HZ appropriately. at manufacturing, the manufacturer or end customer verifies
• Select all the HCONFIG register bits. the energy meter calibration. One convenient way to verify the
meter calibration is to provide an output frequency proportional to
Rev. C | Page 66 of 107
Data Sheet ADE7880
the active, reactive, or apparent powers under steady load First, Bits[2:0] (TERMSEL1[2:0]), Bits[5:3] (TERMSEL2[2:0]),
conditions. This output frequency can provide a simple, single- and Bits[8:6] (TERMSEL3[2:0]) of the COMPMODE register
wire, optically isolated interface to external calibration decide which phases, or which combination of phases, are added.
equipment. Figure 90 illustrates the energy-to-frequency
The TERMSEL1 bits refer to the CF1 pin, the TERMSEL2 bits
conversion in the ADE7880.
refer to the CF2 pin, and the TERMSEL3 bits refer to the CF3
The DSP computes the instantaneous values of all phase powers: pin. The TERMSELx[0] bits manage Phase A. When set to 1,
total active, fundamental active, fundamental reactive, and Phase A power is included in the sum of powers at the CFx
apparent. The process in which the energy is sign accumulated converter. When cleared to 0, Phase A power is not included.
in various xWATTHR, xFVARHR, and xVAHR registers has The TERMSELx[1] bits manage Phase B, and the TERMSELx[2]
already been described in the energy calculation sections: Active bits manage Phase C. Setting all TERMSELx bits to 1 means all
Energy Calculation, Fundamental Reactive Energy Calculation, 3-phase powers are added at the CFx converter. Clearing all
and Apparent Energy Calculation. In the energy-to-frequency TERMSELx bits to 0 means no phase power is added and no
conversion process, the instantaneous powers generate signals CF pulse is generated.
at the frequency output pins (CF1, CF2, and CF3). One energy-
to-frequency converter is used for every CFx pin. Every converter Second, Bits[2:0] (CF1SEL[2:0]), Bits[5:3] (CF2SEL[2:0]), and
sums certain phase powers and generates a signal proportional Bits[8:6] (CF3SEL[2:0]) in the CFMODE register decide what
to the sum. Two sets of bits decide what powers are converted. type of power is used at the inputs of the CF1, CF2, and CF3
converters, respectively. Table 23 shows the values that CFxSEL
can have: total active, apparent, fundamental active, or fundamental
reactive powers.
Table 23. CFxSEL Bits Description
CFxSEL Description Registers Latched When CFxLATCH = 1
000 CFx signal proportional to the sum of total phase active powers AWATTHR, BWATTHR, CWATTHR
001 Reserved
010 CFx signal proportional to the sum of phase apparent powers AVAHR, BVAHR, CVAHR
011 CFx signal proportional to the sum of fundamental phase active AFWATTHR, BFWATTHR, CFWATTHR
powers
100 CFx signal proportional to the sum of fundamental phase reactive AFVARHR, BFVARHR, CFVARHR
powers
101 to 111 Reserved
CFxSEL BITS IN
CFMODE
INSTANTANEOUS
PHASE A
ACTIVE POWER VA
27
INSTANTANEOUS WATT REVPSUMx BIT OF
PHASE B STATUS0[31:0]
ACTIVE POWER INTERNAL
FWATT ACCUMULATOR
CFx PULSE
FREQ DIVIDER OUTPUT
INSTANTANEOUS
PHASE C FVAR
ACTIVE POWER THRESHOLD
CFxDEN
DIGITAL SIGNAL
PROCESSOR 34 27 26 0 27
10193-062
WTHR 0
10193-090
Energy Registers and CF Outputs for Various
CFx PIN Accumulation Modes
Figure 91. CFx Pin Recommended Connection Bits[1:0] (WATTACC[1:0]) in the ACCMODE register deter-
Bits[11:9] (CF3DIS, CF2DIS, and CF1DIS) of the CFMODE mine the accumulation modes of the total and fundamental active
register decide if the frequency converter output is generated at powers when signals proportional to the active powers are chosen
the CF3, CF2, or CF1 pin. When Bit CFxDIS is set to 1 (the at the CFx pins (the CFxSEL[2:0] bits in the CFMODE register
default value), the CFx pin is disabled and the pin stays high. equal 000 or 011). They also determine the accumulation modes
When Bit CFxDIS is cleared to 0, the corresponding CFx pin of the watt-hour energy registers (AWATTHR, BWATTHR,
output generates an active low signal. CWATTHR, AFWATTHR, BFWATTHR and CFWATTHR).
When WATTACC[1:0] = 00 (the default value), the active powers
Bits[16:14] (CF3, CF2, CF1) in the Interrupt Mask register MASK0
are sign accumulated in the watt-hour registers and before entering
manage the CF3, CF2, and CF1 related interrupts. When the CFx
the energy-to-frequency converter. Figure 93 shows how signed
bits are set, whenever a high-to-low transition at the corresponding
active power accumulation works. In this mode, the CFx pulses
frequency converter output occurs, an interrupt IRQ0 is triggered
synchronize perfectly with the active energy accumulated in
and a status bit in the STATUS0 register is set to 1. The interrupt
xWATTHR registers because the powers are sign accumulated
is available even if the CFx output is not enabled by the CFxDIS
in both data paths.
bits in the CFMODE register.
Synchronizing Energy Registers with CFx Outputs
The ADE7880 contains a feature that allows synchronizing the
content of phase energy accumulation registers with the generation ACTIVE ENERGY
The CFCYC 8-bit unsigned register contains the number of xWSIGN BIT
IN PHSIGN
high to low transitions at the frequency converter output between
10193-065
two consecutive latches. Avoid writing a new value into the APNOLOAD POS NEG POS NEG
SIGN = POSITIVE
CFCYC register during a high-to-low transition at any CFx pin.
Figure 93. Active Power Signed Accumulation Mode
CF1 PULSE
BASED ON
PHASE A AND When WATTACC[1:0] = 01, the active powers are accumulated
PHASE B
APPARENT CFCYC = 2
in positive only mode. When the powers are negative, the watt-
POWERS
hour energy registers are not accumulated. CFx pulses are
AVAHR, BVAHR, AVAHR, BVAHR,
generated based on signed accumulation mode. In this mode,
10193-064
ACTIVE POWER
NO-LOAD
ACTIVE ENERGY THRESHOLD
REVAPx BIT
IN STATUS0
10193-067
APNOLOAD POS NEG POS NEG
ACTIVE POWER
SIGN = POSITIVE
REVAPx BIT
IN STATUS0
10193-068
VARNOLOAD POS NEG POS NEG
reactive power accumulation works. In this mode, the CFx SIGN = POSITIVE
pulses synchronize perfectly with the fundamental reactive Figure 96. Fundamental Reactive Power Signed Accumulation Mode
energy accumulated in the xFVARHR registers because the
powers are sign accumulated in both data paths. When VARACC[1:0] = 11, the fundamental reactive powers are
accumulated in absolute mode. When the powers are negative,
VARACC[1:0] = 01 setting is reserved and ADE7880 behaves they change sign and accumulate together with the positive
identically to the case when VARACC[1:0] = 00. power in the var-hour registers. CFx pulses are generated based
When VARACC[1:0] = 10, the fundamental reactive powers are on signed accumulation mode. In this mode, the CFx pulses do
accumulated depending on the sign of the corresponding active not synchronize perfectly with the fundamental reactive energy
power in the var-hour energy registers and before entering the accumulated in x VARHR registers because the powers are
energy-to-frequency converter. If the fundamental active power accumulated differently in each data path. Figure 98 shows how
is positive or considered 0 when lower than the no load threshold, absolute fundamental reactive power accumulation works.
the fundamental reactive power is accumulated as is. If the Sign of Sum of Phase Powers in the CFx Data Path
fundamental active power is negative, the sign of the fundamental
The ADE7880 has sign detection circuitry for the sum of phase
reactive power is changed for accumulation. Figure 97 shows how
powers that are used in the CFx data path. As seen in the beginning
the sign adjusted fundamental reactive power accumulation
of the Energy-to-Frequency Conversion section, the energy
mode works. In this mode, the CFx pulses synchronize perfectly
accumulation in the CFx data path is executed in two stages.
with the fundamental reactive energy accumulated in xFVARHR
Every time a sign change is detected in the energy accumulation
registers because the powers are accumulated in the same way in
at the end of the first stage, that is, after the energy accumulated
both data paths.
Rev. C | Page 70 of 107
Data Sheet ADE7880
into the accumulator reaches one of the WTHR, VARTHR, or indicate the sign of the sum of phase powers. When cleared to
VATHR thresholds, a dedicated interrupt can be triggered 0, the sum is positive. When set to 1, the sum is negative.
synchronously with the corresponding CFx pulse. The sign Interrupts attached to Bit 18, Bit 13, and Bit 9 (REVPSUM3,
of each sum can be read in the PHSIGN register. REVPSUM2, and REVPSUM1, respectively) in the STATUS0
register are enabled by setting Bit 18, Bit 13, and Bit 9 in the
MASK0 register. If enabled, the IRQ0 pin is set low, and the
REACTIVE status bit is set to 1 whenever a change of sign occurs. To find
ENERGY
the phase that triggered the interrupt, the PHSIGN register is
NO-LOAD read immediately after reading the STATUS0 register. Next, the
THRESHOLD
REACTIVE status bit is cleared, and the IRQ0 pin is set high again by writing
POWER
to the STATUS0 register with the corresponding bit set to 1.
NO-LOAD
THRESHOLD
NO LOAD CONDITION
NO-LOAD
THRESHOLD The no load condition is defined in metering equipment standards
ACTIVE as occurring when the voltage is applied to the meter and no cur-
POWER
rent flows in the current circuit. To eliminate any creep effects in
the meter, the ADE7880 contains three separate no load detection
REVRPx BIT
IN STATUS0 circuits: one related to the total active power, one related to the
xVARSIGN BIT
IN PHSIGN fundamental active and reactive powers, and one related to the
10193-069
LFSR
ARRAY OF 2272 BITS GENERATOR
g0 g1 g2 g3 g31
FB
b0 b1 b2 b31
LFSR
10193-072
10193-073
PROGRAM JUMP READ ISR ACTION JUMP
SEQUENCE TO ISR INTERRUPT INTERRUPT STATUSx BACK GLOBAL INTERRUPT
STATUSx (BASED ON STATUSx CONTENTS) TO ISR
MASK FLAG MASK RESET
IRQx
10193-074
PROGRAM JUMP READ READ ISR ACTION JUMP
SEQUENCE TO ISR INTERRUPT INTERRUPT STATUSx BACK (BASED ON STATUSx CONTENTS) GLOBAL INTERRUPT TO ISR
PHx STATUSx
MASK FLAG MASK RESET
Figure 102. Interrupt Management when PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers are Involved
SERIAL INTERFACES read using either the I2C or SPI interfaces. The HSDC port
The ADE7880 has three serial port interfaces: one fully licensed provides the state of up to 16 registers representing instantaneous
I2C interface, one serial peripheral interface (SPI), and one high values of phase voltages and neutral currents, and active, reactive,
speed data capture port (HSDC). As the SPI pins are multiplexed and apparent powers.
with some of the pins of the I2C and HSDC ports, the ADE7880 Communication Verification
accepts two configurations: one using the SPI port only and one The ADE7880 includes a set of three registers that allow any
using the I2C port in conjunction with the HSDC port. communication via I2C or SPI to be verified. The LAST_OP
Serial Interface Choice (Address 0xEA01), LAST_ADD (Address 0xE9FE) and
After reset, the HSDC port is always disabled. Choose between LAST_RWDATA registers record the nature, address and data
of the last successful communication respectively. The
the I2C and SPI ports by manipulating the SS/HSA pin after
LAST_RWDATA register has three separate addresses
power-up or after a hardware reset. If the SS/HSA pin is kept
depending on the length of the successful communication.
high, then the ADE7880 uses the I2C port until a new hardware
reset is executed. If the SS/HSA pin is toggled high to low three Table 24. LAST_RWDATA Register Locations
times after power-up or after a hardware reset, the ADE7880 Communication Type Address
uses the SPI port until a new hardware reset is executed. This 8-Bit Read/Write 0xE7FD
manipulation of the SS/HSA pin can be accomplished in two 16-Bit Read/Write 0xE9FF
ways. First, use the SS/HSA pin of the master device (that is, the 32-Bit Read/Write 0xE5FF
microcontroller) as a regular I/O pin and toggle it three times. After each successful communication with the ADE7880, the
Second, execute three SPI write operations to a location in the address of the last accessed register is stored in the 16-bit
address space that is not allocated to a specific ADE7880 register LAST_ADD register (Address 0xE9FE). This is a read only
(for example 0xEBFF, where eight bit writes can be executed). register that stores the value until the next successful read or
These writes allow the SS/HSA pin to toggle three times. See the write is complete. The LAST_OP register (Address 0xEA01)
SPI Write Operation section for details on the write protocol stores the nature of the operation. That is, it indicates whether a
involved. read or a write was performed. If the last operation is a write, the
After the serial port choice is completed, it needs to be locked. LAST_OP register stores the value 0xCA. If the last operation is
Consequently, the active port remains in use until a hardware a read, the LAST_OP register stores the value 0x35. The
reset is executed in PSM0 normal mode or until a power-down. LAST_RWDATA register stores the data that was written or
If I2C is the active serial port, Bit 1 (I2C_LOCK) of the CONFIG2 read from the register. Any unsuccessful read or write operation
register must be set to 1 to lock it in. From this moment, the is not reflected in these registers.
ADE7880 ignores spurious toggling of the SS pin and an eventual When LAST_OP, LAST_ADD and LAST_RWDATA registers
switch into using the SPI port is no longer possible. If the SPI is are read, their values are not stored into themselves.
the active serial port, any write to the CONFIG2 register locks
the port. From this moment, a switch into using the I2C port is
no longer possible. Once locked, the serial port choice is
maintained when the ADE7880 changes PSMx power modes.
The functionality of the ADE7880 is accessible via several on-
chip registers. The contents of these registers can be updated or
Rev. C | Page 75 of 107
ADE7880 Data Sheet
I2C-Compatible Interface I2C Write Operation
The ADE7880 supports a fully licensed I C interface. The I C
2 2
The write operation using the I2C interface of the ADE7880
interface is implemented as a full hardware slave. SDA is the initiate when the master generates a start condition and consists
data I/O pin, and SCL is the serial clock. These two pins are in one byte representing the address of the ADE7880 followed
shared with the MOSI and SCLK pins of the on-chip SPI by the 16-bit address of the target register and by the value of
interface. The maximum serial clock frequency supported by this the register.
interface is 400 kHz.
The most significant seven bits of the address byte constitute
The two pins used for data transfer, SDA and SCL, are configured the address of the ADE7880 and they are equal to 0111000b.
in a wire-AND’ed format that allows arbitration in a multimaster Bit 0 of the address byte is a read/write bit. Because this is a
system. Note that the ADE7880 requires a minimum of 100 ns write operation, it has to be cleared to 0; therefore, the first byte
hold time for I2C communication. Refer to the tHD;DAT specification of the write operation is 0x70. After every byte is received, the
in Table 2. ADE7880 generates an acknowledge. As registers can have 8, 16,
The transfer sequence of an I2C system consists of a master device or 32 bits, after the last bit of the register is transmitted and the
initiating a transfer by generating a start condition while the bus ADE7880 acknowledges the transfer, the master generates a stop
is idle. The master transmits the address of the slave device and condition. The addresses and the register content are sent with
the direction of the data transfer in the initial address transfer. If the most significant bit first. See Figure 103 for details of the I2C
the slave acknowledges, the data transfer is initiated. This continues write operation.
until the master issues a stop condition, and the bus becomes idle.
START
STOP
15 8 7 0 31 24 23 16 15 8 7 0
S 0 1 1 1 0 0 0 0 S
SLAVE ADDRESS MOST SIGNIFICANT LESS SIGNIFICANT BYTE 3 (MOST BYTE 2 OF REGISTER BYTE 1 OF REGISTER BYTE 0 (LESS
8 BITS OF REGISTER 8 BITS OF REGISTER SIGNIFICANT) SIGNIFICANT) OF
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ADDRESS ADDRESS OF REGISTER REGISTER
10193-075
ACK GENERATED
BY ADE7880
15 8 7 0
S 0 1 1 1 0 0 0 0
ACK
ACK
8 BITS OF REGISTER 8 BITS OF REGISTER
ADDRESS ADDRESS
ACK GENERATED
BY ADE7880
ACKNOWLEDGE
GENERATED BY
MASTER
NOACK
START
STOP
31 24 23 16 15 8 7 0
ACK
ACK
ACK
S 0 1 1 1 0 0 0 1 S
10193-076
ACK GENERATED
BY ADE7880
15 8 7 0
S 0 1 1 1 0 0 0 0
ACK
ACK
ACK GENERATED
BY ADE7880
ACKNOWLEDGE
GENERATED BY
MASTER
NOACK
START
STOP
31 24 7 0 31 24 7 0
ACK
ACK
ACK
ACK
S 0 1 1 1 0 0 0 1 S
ACK GENERATED
BY ADE7880
10193-078
SS SS
are sent, if the master acknowledges the last byte, the ADE7880
increments the pointer by one location to position it at the next Figure 106. Connecting ADE7880 SPI with an SPI Device
register and begins to send it out byte by byte, most significant SPI Read Operation
bit first. If the master acknowledges the last byte, the ADE7880
increments the pointer again and begins to send data from the The read operation using the SPI interface of the ADE7880
next register. The process continues until the master ceases to initiates when the master sets the SS/HSA pin low and begins
generate an acknowledge at the last byte of the register and then sending one byte, representing the address of the ADE7880, on
generates a stop condition. It is recommended to not allow the MOSI line. The master sets data on the MOSI line starting
locations greater than 0xE89F, the last location of the harmonic with the first high-to-low transition of SCLK. The SPI of the
calculations registers. ADE7880 samples data on the low-to-high transitions of SCLK.
The most significant seven bits of the address byte can have any
SPI-Compatible Interface
value, but as a good programming practice, it is recommended
The SPI of the ADE7880 is always a slave of the communication they be different from 0111000b, the seven bits used in the I2C
and consists of four pins (with dual functions): SCLK/SCL, protocol. Bit 0 (read/write) of the address byte must be 1 for a
MOSI/SDA, MISO/HSD, and SS/HSA. The functions used in read operation. Next, the master sends the 16-bit address of the
the SPI-compatible interface are SCLK, MOSI, MISO, and SS. register that is read. After the ADE7880 receives the last bit of
The serial clock for a data transfer is applied at the SCLK logic address of the register on a low-to-high transition of SCLK, it
input. All data transfer operations synchronize to the serial begins to transmit its contents on the MISO line when the next
clock. Data shifts into the ADE7880 at the MOSI logic input SCLK high-to-low transition occurs; thus, the master can sample
on the falling edge of SCLK and the ADE7880 samples it on the data on a low-to-high SCLK transition. After the master
the rising edge of SCLK. Data shifts out of the ADE7880 at receives the last bit, it sets the SS and SCLK lines high and the
the MISO logic output on a falling edge of SCLK and can be communication ends. The data lines, MOSI and MISO, go into
sampled by the master device on the raising edge of SCLK. The a high impedance state. See Figure 107 for details of the SPI
most significant bit of the word is shifted in and out first. The read operation.
maximum serial clock frequency supported by this interface
is 2.5 MHz. MISO stays in high impedance when no data is
transmitted from the ADE7880. See Figure 106 for details of the
SCLK
15 14 1 0
10193-079
MISO REGISTER VALUE
SS
SCLK
REGISTER
MOSI ADDRESS
0 0 0 0 0 0 0 1
31 0 31 0
10193-080
MISO REGISTER 0 REGISTER n
VALUE VALUE
SPI Read Operation of Harmonic Calculations Registers lines, MOSI and MISO, go into a high impedance state. See
The registers containing the harmonic calculation results are Figure 108 for details of the SPI read operation of harmonic
located starting at Address 0xE880 and are all 32-bit width. calculations registers.
They can be read in two ways: one register at a time (see the SPI SPI Write Operation
Read Operation section for details) or multiple consecutive The write operation using the SPI interface of the ADE7880
registers at a time in a burst mode. The burst mode initiates initiates when the master sets the SS/HSA pin low and begins
when the master sets the SS/HSA pin low and begins sending sending one byte representing the address of the ADE7880 on
one byte, representing the address of the ADE7880, on the the MOSI line. The master sets data on the MOSI line starting
MOSI line. The address is the same address byte used for with the first high-to-low transition of SCLK. The SPI of the
reading only one register. The master sets data on the MOSI line ADE7880 samples data on the low-to-high transitions of SCLK.
starting with the first high-to-low transition of SCLK. The SPI The most significant seven bits of the address byte can have any
of the ADE7880 samples data on the low-to-high transitions of value, but as a good programming practice, it is recommended
SCLK. Next, the master sends the 16-bit address of the first they be different from 0111000b, the seven bits used in the I2C
harmonic calculations register that is read. After the ADE7880 protocol. Bit 0 (read/write) of the address byte must be 0 for a
receives the last bit of the address of the register on a low-to-
write operation. Next, the master sends the 16-bit address of the
high transition of SCLK, it begins to transmit its contents on the
register that is written and the 32-, 16-, or 8-bit value of that
MISO line when the next SCLK high-to-low transition occurs;
register without losing any SCLK cycle. After the last bit is
thus, the master can sample the data on a low-to-high SCLK
transmitted, the master sets the SS and SCLK lines high at the
transition. After the master receives the last bit of the first
end of the SCLK cycle and the communication ends. The data
register, the ADE7880 sends the harmonic calculations register
lines, MOSI and MISO, go into a high impedance state. See
placed at the next location and so forth until the master sets the
Figure 109 for details of the SPI write operation.
SS and SCLK lines high and the communication ends. The data
SCLK
15 14 1 0 31 30 1 0
10193-081
MOSI REGISTER ADDRESS REGISTER VALUE
0 0 0 0 0 0 0 0
HSA SS
progress. When a communication is executed, HSA is low when
Figure 110. Connecting the ADE7880 HSDC with an SPI the 32-bit or 8-bit packages are transferred, and it is high during
the gaps. When HSAPOL is 1, the HSA function of the SS/HSA
The HSDC communication is managed by the HSDC_CFG
pin is active high during the communication. This means that
register (see Table 52). It is recommended to set the HSDC_CFG
HSA stays low when no communication is in progress. When a
register to the desired value before enabling the port using Bit 6
communication is executed, HSA is high when the 32-bit or
(HSDCEN) in the CONFIG register. In this way, the state of
8-bit packages are transferred, and it is low during the gaps.
various pins belonging to the HSDC port do not take levels incon-
sistent with the desired HSDC behavior. After a hardware reset Bits[7:6] of the HSDC_CFG register are reserved. Any value
or after power-up, the MISO/HSD and SS/HSA pins are set high. written into these bits does not have any consequence on HSDC
behavior.
Bit 0 (HCLK) in the HSDC_CFG register determines the serial
clock frequency of the HSDC communication. When HCLK is
0 (the default value), the clock frequency is 8 MHz. When HCLK
HSCLK
31 0 31 0 31 0 31 0
HSA
Figure 111. HSDC Communication for HGAP = 0, HXFER[1:0] = 00, and HSAPOL = 0; HSIZE Is Irrelevant
31 0 31 0 31 0 31 0
HSD IAVW (32-BIT) VAWV (32-BIT) IBWV (32-BIT) CFVAR (32-BIT)
7 HCLK 7 HCLK
CYCLES CYCLES
10193-084
HSA
Figure 112. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
HSCLK
31 24 23 16 15 8 7 0
HSD IAVW (BYTE 3) IAVW (BYTE 2) IAVW (BYTE 1) CFVAR (BYTE 0)
7 HCLK 7 HCLK
CYCLES CYCLES
10193-085
HSA
Figure 113. HSDC Communication for HSIZE = 1, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0
ADE7880 QUICK SETUP AS ENERGY METER 7. Enable the data memory RAM protection by writing 0xAD
to an internal 8-bit register located at Address 0xE7FE
An energy meter is usually characterized by the nominal followed by a write of 0x80 to an internal 8-bit register
current In, nominal voltage Vn, nominal frequency fn, and the located at Address 0xE7E3.
meter constant MC. 8. Read back all data memory RAM registers to ensure that
To quickly set up the ADE7880, execute the following steps: they initialized with the desired values. If one or more
1. Select the PGA gains in the phase currents, voltages and registers did not initialize correctly, disable the protection by
neutral current channels: Bits[2:0] (PGA1), Bits[5:3] writing 0xAD to an internal 8-bit register at Address 0xE7FE,
(PGA2) and Bits[8:6] (PGA3) in the Gain register. followed by a write of 0x00 to an internal 8-bit register located
at Address 0xE7E3. Reinitialize the registers, and write the
2. If Rogowski coils are used, enable the digital integrators in the
last register in the queue three times. Enable the write
phase and neutral currents: Bit 0 (INTEN)set to 1 in the protection by writing 0xAD to an internal 8-bit register
CONFIG register. Initialize the DICOEFF register to 0xFF8000
located at Address 0xE7FE, followed by a write of 0x80 to
before setting the INTEN bit in the CONFIG register.
an internal 8-bit register located at Address 0xE7E3.
3. If fn is between 55 Hz and 66 Hz, set Bit 14 (SELFREQ) in
9. Start the DSP by setting Run = 1.
the COMPMODE register.
10. Read the energy registers xWATTHR, xVAHR, xFWATTHR,
4. Initialize all the other data memory RAM registers. Write
and xFVARHR to erase their content and start energy
the last register in the queue three times to ensure that its accumulation from a known state.
value is written into the RAM.
11. Enable the CF1, CF2, and CF3 frequency converter outputs
5. Initialize the WTHR, VARTHR, VATHR, VLEVEL and
by clearing bits 9, 10, and 11 (CF1DIS, CF2DIS, and
VNOM registers based on Equation 26, Equation 37,
CF3DIS) to 0 in the CFMODE register.
Equation 44, Equation 22, and Equation 42, respectively.
For a quick setup of the ADE7880 harmonic calculations, see the
6. Initialize CF1DEN, CF2DEN, and CF3DEN based on
Recommended Approach to Managing Harmonic Calculations
Equation 49.
section.
C3 C4
4.7µF 0.22µF
C1 C2 C5 C6
4.7µF 0.22µF 0.1µF 10µF
24 5 26 U1
VDD
AVDD
DVDD
2 C7 C10
PM0 0.1µF 4.7µF
3 PM1 17
4 REFIN/OUT
RESET 28
7 IAP CLKOUT
C8 Y1
16.384MHz
8 IAN
9 29 20pF R1
2
IBP IRQ0
10193-214
12 IBN 32 5MΩ
13 IRQ1 C9 1
ICP 20pF
14 ICN 33
15 CF1 Figure 115. ADE7880 Top Layer Printed Circuit Board
INP 34
16 INN CF2
18 35
VN CF3/HSCLK
23 VAP
The exposed pad of the ADE7880 is soldered to an equivalent
22 MISQ/HSD 37
19
VBP 39 pad on the PCB. The AGND and DGND traces of the ADE7880
VCP SS/HSA
27
36
CLKIN are then routed directly into the PCB pad.
SCLK/SCL
38 MOSI/SDA
25 AGND
6 DGND
NC
surrounding as much as possible the crystal traces.
1
10
11
21
30
31
40
20
10193-213
ADE7880ACPZ
The recommended typical value of total capacitance at each It is also recommended that a 5 MΩ resistor be attached in
clock pin, CLKIN and CLKOUT, is 24 pF, which means that parallel to the crystal, as shown in Figure 117.
CL2
Total Capacitance = CP1 + CL1 = CP2 + CL2 = 24 pF
CLKIN GND
Crystal manufacturer data sheets specify the load capacitance CP2
value. A total capacitance of 24 pF per clock pin is recommended; ADE7880 IC 5MΩ 16.384MHz CRYSTAL
therefore, select a crystal with a 12 pF load capacitance. In CP1
CLKOUT
addition, when selecting the ceramic capacitors, CL1 and CL2,
10193-216
GND
the parasitic capacitances, CP1 and CP2, on the crystal pins of CL1
the IC must be taken into account. Thus, the values of CL1 and Figure 117. Crystal Circuit
CL2 must be based on the following expression:
ADE7880 EVALUATION BOARD
CL1 = CL2 = 2 × Crystal Load Capacitance − CP1
An evaluation board built upon the ADE7880 configuration is
where CP1 = CP2. available. Visit www.analog.com/ADE7880 for details.
For example, if a 12 pF crystal is chosen and the parasitic capaci- DIE VERSION
tances on the clock pins are CP1 = CP2 = 2 pF, the ceramic capacitors
that must be used in the crystal circuit are CL1 = CL2 = 22 pF. The register named version identifies the version of the die. It is
an 8-bit, read-only register located at Address 0xE707.
SILICON ANOMALY
This anomaly list describes the known issues with the ADE7880 silicon identified by the Version register (Address 0xE707) being equal to 1.
Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended
workarounds outlined here.
FUNCTIONALITY ISSUES
Table 26. LAST_ADDR and LAST_RWDATA_x Registers Show Wrong Value in Burst SPI Mode [er001, Version = 1 Silicon]
Background When any ADE7880 register is read using SPI or I2C communication, the address is stored in the LAST_ADDR register and
the data is stored in the respective LAST_RWDATA_x register.
Issue When the waveform registers located between Address 0xE880 and Address 0xE89F are read using burst SPI mode, the
LAST_ADDR register contains the address of the register incremented by 1 and the LAST_RWDATA_x register contains the
data corresponding to the faulty address in the LAST_ADDR register. The issue is not present if the I2C communication is used.
Workaround After accessing the waveform registers in burst SPI mode, perform another read/write operation elsewhere before using
the communication verification registers.
Related Issues None.
Table 27. To Obtain Best Accuracy Performance, Internal Setting Must Be Changed [er002, Version = 1 Silicon]
Background Internal default settings provide best accuracy performance for ADE7880.
Issue It was found that if a different setting is used, the accuracy performance can be improved.
Workaround To enable a new setting for this internal register, execute three consecutive write operations:
The first write operation is to an 8-bit location: 0xAD is written to Address 0xE7FE.
The second write operation is to a 16-bit location: 0x3BD is written to Address 0xE90C.
The third write operation is to an 8-bit location: 0x00 is written to Address 0xE7FE.
The write operations must be executed consecutively without any other read/write operation in between. As a
verification that the value was captured correctly, a simple 16-bit read of Address 0xE90C shows the 0x3BD value.
Related Issues None.
Table 28. High-Pass Filter Cannot be Disabled in Phase C Voltage Data Path [er003, Version = 1 Silicon]
Background When Bit 0 (HPFEN) of the CONFIG3 register is 0, all high-pass filters (HPF) in the phase and neutral currents and phase
voltages data paths are disabled (see the ADE7880 data sheet for more information about the current channel HPF and
the voltage channel HPF).
Issue The HPF in the Phase C voltage data path remains enabled independent of the state of Bit HPFEN.
Workaround There is no workaround.
Related Issues None.
Table 29. No Load Condition Does Not Function as Defined [er004, Version = 1 Silicon]
Background Total active power no load uses the total active energy and the apparent energy to trigger the no load condition. If
neither total active energy nor apparent energy are accumulated for a time indicated in the respective APNOLOAD and
VANOLOAD unsigned, 16-bit registers, the no load condition is triggered, the total active energy of that phase is not
accumulated and no CF pulses are generated based on the total active energy.
Fundamental active and reactive powers no load uses the fundamental active and reactive energies to trigger the no load
condition. If neither the fundamental active energy nor the fundamental reactive energy are accumulated for a time
indicated in the respective APNOLOAD and VARNOLOAD unsigned 16-bit registers, the no load condition is triggered, the
fundamental active and reactive energies of that phase are not accumulated, and no CF pulses are generated based on
the fundamental active and reactive energies.
Issue When the total active energy on Phase x (x = A, B, or C) is lower than APNOLOAD and the apparent energy is above
VANOLOAD, the no load condition is not triggered. It was observed that although CF pulses continue to be generated, the
Bit 0 (NLOAD) and Bits[2:0] (NLPHASE) in STATUS1 and PHNOLOAD registers continue to be cleared to 0 indicating an out
of no load condition, the xWATTHR register stops accumulating energy.
It was observed that the fundamental active energy no load functions independently of the fundamental reactive energy
no load. If, for example, the fundamental active energy is below APNOLOAD and the fundamental reactive energy is
above VARNOLOAD, both energies continue to accumulate because the phase is out of no load condition. Instead, the CF
pulses, based on the phase fundamental active energy, are not generated and the FWATTHR registers are blocked, while
the CF pulses, based on the fundamental reactive energy, are generated. Thus, the FVARHR registers continue to
accumulate and the Bit 1 (FNLOAD) in the STATUS1 register and Bits[5:3] (FNLPHASE) in the PHNOLOAD register are
cleared to 0. IRQ
Workaround The workaround suggested here uses the VANOLOAD register only to determine the no-load condition.
1. Clear VARNOLOAD and APNOLOAD to 0.
2. Set VANOLOAD at desired value.
3. When the apparent energy on any one of the phases becomes less than VANOLOAD, or when it has just become
larger than VANOLOAD, Bit 2 (VANLOAD) in the STATUS1 register is set to 1. The corresponding interrupt can be
observed via the IRQ pin if the Bit 2 in MASK1 register is set to 1. The IRQ pin goes low whenever any of the phases
enters or leaves the no-load condition.
4. To find the phase that triggered the interrupt, read the PHNOLOAD register immediately. One of the bits
VANLPHASE [2:0] changes state, indicating that the particular phase has either entered or left no-load condition.
5. If the particular phase has entered no-load condition, remove the contribution of the energies of that phase to the
CFx output by clearing the appropriate TERMSEL_x bits of the COMPMODE register. If that particular phase has left
no-load condition, include the contribution of the energies of that phase to the CFx output by setting the
appropriate TERMSEL_x bits of the COMPMODE register.
6. Write 1 to the VANLOAD bit of the STATUS1 register, to clear the status bit and to bring the IRQ pin high.
7. If the phase comes out of no-load condition, read with reset all the energy registers to flush out the unnecessary
values in the signal path before taking further energy measurements. This can be done by reading the energy
registers while the RSTREAD bit (Bit 6) is set to 1 in the LCYCMODE register.
8. Whenever the IRQ pin goes low again, perform the actions starting from Step 3 to service the interrupt.
Related Issues None.
REGISTERS LIST
Table 30. Registers Located in DSP Data Memory RAM
Register Bit Bit Length During
Address Name R/W 1 Length Communication 2 Type 3 Default Value Description
0x4380 AIGAIN R/W 24 32 ZPSE S 0x000000 Phase A current gain adjust.
0x4381 AVGAIN R/W 24 32 ZPSE S 0x000000 Phase A voltage gain adjust.
0x4382 BIGAIN R/W 24 32 ZPSE S 0x000000 Phase B current gain adjust.
0x4383 BVGAIN R/W 24 32 ZPSE S 0x000000 Phase B voltage gain adjust.
0x4384 CIGAIN R/W 24 32 ZPSE S 0x000000 Phase C current gain adjust.
0x4385 CVGAIN R/W 24 32 ZPSE S 0x000000 Phase C voltage gain adjust.
0x4386 NIGAIN R/W 24 32 ZPSE S 0x000000 Neutral current gain adjust.
0x4387 Reserved R/W 24 32 ZPSE S 0x000000 Do not write this location for proper operation.
0x4388 DICOEFF R/W 24 32 ZPSE S 0x0000000 Register used in the digital integrator algorithm.
If the integrator is turned on, it must be set at
0xFF8000. In practice, it is transmitted as 0xFFF8000.
0x4389 APGAIN R/W 24 32 ZPSE S 0x000000 Phase A power gain adjust.
0x438A AWATTOS R/W 24 32 ZPSE S 0x000000 Phase A total active power offset adjust.
0x438B BPGAIN R/W 24 32 ZPSE S 0x000000 Phase B power gain adjust.
0x438C BWATTOS R/W 24 32 ZPSE S 0x000000 Phase B total active power offset adjust.
0x438D CPGAIN R/W 24 32 ZPSE S 0x000000 Phase C power gain adjust.
0x438E CWATTOS R/W 24 32 ZPSE S 0x000000 Phase C total active power offset adjust.
0x438F AIRMSOS R/W 24 32 ZPSE S 0x000000 Phase A current rms offset.
0x4390 AVRMSOS R/W 24 32 ZPSE S 0x000000 Phase A voltage rms offset.
0x4391 BIRMSOS R/W 24 32 ZPSE S 0x000000 Phase B current rms offset.
0x4392 BVRMSOS R/W 24 32 ZPSE S 0x000000 Phase B voltage rms offset.
0x4393 CIRMSOS R/W 24 32 ZPSE S 0x000000 Phase C current rms offset.
0x4394 CVRMSOS R/W 24 32 ZPSE S 0x000000 Phase C voltage rms offset.
0x4395 NIRMSOS R/W 24 32 ZPSE S 0x000000 Neutral current rms offset.
0x4396- Reserved N/A N/A N/A N/A 0x000000 Do not write these memory locations for proper
0x4397 operation.
0x4398 HPGAIN R/W 24 32 ZPSE S 0x000000 Harmonic powers gain adjust.
0x4399 ISUMLVL R/W 24 32 ZPSE S 0x000000 Threshold used in comparison between the sum
of phase currents and the neutral current.
0x439A- Reserved N/A N/A N/A N/A 0x000000 Do not write these memory locations for proper
0x439E operation.
0x439F VLEVEL R/W 28 32 ZP S 0x0000000 Register used in the algorithm that computes the
fundamental active and reactive powers. Set this
register according to Equation 22 for proper
functioning of fundamental powers and harmonic
computations.
0x43A0- Reserved N/A N/A N/A N/A 0x000000 Do not write these memory locations for proper
0x43A1 operation.
0x43A2 AFWATTOS R/W 24 32 ZPSE S 0x000000 Phase A fundamental active power offset adjust.
0x43A3 BFWATTOS R/W 24 32 ZPSE S 0x000000 Phase B fundamental active power offset adjust.
0x43A4 CFWATTOS R/W 24 32 ZPSE S 0x000000 Phase C fundamental active power offset adjust.
0x43A5 AFVAROS R/W 24 32 ZPSE S 0x000000 Phase A fundamental reactive power offset adjust.
0x43A6 BFVAROS R/W 24 32 ZPSE S 0x000000 Phase B fundamental reactive power offset adjust.
0x43A7 CFVAROS R/W 24 32 ZPSE S 0x000000 Phase C fundamental reactive power offset adjust.
0x43A8 AFIRMSOS R/W 24 32 ZPSE S 0x000000 Phase A fundamental current rms offset.
0x43A9 BFIRMSOS R/W 24 32 ZPSE S 0x000000 Phase B fundamental current rms offset.
0x43AA CFIRMSOS R/W 24 32 ZPSE S 0x000000 Phase C fundamental current rms offset.
0x43AB AFVRMSOS R/W 24 32 ZPSE S 0x000000 Phase A fundamental voltage rms offset.
0x43AC BFVRMSOS R/W 24 32 ZPSE S 0x000000 Phase B fundamental voltage rms offset.
0x43AD CFVRMSOS R/W 24 32 ZPSE S 0x000000 Phase C fundamental voltage rms offset.
0x43AE HXWATTOS R/W 24 32 ZPSE S 0x000000 Active power offset adjust on harmonic X
(see Harmonics Calculations section for details).
1
R is read, and W is write.
2
32 ZP = 24- or 20-bit signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE = 24-bit signed register that
is transmitted as a 32-bit word sign extended to 32 bits. 16 ZP = 10-bit unsigned register that is transmitted as a 16-bit word with six MSBs padded with 0s.
3
U is unsigned register, and S is signed register in twos complement format.
4
N/A is not applicable.
Table 45. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)
Bit Mnemonic Default Value Description
9:0 PHCALVAL 0000000000 If the current leads the voltage, these bits can vary between 0 and 383.
If the current lags the voltage, these bits can vary between 512 and 575.
If the PHCALVAL bits are set with numbers between 384 and 511, the compensation behaves
like PHCALVAL set between 256 and 383.
If the PHCALVAL bits are set with numbers between 576 and 1023, the compensation
behaves like PHCALVAL bits set between 384 and 511.
15:10 Reserved 000000 Reserved. These bits do not manage any functionality.
OUTLINE DIMENSIONS
6.10 0.30
6.00 SQ 0.23
PIN 1 5.90 0.18
INDICATOR PIN 1
31 40
INDICATOR
30 1
0.50
BSC 4.45
EXPOSED
PAD 4.30 SQ
4.25
21 10
11
0.45 20
0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.35 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE
05-06-2011-A
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
ADE7880ACPZ −40°C to +85°C 40-Lead LFCSP_WQ CP-40-10
ADE7880ACPZ-RL −40°C to +85°C 40-Lead LFCSP_WQ, 13” Tape and Reel CP-40-10
EVAL-ADE7880EBZ Evaluation Board
1
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).