LMS7002M DataSheet 2 2r0 PDF
LMS7002M DataSheet 2 2r0 PDF
RXLNAL
RXINL
ADC
LimeLightTM Digital IQ Interface, Port 2
RXLNAH
RXINH RXMIX RXTIA RXLPF RXPGA
RXLNAW ADC
RXINW
TX BB RXOUTSW
LPF
RF RX LO RX RXOUTI, RXOUTQ
RSSI Chain Synthesizer
TX BB RXOUTI, RXOUTQ
LPF RXOUTSW
RXLNAL
RXINL
ADC
Transceiver Signal Processor (TSP)
RXLNAH
RXINH RXMIX RXTIA RXLPF RXPGA
RXLNAW ADC
RXINW
RF Micro
SPI Clock PLL
RSSI Controller DLB
Connects to LNA TX BB
TXINI, TXINQ
output in RF Loop Back LPF
Switch mode
LimeLightTM Digital IQ Interface, Port 1
TXOUT1
DAC
Power
Det. TXPAD
RX BB TXMIX TXLPF
Power TXPAD
Det.
DAC
TXOUT2
TXOUT1
DAC
Power
Det.
TXPAD
RX BB TXMIX TXLPF
Power TXPAD
Det.
DAC
TXOUT2
LMS7002M 2
LMS7002M – FPRF MIMO Transceiver IC
The functionality of the LMS7002M is fully controlled by a set of internal TXMIX TXPAD
registers which can be accessed through a serial port and rapidly
reprogrammed on the fly for advanced system architectures.
TXINQ
TXOUT2
In order to enable full duplex operation, LMS7002M contains two
separate synthesisers (TXPLL, RXPLL) both driven from the same
reference clock source PLLCLK.
TXPLL
TX GAIN CONTROL
The LMS7002M transmitter has two programmable gain stages, where Figure 2: TX analog/RF gain control architecture
the TSP provides digital gain control and the TXPAD gives
programmable gain of the RF signal.
LMS7002M 3
LMS7002M – FPRF MIMO Transceiver IC
RX GAIN CONTROL
The LMS7002M receiver has three gain control elements, RXLNA, RXLNAL
RXTIA, and RXPGA. RXINL
RXOUTI
SYNTHESISERS
The LMS7002M has two low phase noise synthesizers to enable full 0º
in Figure 4. The same reference frequency is used for both synthesizers VCO
and is flexible between 10 to 52 MHz clock frequencies. The
/N
synthesizers produce complex outputs with suitable levels to drive IQ
mixers in both the TX and the RX paths. The transmit PLL could also be
routed via switches to the receive PLL so as to offer phase coherent
operation in TDD mode. ∆∑
The LMS7002M can accept clipped sine as well as CMOS level signals NINT, NFRAC
for the PLL reference clock. Both DC and AC coupling are supported as
shown in Figure 5. Internal buffer self-biasing must be enabled for AC Figure 4: PLL architecture
coupling mode. The PLL reference clock input can also be low voltage
CMOS (<1.2V) which is implemented by lowering the clock buffer
supply.
VDD VDD
PLLCLK
PLLCLK
External External
CLKBUF CLKBUF
Reference Reference
VSS VSS
(a) (b)
Figure 5: PLL reference clock input buffer, (a) DC coupled (b) AC coupled
LMS7002M 4
LMS7002M – FPRF MIMO Transceiver IC
RF PORTS illustrate the analog tunable filter bandwidths. The digital filters provide
a lower pass band of 0.7 MHz. Using such mixed mode filtering (digital
LMS7002M has two transmitter outputs and three receiver inputs for and analog) provides 60 dB anti alias performance and 40 dB adjacent
each of the dual transceivers. channel rejection as the worst case scenario. Obviously, the lower pass
band and/or higher decimation will give better results. The TX filtering
The optimum transmitter output load is 40Ω differential at the output chain works in the same manner.
pads. The final stage amplifiers are open drain and require +1.8V
voltage supply.
RXLPFH
RXTIA
RXLPFL
IQ imbalance (gain and phase error) in the transmitter and receiver are
due to imbalances in the LO generation circuitry and also caused by
amplitude differences in the I/Q chains. Correcting the transmit and the
receive IQ quadrature errors is a two-step process. The transmit IQ
imbalances are corrected first by using the power/envelop detector
(PED) and bypassing the receiver. The PED output is applied to the
ADCs as shown in Figure 1. The PED will generate a tone at twice the
frequency of the applied baseband tone if an image is present. This
information can be used by the digital modem to apply amplitude and
phase corrections to minimize IQ imbalance in the system. After the IQ
Figure 10: Analog RX LPFH amplitude response quadrature error is minimized in the transmitter, then the receiver can
be corrected. This is achieved by looping back the transmit signal from
the TXPAD output and passing it through the receive chain circuitry.
The signal is then sampled by the ADCs and analyzed in the digital
modem. After being analyzed in the digital domain the proper post-
LMS7002M 6
LMS7002M – FPRF MIMO Transceiver IC
The TSP is placed between the data converters and the LimeLight™
digital IQ interface as shown in Figure 12. Functionally, the RX and TX
parts of the TSP are similar, as shown in Figure 13 and 14, Figure 12: TSP part of the LMS7002M
respectively.
RXNCO
IQ Gain IQ Phase RX DC G. P. G. P. G. P.
RXI Decimation RYI
Corr Corr Corr FIR 1 FIR 2 FIR 3
AGC
CMIX RSSI
IQ Gain IQ Phase RX DC G. P. G. P. G. P.
RXQ Decimation RYQ
Corr Corr Corr FIR 1 FIR 2 FIR 3
TX DC IQ Phase IQ Gain G. P. G. P. G. P.
TYI INVSINC Interpolation TXI
Corr Corr Corr FIR 3 FIR 2 FIR 1
CMIX
TX DC IQ Phase IQ Gain G. P. G. P. G. P.
TYQ INVSINC Interpolation TXQ
Corr Corr Corr FIR 3 FIR 2 FIR 1
TXNCO
The interpolation block within the TXTSP takes IQ data from the BB Inverse sinc filters (INVSINC) within the TXTSP chain compensate for
modem and increases the data sample rate. The advantages of having sinx/x amplitude roll off imposed by the DACs themselves.
interpolation are as follows. For narrow band systems (GSM/EDGE) or
even moderately broad band (WCDMA, CDMA2000) modulation The Tx DC Corr block is used to cancel residual DC offset of TXLPF. It
standards, the BB modem does not need to interpolate IQ data to the is also used to cancel TX LO leakage feed-through as mentioned
target system clock. The base band can provide output data at a much earlier.
lower sample rate saving on power at the digital interface. Having a low
data rate interface also simplifies the PCB design. However, the
LMS7002M 7
LMS7002M – FPRF MIMO Transceiver IC
There are three sources of the DC component at the RX output. These value to minimize the unwanted side band component. The BB modem
are the residual DC offset of the RXVGAs and RXLPF, RX LO leakage can also use the following approximation formula:
feed-through and second order distortion (IP2). The Rx DC Corr blocks
compensate for all of these sources of offset. The block is implemented
as a real time tracking loop so any change of the RX DC due to either tan
2 2
the signal level change, or due to RX gain change as well as any
temperature effect will be tracked and cancelled automatically.
when is small, which is usually the case. The IQ phase corrector of
the LMS7002M is designed to correct an IQ phase error up to +/- 20o.
The IQ Gain Corr and IQ Phase Corr blocks correct IQ imbalance in
both TXTSP and RXTSP in order to minimize the level of unwanted side
band (image) component.
Iin Iout
IQ GAIN CORRECTION
This block implements the following equation: Figure 16: Implementation of IQ phase correction
Iout Iin G _ I .
Qout Qin G _ Q TX DC CORRECTION
DC offset correction in the TXTSP path is achieved by using the
Corresponding hardware is given in Figure 15. G_I and G_Q are
following equation:
programmable correction factors which are altered by the BB modem to
minimize any unwanted side band component. The BB modem can
Iout Iin DC _ I .
combine IQ gain correction and digital gain control using the same
module by calculating G_I and G_Q in the following way: Qout Qin DC _ Q
G _ I G _ I _ corr * G _ digi , Here, DC_I and DC_Q are programmable DC offset correction
G _ Q G _ Q _ corr * G _ digi parameters which the BB modem should adjust to minimize the TX LO
leakage feed-through. This tuning should be performed after executing
where G_I_corr and G_Q_corr are IQ gain correction factors and G_digi TXLPF DC offset cancellation. The hardware implementation is given
is the desired digital gain. below.
Iin Iout
Iin Iout
DC_I
G_I
DC_Q
G_Q
Qin Qout
Qin Qout
The value of tan(/2) should be stored in the configuration register as a The only programmable parameter in the loop is DCAVG which defines
programmable correction parameter. The BB modem should adjust this the averaging window size.
LMS7002M 8
LMS7002M – FPRF MIMO Transceiver IC
QIN IIN
Iin Iout
-
COMB
INCO
+
DCAVG
IOUT
-/+
COMB
- QNCO
Qin Qout
+/-
QOUT
Figure 18: RX DC offset correction module
+
INVERSE SINC FILTER
The inverse sinc filter compensates for sinx/x amplitude roll off imposed Figure 21: Complex mixer
by the DAC. The filter is designed to compensate from DC to 0.35fs
where fs is the DAC sampling frequency. Impulse and amplitude
NUMERICALLY CONTROLLED OSCILLATOR
responses are shown in Figure 19 and Figure 20.a respectively. Figure
20.b plots the equivalent DAC amplitude response with the inverse sinc The quadrature carrier signal, required to implement low digital IF, is
function compensation applied. The in band (0 - 0.35fs ) amplitude ripple generated by the local NCO. The internal NCO design is based on a
is less than +/- 0.04 dB. DDFS (Direct Digital Frequency Synthesis) algorithm with a 32-bit
phase accumulator, 19-bit phase precision and provides 14 bit digital
sine and cosine waveforms with the spurious performance better than
h( 0) = 0.0101318 = h( 4) –114 dBc.
h( 1) = -0.0616455 = h( 3)
h( 2) = 0.855469 The carrier frequency fc generated by the NCO is defined using the
following formula:
-0.5
where fcw represents the decimal value of the 32-bit frequency control
word and fclk is the NCO clock frequency.
-1
(a)
Magnitude [dB]
-1.5 As shown in Figure 22, carrier phase offset can also be adjusted using
the 16-bit configuration parameter pho. The carrier phase shift is
-2 calculated as follows:
-2.5
(b)
pho
2 ,
-3 216
-3.5
with pho being the decimal value stored in the carrier phase offset
-4
register.
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency [f/fs]
Sine
Figure 20: INVSINC (a) and equivalent DAC (b) amplitude response LUT
QNCO
COMPLEX MIXER
Cosine
INCO
The complex mixer used in the RXTSP and TXTSP is designed to LUT
LMS7002M 9
LMS7002M – FPRF MIMO Transceiver IC
20
K 1, 2, 4, 8 ,16 or 32 . 0
Interpolation by 1 is achieved by bypassing all the interpolation filters.
The filters are designed to provide a wide signal pass band from DC to -20
fp where:
f -40
Magnitude [dB]
f p 0.27 clk , K = 2, 4, 8, 16, 32.
K -60
-80
MUX
Y
-140
Figure 23: Programmable rate interpolation implemented by half band 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
filters Frequency
MUX
h(12) = -0.0882454 = h(18)
MUX
MUX
MUX
MUX
Y
h(13) = 0 = h(17)
X
h(14) = 0.3119 = h(16)
h(15) = 0.5
Figure 28: Programmable rate decimation implemented by half band
filters
Figure 24: HB1 impulse response
Decimation ratio K can be programmed to be:
20
0 K 1, 2, 4, 8,16 or 32 .
-20
-60
interpolator i.e. pass band is:
-80
f
-100
f p 0.27 clk , K = 2, 4, 8, 16, 32,
-120
K
-140
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 alias suppression is better than –108 dB while in band amplitude
Frequency
distortion is negligible.
Figure 25: HB1 amplitude response
GENERAL PURPOSE FIR FILTERS
Only two different configurations are used within the filtering chain of The LMS7002M features general purpose filters 1 and 2, which are
Figure 23, HB1 and HB2. The impulse and amplitude response of HB1 based on a Multiply Accumulate (MAC) FIR architecture. They can
are shown in Figure 24 and Figure 25, respectively. The remaining implement up to a 40-tap filtering function and the coefficients are fully
three filters (HB2A, HB2B and HB2C) are all the same with their programmable via SPI. The hardware implementation does not impose
coefficients and amplitude response given in Figure 26 and Figure 27, the constraint for the filter impulse response to be symmetrical hence
respectively. The overall interpolator provides image suppression of the filter phase response can but does not need to be ideally linear.
better than –108 dB with negligible amplitude distortion (pass band Therefore, it can be used in general filtering, as well as nonlinear
ripple is less than10-5 dB). applications which can be used to implement phase equalization.
h( 0) = -0.00164032 = h(14) The filter coefficients are stored in five 8x16-bit internal memory banks
h( 1) = 0 = h(13) as two’s complement signed integers as shown in Figure 29 where L is
h( 2) = 0.0138855 = h(12) related to the filter length N as follows:
h( 3) = 0 = h(11)
h( 4) = -0.0630875 = h(10) N
h( 5) = 0 = h( 9) L .
h( 6) = 0.300842 = h( 8) 5
h( 7) = 0.5
Grey locations in Figure 29 highlight the memory registers which are set
Figure 26: HB2 impulse response to zero for 5L > N.
Evidently, the number of the filter taps N is limited by the size of the
coefficients memory to:
LMS7002M 10
LMS7002M – FPRF MIMO Transceiver IC
N 5 * 8 40 . After the loop gain stage, the error is integrated to construct the
digital VGAs gain control signal. Loop gain K is programmable via
The following relationship should be satisfied: SPI.
VGAs gain cannot be negative and should not be zero either,
LK , hence max(1,x) module is provided in the feedback path.
- I2 + Q2
MAX(1, X) Z-1 K/2N-1 COMB
error 2
L
+
N
K ADESIRED AVG
Memory Bank 0 Memory Bank 1 Memory Bank 4 QIN QOUT
N min a , b
(a) (b)
LMS7002M 11
LMS7002M – FPRF MIMO Transceiver IC
Figure 32: LimeLight™ port, JESD mode Timing diagrams for the TRXIQ DDR and SDR modes can be seen in
Figure 39 - Figure 42.
BBIC RFIC
MCLK MCLK_n BBIC RFIC
MCLK MCLK_n
FCLK FCLK_n
vcc vcc FCLK FCLK_n
TXNRX TXNRX_n gnd gnd
TXNRX TXNRX_n
ENABLE ENABLE_IQSEL_n
ENABLE ENABLE_IQSEL_n
DIQ[11:0] DIQ[11:0]_n
DIQ[11:0] DIQ[11:0]_n
tCP
MCLK_n ...
tCD tCD
FCLK_n ...
tHc tSc
TXNRX_n ...
tHc tSc tHc tSc
ENABLE_IQ_SEL_n ...
tDDtx
tSTARTtx = 2x tCP + tDDtx tStx tStx
tHtx tHtx
DIQ[11:0]_n XXX I1A Q1A I1B Q1B I2A Q2A I2B ...
MCLK_n ...
FCLK_n ...
tHc tSc
TXNRX_n ...
tHc tSc tHc tSc
ENABLE_IQ_SEL_n ...
tDDtx tFINISHtx = 2x tCP + tDDtx
DIQ[11:0]_n ... Q(k-2)B I(k-1)A Q(k-1)A I(k-1)B Q(k-1)B I(k)A Q(k)A I(k)B Q(k)B XXX
tCP
MCLK_n ...
tCD tCD
FCLK_n ...
tHc tSc
TXNRX_n ...
tHc tSc tHc tSc
ENABLE_IQ_SEL_n ...
tDDrx
tST ARTrx = 2x tCP - tCD + tDDrx tSrx tSrx
tRPRE tHrx tHrx
DIQ[11:0]_n X XX I1A Q1A I1B Q1B I2A Q2A I2B ...
Note: n = 1 for LimeLight Port 1, n = 2 for LimeLight Port 2.
Figure 37: Data path receive burst start (JESD207 mode)
LMS7002M 12
LMS7002M – FPRF MIMO Transceiver IC
MCLK_n ...
FCLK_n ...
tHc tSc
TXNRX_n ...
tHc tSc tHc tSc
ENABLE_IQ_SEL_n ...
tDDrx tFI NI SHrx = 2x tCP - tCD + tDDrx
tRPS T
DIQ[11:0]_n ... Q(k-2)B I(k-1)A Q(k-1)A I(k-1)B Q(k-1)B I(k)A Q(k)A I(k)B Q(k)B X XX
tSetup tSetup
tHold tHold
MCLK_n ... ...
DIQ[11:0]_n ... I(k-3)A Q(k-3)A I(k-3)B Q(k-3)B I(k-2)A Q(k-2)A I(k-2)B Q(k-2)B I(k-1)A Q(k-1)A I(k-1)B Q(k-1)B I(k)A Q(k)A ...
tCP
MCLK_n ... ...
tCD tCD
tSetup tSetup
tHold tHold
FCLK_n ... ...
DIQ[11:0]_n ... I(k-3)A Q(k-3)A I(k-3)B Q(k-3)B I(k-2)A Q(k-2)A I(k-2)B Q(k-2)B I(k-1)A Q(k-1)A I(k-1)B Q(k-1)B I(k)A Q(k)A ...
tSetup
tHold
MCLK_n ... ...
DIQ[11:0]_n ... I(k-3)A Q(k-3)A I(k-2)A Q(k-2)A I(k-1)A Q(k-1)A I(k)A ...
tCP
MCLK_n ... ...
tCD tCD
tSetup
tHold
FCLK_n ... ...
DIQ[11:0]_n ... I(k-3)A Q(k-3)A I(k-2)A Q(k-2)A I(k-1)A Q(k-1)A I(k)A ...
LMS7002M 13
LMS7002M – FPRF MIMO Transceiver IC
LMS7002M
1.8V – 3.3V
Implementing Low Voltage Digital IQ Interface DVDD
DIGPRVDD2 (W33)
DIGPRVDD2 (T32)
Digital IO buffers in LMS7002M are supplied using four pins (pin name - DIGPRVDD2 (H32)
IO Buffers
Supplies
DIGPRVDD2, pin ID - W33, T32, H32, AH30). All these pins must be DIGPRVDD2 (AH30)
supplied by the same supply DVDD. There is one additional supply pin DIGPRPOC (W31)
0 – DVDD CMOS
BASE BAND
Logic Levels
interface operation. MCLK_1
12
/ DIQ[11:0]_2
ENABLE_IQSEL_2
2nd Channel
TXNRX_2
Interface
FCLK_2
MCLK_2
LMS7002M 14
LMS7002M – MIMO Multi-Band Multi-Standard
Transceiver IC
Description All configuration registers are 16-bit wide. Write/read sequence consists
The functionality of the LMS7002M transceiver is fully controlled by a of 16-bit instruction followed by 16-bit data to write or read. MSB of the
set of internal registers which can be accessed through a serial port instruction bit stream is used as SPI command where CMD = 1 for write
interface. Both write and read SPI operations are supported. The serial and CMD = 0 for read. Next 4 bits are reserved (Reserved[3:0]) and
port can be configured to run in 3 or 4 wire mode with the following pins must be zeroes. Next 5 bits represent module address (Maddress[4:0])
used: since the LMS7002M configuration registers are divided into logical
blocks as shown in Table 11. The remaining 6 bits of the instruction are
SEN serial port enable, active low used to address particular registers (Reg[5:0]) within the block.
SCLK serial clock, positive edge sensitive Maddress and Reg compiles global 11-bit register address when
concatenated ((Maddress << 6) | Reg).
SDIO serial data in/out in 3 wire mode
serial data input in 4 wire mode
The write/read cycle waveforms are shown in Figure 44, Figure 45 and
SDO serial data out in 4 wire mode
Figure 46. Note that the write operation is the same for both 3-wire and
don’t care in 3 wire mode
4-wire modes. Although not shown in the figures, multiple write/read is
Serial port key features:
possible by repeating the instruction/data sequence while keeping SEN
low.
32 SPI clock cycles are required to complete a write operation.
32 SPI clock cycles are required to complete a read operation.
Write Operation
SDIO Don’t care 1 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Don’t care
LMS7002M 15
LMS7002M – FPRF MIMO Transceiver IC
Read Operation
SDIO Don’t care 0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Don’t care
Read instruction
SDO Don’t care D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Don’t care
Output Data
SDIO Don’t care 0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Don’t care
SDO
BASE BAND
Logic Levels
LMS7002M 16
LMS7002M – FPRF MIMO Transceiver IC
ON CHIP MICROCONTROLLER
SCLK bbSCLK SPI Switch trxSCLK
L
TR
ucSDOUT
Transceiver Part
ucSCLK
_C
ucSDIN
needs to implement a set of calibration, tuning and control functions to
ucSEN
ISW
get the best performance out of the transceiver. The on chip
SP
microcontroller unit (MCU) provides the option for independent control
mSPI
Micro
Controller
using code provided by Lime. This allows the LMS7002M to be LMS7002M
independent of the BB/DSP/FPGA and off-loads these devices. Users SDA SCL
can still implement full control in their preferred way by developing their
own code and/or bypassing on chip microcontroller.
EEPROM
MCU integration within the LMS7002M chip is shown in Figure 48. (Optional)
Since the chip communication to the outside world is done through SPI,
the MCU uses the same protocol hence the block mSPI (master SPI) is Figure 48: On chip microcontroller connection
placed in front of it. The MCU communicates to the transceiver circuitry
using the same SPI protocol as the BB processor itself. This is Specifications
implemented via ucSPI lines shown in Figure 48. There is two way
8-bit microcontroller.
communication between the MCU and BB via mSPI. The baseband can
trigger different calibration/tuning/control functions the MCU is Industry standard 8051 instruction set compatible.
programmed to perform. The MCU reports a success, failure or an error Running up to 60 MHz.
code back to the base band processor. Memory
o 8 KB SRAM program memory
In this architecture, the base band processor acts as master since it o 2 kB SRAM working memory
controls the whole chip, (transceiver as well as MCU). The base band o 256 B dual port RAM
processor also controls the SPI switch (via SPISW_CTRL control o All on chip, integrated.
bit/line of mSPI) i.e. taking control over the transceiver part or handing it
over to the MCU. The MCU acts as a slave processor. It can control the DATA CONVERTERS CLOCK GENERATION
transceiver only if the base band allows that via the SPI switch.
The clock generation circuit for the data converters is shown in Figure
The base band has full control over the chip including calibration, tuning 49. It shares the same reference clock input REFCLK with the RF
and control. It also can trigger the MCU for assistance. In this case, it synthesizers as specified in Table 1. The clock PLL then generates a
works in the following way: continuous frequency range centered around 2.5 GHz. The feed
forward divider (FFDIV) is programmable and capable of implementing
1. The base band sets the transceiver for the targets (TX LO any division ratio between Nmin, Nmax i.e. division can be:
frequency, RX LO frequency, TX gain, RX gain, …).
2. The base band hands over SPI control to the MCU by setting Nmin, Nmin+1, Nmin+2, … Nmax, where, Nmin=4, Nmax=512
SPISW_CTRL.
3. The base band triggers the function for the MCU to execute. There is a fixed divide by 4 within the ADC block hence clock division
4. The base band periodically checks to see if the MCU has finished on the DAC side to provide more flexibility. There is a MUX to connect
and for the status (success, failure, error code). either Fpll, or Fpll/M to either ADC or DAC Clocks. The other CLKMUX
output will be connected to the other data converter clock input.
MCU Boot Up and EEPROM Programming TSP blocks receive the same clock as the corresponding data
Two options are supported, one using external (off chip) EEPROM and converter, hence there is no need for complex non-power of two or
another without external EEPROM. fractional interpolation/decimation. TSP blocks have programmable
interpolation/decimation and generate MCLK clocks going back to the
Option A: Using external EEPROM base band processor via the LimeLight™ port.
1. The base band processor uploads 8 KB into the on chip program
memory. The circuit implements a continuous clock frequency range from 5 MHz
2. After receiving 8 KB, the MCU flushes program memory into to 320 MHz for the data converters. It is still possible to generate the
EEPROM. maximum DAC clock of 640 MHz, however it is not continuous in the
3. The base band resets the MCU. range of 320 MHz - 640 MHz.
4. The MCU reads EEPROM content back into the program memory
and starts executing the code.
After initial EEPROM programming only steps 3 and 4 are required. CLKGEN Block DACs/ADCs Block
CLKMUX
2. After receiving 8 KB, the MCU starts executing the code. TXD[11:0]
Clock PLL
REFCLK FFDIV
Fractional-N RXMCLK
RX TSP ADCs
RXD[11:0]
ADC
Clock
/4
LMS7002M 17
LMS7002M – FPRF MIMO Transceiver IC
where fTXLO and fRXLO are effective TX and RX LO frequencies, fPLL is the
shared PLL output frequency while fDAC and fADC are data converter
sampling rates. Note that the Nyquist frequency of the NCOs is scaled
by a factor of 0.6 to make space for TXLPF and RXLPF to operate.
LMS7002M 18
LMS7002M – FPRF MIMO Transceiver IC
0.666 mm 1.332 mm
11.500 mm
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
252 247 242 233 223 215
A A5 A7 A9 A13 A17 A21 A
260 256 246 241 236 231 226 222 217 211
B B2 B4 B8 B10 B12 B14 B16 B18 B20 B22 B
1 258 255 251 245 239 235 229 224 219 213 209 205 201 197 193
C C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C
2 261 254 250 244 238 232 227 221 216 210 206 202 198 194 192
D D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D
3 257 249 243 237 230 225 218 212 207 203 199 195 191
E E3 E5 E9 E11 E13 E15 E17 E19 E21 E23 E25 E27 E29 E31 E
7 4 259 253 248 240 234 228 220 214 208 204 200 196 190 188
F F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 F32 F
11 8 5 189 187
G G1 G3 G5 G29 G31 G
12 6 186 185
H H2 H6 H30 H32 H
16 13 9 184 182
J J1 J3 J5 J31 J33 J
1.332 mm
10.989 mm
10.323 mm
261L aQFN
6.989 mm
32 31 30 165 164 163
U U1 U3 U5 U29 U31 U33 U
11.5 x11.5 mm
33 34 35 160 161 162
V V2 V4 V6 V30 V32 V34 V
36 157 158 159
W W3 W29 W31 W33 W
37 38 40 155 156
Y Y2 Y4 Y6 Y30 Y32 Y
39 41 42 151 153 154
AA AA1 AA3 AA5 AA29 AA31 AA33 AA
43 44 46 148 150 152
AB AB2 AB4 AB6 AB30 AB32 AB34 AB
45 48 145 147 149
AC AC3 AC5 AC29 AC31 AC33 AC
47 50 53 142 146
AD AD2 AD4 AD6 AD30 AD32 AD
0.666 mm
6.989 mm
10.323 mm
10.989 mm
LMS7002M 19
LMS7002M – FPRF MIMO Transceiver IC
LMS7002M 20
LMS7002M – FPRF MIMO Transceiver IC
LMS7002M 21
LMS7002M – FPRF MIMO Transceiver IC
LMS7002M 22
LMS7002M – FPRF MIMO Transceiver IC
LMS7002M 23
LMS7002M – FPRF MIMO Transceiver IC
TYPICAL APPLICATION
A typical application circuit of the LMS7002M is given in Figure 51. Note that only the RF part of a single MIMO TRX chain is shown. More details
can be found in the LMS7002M evaluation board schematics.
LMS7002M 24
ORDERING INFORMATION
NOTICE OF DISCLAMER
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