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    Nptel lecture by professors from IIT.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    301 views5 pages

    Assignment 3

    Uploaded by

    Rahi Sarkar
    Nptel lecture by professors from IIT.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 5

    Microprocessors and Microcontrollers - - Unit 10... https://onlinecourses.nptel.ac.in/noc18_ec03/un...

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    Courses » Microprocessors and Microcontrollers

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    Unit 10 - Week 9

    Course
    outline
    Week 9 Assignment
    The due date for submitting this assignment has passed. Due on 2018-03-28, 23:59 IST.
    How to access
    the portal Submitted assignment

    Week 1 1) An ARM instruction is 1 point

    Week 2 8 bits long


    16 bits long
    Week 3
    32 bits long
    Week 4 64 bits long
    Week 5 No, the answer is incorrect.
    Score: 0
    Week 6 Accepted Answers:
    32 bits long
    Week 7
    2) Which of the following ARM instructions is same as multiplying the contents 1 point
    Week 8 of r0 by nine and storing the product in r7?

    Week 9 ADD r0, r7, r7, LSL #3


    Lecture 42 : ADD r0, r7, r0, LSL #3
    ARM (Contd.)
    ADD r7, r7, r0, LSL #3
    Lecture 43 :
    ARM(Contd.) ADD r7, r0, r0, LSL #3
    Lecture 44 : No, the answer is incorrect.
    ARM (Contd.) Score: 0

    Lecture 45 : Accepted Answers:


    ARM (Contd.) ADD r7, r0, r0, LSL #3
    Lecture 46 : 3) Which of the following statements is TRUE for ARM architecture? 1 point
    ARM (Contd.)

    Quiz : Week 9 A data processing instruction neither processes data nor moves it around; it
    Assignment simply determines which instructions get executed next.
    Week 9: A data transfer instruction neither processes data nor moves it around; it simply
    Lecture
    determines which instructions get executed next.
    Material
    © 2014 NPTEL - Privacy & Terms - Honor Code - FAQs -
    A control flow instruction neither processes data nor moves it around; it simply
    Feedback
    A project of for In association with next.
    week 9 determines which instructions get executed

    Week 9 None of the above


    Assignment
    No, the answer is incorrect. Funded by
    Answers
    Score: 0

    1 of 5 Wednesday 16 May 2018 04:59 PM


    Microprocessors and Microcontrollers - - Unit 10... https://onlinecourses.nptel.ac.in/noc18_ec03/un...

    Accepted Answers:
    Powered by
    Week 10
    A control flow instruction neither processes data nor moves it around; it simply determines
    Week 11 which instructions get executed next.
    4) Which of the following instructions corresponds to a Multiply Accumulate 1 point
    Week 12
    instruction in ARM architecture?
    DOWNLOAD
    VIDEOS
    MUL
    UMULL
    SMULL
    SMLAL
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    SMLAL
    5) Whichof the following instructions corresponds to loading a signed half word 1 point
    in ARM architecture?

    LDR
    LDRS
    LDRSH
    LDRH
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    LDRSH
    6) Which of the following instructions corresponds to storing a signed byte in 1 point
    ARM architecture?

    STR
    STRSB
    STRB
    STRSH
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    STRSB
    7) On executing the SWI instruction, the processor mode of ARM changes to 1 point

    User mode
    Supervisor mode
    Abort mode
    Undefined mode
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    Supervisor mode
    8) ARM10TDMI is a 1 point

    2 of 5 Wednesday 16 May 2018 04:59 PM


    Microprocessors and Microcontrollers - - Unit 10... https://onlinecourses.nptel.ac.in/noc18_ec03/un...

    3-stage pipeline processor


    5-stage pipeline processor
    6-stage pipeline processor
    8-stage pipeline processor
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    6-stage pipeline processor
    9) Which of the following statements is TRUE for 6-stage pipeline ARM 1 point
    architecture?

    Both instruction and data buses are 32-bit wide


    Instruction bus is 32-bit wide, but data bus is 64-bit wide
    Instruction bus is 64-bit wide, but data bus is 32-bit wide
    Both instruction and data buses are 64-bit wide
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    Both instruction and data buses are 64-bit wide
    10)ARM instruction set supports 1 point

    Multiple load/store instruction that allows to load/store up to 4 registers at once


    Multiple load/store instruction that allows to load/store up to 8 registers at once
    Multiple load/store instruction that allows to load/store up to 16 registers at once
    Multiple load/store instruction that allows to load/store up to 32 registers at once
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    Multiple load/store instruction that allows to load/store up to 16 registers at once
    11)When a procedure call is made in ARM, the return address is automatically 1 point
    placed into

    Program Counter (r15)


    Link Register (r14)
    Stack Pointer (r15)
    Stack Pointer (r13)
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    Link Register (r14)
    12)In
    which of the following modes of an ARM processor, CPSR cannot be 1 point
    modified?

    Fast Interrupt Processing (FIQ) mode


    Normal Interrupt Processing (IRQ) mode
    User mode
    Supervisor (SVC) mode

    3 of 5 Wednesday 16 May 2018 04:59 PM


    Microprocessors and Microcontrollers - - Unit 10... https://onlinecourses.nptel.ac.in/noc18_ec03/un...

    No, the answer is incorrect.


    Score: 0
    Accepted Answers:
    User mode
    13)On a hard reset, ARM enters which of the following modes? 1 point

    Fast Interrupt Processing (FIQ) mode


    Normal Interrupt Processing (IRQ) mode
    Supervisor (SVC) mode
    User mode
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    Supervisor (SVC) mode
    14)Which of the following is a valid multiplication (not multiply accumulate) 1 point
    instruction in ARM architecture?

    MUL r15, r0, r3


    MLA r1, r1, r6
    MUL r10, r2, r5
    MLA r10, r2, r1, r5
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    MUL r10, r2, r5
    15)Which part of an ARM instruction contains one of the 16 condition codes? 1 point

    Bit 24 to bit 21
    Bit 31 to bit 28
    Bit 19 to bit 16
    Bit 15 to bit 12
    No, the answer is incorrect.
    Score: 0
    Accepted Answers:
    Bit 31 to bit 28

    Previous Page End

    4 of 5 Wednesday 16 May 2018 04:59 PM


    Microprocessors and Microcontrollers - - Unit 10... https://onlinecourses.nptel.ac.in/noc18_ec03/un...

    5 of 5 Wednesday 16 May 2018 04:59 PM

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