Assignment 1 MCQ

ASSIGNMENT 1
CS401: COMPUTER ARCHITECTURE

Multiple Choice Question
1. RISC stands for: (a) Register Instruction Set Computer (b) Reduced Instruction Set
Computer (c) Reduced Instruction Set Clock (d) None of the above (CO1)
2. CISC processor have...............length instruction format. (a) Variable (b) Fixed (c) Can
not say (d) None of the above (CO1)
3. CISC stands for: (a) Clock Instruction Set Computer (b) Control Instruction Set Computer
(c) Complex Instruction Set Computer (d) None of the above (CO1)
4. ........................is a term used to denote a large class of techniques that are used to provide
simultaneous data processing tasks (a) Shared memory (b) Parallel Processing (c) Memory
hierarchy (d) None of the above (CO1)
5. ...............................is a technique of decomposing a sequential process into sub operations.

(a) Pipelining (b) Parallel Processing (c) Vector Processing (d) None of the above (CO1)
6. Personal computer were appeared in: (a) Ist generation (b) 2nd generation (c) 4th
generation (d) 5th generation (CO1)
7. A.............contains the address of the next instructions to be executed. (a) Data Register (b)
Accumulator (c) Instruction Register (d) Program Counter (CO1)
8. A......................is an interconnected set of processing elements which cooperate by

communicating with one another to solve large problem (a) Parallel Computer (b) Personal
Computer (c) Laptop Computer (d) None of the above (CO1)
9. Many operating system are designed to enable the CPU to process a number of independent
program concurrently. This concept is called: (a) Cache Memory (b) Multiprogramming
(c) Multiprocessor (d) None of the above (CO2)
10. A.......................system is an interconnection of two more CPU with memory and I/O
equipment. (a) Processor (b) Synchronization (c) Multiprocessor (d) None of the above
(CO2)
11. MIMD stands for: (a) More Instruction Stream, Multiple data Stream (b) Multiple
Instruction Stream, Multiple Data Stream (c) Many Instruction Stream, Many Data Stream (d)
None of the above (CO3)
12. The components that form a multiprocessor system are: (a) CPUs (b) IOPs (c) Memory
Unit (d) All of the above (CO3)
13. Computers are interconnected with each other by means of communication lines to form a:
(a) Computer Network (b) Multiprocessor (c) Data Dependency (d) None of the above
(CO3)
14. A multiprocessor system with common shared memory is called: (a) Loosely coupled
system (b) Tightly coupled system (c) Both a and b (d) None of the above (CO3)
15. Loosely coupled system are more efficient when the interaction between task is:
Advanced Computer Arc. (a) Maximum (b) Minimum (c) Can not say (d) None of the
above (CO3)
16. In a ......................has it own private local memory (a) Crossbar switch (b) Tightly coupled
system (c) Loosely coupled system (d) None of the above (CO2)
17. A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block
size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. What
is the number of bits for the TAG field? (a) 5 (b) 15 (c) 20 (d) 25 (CO2)
18. The ...........................organization consists of number of cross points that are placed at
intersection between buses and memory module paths (a) Multiport memory (b) Crossbar
switch (c) Multistage switch (d) None of the above (CO3)
19. A bus that connects components in a multiprocessor system, is called: (a) Control bus (b)
Data bus (c) Address bus (d) System bus (CO3)
20. The prefetching is a solution for (a) Data hazard (b) Structural hazard (c) Control
hazard (d)None of these (CO1)
21. How many smaller RAM chips of size 256X2 are required to construct a large RAM of size
1K X 8? (a)4 (b) 16 (c) 64 (d) 32 (CO2)
22. The purpose of parallel processing is to: (a) Speed up the processing (b) Increase memory
(c) Decrease memory (d) None of the above (CO3)
23. M.J. Flynn's parallel processing classification is based on: (a) Multiple Instructions (b)
Multiple data (c) Both (a) and (b) (d) None of the above (CO3)
24. ..................................represents an organization that includes many processing units under

the supervision of a common control unit. (a) SISD (b) SIMD (c) MIMD (d) None of the
above (CO3)
25. Associative memory is a

a) Pointer addressable memory
b) Content addressable memory
c) Very cheap memory
d) Slow memory (CO2)
26. The pipeline used for floating point operations is called: (a) Arithmetic pipeline (b)
Instruction pipeline (c) Both (a) and (b) (d) None of the above (CO1)
27. The largest delay in accessing data on a disk is due to
a) Seek time
b) Rotation time
c) data transfer time
d) none of these (CO2)
28. VLIW stands for: (a) Very Long Instruction Word (b) Very Long Instruction Word (c)
Very Large Information Word (d) None of the above (CO1)
29. MIPS stands for: (a) Memory Instruction Per Second (b) Major Instruction Per Second (c)
Main Information Per Second (d) Million Instruction Per Second (CO1)
30. A direct mapped cache memory with n blocks is nothing but which of the following set
associative cache memory organizations?
a) 0-way set associative
b) 1-way set associative
c) 2-way set associative
d) n-way set associative. (CO2)
31. A pipeline stage
a) is sequential circuit
b) is combinational circuit
c) consists of both sequential and combinational circuits
d) None of these. (CO1)
32. Increasing the RAM of a computer typically improves performance because
a) Virtual memory increases
b) Larger RAM are faster
c) Fewer page faults occur
d) Fewer segmentation fault occur (CO2)
33. The total size of address space in a virtual memory system is limited by
a. The length of MAR
b. The available secondary storage
c. The available main memory
d. All of the above (CO2)
34. The control unit controls other units by generating
a) Control signals
b) B. Timing signals
c) Command signals
d) Transfer signals (CO1)
35. The most frequently used instructions of a computer program are most likely to be fetched
from
a) RAM
b) Cache memory
c) ROM
d) Hard disk (CO2)

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ASSIGNMENT 1

CS401: COMPUTER ARCHITECTURE

5. ...............................is a technique of decomposing a sequential process into sub operations.

8. A......................is an interconnected set of processing elements which cooperate by

24. ..................................represents an organization that includes many processing units under

25. Associative memory is a

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