ST7789V PDF
ST7789V PDF
Datasheet
Sitronix reserves the right to change the contents in this document
without prior notice, please contact Sitronix to obtain the latest
version of datasheet before placing your order. No responsibility is
assumed by Sitronix for any infringement of patent or other rights
of third parties which may result from its use.
2013 Sitronix Technology Corporation. All rights reserved.
Version 1.3
2014/03
ST7789V
LIST OF CONTENT
1 GENERAL DESCRIPTION................................................................................................................................. 12
2 FEATURES ............................................................................................................................................................ 13
A1
VCOM
VCOM
VCOM DUMMY
VCOM DUMMY
14µmx100µm VCOM
VCOM DUMMY
10
VCOM G1
DUMMY G3
VAG
VAG G5
VDDS G7
VDDS
G9
Gate : G1~G320 VDDGX
VDDGX
DUMMY
DUMMY
G 11
G 13
20
DUMMY
………
DUMMY
DUMMY
DUMMY
30
VGL
VGL
40µmx56µm AVDD
AVDD
AVDD
AVDD G303
AVDD
AVDD G305
AVDD
AVCL
G307
G309
Input Pads : Pad 12 to Pad 239 AVCL
40
AVCL G311
AVCL G313
AVCL G315
AVCL
AVCL G317
VAN G319
VAN
DUMMY
DUMMY
50
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
Face Up
ST7789V
DUMMY
DUMMY
DUMMY
VAP
VAP
60
V20 S1
V20 S2
V20
V20 S3
V20 S4
V20 S5
V20
DUMMY S6
DUMMY
DUMMY
70
DUMMY
DUMMY
DUMMY
DUMMY
VDD
VDD
VDD
VDD
VDD
VDD
80
………
VDD
VDD
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
90
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND S353
100
DGND
DGND S354
DGND S355
DGND S356
DGND
DGND S357
DGND S358
TEST3 S359
DUMMY
DUMMY S360
110
EXTC
IM3
Bump View
IM2
Y
IM1
IM0
RESX
CSX
DCX
WRX S361
RDX
S362
120
TEST2
VSYNC S363
HSYNC S364
ENABLE S365
DOTCLK
DUMMY S366
SDA S367
DB0
DB1 S368
DB2
130
DB3
TEST1
DB4
………
DB5
X
DB6
DB7
DUMMY
DB8
DB9
DB10
140
DB11
DUMMY
DB12
DB13
DB14
DB15
DUMMY
DB16
DB17
TEST0
S712
150
TE
SDO S713
LED_PWM S714
LED_EN S715
VDDI_LED
VDDI_LED S716
TE2 S717
TESTO1
TESTO2 S718
TESTO3 S719
160
TESTO4 S720
TESTO5
TESTO6
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
170
VCC
VCC
VCC G320
VCC
VCC G318
VCC G316
VCC
VCC G314
VCC G312
VCC G310
180
VCC
VCC G308
VCC G306
VCC
DUMMY
VPP
VPP
VPP
VPP
DUMMY
190
DUMMY
VGH
VGH
VGH
………
VGH
VGH
VGH
VGH
VGH
DUMMY
200
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
AGND
AGND
AGND
210
AGND
AGND
AGND
AGND
AGND
DUMMYR1
DUMMYR2 G12
DUMMY G10
DUMMY
DUMMY G8
220
DUMMY
DUMMY
G6
G4
DUMMY G2
DUMMY
VCOM DUMMY
VCOM DUMMY
VCOM DUMMY
VCOM
VCOM
VCOM
230
VCOM
A2
VCOM
DUMMY
DUMMY
Output Pads
S1~S720、G1~G320、DUMMY
(No.233~1278)
Input Pads
No.1~232
E F
Symbol Item Size
E Bump Width 40 um
F Bump Gap 20、32.5、45 um
G
G Bump Height 56 um
H Bump Pitch 60、72.5、85 um
10 30 30 30 10
20 10
20 30
30
30
10
10 30 30 30 10
10 20
30 20
30
30
10
97 AGND -1532.5 -256.62 131 DB4 645 -256.62 165 VDDI 3272.5 -256.62
98 DGND -1472.5 -256.62 132 DB5 730 -256.62 166 VDDI 3332.5 -256.62
99 DGND -1412.5 -256.62 133 DB6 815 -256.62 167 VDDI 3392.5 -256.62
100 DGND -1352.5 -256.62 134 DB7 900 -256.62 168 VDDI 3452.5 -256.62
101 DGND -1292.5 -256.62 135 DUMMY 972.5 -256.62 169 VCC 3512.5 -256.62
102 DGND -1232.5 -256.62 136 DB8 1045 -256.62 170 VCC 3572.5 -256.62
103 DGND -1172.5 -256.62 137 DB9 1130 -256.62 171 VCC 3632.5 -256.62
104 DGND -1112.5 -256.62 138 DB10 1215 -256.62 172 VCC 3692.5 -256.62
105 DGND -1052.5 -256.62 139 DB11 1300 -256.62 173 VCC 3752.5 -256.62
106 TEST3 -992.5 -256.62 140 DUMMY 1372.5 -256.62 174 VCC 3812.5 -256.62
107 DUMMY -932.5 -256.62 141 DB12 1445 -256.62 175 VCC 3872.5 -256.62
108 DUMMY -872.5 -256.62 142 DB13 1530 -256.62 176 VCC 3932.5 -256.62
109 EXTC -812.5 -256.62 143 DB14 1615 -256.62 177 VCC 3992.5 -256.62
110 IM3 -752.5 -256.62 144 DB15 1700 -256.62 178 VCC 4052.5 -256.62
111 IM2 -692.5 -256.62 145 DUMMY 1772.5 -256.62 179 VCC 4112.5 -256.62
112 IM1 -632.5 -256.62 146 DB16 1845 -256.62 180 VCC 4172.5 -256.62
113 IM0 -572.5 -256.62 147 DB17 1930 -256.62 181 VCC 4232.5 -256.62
114 RESX -512.5 -256.62 148 TEST0 2002.5 -256.62 182 VCC 4292.5 -256.62
115 CSX -452.5 -256.62 149 TE 2075 -256.62 183 DUMMY 4352.5 -256.62
116 DCX -392.5 -256.62 150 SDO 2160 -256.62 184 VPP 4412.5 -256.62
117 WRX -332.5 -256.62 151 LED_PWM 2245 -256.62 185 VPP 4472.5 -256.62
118 RDX -272.5 -256.62 152 LED_EN 2330 -256.62 186 VPP 4532.5 -256.62
119 TEST2 -212.5 -256.62 153 VDDI_LED 2402.5 -256.62 187 VPP 4592.5 -256.62
120 VSYNC -152.5 -256.62 154 VDDI_LED 2462.5 -256.62 188 DUMMY 4652.5 -256.62
121 HSYNC -92.5 -256.62 155 TE2 2535 -256.62 189 DUMMY 4712.5 -256.62
122 ENABLE -32.5 -256.62 156 TESTO1 2620 -256.62 190 VGH 4772.5 -256.62
123 DOTCLK 27.5 -256.62 157 TESTO2 2705 -256.62 191 VGH 4832.5 -256.62
124 DUMMY 87.5 -256.62 158 TESTO3 2790 -256.62 192 VGH 4892.5 -256.62
125 SDA 160 -256.62 159 TESTO4 2875 -256.62 193 VGH 4952.5 -256.62
126 DB0 245 -256.62 160 TESTO5 2960 -256.62 194 VGH 5012.5 -256.62
127 DB1 330 -256.62 161 TESTO6 3032.5 -256.62 195 VGH 5072.5 -256.62
128 DB2 415 -256.62 162 VDDI 3092.5 -256.62 196 VGH 5132.5 -256.62
129 DB3 500 -256.62 163 VDDI 3152.5 -256.62 197 VGH 5192.5 -256.62
130 TEST1 572.5 -256.62 164 VDDI 3212.5 -256.62 198 DUMMY 5252.5 -256.62
199 DUMMY 5312.5 -256.62 233 DUMMY 7399 250.58 267 G64 6923 250.58
200 DUMMY 5372.5 -256.62 234 DUMMY 7385 119.58 268 G66 6909 119.58
201 DUMMY 5432.5 -256.62 235 DUMMY 7371 250.58 269 G68 6895 250.58
202 DUMMY 5492.5 -256.62 236 G2 7357 119.58 270 G70 6881 119.58
203 DUMMY 5552.5 -256.62 237 G4 7343 250.58 271 G72 6867 250.58
204 DUMMY 5612.5 -256.62 238 G6 7329 119.58 272 G74 6853 119.58
205 DUMMY 5672.5 -256.62 239 G8 7315 250.58 273 G76 6839 250.58
206 AGND 5732.5 -256.62 240 G10 7301 119.58 274 G78 6825 119.58
207 AGND 5792.5 -256.62 241 G12 7287 250.58 275 G80 6811 250.58
208 AGND 5852.5 -256.62 242 G14 7273 119.58 276 G82 6797 119.58
209 AGND 5912.5 -256.62 243 G16 7259 250.58 277 G84 6783 250.58
210 AGND 5972.5 -256.62 244 G18 7245 119.58 278 G86 6769 119.58
211 AGND 6032.5 -256.62 245 G20 7231 250.58 279 G88 6755 250.58
212 AGND 6092.5 -256.62 246 G22 7217 119.58 280 G90 6741 119.58
213 AGND 6152.5 -256.62 247 G24 7203 250.58 281 G92 6727 250.58
214 DUMMYR1 6212.5 -256.62 248 G26 7189 119.58 282 G94 6713 119.58
215 DUMMYR2 6272.5 -256.62 249 G28 7175 250.58 283 G96 6699 250.58
216 DUMMY 6332.5 -256.62 250 G30 7161 119.58 284 G98 6685 119.58
217 DUMMY 6392.5 -256.62 251 G32 7147 250.58 285 G100 6671 250.58
218 DUMMY 6452.5 -256.62 252 G34 7133 119.58 286 G102 6657 119.58
219 DUMMY 6512.5 -256.62 253 G36 7119 250.58 287 G104 6643 250.58
220 DUMMY 6572.5 -256.62 254 G38 7105 119.58 288 G106 6629 119.58
221 DUMMY 6632.5 -256.62 255 G40 7091 250.58 289 G108 6615 250.58
222 DUMMY 6692.5 -256.62 250.58 G42 7077 119.58 290 G110 6601 119.58
223 VCOM 6752.5 -256.62 257 G44 7063 250.58 291 G112 6587 250.58
224 VCOM 6812.5 -256.62 258 G46 7049 119.58 292 G114 6573 119.58
225 VCOM 6872.5 -256.62 259 G48 7035 250.58 293 G116 6559 250.58
226 VCOM 6932.5 -256.62 260 G50 7021 119.58 294 G118 6545 119.58
227 VCOM 6992.5 -256.62 261 G52 7007 250.58 295 G120 6531 250.58
228 VCOM 7052.5 -256.62 262 G54 6993 119.58 296 G122 6517 119.58
229 VCOM 7112.5 -256.62 263 G56 6979 250.58 297 G124 6503 250.58
230 VCOM 7172.5 -256.62 264 G58 6965 119.58 298 G126 6489 119.58
231 DUMMY 7232.5 -256.62 265 G60 6951 250.58 299 G128 6475 250.58
232 DUMMY 7292.5 -256.62 266 G62 6937 119.58 300 G130 6461 119.58
301 G132 6447 250.58 335 G200 5971 250.58 369 G268 5495 250.58
302 G134 6433 119.58 336 G202 5957 119.58 370 G270 5481 119.58
303 G136 6419 250.58 337 G204 5943 250.58 371 G272 5467 250.58
304 G138 6405 119.58 338 G206 5929 119.58 372 G274 5453 119.58
305 G140 6391 250.58 339 G208 5915 250.58 373 G276 5439 250.58
306 G142 6377 119.58 340 G210 5901 119.58 374 G278 5425 119.58
307 G144 6363 250.58 341 G212 5887 250.58 375 G280 5411 250.58
308 G146 6349 119.58 342 G214 5873 119.58 376 G282 5397 119.58
309 G148 6335 250.58 343 G216 5859 250.58 377 G284 5383 250.58
310 G150 6321 119.58 344 G218 5845 119.58 378 G286 5369 119.58
311 G152 6307 250.58 345 G220 5831 250.58 379 G288 5355 250.58
312 G154 6293 119.58 346 G222 5817 119.58 380 G290 5341 119.58
313 G156 6279 250.58 347 G224 5803 250.58 381 G292 5327 250.58
314 G158 6265 119.58 348 G226 5789 119.58 382 G294 5313 119.58
315 G160 6251 250.58 349 G228 5775 250.58 383 G296 5299 250.58
316 G162 6237 119.58 350 G230 5761 119.58 384 G298 5285 119.58
317 G164 6223 250.58 351 G232 5747 250.58 385 G300 5271 250.58
318 G166 6209 119.58 352 G234 5733 119.58 386 G302 5257 119.58
319 G168 6195 250.58 353 G236 5719 250.58 387 G304 5243 250.58
320 G170 6181 119.58 354 G238 5705 119.58 388 G306 5229 119.58
321 G172 6167 250.58 355 G240 5691 250.58 389 G308 5215 250.58
322 G174 6153 119.58 356 G242 5677 119.58 390 G310 5201 119.58
323 G176 6139 250.58 357 G244 5663 250.58 391 G312 5187 250.58
324 G178 6125 119.58 358 G246 5649 119.58 392 G314 5173 119.58
325 G180 6111 250.58 359 G248 5635 250.58 393 G316 5159 250.58
326 G182 6097 119.58 360 G250 5621 119.58 394 G318 5145 119.58
327 G184 6083 250.58 361 G252 5607 250.58 395 G320 5131 250.58
328 G186 6069 119.58 362 G254 5593 119.58 396 S720 5075 119.58
329 G188 6055 250.58 363 G256 5579 250.58 397 S719 5061 250.58
330 G190 6041 119.58 364 G258 5565 119.58 398 S718 5047 119.58
331 G192 6027 250.58 365 G260 5551 250.58 399 S717 5033 250.58
332 G194 6013 119.58 366 G262 5537 119.58 400 S716 5019 119.58
333 G196 5999 250.58 367 G264 5523 250.58 401 S715 5005 250.58
334 G198 5985 119.58 368 G266 5509 119.58 402 S714 4991 119.58
403 S713 4977 250.58 437 S679 4501 250.58 471 S645 4025 250.58
404 S712 4963 119.58 438 S678 4487 119.58 472 S644 4011 119.58
405 S711 4949 250.58 439 S677 4473 250.58 473 S643 3997 250.58
406 S710 4935 119.58 440 S676 4459 119.58 474 S642 3983 119.58
407 S709 4921 250.58 441 S675 4445 250.58 475 S641 3969 250.58
408 S708 4907 119.58 442 S674 4431 119.58 476 S640 3955 119.58
409 S707 4893 250.58 443 S673 4417 250.58 477 S639 3941 250.58
410 S706 4879 119.58 444 S672 4403 119.58 478 S638 3927 119.58
411 S705 4865 250.58 445 S671 4389 250.58 479 S637 3913 250.58
412 S704 4851 119.58 446 S670 4375 119.58 480 S636 3899 119.58
413 S703 4837 250.58 447 S669 4361 250.58 481 S635 3885 250.58
414 S702 4823 119.58 448 S668 4347 119.58 482 S634 3871 119.58
415 S701 4809 250.58 449 S667 4333 250.58 483 S633 3857 250.58
416 S700 4795 119.58 450 S666 4319 119.58 484 S632 3843 119.58
417 S699 4781 250.58 451 S665 4305 250.58 485 S631 3829 250.58
418 S698 4767 119.58 452 S664 4291 119.58 486 S630 3815 119.58
419 S697 4753 250.58 453 S663 4277 250.58 487 S629 3801 250.58
420 S696 4739 119.58 454 S662 4263 119.58 488 S628 3787 119.58
421 S695 4725 250.58 455 S661 4249 250.58 489 S627 3773 250.58
422 S694 4711 119.58 456 S660 4235 119.58 490 S626 3759 119.58
423 S693 4697 250.58 457 S659 4221 250.58 491 S625 3745 250.58
424 S692 4683 119.58 458 S658 4207 119.58 492 S624 3731 119.58
425 S691 4669 250.58 459 S657 4193 250.58 493 S623 3717 250.58
426 S690 4655 119.58 460 S656 4179 119.58 494 S622 3703 119.58
427 S689 4641 250.58 461 S655 4165 250.58 495 S621 3689 250.58
428 S688 4627 119.58 462 S654 4151 119.58 496 S620 3675 119.58
429 S687 4613 250.58 463 S653 4137 250.58 497 S619 3661 250.58
430 S686 4599 119.58 464 S652 4123 119.58 498 S618 3647 119.58
431 S685 4585 250.58 465 S651 4109 250.58 499 S617 3633 250.58
432 S684 4571 119.58 466 S650 4095 119.58 500 S616 3619 119.58
433 S683 4557 250.58 467 S649 4081 250.58 501 S615 3605 250.58
434 S682 4543 119.58 468 S648 4067 119.58 502 S614 3591 119.58
435 S681 4529 250.58 469 S647 4053 250.58 503 S613 3577 250.58
436 S680 4515 119.58 470 S646 4039 119.58 504 S612 3563 119.58
505 S611 3549 250.58 539 S577 3073 250.58 573 S543 2597 250.58
506 S610 3535 119.58 540 S576 3059 119.58 574 S542 2583 119.58
507 S609 3521 250.58 541 S575 3045 250.58 575 S541 2569 250.58
508 S608 3507 119.58 542 S574 3031 119.58 576 S540 2555 119.58
509 S607 3493 250.58 543 S573 3017 250.58 577 S539 2541 250.58
510 S606 3479 119.58 544 S572 3003 119.58 578 S538 2527 119.58
511 S605 3465 250.58 545 S571 2989 250.58 579 S537 2513 250.58
512 S604 3451 119.58 546 S570 2975 119.58 580 S536 2499 119.58
513 S603 3437 250.58 547 S569 2961 250.58 581 S535 2485 250.58
514 S602 3423 119.58 548 S568 2947 119.58 582 S534 2471 119.58
515 S601 3409 250.58 549 S567 2933 250.58 583 S533 2457 250.58
516 S600 3395 119.58 550 S566 2919 119.58 584 S532 2443 119.58
517 S599 3381 250.58 551 S565 2905 250.58 585 S531 2429 250.58
518 S598 3367 119.58 552 S564 2891 119.58 586 S530 2415 119.58
519 S597 3353 250.58 553 S563 2877 250.58 587 S529 2401 250.58
520 S596 3339 119.58 554 S562 2863 119.58 588 S528 2387 119.58
521 S595 3325 250.58 555 S561 2849 250.58 589 S527 2373 250.58
522 S594 3311 119.58 556 S560 2835 119.58 590 S526 2359 119.58
523 S593 3297 250.58 557 S559 2821 250.58 591 S525 2345 250.58
524 S592 3283 119.58 558 S558 2807 119.58 592 S524 2331 119.58
525 S591 3269 250.58 559 S557 2793 250.58 593 S523 2317 250.58
526 S590 3255 119.58 560 S556 2779 119.58 594 S522 2303 119.58
527 S589 3241 250.58 561 S555 2765 250.58 595 S521 2289 250.58
528 S588 3227 119.58 562 S554 2751 119.58 596 S520 2275 119.58
529 S587 3213 250.58 563 S553 2737 250.58 597 S519 2261 250.58
530 S586 3199 119.58 564 S552 2723 119.58 598 S518 2247 119.58
531 S585 3185 250.58 565 S551 2709 250.58 599 S517 2233 250.58
532 S584 3171 119.58 566 S550 2695 119.58 600 S516 2219 119.58
533 S583 3157 250.58 567 S549 2681 250.58 601 S515 2205 250.58
534 S582 3143 119.58 568 S548 2667 119.58 602 S514 2191 119.58
535 S581 3129 250.58 569 S547 2653 250.58 603 S513 2177 250.58
536 S580 3115 119.58 570 S546 2639 119.58 604 S512 2163 119.58
537 S579 3101 250.58 571 S545 2625 250.58 605 S511 2149 250.58
538 S578 3087 119.58 572 S544 2611 119.58 606 S510 2135 119.58
607 S509 2121 250.58 641 S475 1645 250.58 675 S441 1169 250.58
608 S508 2107 119.58 642 S474 1631 119.58 676 S440 1155 119.58
609 S507 2093 250.58 643 S473 1617 250.58 677 S439 1141 250.58
610 S506 2079 119.58 644 S472 1603 119.58 678 S438 1127 119.58
611 S505 2065 250.58 645 S471 1589 250.58 679 S437 1113 250.58
612 S504 2051 119.58 646 S470 1575 119.58 680 S436 1099 119.58
613 S503 2037 250.58 647 S469 1561 250.58 681 S435 1085 250.58
614 S502 2023 119.58 648 S468 1547 119.58 682 S434 1071 119.58
615 S501 2009 250.58 649 S467 1533 250.58 683 S433 1057 250.58
616 S500 1995 119.58 650 S466 1519 119.58 684 S432 1043 119.58
617 S499 1981 250.58 651 S465 1505 250.58 685 S431 1029 250.58
618 S498 1967 119.58 652 S464 1491 119.58 686 S430 1015 119.58
619 S497 1953 250.58 653 S463 1477 250.58 687 S429 1001 250.58
620 S496 1939 119.58 654 S462 1463 119.58 688 S428 987 119.58
621 S495 1925 250.58 655 S461 1449 250.58 689 S427 973 250.58
622 S494 1911 119.58 656 S460 1435 119.58 690 S426 959 119.58
623 S493 1897 250.58 657 S459 1421 250.58 691 S425 945 250.58
624 S492 1883 119.58 658 S458 1407 119.58 692 S424 931 119.58
625 S491 1869 250.58 659 S457 1393 250.58 693 S423 917 250.58
626 S490 1855 119.58 660 S456 1379 119.58 694 S422 903 119.58
627 S489 1841 250.58 661 S455 1365 250.58 695 S421 889 250.58
628 S488 1827 119.58 662 S454 1351 119.58 696 S420 875 119.58
629 S487 1813 250.58 663 S453 1337 250.58 697 S419 861 250.58
630 S486 1799 119.58 664 S452 1323 119.58 698 S418 847 119.58
631 S485 1785 250.58 665 S451 1309 250.58 699 S417 833 250.58
632 S484 1771 119.58 666 S450 1295 119.58 700 S416 819 119.58
633 S483 1757 250.58 667 S449 1281 250.58 701 S415 805 250.58
634 S482 1743 119.58 668 S448 1267 119.58 702 S414 791 119.58
635 S481 1729 250.58 669 S447 1253 250.58 703 S413 777 250.58
636 S480 1715 119.58 670 S446 1239 119.58 704 S412 763 119.58
637 S479 1701 250.58 671 S445 1225 250.58 705 S411 749 250.58
638 S478 1687 119.58 672 S444 1211 119.58 706 S410 735 119.58
639 S477 1673 250.58 673 S443 1197 250.58 707 S409 721 250.58
640 S476 1659 119.58 674 S442 1183 119.58 708 S408 707 119.58
709 S407 693 250.58 743 S373 217 250.58 777 S339 -343 250.58
710 S406 679 119.58 744 S372 203 119.58 778 S338 -357 119.58
711 S405 665 250.58 745 S371 189 250.58 779 S337 -371 250.58
712 S404 651 119.58 746 S370 175 119.58 780 S336 -385 119.58
713 S403 637 250.58 747 S369 161 250.58 781 S335 -399 250.58
714 S402 623 119.58 748 S368 147 119.58 782 S334 -413 119.58
715 S401 609 250.58 749 S367 133 250.58 783 S333 -427 250.58
716 S400 595 119.58 750 S366 119 119.58 784 S332 -441 119.58
717 S399 581 250.58 751 S365 105 250.58 785 S331 -455 250.58
718 S398 567 119.58 752 S364 91 119.58 786 S330 -469 119.58
719 S397 553 250.58 753 S363 77 250.58 787 S329 -483 250.58
720 S396 539 119.58 754 S362 63 119.58 788 S328 -497 119.58
721 S395 525 250.58 755 S361 49 250.58 789 S327 -511 250.58
722 S394 511 119.58 756 S360 -49 119.58 790 S326 -525 119.58
723 S393 497 250.58 757 S359 -63 250.58 791 S325 -539 250.58
724 S392 483 119.58 758 S358 -77 119.58 792 S324 -553 119.58
725 S391 469 250.58 759 S357 -91 250.58 793 S323 -567 250.58
726 S390 455 119.58 760 S356 -105 119.58 794 S322 -581 119.58
727 S389 441 250.58 761 S355 -119 250.58 795 S321 -595 250.58
728 S388 427 119.58 762 S354 -133 119.58 796 S320 -609 119.58
729 S387 413 250.58 763 S353 -147 250.58 797 S319 -623 250.58
730 S386 399 119.58 764 S352 -161 119.58 798 S318 -637 119.58
731 S385 385 250.58 765 S351 -175 250.58 799 S317 -651 250.58
732 S384 371 119.58 766 S350 -189 119.58 800 S316 -665 119.58
733 S383 357 250.58 767 S349 -203 250.58 801 S315 -679 250.58
734 S382 343 119.58 768 S348 -217 119.58 802 S314 -693 119.58
735 S381 329 250.58 769 S347 -231 250.58 803 S313 -707 250.58
736 S380 315 119.58 770 S346 -245 119.58 804 S312 -721 119.58
737 S379 301 250.58 771 S345 -259 250.58 805 S311 -735 250.58
738 S378 287 119.58 772 S344 -273 119.58 806 S310 -749 119.58
739 S377 273 250.58 773 S343 -287 250.58 807 S309 -763 250.58
740 S376 259 119.58 774 S342 -301 119.58 808 S308 -777 119.58
741 S375 245 250.58 775 S341 -315 250.58 809 S307 -791 250.58
742 S374 231 119.58 776 S340 -329 119.58 810 S306 -805 119.58
811 S305 -819 250.58 845 S271 -1295 250.58 879 S237 -1771 250.58
812 S304 -833 119.58 846 S270 -1309 119.58 880 S236 -1785 119.58
813 S303 -847 250.58 847 S269 -1323 250.58 881 S235 -1799 250.58
814 S302 -861 119.58 848 S268 -1337 119.58 882 S234 -1813 119.58
815 S301 -875 250.58 849 S267 -1351 250.58 883 S233 -1827 250.58
816 S300 -889 119.58 850 S266 -1365 119.58 884 S232 -1841 119.58
817 S299 -903 250.58 851 S265 -1379 250.58 885 S231 -1855 250.58
818 S298 -917 119.58 852 S264 -1393 119.58 886 S230 -1869 119.58
819 S297 -931 250.58 853 S263 -1407 250.58 887 S229 -1883 250.58
820 S296 -945 119.58 854 S262 -1421 119.58 888 S228 -1897 119.58
821 S295 -959 250.58 855 S261 -1435 250.58 889 S227 -1911 250.58
822 S294 -973 119.58 856 S260 -1449 119.58 890 S226 -1925 119.58
823 S293 -987 250.58 857 S259 -1463 250.58 891 S225 -1939 250.58
824 S292 -1001 119.58 858 S258 -1477 119.58 892 S224 -1953 119.58
825 S291 -1015 250.58 859 S257 -1491 250.58 893 S223 -1967 250.58
826 S290 -1029 119.58 860 S256 -1505 119.58 894 S222 -1981 119.58
827 S289 -1043 250.58 861 S255 -1519 250.58 895 S221 -1995 250.58
828 S288 -1057 119.58 862 S254 -1533 119.58 896 S220 -2009 119.58
829 S287 -1071 250.58 863 S253 -1547 250.58 897 S219 -2023 250.58
830 S286 -1085 119.58 864 S252 -1561 119.58 898 S218 -2037 119.58
831 S285 -1099 250.58 865 S251 -1575 250.58 899 S217 -2051 250.58
832 S284 -1113 119.58 866 S250 -1589 119.58 900 S216 -2065 119.58
833 S283 -1127 250.58 867 S249 -1603 250.58 901 S215 -2079 250.58
834 S282 -1141 119.58 868 S248 -1617 119.58 902 S214 -2093 119.58
835 S281 -1155 250.58 869 S247 -1631 250.58 903 S213 -2107 250.58
836 S280 -1169 119.58 870 S246 -1645 119.58 904 S212 -2121 119.58
837 S279 -1183 250.58 871 S245 -1659 250.58 905 S211 -2135 250.58
838 S278 -1197 119.58 872 S244 -1673 119.58 906 S210 -2149 119.58
839 S277 -1211 250.58 873 S243 -1687 250.58 907 S209 -2163 250.58
840 S276 -1225 119.58 874 S242 -1701 119.58 908 S208 -2177 119.58
841 S275 -1239 250.58 875 S241 -1715 250.58 909 S207 -2191 250.58
842 S274 -1253 119.58 876 S240 -1729 119.58 910 S206 -2205 119.58
843 S273 -1267 250.58 877 S239 -1743 250.58 911 S205 -2219 250.58
844 S272 -1281 119.58 878 S238 -1757 119.58 912 S204 -2233 119.58
913 S203 -2247 250.58 947 S169 -2723 250.58 981 S135 -3199 250.58
914 S202 -2261 119.58 948 S168 -2737 119.58 982 S134 -3213 119.58
915 S201 -2275 250.58 949 S167 -2751 250.58 983 S133 -3227 250.58
916 S200 -2289 119.58 950 S166 -2765 119.58 984 S132 -3241 119.58
917 S199 -2303 250.58 951 S165 -2779 250.58 985 S131 -3255 250.58
918 S198 -2317 119.58 952 S164 -2793 119.58 986 S130 -3269 119.58
919 S197 -2331 250.58 953 S163 -2807 250.58 987 S129 -3283 250.58
920 S196 -2345 119.58 954 S162 -2821 119.58 988 S128 -3297 119.58
921 S195 -2359 250.58 955 S161 -2835 250.58 989 S127 -3311 250.58
922 S194 -2373 119.58 956 S160 -2849 119.58 990 S126 -3325 119.58
923 S193 -2387 250.58 957 S159 -2863 250.58 991 S125 -3339 250.58
924 S192 -2401 119.58 958 S158 -2877 119.58 992 S124 -3353 119.58
925 S191 -2415 250.58 959 S157 -2891 250.58 993 S123 -3367 250.58
926 S190 -2429 119.58 960 S156 -2905 119.58 994 S122 -3381 119.58
927 S189 -2443 250.58 961 S155 -2919 250.58 995 S121 -3395 250.58
928 S188 -2457 119.58 962 S154 -2933 119.58 996 S120 -3409 119.58
929 S187 -2471 250.58 963 S153 -2947 250.58 997 S119 -3423 250.58
930 S186 -2485 119.58 964 S152 -2961 119.58 998 S118 -3437 119.58
931 S185 -2499 250.58 965 S151 -2975 250.58 999 S117 -3451 250.58
932 S184 -2513 119.58 966 S150 -2989 119.58 1000 S116 -3465 119.58
933 S183 -2527 250.58 967 S149 -3003 250.58 1001 S115 -3479 250.58
934 S182 -2541 119.58 968 S148 -3017 119.58 1002 S114 -3493 119.58
935 S181 -2555 250.58 969 S147 -3031 250.58 1003 S113 -3507 250.58
936 S180 -2569 119.58 970 S146 -3045 119.58 1004 S112 -3521 119.58
937 S179 -2583 250.58 971 S145 -3059 250.58 1005 S111 -3535 250.58
938 S178 -2597 119.58 972 S144 -3073 119.58 1006 S110 -3549 119.58
939 S177 -2611 250.58 973 S143 -3087 250.58 1007 S109 -3563 250.58
940 S176 -2625 119.58 974 S142 -3101 119.58 1008 S108 -3577 119.58
941 S175 -2639 250.58 975 S141 -3115 250.58 1009 S107 -3591 250.58
942 S174 -2653 119.58 976 S140 -3129 119.58 1010 S106 -3605 119.58
943 S173 -2667 250.58 977 S139 -3143 250.58 1011 S105 -3619 250.58
944 S172 -2681 119.58 978 S138 -3157 119.58 1012 S104 -3633 119.58
945 S171 -2695 250.58 979 S137 -3171 250.58 1013 S103 -3647 250.58
946 S170 -2709 119.58 980 S136 -3185 119.58 1014 S102 -3661 119.58
1015 S101 -3675 250.58 1049 S67 -4151 250.58 1083 S33 -4627 250.58
1016 S100 -3689 119.58 1050 S66 -4165 119.58 1084 S32 -4641 119.58
1017 S99 -3703 250.58 1051 S65 -4179 250.58 1085 S31 -4655 250.58
1018 S98 -3717 119.58 1052 S64 -4193 119.58 1086 S30 -4669 119.58
1019 S97 -3731 250.58 1053 S63 -4207 250.58 1087 S29 -4683 250.58
1020 S96 -3745 119.58 1054 S62 -4221 119.58 1088 S28 -4697 119.58
1021 S95 -3759 250.58 1055 S61 -4235 250.58 1089 S27 -4711 250.58
1022 S94 -3773 119.58 1056 S60 -4249 119.58 1090 S26 -4725 119.58
1023 S93 -3787 250.58 1057 S59 -4263 250.58 1091 S25 -4739 250.58
1024 S92 -3801 119.58 1058 S58 -4277 119.58 1092 S24 -4753 119.58
1025 S91 -3815 250.58 1059 S57 -4291 250.58 1093 S23 -4767 250.58
1026 S90 -3829 119.58 1060 S56 -4305 119.58 1094 S22 -4781 119.58
1027 S89 -3843 250.58 1061 S55 -4319 250.58 1095 S21 -4795 250.58
1028 S88 -3857 119.58 1062 S54 -4333 119.58 1096 S20 -4809 119.58
1029 S87 -3871 250.58 1063 S53 -4347 250.58 1097 S19 -4823 250.58
1030 S86 -3885 119.58 1064 S52 -4361 119.58 1098 S18 -4837 119.58
1031 S85 -3899 250.58 1065 S51 -4375 250.58 1099 S17 -4851 250.58
1032 S84 -3913 119.58 1066 S50 -4389 119.58 1100 S16 -4865 119.58
1033 S83 -3927 250.58 1067 S49 -4403 250.58 1101 S15 -4879 250.58
1034 S82 -3941 119.58 1068 S48 -4417 119.58 1102 S14 -4893 119.58
1035 S81 -3955 250.58 1069 S47 -4431 250.58 1103 S13 -4907 250.58
1036 S80 -3969 119.58 1070 S46 -4445 119.58 1104 S12 -4921 119.58
1037 S79 -3983 250.58 1071 S45 -4459 250.58 1105 S11 -4935 250.58
1038 S78 -3997 119.58 1072 S44 -4473 119.58 1106 S10 -4949 119.58
1039 S77 -4011 250.58 1073 S43 -4487 250.58 1107 S9 -4963 250.58
1040 S76 -4025 119.58 1074 S42 -4501 119.58 1108 S8 -4977 119.58
1041 S75 -4039 250.58 1075 S41 -4515 250.58 1109 S7 -4991 250.58
1042 S74 -4053 119.58 1076 S40 -4529 119.58 1110 S6 -5005 119.58
1043 S73 -4067 250.58 1077 S39 -4543 250.58 1111 S5 -5019 250.58
1044 S72 -4081 119.58 1078 S38 -4557 119.58 1112 S4 -5033 119.58
1045 S71 -4095 250.58 1079 S37 -4571 250.58 1113 S3 -5047 250.58
1046 S70 -4109 119.58 1080 S36 -4585 119.58 1114 S2 -5061 119.58
1047 S69 -4123 250.58 1081 S35 -4599 250.58 1115 S1 -5075 250.58
1048 S68 -4137 119.58 1082 S34 -4613 119.58 1116 G319 -5131 119.58
1117 G317 -5145 250.58 1151 G249 -5621 250.58 1185 G181 -6097 250.58
1118 G315 -5159 119.58 1152 G247 -5635 119.58 1186 G179 -6111 119.58
1119 G313 -5173 250.58 1153 G245 -5649 250.58 1187 G177 -6125 250.58
1120 G311 -5187 119.58 1154 G243 -5663 119.58 1188 G175 -6139 119.58
1121 G309 -5201 250.58 1155 G241 -5677 250.58 1189 G173 -6153 250.58
1122 G307 -5215 119.58 1156 G239 -5691 119.58 1190 G171 -6167 119.58
1123 G305 -5229 250.58 1157 G237 -5705 250.58 1191 G169 -6181 250.58
1124 G303 -5243 119.58 1158 G235 -5719 119.58 1192 G167 -6195 119.58
1125 G301 -5257 250.58 1159 G233 -5733 250.58 1193 G165 -6209 250.58
1126 G299 -5271 119.58 1160 G231 -5747 119.58 1194 G163 -6223 119.58
1127 G297 -5285 250.58 1161 G229 -5761 250.58 1195 G161 -6237 250.58
1128 G295 -5299 119.58 1162 G227 -5775 119.58 1196 G159 -6251 119.58
1129 G293 -5313 250.58 1163 G225 -5789 250.58 1197 G157 -6265 250.58
1130 G291 -5327 119.58 1164 G223 -5803 119.58 1198 G155 -6279 119.58
1131 G289 -5341 250.58 1165 G221 -5817 250.58 1199 G153 -6293 250.58
1132 G287 -5355 119.58 1166 G219 -5831 119.58 1200 G151 -6307 119.58
1133 G285 -5369 250.58 1167 G217 -5845 250.58 1201 G149 -6321 250.58
1134 G283 -5383 119.58 1168 G215 -5859 119.58 1202 G147 -6335 119.58
1135 G281 -5397 250.58 1169 G213 -5873 250.58 1203 G145 -6349 250.58
1136 G279 -5411 119.58 1170 G211 -5887 119.58 1204 G143 -6363 119.58
1137 G277 -5425 250.58 1171 G209 -5901 250.58 1205 G141 -6377 250.58
1138 G275 -5439 119.58 1172 G207 -5915 119.58 1206 G139 -6391 119.58
1139 G273 -5453 250.58 1173 G205 -5929 250.58 1207 G137 -6405 250.58
1140 G271 -5467 119.58 1174 G203 -5943 119.58 1208 G135 -6419 119.58
1141 G269 -5481 250.58 1175 G201 -5957 250.58 1209 G133 -6433 250.58
1142 G267 -5495 119.58 1176 G199 -5971 119.58 1210 G131 -6447 119.58
1143 G265 -5509 250.58 1177 G197 -5985 250.58 1211 G129 -6461 250.58
1144 G263 -5523 119.58 1178 G195 -5999 119.58 1212 G127 -6475 119.58
1145 G261 -5537 250.58 1179 G193 -6013 250.58 1213 G125 -6489 250.58
1146 G259 -5551 119.58 1180 G191 -6027 119.58 1214 G123 -6503 119.58
1147 G257 -5565 250.58 1181 G189 -6041 250.58 1215 G121 -6517 250.58
1148 G255 -5579 119.58 1182 G187 -6055 119.58 1216 G119 -6531 119.58
1149 G253 -5593 250.58 1183 G185 -6069 250.58 1217 G117 -6545 250.58
1150 G251 -5607 119.58 1184 G183 -6083 119.58 1218 G115 -6559 119.58
1219 G113 -6573 250.58 1240 G71 -6867 119.58 1261 G29 -7161 250.58
1220 G111 -6587 119.58 1241 G69 -6881 250.58 1262 G27 -7175 119.58
1221 G109 -6601 250.58 1242 G67 -6895 119.58 1263 G25 -7189 250.58
1222 G107 -6615 119.58 1243 G65 -6909 250.58 1264 G23 -7203 119.58
1223 G105 -6629 250.58 1244 G63 -6923 119.58 1265 G21 -7217 250.58
1224 G103 -6643 119.58 1245 G61 -6937 250.58 1266 G19 -7231 119.58
1225 G101 -6657 250.58 1246 G59 -6951 119.58 1267 G17 -7245 250.58
1226 G99 -6671 119.58 1247 G57 -6965 250.58 1268 G15 -7259 119.58
1227 G97 -6685 250.58 1248 G55 -6979 119.58 1269 G13 -7273 250.58
1228 G95 -6699 119.58 1249 G53 -6993 250.58 1270 G11 -7287 119.58
1229 G93 -6713 250.58 1250 G51 -7007 119.58 1271 G9 -7301 250.58
1230 G91 -6727 119.58 1251 G49 -7021 250.58 1272 G7 -7315 119.58
1231 G89 -6741 250.58 1252 G47 -7035 119.58 1273 G5 -7329 250.58
1232 G87 -6755 119.58 1253 G45 -7049 250.58 1274 G3 -7343 119.58
1233 G85 -6769 250.58 1254 G43 -7063 119.58 1275 G1 -7357 250.58
1234 G83 -6783 119.58 1255 G41 -7077 250.58 1276 DUMMY -7371 119.58
1235 G81 -6797 250.58 1256 G39 -7091 119.58 1277 DUMMY -7385 250.58
1236 G79 -6811 119.58 1257 G37 -7105 250.58 1278 DUMMY -7399 119.58
1237 G77 -6825 250.58 1258 G35 -7119 119.58 A1 -7480 251.58
1238 G75 -6839 119.58 1259 G33 -7133 250.58 A2 7480 255.58
Note2. When in parallel mode, unused data pins must be connected to “1” or “0”.
Note3. When CSX=”1”, there is no influence to the parallel and serial interface.
Absolute maximum limitation, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the
3. The Max. value is between measured point of source output and gamma setting value.
Current Consumption
Typical Maximum
Operation Mode Image
IDDI IDD IDDI IDD
(mA) (mA) (mA) (mA)
Normal Mode Black 0.005 6.0 0.01 7.5
Partial + Idle Mode (48 lines) Black 0.005 5.0 0.01 6.0
Sleep-in Mode N/A 0.005 0.015 0.01 0.03
Table 3 Power Consumption
Notes:
Trgbf
Trgbr TSYNCS
HSYNC
VSYNC
TENS TENH
VIH VIH
ENABLE
VIL VIL
Trgbf Trgbr
PWDL PWDH
TPDS TPDH
TRT
Display
Normal operation During reset Initial condition
status (Default for H/W reset)
Notes:
1. The reset cancel includes also required time for loading ID bytes, VCOM setting and other settings from NVM (or similar device) to
registers. This loading is done every time when there is HW reset cancel time (tRT) within 5 ms after a rising edge of RESX.
2. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below:
3. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120
ms, when Reset Starts in Sleep Out –mode. The display remains the blank state in Sleep In –mode.) and then return to Default condition
4. Spike Rejection also applies during a valid reset pulse as shown below:
7. It is necessary to wait 5msec after releasing RESX before sending commands. Also Sleep Out command cannot be sent for
120msec.
IM3 IM2 IM1 IM0 Interface D/CX RDX WRX Read back selection
RESX “1”
CSX
D/CX
RDX
WRX
Figure 11 8080-series parallel bus protocol, read data from register or display RAM
The LCD driver reads the data at the rising edge of WRX signal. The D/CX is the data/command flag.
When D/CX=’1’, D[17:0] bits is either display data or command parameter. When D/C=’0’, D[17:0] bits is
command.
The 8080-Ⅱ series bi-directional interface can be used for communication between the micro controller
and LCD driver. Interface bus width can be selected with IM3, IM2, IM1 and IM0.The interface functions of
8080-Ⅱ series parallel interface are given in Table 12 The function of 8080-Ⅱ series parallel interface.
Any instruction can be sent in any order to the driver. The MSB is transmitted first. The serial interface is
initialized when CSX is high. In this state, SCL clock pulse or SDA data have no effect. A falling edge on CSX
enables the serial interface and indicates the start of data transmission.
Figure 13 3-line serial interface write protocol (write to register with control bit in transmission)
Figure 14 4-line serial interface write protocol (write to register with control bit in transmission)
After the read status command has been sent, the SDA line must be set to tri-state no later than at the
falling edge of SCL of the last bit.
S TB TB P S
CSX
SCL
D/CX 0
Interface-І SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7
Hi-Z
SDA D7 D6 D5 D4 D3 D2 D1 D0 D7
Interface-!
Hi-Z
SDO D7 D6 D5 D4 D3 D2 D1 D0
2-wire data lane serial interface use: CSX (chip enable), DCX (serial clock) and SDA (serial data
input/output 1), and WRX (serial data input 2). To enter this interface, command E7h need set 10h.
Figure 18 3-line serial interface write protocol (write to register with control bit in transmission)
Read function:
The read mode of 2-wire data lane serial interface is the same with the 3-line serial interface and WRX
pin can be ignored. To achieve read function, the micro controller first has to send a command (read ID or
register command) and then the following byte is transmitted in the opposite direction. After that CSX is
required to go to high before a new command is send (see the below figure). The driver samples the SDA
(input data) at rising edge of SCL, but shifts SDA (output data) at the falling edge of SCL. Thus the micro
controller is supported to read at the rising edge of SCL.
After the read status command has been sent, the SDA line must be set to tri-state no later than at the
falling edge of SCL of the last bit.
If there is a break in data transmission by CSX pulse, while transferring a command or frame memory
data or multiple parameter command data, before Bit D0 of the byte has been completed, then driver will
reject the previous bits and have reset the interface such that it will be ready to receive the same byte
re-transmitted when the chip select line (CSX) is next activated.
If 1, 2 or more parameter commands are being sent and a break occurs while sending any parameter
before the last one and if the host then sends a new command rather than re-transmitting the parameter that
was interrupted, then the parameters that were successfully sent are stored and the parameter where the
break occurred is rejected. The interface is ready to receive next byte as shown below.
If a 2 or more parameter commands are being sent and a break occurs by the other command before the
last one is sent, then the parameters that were successfully sent are stored and the other parameter of that
command remains previous value.
Note 1: These apply to all data transfer Color modes on both serial and parallel interfaces.
Note 2: The frame memory can contain both odd and even number of pixels for both methods. Only complete pixel data will be stored in
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
12 bits 12 bits
Look-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-time transfer is used to transmit 2 pixel data with the 12-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
16 bits 16 bits
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
D1 0 - - - -
D0 0 - - - -
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Note 1: The data order is as follows, MSB=D17, LSB=D10 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit
0 for Red and Blue data.
Note 2: 2-times transfer transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
D11 0 - - - -
D10 0 - - - -
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D10 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
D15 - - - - -
D14 - - - - -
D13 - - - - -
D12 - - - - -
12 bits 12 bits
Look-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 1-times transfer (D11 to D0) is used to transmit 1 pixel data with the 12-bit color depth information.
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
Note 2: 1-times transfer (D15 to D0) is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
D9 - - - - -
D8 - - - - -
D1 0 - - - -
D0 0 - - - -
18 bits
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
D9 - - - - -
D8 - - - - -
D1 0 - - - -
D0 0 - - - -
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
Note 2: 1-times transfer (D17~D10, D8~D1) is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
D11 - - - - -
D10 - - - - -
D2 0 - - - -
D1 0 - - - -
18 bits
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
D11 - - - - -
D10 - - - - -
D2 0 - - - -
D1 0 - - - -
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
8.8.19 16-bit data bus for 18-bit/pixel (RGB-6-6-6-bit input), 262K-Colors, 3Ah=”06h”,
Version 1.3 Page 84 of 316 2014/03
Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or
disclosed in whole or in part without prior written permission of Sitronix.
ST7789V
MDT[1:0]=”10b”
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D1 and picture data is MSB=Bits 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-times transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Note 1: The data order is as follows, MSB=D7, LSB=D0 and picture data is MSB=Bit 4, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-time transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
D8 - - - - -
D1 0 - - - -
D0 0 - - - -
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D8, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-time transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
Note 1: The data order is as follows, MSB=D16, LSB=D9 and picture data is MSB=Bit 4, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-time transfer is used to transmit 1 pixel data with the 16-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D9 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 2-time transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
“1”
RESX
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
D17 0 - - - -
D10 0 - - - -
D9 - - - - -
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D16, LSB=D11 and picture data is MSB=Bit 5, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 3-time transfer is used to transmit 1 pixel data with the 18-bit color depth information.
Note 3: ‘-‘ = Don’t care – Can be set to ‘0’ or ‘1’
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
D17 - - - - -
D16 - - - - -
D15 - - - - -
D14 - - - - -
D13 - - - - -
D12 - - - - -
12 bits 12 bits
Look-Up Table for 4096 Color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D11, LSB=D0 and picture data is MSB=Bit 3, LSB=Bit 0 for Red, Green and Blue data.
Note 2: 1-times transfer is used to transmit 1 pixel data with the 12-bit color depth information.
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data.
Note 2: 1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.
Note 1: The data order is as follows, MSB=D15, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Green, and MSB=Bit 4, LSB=Bit 0
for Red and Blue data.
CSX
D/CX
WRX
“1”
RDX
8080-series control pins
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Note 1: The data order is as follows, MSB=D17, LSB=D0 and picture data is MSB=Bit 5, LSB=Bit 0 for Read, Green and Blue data.
Note 2: 1-times transfer (D17o D0) is used to transmit 1 pixel data with the 18-bit color depth information.
CSX
D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDA 1 R15 R14 R13 R12 R11 R10 - - 1 G15 G14 G13 G12 G11 G10 - - 1 B15 B14 B13 B12 B11 B10 - -
Pixel n
SCL
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
8.8.41 Write data for 12-bit/pixel (RGB 4-4-4-bit input), 4K-Colors, 3Ah=”03h”
“1”
RESX
CSX
“1”
D/CX
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA R13 R12 R11 R10 G13 G12 G11 G10 B13 B12 B11 B10 R23 R22 R21 R20 G23 G22 G21 G20 B23 B22 B21 B20
SCL
12 bits 12 bits
Look-up table for 4096 color data mapping (12 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
CSX
“1”
D/CX
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SDA R14 R13 R12 R11 R10 G15 G14 G13 G12 G11 G10 B14 B13 B12 B11 B10 R24 R23 R22 R21 R20 G25 G24 G23
SCL
16 bits 16 bits
Look-up table for 65k color data mapping (16 bits to 18 bits)
18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
D17 R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4 R5, Bit 4
D16 R1, Bit 3 R2, Bit 3 R3, Bit 3 R4, Bit 3 R5, Bit 3
D15 R1, Bit 2 R2, Bit 2 R3, Bit 2 R4, Bit 2 R5, Bit 2
D14 R1, Bit 1 R2, Bit 1 R3, Bit 1 R4, Bit 1 R5, Bit 1
D13 R1, Bit 0 R2, Bit 0 R3, Bit 0 R4, Bit 0 R5, Bit 0
D12 - - - - -
D11 G1, Bit 5 G2, Bit 5 G3, Bit 5 G4, Bit 5 G5, Bit 5
D10 G1, Bit 4 G2, Bit 4 G3, Bit 4 G4, Bit 4 G5, Bit 4
D9 G1, Bit 3 G2, Bit 3 G3, Bit 3 G4, Bit 3 G5, Bit 3
D8 G1, Bit 2 G2, Bit 2 G3, Bit 2 G4, Bit 2 G5, Bit 2
D7 G1, Bit 1 G2, Bit 1 G3, Bit 1 G4, Bit 1 G5, Bit 1
D6 G1, Bit 0 G2, Bit 0 G3, Bit 0 G4, Bit 0 G5, Bit 0
D5 B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4 B5, Bit 4
D4 B1, Bit 3 B2, Bit 3 B3, Bit 3 B4, Bit 3 B5, Bit 3
D3 B1, Bit 2 B2, Bit 2 B3, Bit 2 B4, Bit 2 B5, Bit 2
D2 B1, Bit 1 B2, Bit 1 B3, Bit 1 B4, Bit 1 B5, Bit 1
D1 B1, Bit 0 B2, Bit 0 B3, Bit 0 B4, Bit 0 B5, Bit 0
D0 - - - - -
16 bits 16 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
D17 R1, Bit 5 R2, Bit 5 R3, Bit 5 R4, Bit 5 R5, Bit 5
D16 R1, Bit 4 R2, Bit 4 R3, Bit 4 R4, Bit 4 R5, Bit 4
D15 R1, Bit 3 R2, Bit 3 R3, Bit 3 R4, Bit 3 R5, Bit 3
D14 R1, Bit 2 R2, Bit 2 R3, Bit 2 R4, Bit 2 R5, Bit 2
D13 R1, Bit 1 R2, Bit 1 R3, Bit 1 R4, Bit 1 R5, Bit 1
D12 R1, Bit 0 R2, Bit 0 R3, Bit 0 R4, Bit 0 R5, Bit 0
D11 G1, Bit 5 G2, Bit 5 G3, Bit 5 G4, Bit 5 G5, Bit 5
D10 G1, Bit 4 G2, Bit 4 G3, Bit 4 G4, Bit 4 G5, Bit 4
D9 G1, Bit 3 G2, Bit 3 G3, Bit 3 G4, Bit 3 G5, Bit 3
D8 G1, Bit 2 G2, Bit 2 G3, Bit 2 G4, Bit 2 G5, Bit 2
D7 G1, Bit 1 G2, Bit 1 G3, Bit 1 G4, Bit 1 G5, Bit 1
D6 G1, Bit 0 G2, Bit 0 G3, Bit 0 G4, Bit 0 G5, Bit 0
D5 B1, Bit 5 B2, Bit 5 B3, Bit 5 B4, Bit 5 B5, Bit 5
D4 B1, Bit 4 B2, Bit 4 B3, Bit 4 B4, Bit 4 B5, Bit 4
D3 B1, Bit 3 B2, Bit 3 B3, Bit 3 B4, Bit 3 B5, Bit 3
D2 B1, Bit 2 B2, Bit 2 B3, Bit 2 B4, Bit 2 B5, Bit 2
D1 B1, Bit 1 B2, Bit 1 B3, Bit 1 B4, Bit 1 B5, Bit 1
D0 B1, Bit 0 B2, Bit 0 B3, Bit 0 B4, Bit 0 B5, Bit 0
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
D5 R1, Bit 4 G1, Bit 5 B1, Bit 4 R2, Bit 4 G2, Bit 5
D4 R1, Bit 3 G1, Bit 4 B1, Bit 3 R2, Bit 3 G2, Bit 4
D3 R1, Bit 2 G1, Bit 3 B1, Bit 2 R2, Bit 2 G2, Bit 3
D2 R1, Bit 1 G1, Bit 2 B1, Bit 1 R2, Bit 1 G2, Bit 2
D1 R1, Bit 0 G1, Bit 1 B1, Bit 0 R2, Bit 0 G2, Bit 1
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
D4 R1, Bit 4 G1, Bit 4 B1, Bit 4 R2, Bit 4 G2, Bit 4
D3 R1, Bit 3 G1, Bit 3 B1, Bit 3 R2, Bit 3 G2, Bit 3
D2 R1, Bit 2 G1, Bit 2 B1, Bit 2 R2, Bit 2 G2, Bit 2
D1 R1, Bit 1 G1, Bit 1 B1, Bit 1 R2, Bit 1 G2, Bit 1
D0 R1, Bit 0 G1, Bit 0 B1, Bit 0 R2, Bit 0 G2, Bit 0
18 bits 18 bits
Frame memory
R1 G1 B1 R2 G2 B2 R3 G3 B3
Typical value are related to the setting of dot clock is 7MHz and frame rate is 70Hz..
If the setting of hpw is 10 dot clocks and hbp is 10 dot clocks, the setting of HBP in command B1h is 20 dot clocks
Typical value are related to the setting of dot clock is 17MHz and frame rate is 60Hz..
Note: The setting of front porch and back porch in host must match that in IC as this mode.
VSYNC
Display Scan
Write Data to
Frame Memory 1 Line
D[17:0]
Gate1
Gate2
Gate320
Source
1. VSYNC period should always be constant. If not, some degradation of display such as flicker may occur in LCD system.
2. Display data don’t need to be written for every VSYNC period. For example, any system is working under 60Hz frame rate and
30-fps motion picture condition. So being written display data for every other frame would be enough.
1. When RAM writing does not start immediately after the falling edge of VSYNC, the time between the falling edge of VSYNC and
1. The minimum DRAM write speed must be satisfied and the frequency variation must be taken into consideration.
2. The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an
entire display.
3. When switching from the internal clock operation mode to the VSYNC interface mode or inversely, the switching starts from the
next VSYNC cycle, i.e. after completing the display of the frame.
4. The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to
TF-LCD panel
(240 x RGB x 320)
239 238 0
(MADCTR) MX=1
Color R G B R G B R G B
Data
Page
(MADCTR) (MADCTR)
MY=0 MY=1
0 319
1 318
2 317
3 316
4 315
5 314
6 313
7 312
: :
312 7
313 6
314 5
315 4
316 3
317 2
318 1
319 0
Source output 0 1 2 3 4 5 717 718 719
For example the whole display contents will be written, the window is defined by the following values:
XS=0 (0h) YS=0 (0h) and XE=239 (Efh), YE=319 (13Fh).
In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address
(Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode
(V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and
Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers
wrap around to address (X=XS and Y=YS).
For flexibility in handling a wide variety of display architectures, the commands “CASET, RASET and
MADCTL”, define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations
of flags are allowed. Section 8.12 show the available combinations of writing to the display RAM. When MX,
MY and MV will be changed the data bust be rewritten to the display RAM.
For each image condition, the controls for the column and row counters apply as below
Condition Column Counter Row Counter
Return to Return to
When RAMWR/RAMRD command is accepted
“Start Column (XS)” “Start Row (YS)”
Complete Pixel Read / Write action Increment by 1 No change
Return to
The Column counter value is larger than “End Column (XE)” Increment by 1
“Start Column (XS)”
The Column counter value is larger than “End Column (XE)” Return to Return to
and the Row counter value is larger than “End Row (YE)” “Start Column (XS)” “Start Row (YS)”
Y-Mirror 0 0 1
X-Mirror 0 1 0
X-Mirror 0 1 1
Y-Mirror
X-Y 1 0 0
Exchange
X-Y 1 0 1
Exchange
Y-Mirror
X-Y 1 1 0
Exchange
X-Mirror
X-Y 1 1 1
Exchange
X-Mirror
Y-Mirror
Figure 33 Display data RAM organization
Example2) Partial Display On: PSL[15:0] = 0004h, PEL[15:0] = 013Ch, MADCTR (ML)=0
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA) =320. In this case, ‘rolling’ scrolling is
applied as shown below. All the memory contents will be used.
Example1) Panel size=240 x 320, TFA =3, VSA=315, BFA=2, SSA=4, MADCTR ML=0: Rolling Scroll
1
1
2
2
1
1
3
3
2
1
1
2
3
3
2
1
tvdh= The LCD display is not updated from the Frame Memory
tvdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)
Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information, there is one
V-sync and 320 H-sync pulses per field.
thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line – see above)
Note: During Sleep In Mode, the Tearing Output Pin is active Low.
The signal’s rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to avoid
Tearing Effect:
Data write to Frame Memory is now synchronized to the Panel Scan. It should be written during the
vertical sync pulse of the Tearing Effect Output Line. This ensures that data is always written ahead of the
panel scan and each Panel Frame refresh has a complete new image:
The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one horizontal
sync pulse of the Tearing Effect Output Line. This allows time for the image to download behind the Panel
Read pointer and finishing download during the subsequent Frame before the Read Pointer “catches” the
MPU to Frame memory write position.
Note 1: There will be no damage to the display module if the power sequences are not met.
Note 2: There will be no abnormal visible effects on the display panel during the Power On/Off Sequences.
Note 3: There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out
command. Also between receiving Sleep In command and Power Off Sequence.
Note 4: If RESX line is not held stable by host during Power On Sequence as defined in the sequence below, then it will be necessary to
apply a Hardware Reset (RESX) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not
guaranteed.
VDD
VDDI
Timing when the latter signal rises up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross
point of 90% of 2.75V, not 90% of 2.6V.
Timing when the latter signal falls up to 90% of its typical value.
e.g. When VDD comes later, this timing is defined at the cross
point of 90% of 2.75V, not 90% of 2.6V.
CSX H or L
TrPW-RESX = + no limit
If uncontrolled power-off happened, the display will go blank and there will not any visible effect on the
display (blank display) and remains blank until “Power On Sequence” powers it up.
5. Sleep In Mode
In this mode, the DC: DC converter, internal oscillator and panel driver circuit are stopped. Only the MCU
interface and memory works with VDDI power supply. Contents of the memory are safe.
Note: Transition between modes 1-5 is controllable by MCU commands. Mode 6 is entered only when both Power supplies are removed.
SLP IN
Sleep out Sleep in
Normal display mode on SLP OUT Normal display mode on
Idle mode on Idle mode on
SLP IN
Sleep out Sleep in
Partial display mode on SLP OUT Partial display mode on
Idle mode off Idle mode off
Percentage adjustment:
J0P[1:0], J1P[1:0], J0N[1:0], J1N[1:0] these register are used to adjust the voltage level of interpolation
point. The following table is the detail description.
J0P[1:0]/J0N[1:0]:
00h 01h 02h 03h
VP3/VN3 50% 56% 50% 60%
VP5/VN5 50% 44% 50% 42%
VP7/VN7 86% 71% 80% 66%
VP8/VN8 71% 57% 63% 49%
VP9/VN9 57% 40% 49% 34%
VP10/VN10 43% 29% 34% 23%
VP11/VN11 29% 17% 20% 14%
VP12/VN12 14% 6% 9% 6%
J1P[1:0]/J1N[1:0]:
00h 01h 02h 03h
VP51/VN51 86% 86% 86% 89%
VP52/VN52 71% 71% 77% 80%
VP53/VN53 57% 60% 63% 69%
VP54/VN54 43% 46% 46% 51%
VP55/VN55 29% 34% 31% 37%
VP56/VN56 14% 17% 14% 20%
VP58/VN58 50% 56% 47% 47%
VP60/VN60 50% 50% 50% 53%
ST7789V digital gamma function can implement the RGB gamma correction independently. ST7789V
utilizes look-up table of digital gamma to change ram data, and then display the changed data from source
driver. The following diagram shows the data flow of digital gamma.
There are 2 registers and each register has 64 bytes to set R, G, B gamma independently. When bit
DGMEN be set to 1, R and B gamma will be mapped via look-up table of digital gamma to gray level voltage.
Dimming function can be enable and disable. See “Write CTRL Display (53h)” (bit DD) for more
information.
The dimming function is working similarly in both upward and downward directions.
Note 1: Updating partial area of the image data should be supported by CABC functionality.
Note 2: Processing power consumption of CABC should be minimized.
Note 3: Customer need program OTP GAMMA when using CABC.
Transition time from the previous image to the current displayed image is “transition time A”.
100%
90%
Display brightness
80%
70% Content Adaptive
Brightness Control
50%
0%
Time
This function does not affect to the other function, manual brightness setting. Manual brightness can be
set the display brightness to less than CABC minimum brightness. Smooth transition and dimming function
can be worked as normal.
When display brightness is turned off (BCTRL=0 of “9.1.39 Write CTRL Display (53h)”), CABC minimum
brightness setting is ignored. “9.1.44 Read CABC minimum brightness (5Fh)” always read the setting value of
“9.1.43 Write CABC minimum brightness (5Eh)”.
Below drawing is for the explanation of the CABC minimum brightness setting.
brightness formula
At the case 2, the calculation result of the display brightness is 14%. CABC minimum brightness value is
set to 20% brightness. Actual display brightness is 20% as the CABC minimum brightness setting.
1 1 ↑ - - - - - - - - - Dummy read
RDDID 1 1 ↑ - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID1 read
1 1 ↑ - ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID2 read
1 1 ↑ - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 ID3 read
Read display
0 ↑ 1 - 0 0 0 0 1 0 0 1 (09h)
status
1 1 ↑ - - - - - - - - - Dummy read
Read display
0 ↑ 1 - 0 0 0 0 1 0 1 0 (0Ah)
power
RDDPM
1 1 ↑ - - - - - - - - - Dummy read
Read display
0 ↑ 1 - 0 0 0 0 1 1 0 0 (0Ch)
RDD pixel
1 1 ↑ - 0 D6 D5 D4 0 D2 D1 D0 -
Read display
0 ↑ 1 - 0 0 0 0 1 1 0 1 (0Dh)
image
RDDIM
1 1 ↑ - - - - - - - - - Dummy read
Read display
0 ↑ 1 - 0 0 0 0 1 1 1 0 (0Eh)
RDDSM signal
1 1 ↑ - - - - - - - - - Dummy read
1 1 ↑ - TEON TEM 0 0 0 0 0 0 -
Read display
0 ↑ 1 - 0 0 0 0 1 1 1 1 (0Fh) self-diagnostic
RDDSDR result
1 1 ↑ - - - - - - - - - Dummy read
1 1 ↑ - D7 D6 0 0 0 0 0 0 -
Partial off
NORON 0 ↑ 1 - 0 0 0 1 0 0 1 1 (13h)
(Normal)
Display inversion
INVOFF 0 ↑ 1 - 0 0 1 0 0 0 0 0 (20h)
off
Display inversion
INVON 0 ↑ 1 - 0 0 1 0 0 0 0 1 (21h)
on
Column address
0 ↑ 1 - 0 0 1 0 1 0 1 0 (2Ah)
set
1 ↑ 1 - XS15 XS14 XS13 XS12 XS11 XS10 XS9 XS8 X address start:
CASET
1 ↑ 1 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 0≦XS≦X
1 ↑ 1 XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE8 X address start:
1 ↑ 1 - YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS8 Y address start:
RASET 1 ↑ 1 YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 0≦YS≦Y
1 ↑ 1 YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE8 Y address start:
1 1 ↑ - - - - - - - - - Dummy read
1 1 ↑ Dx[17:8] Dx[7] Dx[6] Dx[5] Dx[4] Dx[3] Dx[2] Dx[1] Dx[0] Read data
Partial sart/end
0 ↑ 1 - 0 0 1 1 0 0 0 0 (30h)
address set
1 ↑ 1 - PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8 Partial start
address: (0,
PTLAR 1 ↑ 1 - PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0
1,2, ..P)
1 ↑ 1 - PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8 Partial end
Vertical scrolling
0 ↑ 1 - 0 0 1 1 0 0 1 1 (33h)
definition
Tearing effect
TEOFF 0 ↑ 1 - 0 0 1 1 0 1 0 0 (34h)
line off
Tearing effect
TEON 0 ↑ 1 - 0 0 1 1 0 1 0 1 (35h)
line on
1 ↑ 1 - - - - - - - - TEM
Memory data
0 ↑ 1 - 0 0 1 1 0 1 1 0 (36h)
MADCTL access control
1 ↑ 1 - MY MX MV ML RGB 0 0 0 -
Vertical scrolling
0 ↑ 1 - 0 0 1 1 0 1 1 1 (37h)
start address
VSCRSADD
1 ↑ 1 - VSP15 VSP14 VSP13 VSP12 VSP11 VSP10 VSP9 VSP8
Interface pixel
0 ↑ 1 - 0 0 1 1 1 0 1 0 (3Ah)
COLMOD format
1 ↑ 1 - 0 D6 D5 D4 0 D2 D1 D0 Interface format
Memory write
0 ↑ 1 - 0 0 1 1 1 1 0 0 (3Ch)
continue
RAMWRC 1 ↑ 1 D1[17:8] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0]
1 ↑ 1 Dx[17:8] Dx[7] Dx[6] Dx[5] Dx[4] Dx[3] Dx[2] Dx[1] Dx[0] Write data
Memory read
0 ↑ 1 - 0 0 1 1 1 1 1 0 (3Eh)
continue
1 1 ↑ - - - - - - - - - Dummy Read
RAMRDC
1 1 ↑ D1[17:8] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0]
1 ↑ 1 - N7 N6 N5 N4 N3 N2 N1 N0
1 1 ↑ - - - - - - - - - Dummy Read
RDTESCAN
1 1 ↑ - - - - - - - N9 N8
1 1 ↑ - N7 N6 N5 N4 N3 N2 N1 N0
Read display
0 ↑ 1 - 0 1 0 1 0 0 1 0 (52h)
brightness value
RDDISBV
1 1 ↑ - - - - - - - - - Dummy read
Write CTRL
0 ↑ 1 - 0 1 0 1 0 0 1 1 (53h)
WRCTRLD display
1 ↑ 1 - 0 0 BCTRL 0 DD BL 0 0
Read CTRL
0 ↑ 1 - 0 1 0 1 0 1 0 0 (54h)
RDCTRLD value dsiplay
1 1 ↑ - - - - - - - - - Dummy read
1 1 ↑ - 0 0 BCTRL 0 DD BL 0 0
Write content
adaptive
0 ↑ 1 - 0 1 0 1 0 1 0 1 (55h) brightness
WRCACE
control and Color
enhancemnet
Read content
adaptive
0 ↑ 1 - 0 1 0 1 0 1 1 0 (56h)
brightness
RDCABC
control
1 1 ↑ - - - - - - - - - Dummy read
1 1 ↑ - 0 CECTRL 0 0 0 0 C1 C0
Write CABC
0 ↑ 1 - 0 1 0 1 1 1 1 0 (5Eh) minimum
WRCABCMB
brightness
Read CABC
0 ↑ 1 - 0 1 0 1 1 1 1 1 (5Fh) minimum
brightness
RDCABCMB
1 1 ↑ - - - - - - - - - Dummy read
Read Automatic
Brightness
0 ↑ 1 - 0 1 1 0 1 0 0 0 (68h) Control
Self-Diagnostic
RDABCSDR
Result
1 1 ↑ - - - - - - - - - Dummy read
1 1 ↑ - D7 D6 0 0 0 0 0 0 -
1 1 ↑ - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 Read parameter
1 1 ↑ - ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 Read parameter
1 1 ↑ - - - - - - - - - Dummy read
1 1 ↑ ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 Read parameter
NOP 0 ↑ 1 - 0 0 0 0 0 0 0 0 (00h)
Parameter No Parameter -
Restriction
Status Availability
Sleep In Yes
Flow Chart
SWRESET 0 ↑ 1 - 0 0 0 0 0 0 0 1 (01h)
Parameter No Parameter -
Description -The display module performs a software reset, registers are written with their SW reset default values.
It will be necessary to wait 5msec before sending new command following software reset.
The display module loads all display suppliers’ factory default values to the registers during this 5msec.
Restriction
If software reset is sent during sleep in mode, it will be necessary to wait 120msec before sending sleep out command.
Status Availability
Sleep In Yes
SWRESET Command
Parameter
Display whole
blank screen
Display
Set
Flow Chart Commands
to S/W
Default
Value Action
Sleep In Mode
Mode
Sequential
transter
RDDID 0 ↑ 1 - 0 0 0 0 0 1 0 0 (04h)
st
1 parameter 1 1 ↑ - - - - - - - - - -
2nd parameter 1 1 ↑ - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
3rd parameter 1 1 ↑ - ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20
th
4 parameter 1 1 ↑ - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
-Commands RDID1/2/3(Dah, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h,
respectively.
Restriction
Status Availability
Sleep In Yes
Display
Parameter
Dummy Dummy
Clock Read
Display
Flow Chart
Send 2nd Send 2nd
parameter parameter
Action
Sequential
transter
Send 4th Send 4th
parameter parameter
RDDST 0 ↑ 1 - 0 0 0 0 1 0 0 1 (09h)
st
1 parameter 1 1 ↑ - - - - - - - - - -
3rd parameter 1 1 ↑ - ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLOUT NORON
th
4 parameter 1 1 ↑ - ST15 ST14 INVON ST12 ST11 DISON TEON GCS2
5th parameter 1 1 ↑ - GCS1 GCS0 TEM ST4 ST3 ST2 ST1 ST0
This command indicates the current status of the display as described in the table below:
MY Row Address Order (MY) ‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’)
MX Column Address Order (MX) ‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’)
MV Row/Column Exchange (MV) ‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’)
‘1’=Increment,
RGB RGB/ BGR Order (RGB) ‘1’ =BGR, (When MADCTL (36h) D3=’1’)
‘1’ =Increment,
ST15 Vertical Scrolling Status (Not Used) ‘1’ = Scroll on,“0” = Scroll off
ST14 Horizontal Scroll Status (Not Used) ‘0’
INVON Inversion Status ‘1’ = On, “0” = Off
ST12 All Pixels On (Not Used) ‘0’
ST11 All Pixels Off (Not Used) ‘0’
DISON Display On/Off ‘1’ = On, “0” = Off
TEON Tearing effect line on/off ‘1’ = On, “0” = Off
GCSEL2 “000” = GC0
Restriction
Status Availability
Sleep In Yes
Flow Chart
RDDPM 0 ↑ 1 - 0 0 0 0 1 0 1 0 (0Ah)
1st parameter 1 1 ↑ - - - - - - - - - -
This command indicates the current status of the display as described in the table below:
Restriction
Status Availability
Sleep In Yes
Flow Chart
RDDMADCTL 0 ↑ 1 - 0 0 0 0 1 0 1 1 (0Bh)
st
1 parameter 1 1 ↑ - - - - - - - - - -
This command indicates the current status of the display as described in the table below:
MY Row Address Order (MY) ‘1’ =Decrement, (Bottom to Top, when MADCTL (36h) D7=’1’)
MX Column Address Order (MX) ‘1’ =Decrement, (Right to Left, when MADCTL (36h) D6=’1’)
MV Row/Column Exchange (MV) ‘1’ = Row/column exchange, (when MADCTL (36h) D5=’1’)
RGB RGB/ BGR Order (RGB) ‘1’ =BGR, (When MADCTL (36h) D3=’1’)
‘1’ =Increment,
Restriction
Status Availability
Sleep In Yes
Flow Chart
RDDCOLMOD 0 ↑ 1 - 0 0 0 0 1 1 0 0 (0Ch)
st
1 parameter 1 1 ↑ - - - - - - - - - -
2nd parameter 1 1 ↑ - 0 D6 D5 D4 0 D2 D1 D0
This command indicates the current status of the display as described in the table below:
D7 - Set to ‘0’
D6
‘101’ = 16 bit/pixel
D5 RGB interface color format
‘110’ = 18 bit/pixel
D4
Description
D3 - Set to ‘0’
D2
‘101’ = 16 bit/pixel
D1 Control interface color format
‘110’ = 18 bit/pixel
D0
Restriction
Status Availability
Sleep In Yes
Flow Chart
RDDIM 0 ↑ 1 - 0 0 0 0 1 1 0 1 (0Dh)
st
1 parameter 1 1 ↑ - - - - - - - - - -
This command indicates the current status of the display as described in the table below:
Gamma Curve Selection GC2 GC1 GC0 Gamma set (26h) Parameter
Restriction
Status Availability
Sleep In Yes
Flow Chart
RDDSM 0 ↑ 1 - 0 0 0 0 1 1 1 0 (0Eh)
st
1 parameter 1 1 ↑ - - - - - - - - - -
This command indicates the current status of the display as described in the table below:
‘1’ = ON,
TEON Tearing effect line on/off
Description ‘0’ = OFF,
‘1’ = mode2,
TEM Tearing effect line mode
‘0’ = mode1,
Restriction
Status Availability
Sleep In Yes
Flow Chart
RDDSDR 0 ↑ 1 - 0 0 0 0 1 1 1 1 (0Fh)
st
1 parameter 1 1 ↑ - - - - - - - - - -
2nd parameter 1 1 ↑ - D7 D6 0 0 0 0 0 0 -
This command indicates the current status of the display self-diagnostic result after sleep out command as described
below:
Restriction
Status Availability
Sleep In Yes
Flow Chart
SLPIN 0 ↑ 1 - 0 0 0 1 0 0 0 0 (10h)
parameter No Parameter
-This command causes the LCD module to enter the minimum power consumption mode.
-In this mode the DC/DC converter is stopped, internal oscillator is stopped, and panel scanning is stopped.
Description
-MCU interface and memory are still working and the memory keeps its contents.
-This command has no effect when module is already in sleep in mode. Sleep in mode can only be left by the sleep out
command (11h).
-It will be necessary to wait 5msec before sending any new commands to a display module following this command to
Restriction
allow time for the supply voltages and clock circuits to stabilize.
-It will be necessary to wait 120msec after sending sleep out command (when in sleep in mode) before sending an sleep
in command.
Status Availability
Sleep In Yes
Flow Chart
Drain Sleep In Mode
Charge
From LCD Action
Panel
Mode
Sequential
transter
SLPOUT 0 ↑ 1 - 0 0 0 1 0 0 0 1 (11h)
parameter No Parameter
-This command has no effect when module is already in sleep out mode. Sleep out mode can only be left by the sleep in
command (10h).
-It will be necessary to wait 5msec before sending any new commands to a display module following this command to
Restriction allow time for the supply voltages and clock circuits to stabilize.
-It will be necessary to wait 120msec after sending sleep out command (when in sleep in mode) before sending an sleep
in command.
-The display module runs the self-diagnostic functions after this command is received.
Status Availability
Sleep In Yes
SLPOUT Command
Display whole blank
screen for 2 firames
(Automatic No effect
to DISP ON/OFF Parameter
Start
Commands)
Internal
Oscillator
Display
Flow Chart
Start up Display Memory
DC:DC contents In
Converter accordance with
the current Action
command table
settings
Charge
Offset Mode
voltage for
LCD
Panel Sleep Out mode
Sequential
transter
PTLON 0 ↑ 1 - 0 0 0 1 0 0 1 0 (12h)
parameter No Parameter
-This command turns on Partial mode. The partial mode window is described by the Partial Area command (30h)
Description -To leave Partial mode, the Normal Display Mode On command (13h) should be written.
Status Availability
Sleep In Yes
NORON 0 ↑ 1 - 0 0 0 1 0 0 1 1 (13h)
parameter No Parameter
Restriction This command has no effect when normal display mode is active.
Status Availability
Sleep In Yes
Flow Chart See partial area description for details of when to use this command.
INVOFF 0 ↑ 1 - 0 0 1 0 0 0 0 0 (20h)
parameter No Parameter
Restriction This command has no effect when module is already in inversion off mode.
Status Availability
Sleep In Yes
Command
Display Parameter
Inversion On
Mode
Display
Flow Chart
INVOFF (20h)
Action
Display
Inversion OFF
Mode Mode
Sequential
transter
INVON 0 ↑ 1 - 0 0 1 0 0 0 0 1 (21h)
parameter No Parameter
Restriction This command has no effect when module is already in inversion on mode.
Status Availability
Sleep In Yes
Command
Display Parameter
Inversion OFF
Mode
Display
Flow Chart
INVON (21h)
Action
Display
Inversion ON
Mode Mode
Sequential
transter
GAMSET 0 ↑ 1 - 0 0 1 0 0 1 1 0 (26h)
-This command is used to select the desired Gamma curve for the current display. A maximum of 4
curves can be selected. The curve is selected by setting the appropriate bit in the parameter as
Values of GC[7:0] not shown in table above are invalid and will not change the current selected
Restriction
Gamma curve until valid value is received.
Status Availability
Register availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Flow Chart
DISPOFF 0 ↑ 1 - 0 0 1 0 1 0 0 0 (28h)
parameter No Parameter
- This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disabled and
Description
(Example)
Memory Display
Restriction This command has no effect when module is already in display off mode.
Status Availability
Sleep In Yes
Flow Chart
DISPON 0 ↑ 1 - 0 0 1 0 1 0 0 1 (29h)
parameter No Parameter
Description
(Example)
Memory Display
Restriction This command has no effect when module is already in display on mode.
Status Availability
Sleep In Yes
Command
Display Off
Parameter
Mode
Display
Flow Chart
DISPON
Action
Display On
Mode Mode
Sequential
transter
CASET 0 ↑ 1 - 0 0 1 0 1 0 1 0 (2Ah)
st
1 parameter 1 ↑ 1 - XS15 XS14 XS13 XS12 XS11 XS10 XS9 XS8
2nd parameter 1 ↑ 1 - XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0
3rd parameter 1 ↑ 1 - XE15 XE14 XE13 XE12 XE11 XE10 XE9 XE8
th
4 parameter 1 ↑ 1 - XE7 XE6 XE5 XE4 XE3 XE2 XE1 XE0
-The value of XS [7:0] and XE [7:0] are referred when RAMWR command comes.
2. Description
When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will
Restriction be ignored.
(Parameter range: 0 < XS [15:0] < XE [15:0] < 239 (00Efh)): MV=”0”)
(Parameter range: 0 < XS [15:0] < XE [15:0] < 319 (013Fh)): MV=”1”)
Status Availability
Register availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Flow Chart
RASET 0 ↑ 1 - 0 0 1 0 1 0 1 1 (2Bh)
st
1 parameter 1 ↑ 1 - YS15 YS14 YS13 YS12 YS11 YS10 YS9 YS8
2nd parameter 1 ↑ 1 - YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0
3rd parameter 1 ↑ 1 - YE15 YE14 YE13 YE12 YE11 YE10 YE9 YE8
th
4 parameter 1 ↑ 1 - YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0
-This command is used to defined area of frame memory where MCU can access.
-The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes.
YS[15:0]
3. Description
YE[15:0]
When YS [15:0] or YE [15:0] is greater than maximum address like below, data of out of range will
Restriction be ignored.
(Parameter range: 0 < YS [15:0] < YE [15:0] < 239 (00Efh)): MV=”0”)
(Parameter range: 0 < YS [15:0] < YE [15:0] < 319 (013Fh)): MV=”1”)
Status Availability
Register availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
CASET
Legend
Command
1st parameter XS[15:0]
2nd parameter XE[15:0]
Parameter
PASET
Display
Mode
RAMWR
Sequential
transter
Image Data
D1[7:0],D2[7:0]
…….Dn[7:0]
Any Command
RAMWR 0 ↑ 1 - 0 0 1 0 1 1 0 0 (2Ch)
st
1 parameter 1 ↑ 1 D1[17]-1[8] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0]
N parameter 1 ↑ 1 Dn[17]-n[8] Dn[7] Dn[6] Dn[5] Dn[4] Dn[3] Dn[2] Dn[1] Dn[0]
-When this command is accepted, the column register and the page register are reset to the start column/start
-The start column/start page positions are different in accordance with MADCTL setting.
Restriction
Status Availability
Register availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Command
RAMWR
Parameter
Display
Flow Chart
Image Data
D1[17:0],D2[17:0]
…….Dn[17:0] Action
Mode
Sequential
Any Command transter
RAMRD 0 ↑ 1 - 0 0 1 0 1 1 1 0 (2Eh)
st
1 parameter 1 1 ↑ - - - - - - - - -
1 1 ↑
..
..
..
..
..
..
..
..
..
th
(N+1) parameter 1 1 ↑ D17-8 D7 D6 D5 D4 D3 D2 D1 D0
-When this command is accepted, the column register and the row register are reset to the Start Column/Start
Row positions.
-The Start Column/Start Row positions are different in accordance with MADCTL setting.
-Then D[17:0] is read back from the frame memory and the column register and the row register incremented
Description
-Frame Read can be cancelled by sending any other command.
-The data color coding is fixed to 18-bit in reading function. Please see section 9.8 “Data color coding” for color
coding (18-bit cases), when there is used 8, 9, 16 and 18-bit data lines for image data.
Note1: The Command 3Ah should be set to 66h when reading pixel data from frame memory.
Restriction
Status Availability
Register availability Normal Mode On, Idle Mode On, Sleep Out Yes
Sleep In Yes
Flow Chart
PTLAR 0 ↑ 1 - 0 0 1 1 0 0 0 0 (30h)
st
1 parameter 1 ↑ 1 - PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8
2nd parameter 1 ↑ 1 - PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0
3rd parameter 1 ↑ 1 - PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8
th
4 parameter 1 ↑ 1 - PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0
-There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End
Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter.
PSL [15:0]
Non-display area
Start row
PEL [15:0]
Non-display area
End row
Non-display area
PSL [15:0]
Start row
Partial display area
Restriction Each detail initial value by the display resolution will be updated.
Status Availability
Sleep In Yes
Flow Chart
VSCRDEF 0 ↑ 1 - 0 0 1 1 0 0 1 1 (33h)
st
1
1 ↑ 1 - TFA15 TFA14 TFA13 TFA12 TFA11 TFA10 TFA9 TFA8
parameter
2nd
1 ↑ 1 - TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0
parameter
3rd
1 ↑ 1 - VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 VSA9 VSA8
parameter
4th
1 ↑ 1 - VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
parameter
5th
1 ↑ 1 BFA15 BFA14 BFA13 BFA12 BFA11 BFA10 BFA9 BFA8
parameter
6th
1 ↑ 1 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0
parameter
-This command just defines the Vertical Scrolling Area of the display and not performs vertical scroll
-The 1st & 2nd parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display).
-The 3rd & 4th parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory
[not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the bottom most line of the
-The 4th & 5th parameter BFA [6:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and
Display).
TFA, VSA and BFA refer to the Frame Memory Line Pointer
Description
Status Availability
Sleep In Yes
Normal Mode
VSCRDEF
Legend
Parameter
3rd parameter BFA[15:0]
CASET
Display
1st &2nd parameter XS[15:0]
Redefines the
3rd & 4th parameter XE[15:0] Frame Memory
Window that Action
Flow Chart
RASET the scroll data
will be written
1st &2nd parameter YS[15:0] to. Mode
Only required
for non-rolling
3rd &4th parameter YE[15:0]
scrolling Optional - It
Sequential
MADCTL
may be transter
necessary to
Parameter redefine the
frame memory
RAMWR
write direction.
VSCSAD
Scroll Mode
TEOFF 0 ↑ 1 - 0 0 1 1 0 1 0 0 (34h)
parameter No Parameter
Description -This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
Restriction This command has no effect when tearing effect output is already off..
Status Availability
Sleep In Yes
Command
TE Line Output
ON
Parameter
TEOFF Display
Flow Chart
Action
TE Line Output
OFF
Mode
Sequential
transter
TEON 0 ↑ 1 - 0 0 1 1 0 1 0 1 (35h)
parameter 1 ↑ 1 - 0 0 0 0 0 0 0 TEM
-This command is used to turn ON the Tearing Effect output signal from the TE signal line.
-The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line:
-When TEM =’0’: The Tearing Effect output line consists of V-Blanking information
only
Tvdl Tvdh
-When TEM =’1’: The Tearing Effect output Line consists of both V-Blanking and H-Blanking information
Tvdl Tvdh
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
Restriction This command has no effect when tearing effect output is already on.
Status Availability
Sleep In Yes
Command
TE Line Output
OFF
Parameter
TEON
Display
Flow Chart
TELOM
Action
TE Line Output
ON
Mode
Sequential
transter
MADCTL 0 ↑ 1 - 0 0 1 1 0 1 1 0 (36h)
parameter 1 ↑ 1 - MY MX MV ML RGB MH - -
RGB="0" RGB="1"
Driver IC Driver IC
R G B R G B R G B R G B R G B R G B
R G B R G B R G B B G R B G R B G R
R G B R G B R G B B G R B G R B G R
MH="0" MH="1"
Sent 2nd
Sent 3rd
Sent First
Sent First
Sent Last
Sent Last
Sent 2nd
Sent 3rd
Restriction
Register
Sleep In Yes
Legend
Command
MADCTL
Parameter
Display
Flow Chart
Action
1st parameter
B[7:0]
Mode
Sequential
transter
VSCSAD 0 ↑ 1 - 0 0 1 1 0 1 1 1 (37h)
ST
1 parameter 1 ↑ 1 - VSP15 VSP14 VSP13 VSP12 VSP11 VSP10 VSP9 VSP8
2ND parameter 1 ↑ 1 - VSP7 VSP6 VSP5 VSP4 VSP3 VSP2 VSP1 VSP0
-These two commands describe the scrolling area and the scrolling mode.
-The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory
will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below:
When ML=0
Example:
When Top Fixed Area = Bottom Fixed Area = 00, vertical Scrolling Area = 320 and VSP = ‘3’
Description
When ML=1
Example:
When Top Fixed Area = Bottom Fixed Area = 00, vertical Scrolling Area = 320 and VSP = ‘3’
NOTE: When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel
Since the value of the vertical scrolling start address is absolute (with reference to the frame memory), it must not
Restriction enter the fixed area (defined by Vertical Scrolling Definition (33h)- otherwise undesirable image will be displayed on
the panel)
Register
Sleep In Yes
IDMOFF 0 ↑ 1 - 0 0 1 1 1 0 0 0 (38h)
parameter No Parameter
Restriction This command has no effect when module is already in idle off mode
Status Availability
Sleep In Yes
Flow Chart
IDMON 0 ↑ 1 - 0 0 1 1 1 0 0 1 (39h)
parameter No Parameter
-There will be no abnormal visible effect on the display mode change transition.
1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame
Description
R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 B5 B4 B3 B4 B1
Color
R0 G0 B0
Black 0xxxxx 0xxxxx 0xxxxx
Blue 0xxxxx 0xxxxx 1xxxxx
Red 1xxxxx 0xxxxx 0xxxxx
Magenta 1xxxxx 0xxxxx 1xxxxx
Green 0xxxxx 1xxxxx 0xxxxx
Cyan 0xxxxx 1xxxxx 1xxxxx
Yellow 1xxxxx 1xxxxx 0xxxxx
White 1xxxxx 1xxxxx 1xxxxx
Restriction This command has no effect when module is already in idle off mode
Status Availability
Sleep In Yes
Legend
Command
IDMON Display
Flow Chart
Mode
Sequential
transter
COLMOD 0 ↑ 1 - 0 0 1 1 1 0 1 0 (3Ah)
1st Parameter 1 ↑ 1 - 0 D6 D5 D4 0 D2 D1 D0
This command is used to define the format of RGB picture data, which is to be transferred via the
1st parameter:
Bit Description
D7 - Set to ‘0’
D6 ‘101’ = 65K of RGB interface
D5 RGB interface color format ‘110’ = 262K of RGB
Description D4 interface
D3 - Set to ‘0’
D2 ‘011’ = 12bit/pixel
D1 ‘101’ = 16bit/pixel
Control interface color format
‘110’ = 18bit/pixel
D0
‘111’ = 16M truncated
Note1: In 12-bit/Pixel, 16-bit/Pixel or 18-bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory.
Note2: The Command 3Ah should be set at 55h when writing 16-bit/pixel data into frame memory, but 3Ah should be
re-set to 66h when reading pixel data from frame memory.
Restriction
Status Availability
Sleep In Yes
WRMEMC 0 ↑ 1 - 0 0 1 1 1 1 0 0 (3Ch)
ST
1 parameter 1 ↑ 1 D1[17]-D1[8] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0]
…
Nth parameter 1 ↑ 1 Dn[17]-Dn[8] Dn[7] Dn[6] Dn[5] Dn[4] Dn[3] Dn[2] Dn[1] Dn[0]
-This command transfers image data from the host processor to the display module’s frame memory continuing from
the pixel location following the previous write memory continue or memory write command.
-If MV=0:
Data is written continuing from the pixel location after the write range of the previous memory write or write memory
continue. The column register is then incremented and pixels are written to the frame memory until the column register
equals the end column (XE) value. The column register is then reset to XS and the page register is incremented. Pixels
are written to the frame memory until the page register equals the end page (YE) value and the column register equals
the XE value, or the host processor sends another command. If the number of pixels exceeds (XE-XS+1)*(YE-YS+1)
If MV=1:
Data is written continuing from the pixel location after the write range of the previous memory write or write memory
continue. The page register is then incremented and pixels are written to the frame memory until the page register
equals the end page (YE) value. The page register is then reset to YS and the column register is incremented. Pixels
are written to the frame memory until the column register equals the end column (XE) value and the page register
equals the YE value, or the host processor sends another command. If the number of pixels exceeds
A memory write should follow a column address set or page address set to define the write address. Otherwise, data
Restriction
written with write memory continue is written to undefined addresses.
Status Availability
Sleep In Yes
Legend
Command
WRMEMC
Parameter
Display
Flow Chart
Image Data
D1[17:0],D2[17:0]
…….Dn[17:0] Action
Mode
Sequential
Any Command transter
RDMEMC 0 ↑ 1 - 0 0 1 1 1 1 1 0 (3Eh)
ST
1 parameter 1 1 ↑ - - - - - - - - -
2nd parameter 1 1 ↑ D1[17]-D1[8] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0]
…
Nth parameter 1 1 ↑ Dn[17]-Dn[8] Dn[7] Dn[6] Dn[5] Dn[4] Dn[3] Dn[2] Dn[1] Dn[0]
-This command transfers image data from the host processor to the display module’s frame memory continuing from
the pixel location following the previous read memory continue or memory read command.
-If MV=0:
Pixels are read continuing from the pixel location after the read range of the previous memory read or read memory
continue. The column register is then incremented and pixels are read from the frame memory until the column register
equals the end column (XE) value. The column register is then reset to XS and the page register is incremented. Pixels
are read from the frame memory until the page register equals the end page (YE) value and the column register equals
If MV=1:
Pixels are read continuing from the pixel location after the read range of the previous memory read or read memory
continue. The page register is then incremented and pixels are read from the frame memory until the page register
equals the end page (YE) value. The page register is then reset to YS and the column register is incremented. Pixels
are read from the frame memory until the column register equals the end column (XE) value and the page register
Regardless of the color mode set in interface pixel format, the pixel format returned by read memory continue is always
Restriction
18-bit so there is no restriction on the length of data
Status Availability
Sleep In Yes
Flow Chart
STE 0 ↑ 1 - 0 1 0 0 0 1 0 0 (44h)
2nd parameter 1 ↑ 1 - N7 N6 N5 N4 N3 N2 N1 N0
-This command turns on the display module’s Tearing Effect output signal on the TE signal line when the display
-The tearing effect line on has one parameter that describes the tearing effect output line mode.
Note that set tear scanline with N=0 is equivalent to tearing effect line on with TEM=0.
The tearing effect output line shall be active low when the display module is in sleep mode
This command takes affect on the frame following the current frame. Therefore, if the tear effect (TE) output is already
Restriction on, the TE output shall continue to operate as programmed by the previous tearing effect line on or set tear scanline
Status Availability
Sleep In Yes
Command
TE Output On or OFF
Parameter
Set Tear on
Display
Flow Chart
Line N (LSB)
Action
Line N (MSB)
Mode
TE Output ON
Sequential
transter
GSCAN 0 ↑ 1 - 0 1 0 0 0 1 0 1 (45h)
st
1 parameter 1 1 ↑ - - - - - - - - -
3rd parameter 1 1 ↑ - N7 N6 N5 N4 N3 N2 N1 N0
-The display module returns the current scanline ,N, used to update the display device. The total number of scanlines
on a display device is defined as VSYNC+VBP+VACT+VFP. The first scanline is defined as the first line of V Sync and
Description
is denoted as Line 0.
Restriction -
Status Availability
Sleep In Yes
Command
Get scanline
Flow Chart
Line N (LSB)
Action
Mode
Sequential
transter
WRDISBV 0 ↑ 1 - 0 1 0 1 0 0 0 1 (51h)
-It should be checked what the relationship between this written value and output brightness of the display is. This
Description
relationship is defined on the display module specification.
-In principle relationship is that 00h value means the lowest brightness and FFh value means the highest brightness.
Restriction
Status Availability
Sleep In Yes
Command
Parameter
WRDISBV
Display
Flow Chart
DBV[7:0]
Action
New Display
Luminance
Value Loaded
Mode
Sequential
transter
RDDISBV 0 ↑ 1 - 0 1 0 1 0 0 1 0 (52h)
st
1 parameter 1 1 ↑ - - - - - - - - -
2nd parameter 1 1 ↑ - DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0
-It should be checked what the relationship between this returned value and output brightness of the display. This
Description -In principle the relationship is that 00h value means the lowest brightness and FFh value means the highest brightness.
-DBV[7:0] is ‘0’ when bit BCTRL of write CTRL display command (53h) is ‘0’
-DBV[7:0] IS manual set brightness specified with write CTRL display command (53h) when bit BCTRL is ‘1’
Restriction -
Status Availability
Sleep In Yes
Flow Chart
WRCTRLD 0 ↑ 1 - 0 1 0 1 0 0 1 1 (53h)
Parameter 1 ↑ 1 - 0 0 BCTRL 0 DD BL 0 0
-BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display.
0 = Off (Completely turn off backlight circuit. Control lines must be low.)
1 = On
-Dimming function is adapted to the brightness registers for display when bit BCTRL is changed at DD=1.
-When BL bit changed from ‘on’ to ‘off’, backlight is turned off without gradual dimming, even if dimming-on (DD=1) are
selected.
Restriction
Status Availability
Sleep In Yes
Command
Parameter
WRCTRLD
Display
BCTRL, DD, BL
Flow Chart
Action
New control
Value loaded
Mode
Sequential
transter
RDCTRLD 0 ↑ 1 - 0 1 0 1 0 1 0 0 (54h)
st
1 parameter 1 1 ↑ - - - - - - - - -
-BCTRL: Brightness Control Block On/Off, This bit is always used to switch brightness for display.
0 = Off
1 = On
Description DD = 0
DD = 1
0 = Off
1 = On
Restriction -
Status Availability
Sleep In Yes
Flow Chart
WRCACE 0 ↑ 1 - 0 1 0 1 0 1 0 1 (55h)
-This command is used to set parameters for image content based adaptive brightness control functionality and Color
Enhancement function.
-There is possible to used 4 different modes for content adaptive image functionality, which are defined on a table
below.
C1 C0 Function
0 0 Off
1 0 Still Picture
1 1 Moving Image
Description
-CECTRL: Color Enhancement Control Bit:
0 0 Low enhancement
0 1 Medium enhancement
1 1 High enhancement
Restriction
Status Availability
Sleep In Yes
Command
Parameter
WRCACE
Display
st
1 parameter:
Flow Chart C[1:0]
Action
New Adaptive
Image Mode
Mode
Sequential
transter
RDCABC 0 ↑ 1 - 0 1 0 1 0 1 1 0 (56h)
st
1 parameter 1 1 ↑ - - - - - - - - -
2nd parameter 1 1 ↑ - 0 0 0 0 0 0 C1 C0
-This command is used to read the settings for image content based adaptive brightness control functionality.
-There is possible to used 4 different modes for content adaptive image functionality, which are defined on a table
below.
C1 C0 Function
Description 0 0 Off
1 0 Still Picture
1 1 Moving Image
Restriction -
Status Availability
Sleep In Yes
Flow Chart
WRCABCMB 0 ↑ 1 - 0 1 0 1 1 1 1 0 (5Eh)
-This command is used to set the minimum brightness value of the display for CABC function.
-In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the brightness
Description
for CABC.
Restriction
Status Availability
Sleep In Yes
Command
Parameter
WRCABCMB
Display
CMB[7:0]
Flow Chart
Action
New Display
Luminance
Value Loaded
Mode
Sequential
transter
RDCABCMB 0 ↑ 1 - 0 1 0 1 1 1 1 1 (5Fh)
st
1 parameter 1 1 ↑ - - - - - - - - -
2nd parameter 1 1 ↑ - CMB7 CMB6 CMB5 CMB4 CMB3 CMB2 CMB1 CMB0
-In principle relationship is that 00h value means the lowest brightness for CABC and FFh value means the brightness for
Description
CABC.
Restriction -
Status Availability
Sleep In Yes
Flow Chart
RDABCSDR 0 ↑ 1 - 0 1 1 0 1 0 0 0 (68h)
st
1 parameter 1 1 ↑ - - - - - - - - - -
2nd parameter 1 1 ↑ - D7 D6 0 0 0 0 0 0 -
This command indicates the current status of the display self-diagnostic results for automatic brightness control after
Restriction
Status Availability
Sleep In Yes
Command
Read RDABCSDR Read RDABCSDR
Host
Display Parameter
Send 2nd
Dummy Read
parameter
Display
Flow Chart
Send 2nd
Action
parameter
Mode
Sequential
transter
RDID1 0 ↑ 1 - 1 1 0 1 1 0 1 0 (Dah)
st
1 parameter 1 1 ↑ - - - - - - - - -
2nd parameter 1 1 ↑ - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
Restriction -
Status Availability
Sleep In Yes
Flow Chart
RDID2 0 ↑ 1 - 1 1 0 1 1 0 1 1 (DBh)
1st parameter 1 1 ↑ - - - - - - - - -
2nd parameter 1 1 ↑ - ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20
Restriction -
Status Availability
Sleep In Yes
Flow Chart
RDID3 0 ↑ 1 - 1 1 0 1 1 1 0 0 (DCh)
st
1 parameter 1 1 ↑ - - - - - - - - -
2nd parameter 1 1 ↑ - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
Restriction -
Status Availability
Sleep In Yes
Flow Chart
0 ↑ 1 - 1 0 1 1 0 0 0 0 (B0h)
RAM
RAMCTRL 1 ↑ 1 - 0 0 0 RM 0 0 DM1 DM0
Control
1 ↑ 1 - 1 1 EPF1 EPF0 ENDIAN RIM MDT1 MDT0
0 ↑ 1 - 1 0 1 1 0 0 0 1 (B1h)
0 ↑ 1 - 1 0 1 1 0 0 1 0 (B2h)
0 ↑ 1 - 1 0 1 1 0 0 1 1 (B3h)
Frame
1 ↑ 1 - 0 0 0 FRSEN 0 0 DIV1 DIV0
FRCTRL1 Rate
1 ↑ 1 - NLB2 NLB1 NLB0 RTNB4 RTNB3 RTNB2 RTNB1 RTNB0
Control 1
1 ↑ 1 - NLC2 NLC1 NLC0 RTNC4 RTNC3 RTNC2 RTNC1 RTNC0
0 ↑ 1 - 1 0 1 1 0 1 0 1 (B5h) Partial
PARCTRL mode
1 ↑ 1 - NDL 0 0 PTGISC ISC3 ISC2 ISC1 ISC0
Control
0 ↑ 1 - 1 0 1 1 0 1 1 1 (B7h) Gate
GCTRL
1 ↑ 1 - 0 VGHS2 VGHS1 VGHS0 0 VGLS2 VGLS1 VGLS0 control
0 ↑ 1 - 1 0 1 1 1 0 0 0 (B8h)
1 ↑ 1 - 0 0 1 0 1 0 1 0 Gate on
GTADJ 1 ↑ 1 - 0 0 1 0 1 0 1 1 timing
0 ↑ 1 - 1 0 1 1 1 0 1 0 (BAh) Digital
DGMEN Gamma
1 ↑ 1 - 0 0 0 0 0 DGMEN 0 0
Enable
0 ↑ 1 - 1 0 1 1 1 0 1 1 (BBh) VCOMS
VCOMS
1 ↑ 1 - 0 0 VCOMS5 VCOMS4 VCOMS3 VCOMS2 VCOMS1 VCOMS0 Setting
0 ↑ 1 - 1 1 0 0 0 0 0 0 (C0h) LCM
LCMCTRL
1 ↑ 1 - 0 XMY XBGR XINV XMX XMH XMV XGS Control
0 ↑ 1 - 1 1 0 0 0 0 0 1 (C1h)
1 ↑ 1 - 0 0 0 0 0 0 0 CMDEN VRH
VDVVRHEN
Command
1 ↑ 1 - 1 1 1 1 1 1 1 1
Enable
0 ↑ 1 1 1 0 0 0 0 1 1 (C3h)
VRHS VRH Set
1 ↑ 1 0 0 VRHS5 VRHS4 VRHS3 VRHS2 VRHS1 VRHS0
0 ↑ 1 - 1 1 0 0 0 1 0 0 (C4h) VDV
VDVSET
1 ↑ 1 - 0 0 VDVS5 VDVS4 VDVS3 VDVS2 VDVS1 VDVS0 Setting
0 ↑ 1 - 1 1 0 0 0 1 0 1 (C5h) VCOMS
VCMOFSET
1 ↑ 1 - 0 0 VCMOFS5 VCMOFS4 VCMOFS3 VCMOFS2 VCMOFS1 VCMOFS0 Offset Set
0 ↑ 1 1 1 0 0 0 1 1 0 (C6h) FR Control
FRCTR2
1 ↑ 1 NLA2 NLA1 NLA0 RTNA4 RTNA3 RTNA2 RTNA1 RTNA0 2
0 ↑ 1 - 1 1 0 0 0 1 1 1 (C7h) CABC
CABCCTRL
1 ↑ 1 - 0 0 0 0 LEDONREV DPOFPWM PWMFIX PWMPOL Control
0 ↑ 1 - 1 1 0 0 1 0 0 0 (C8h) Register
REGSEL1 value
1 ↑ 1 - 0 0 0 0 1 0 0 0
selection1
0 ↑ 1 - 1 1 0 0 1 0 1 0 (CAh) Register
REGSEL2 value
1 ↑ 1 - 0 0 0 0 1 1 1 1
selection2
0 ↑ 1 - 1 1 0 0 1 1 0 0 (CCh) PWM
PWMFRSEL Frequency
1 ↑ 1 - 0 0 CS2 CS1 CS0 CLK2 CLK1 CLK0
Selection
0 ↑ 1 - 1 1 0 1 0 0 0 0 (D0h)
Power
PWCTRL1 1 ↑ 1 - 1 0 1 0 0 1 0 0
Control 1
1 ↑ 1 - AVDD1 AVDD0 AVCL1 AVCL0 0 0 VDS1 VDS0
0 ↑ 1 - 1 1 0 1 0 0 1 0 (D2h) Enable
VAP/VAN
VAPVANEN
1 ↑ 1 - 0 1 0 0 1 1 0 0 signal
output
0 ↑ 1 - 1 1 0 1 1 1 1 1 (DFh)
1 ↑ 1 - 0 1 0 1 1 0 1 0 (5Ah)
Command
CMD2EN 1 ↑ 1 - 0 1 1 0 1 0 0 1 (69h)
2 Enable
1 ↑ 1 - 0 0 0 0 0 0 1 0 (02h)
1 ↑ 1 - 0 0 0 0 0 0 0 EN
0 ↑ 1 - 1 1 1 0 0 0 0 0 (E0h)
Positive
1 ↑ 1 - 0 0 J0P1 J0P0 V13P3 V13P2 V13P1 V13P0
Voltage
PVGAMCTRL 1 ↑ 1 - 0 V20P6 V20P5 V20P4 V20P3 V20P2 V20P1 V20P0
Gamma
1 ↑ 1 - 0 V36P2 V36P1 V36P0 0 V27P2 V27P1 V27P0
Control
0 ↑ 1 - 1 1 1 0 0 0 0 1 (E1h)
Negative
1 ↑ 1 - 0 0 V2N5 V2N4 V2N3 V2N2 V2N1 V2N0
Voltage
NVGAMCTRL 1 ↑ 1 - 0 0 0 V4N4 V4N3 V4N2 V4N1 V4N0
Gamma
1 ↑ 1 - 0 0 0 V6N4 V6N3 V6N2 V6N1 V6N0
Control
0 ↑ 1 - 1 1 1 0 0 0 1 0 (E2h)
1 ↑ 1 - DGM_LUT_R00[7:0]
1 ↑ 1 - DGM_LUT_R01[7:0]
Digital
…
1 ↑ 1 -
Gamma
Table for
1 ↑ 1 - DGM_LUT_R31[7:0]
Red
…
1 ↑ 1 -
1 ↑ 1 - DGM_LUT_R62[7:0]
1 ↑ 1 - DGM_LUT_R63[7:0]
0 ↑ 1 - 1 1 1 0 0 0 1 1 (E3h)
1 ↑ 1 - DGM_LUT_B00[7:0]
1 ↑ 1 - DGM_LUT_B01[7:0]
Digital
…
1 ↑ 1 -
Gamma
Table for
1 ↑ 1 - DGM_LUT_B31[7:0]
Blue
…
1 ↑ 1 -
1 ↑ 1 - DGM_LUT_B62[7:0]
1 ↑ 1 - DGM_LUT_B63[7:0]
0 ↑ 1 - 1 1 1 0 0 1 0 0 (E4h)
1 ↑ 1 - 0 0 1 0 0 SM 0 GS
0 ↑ 1 - 1 1 1 0 1 0 0 0 (E8h) Power
PWCTRL2
1 ↑ 1 - 1 0 SBCLK1 SBCLK0 0 0 STP14CK1 STP14CK0 Control 2
0 ↑ 1 - 1 1 1 0 1 0 0 1 (E9h)
Equalize
1 ↑ 1 - 0 0 0 SEQ4 SEQ3 SEQ2 SEQ1 SEQ0
EQCTRL Time
1 ↑ 1 - 0 0 0 SPRET4 SPRET3 SPRET2 SPRET1 SPRET0
Control
0 ↑ 1 - 1 1 1 0 1 1 0 0 (ECh) Program
PROMCTRL
1 ↑ 1 - 0 0 0 0 0 0 0 1 Control
0 ↑ 1 - 1 1 1 1 1 0 1 0 (FAh)
1 ↑ 1 - 0 1 0 1 1 0 1 0 Program
PROMEN 1 ↑ 1 - 0 1 1 0 1 0 0 1 Mode
Enable
1 ↑ 1 - 1 1 1 0 1 1 1 0
1 ↑ 1 - 0 0 0 0 0 PROMEN 0 0
0 ↑ 1 - 1 1 1 1 1 1 0 0 (FCh)
NVM
NVMSET 1 ↑ 1 - ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
Setting
1 ↑ 1 - D7 D6 D5 D4 D3 D2 D1 D0
0 ↑ 1 - 1 1 1 1 1 1 1 0 (FEh)
Program
PROMACT 1 ↑ 1 - 0 0 0 1 1 0 0 1
Action
1 ↑ 1 - 1 0 1 0 0 1 0 1
RAMCTRL 0 ↑ 1 - 1 0 1 1 0 0 0 0 (B0h)
st
1 Parameter 1 ↑ 1 - 0 0 0 RM 0 0 DM1 DM0
11h Reserved
ENDIAN :
ENDIAN Mode
Note: Little Endian only can be supported in 65K 8-bit and 9-bit interface.
Data Bus DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
EPF=00
Frame
R5 R4 R3 R2 R1 0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 0
Data
Read Data DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Data Bus DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
EPF=01
R5 R4 R3 R2 R1 1 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 1
Read Data DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Data Bus DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
EPF=10
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Read Data DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Data Bus DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
EPF=11
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Read Data DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Register
Availability
Status Availability
Sleep In Yes
RGBCTRL 0 ↑ 1 - 1 0 1 1 0 0 0 1 (B1h)
st
1 parameter 1 ↑ 1 - WO RCM1 RCM0 0 VSPL HSPL DPL EPL
0 Memory
1 Shift register
00
MCU interface
01
10 RGB DE mode
11 RGB HV mode
Sleep In Yes
PORCTRL 0 ↑ 1 - 1 0 1 1 0 0 1 0 (B2h)
st
1 parameter 1 ↑ 1 - 0 BPA6 BPA5 BPA4 BPA3 BPA2 BPA1 BPA0
5th parameter 1 ↑ 1 - BPC3 BPC2 BPC1 BPC0 FPC3 FPC2 FPC1 FPC0
BPA[6:0]: Back porch setting in normal mode. The minimum setting is 0x01.
FPA[6:0]: Front porch setting in normal mode. The minimum setting is 0x01.
PSEN: Enable separate porch control.
PSEN Mode
BPB[3:0]: Back porch setting in idle mode. The minimum setting is 0x01.
FPB[3:0]: Front porch setting in idle mode. The minimum setting is 0x01.
BPC[3:0]: Back porch setting in partial mode. The minimum setting is 0x01.
FPC[3:0]: Front porch setting in partial mode. The minimum setting is 0x01.
Status Availability
Sleep In Yes
FRCTRL1 0 ↑ 1 - 1 0 1 1 0 0 1 1 (B3h)
st
1 parameter 1 ↑ 1 - 0 0 0 FRSEN 0 0 DIV1 DIV0
2nd parameter 1 ↑ 1 - NLB2 NLB1 NLB0 RTNB4 RTNB3 RTNB2 RTNB1 RTNB0
3rd parameter 1 ↑ 1 - NLC2 NLC1 NLC0 RTNC4 RTNC3 RTNC2 RTNC1 RTNC0
00 Divide by 1
01 Divide by 2
10 Divide by 4
11 Divide by 8
03h 99 13h 53
04h 94 14h 52
05h 90 15h 50
06h 86 16h 49
07h 82 17h 48
08h 78 18h 46
09h 75 19h 45
0Bh 69 1Bh 43
0Ch 67 1Ch 42
0Dh 64 1Dh 41
0Eh 62 1Eh 40
0Fh 60 1Fh 39
Note:
RTNC[4:0]: Frame rate control in partial mode. This setting is equal to RTNB.
Status Availability
Sleep In Yes
PARCTRL 0 ↑ 1 - 1 0 1 1 0 1 0 1 (B5h)
Status Availability
Register
Availability
Normal Mode On, Idle Mode Off, Sleep Out Yes
Sleep In Yes
GCTRL 0 ↑ 1 - 1 0 1 1 0 1 1 1 (B7h)
00h 12.2
01h 12.54
02h 12.89
03h 13.26
04h 13.65
05h 14.06
06h 14.5
07h 14.97
Description
00h -7.16
01h -7.67
02h -8.23
03h -8.87
04h -9.6
05h -10.43
06h -11.38
07h -12.5
Status Availability
Sleep In Yes
GTADJ 0 ↑ 1 - 1 0 1 1 1 0 0 0 (B8h)
st
1 Parameter 1 ↑ 1 - 0 0 1 0 1 0 1 0 2Ah
Description
Status Availability
Sleep In Yes
DGMEN 0 ↑ 1 - 1 0 1 1 1 0 1 0 (BAh)
Parameter 1 ↑ 1 - 0 0 0 0 0 DGMEN 0 0
DGMEN:
Description “0”: disable digital gamma.
“1”: enable digital gamma.
Status Availability
Sleep In Yes
VCOMS 0 ↑ 1 - 1 0 1 1 1 0 1 1 (BBh)
VCOMS[5:0]:
VCOMS[5:0] VCOMS (V) VCOMS[5:0] VCOMS (V)
Note:
1. VCOMS is used for feed through voltage compensation.
2. Setting limitation: VCOMS+VCOMS offset+VDV=0.1V~1.675V.
Status Availability
Sleep In Yes
LCMCTRL 0 ↑ 1 - 1 1 0 0 0 0 0 0 (C0h)
st
1 parameter 1 ↑ 1 - 0 XMY XBGR XINV XMX XMH XMV XGS
Status Availability
Sleep In Yes
IDSET 0 ↑ 1 - 1 1 0 0 0 0 0 1 (C1h)
st
Parameter 1 1 ↑ 1 - ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
Parameter 2nd 1 ↑ 1 - ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20
Parameter 3rd 1 ↑ 1 - ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
Sleep In Yes
VDVVRHEN 0 ↑ 1 - 1 1 0 0 0 0 1 0 (C2h)
st
1 Parameter 1 ↑ 1 - 0 0 0 0 0 0 0 CMDEN
2nd Parameter 1 ↑ 1 - 1 1 1 1 1 1 1 1
Status Availability
Sleep In Yes
VRHS 0 ↑ 1 - 1 1 0 0 0 0 1 1 (C3h)
st
1 Parameter 1 ↑ 1 - 0 0 VRHS5 VRHS4 VRHS3 VRHS2 VRHS1 VRHS0
Status Availability
Sleep In Yes
VDVS 0 ↑ 1 - 1 1 0 0 0 1 0 0 (C4h)
st
1 Parameter 1 ↑ 1 - 0 0 VDVS5 VDVS4 VDVS3 VDVS2 VDVS1 VDVS0
Note:
Setting limitation: VCOMS+VCOMS offset+VDV=0.1V~1.675V
Status Availability
Sleep In Yes
VCMOFSET 0 ↑ 1 - 1 1 0 0 0 1 0 1 (C5h)
st
1 Parameter 1 ↑ 1 - 0 0 VCMOFS5 VCMOFS4 VCMOFS3 VCMOFS2 VCMOFS1 VCMOFS0
Note:
Setting limitation: VCOMS+VCOMS offset+VDV=0.1V~1.675V
Status Availability
Sleep In Yes
FRCTRL2 0 ↑ 1 - 1 1 0 0 0 1 1 0 (C6h)
st
1 Parameter 1 ↑ 1 - NLA2 NLA1 NLA0 RTNA4 RTNA3 RTNA2 RTNA1 RTNA0
03h 99 13h 53
04h 94 14h 52
05h 90 15h 50
06h 86 16h 49
08h 78 18h 46
09h 75 19h 45
0Ah 72 1Ah 44
0Bh 69 1Bh 43
0Ch 67 1Ch 42
0Dh 64 1Dh 41
0Eh 62 1Eh 40
0Fh 60 1Fh 39
Note:
1. Frame rate=10MHz/(320+FPA[6:0]+BPA[6:0])*(250+RTNA[4:0]*16).
2. FPA[6:0] and BPA[6:0] are in command B2h
Status Availability
CABCCTRL 0 ↑ 1 - 1 1 0 0 0 1 1 1 (C7h)
st
1 Parameter 1 ↑ 1 - 0 0 0 0 LEDONREV DPOFPWM PWMFIX PWMPOL
Status Availability
Sleep In Yes
REGSEL1 0 ↑ 1 - 1 1 0 0 1 0 0 0 (C8h)
Parameter 1 ↑ 1 - 0 0 0 0 1 0 0 0
Status Availability
Sleep In Yes
REGSEL2 0 ↑ 1 - 1 1 0 0 1 0 1 0 (Cah)
Parameter 1 ↑ 1 - 0 0 0 0 1 1 1 1
Status Availability
Sleep In Yes
PWMFRSEL 0 ↑ 1 - 1 1 0 0 1 1 0 0 (CCh)
st
1 Parameter 1 ↑ 1 - 0 0 CS2 CS1 CS0 CLK2 CLK1 CLK0
CS[2:0]/CLK[2:0]:
CS[2:0]
00h 01h 02h 03h 04h 05h
CLK[2:0]
Unit:kHz
Status Availability
Sleep In Yes
PWCTRL 0 ↑ 1 - 1 1 0 1 0 0 0 0 (D0h)
st
1 Parameter 1 ↑ 1 - 1 0 1 0 0 1 0 0
AVDD[1:0]:
AVDD[1:0] AVDD (V)
00h 6.4
01h 6.6
02h 6.8
03h Reserved
AVCL[1:0]:
AVCL[1:0] AVCL (V)
00h -4.4
01h -4.6
Description
02h -4.8
03h -5.0
VDS[1:0]:
VDS[1:0] VDDS (V)
00h 2.19
01h 2.3
02h 2.4
03h 2.51
Status Availability
Sleep In Yes
VAPVANEN 0 ↑ 1 - 1 1 0 1 0 0 1 0 (D2h)
Parameter 1 ↑ 1 - 0 1 0 0 1 1 0 0
Status Availability
Sleep In Yes
CMD2EN 0 ↑ 1 - 1 1 0 1 1 1 1 1 (DFh)
st
1 Parameter 1 ↑ 1 - 0 1 0 1 1 0 1 0 (5Ah)
EN:
Description “0”: Commands in Command table 2 cannot be executed when EXTC level is “Low”.
“1”: Commands in command table 2 can be executed when EXTC level is “Low”.
Status Availability
Sleep In Yes
PVGAMCTRL 0 ↑ 1 - 1 1 1 0 0 0 0 0 (E0h)
st
1 Parameter 1 ↑ 1 - V63P3 V63P2 V63P1 V63P0 V0P3 V0P2 V0P1 V0P0
VP0[3:0] 0
VP1[5:0] 0
VP2[5:0] 2
VP4[4:0] 7
VP6[4:0] B
VP13[3:0] A
Description
VP20[6:0] 31
VP27[2:0] 4
VP36[2:0] 5
VP43[6:0] 40
VP50[3:0] 9
VP57[4:0] 12
VP59[4:0] 12
VP61[5:0] 12
VP62[5:0] 17
JP0[1:0] 1
JP1[1:0] 2
Status Availability
Sleep In Yes
NVGAMCTRL 0 ↑ 1 - 1 1 1 0 0 0 0 1 (E1h)
st
1 Parameter 1 ↑ 1 - V63N3 V63N2 V63N1 V63N0 V0N3 V0N2 V0N1 V0N0
VN0[3:0] 0
VN1[5:0] 0
VN2[5:0] 2
VN4[4:0] 7
VN6[4:0] 5
VN13[3:0] 5
Description
VN20[6:0] 2D
VN27[2:0] 4
VN36[2:0] 4
VN43[6:0] 44
VN50[3:0] C
VN57[4:0] 18
VN59[4:0] 16
VN61[5:0] 1C
VN62[5:0] 1D
JN0[1:0] 2
JN1[1:0] 1
Status Availability
Sleep In Yes
DGMLUTR 0 ↑ 1 - 1 1 1 0 0 0 1 0 (E2h)
st
1 Parameter 1 ↑ 1 - DGM_LUT_R00[7:0]
…
1 ↑ 1 -
th
31 Parameter 1 ↑ 1 - DGM_LUT_R30[7:0]
…
1 ↑ 1 -
DGM_LUT_R00[7:0] 00h
DGM_LUT_R01[7:0] 04h
…
Description
DGM_LUT_R30[7:0] 78h
DGM_LUT_R31[7:0] 7Ch
…
DGM_LUT_R62[7:0] F8h
DGM_LUT_R63[7:0] FCh
Status Availability
Sleep In Yes
DGMLUTB 0 ↑ 1 - 1 1 1 0 0 0 1 1 (E3h)
st
1 Parameter 1 ↑ 1 - DGM_LUT_B00[7:0]
…
1 ↑ 1 -
th
31 Parameter 1 ↑ 1 - DGM_LUT_B30[7:0]
…
1 ↑ 1 -
DGM_LUT_B00[7:0] 00h
DGM_LUT_B01[7:0] 04h
…
Description
DGM_LUT_B30[7:0] 78h
DGM_LUT_B31[7:0] 7Ch
…
DGM_LUT_B62[7:0] F8h
DGM_LUT_B63[7:0] FCh
Status Availability
Sleep In Yes
GATECTRL 0 ↑ 1 - 1 1 1 0 0 1 0 0 (E4h)
st
1 Parameter 1 ↑ 1 - 0 0 NL5 NL4 NL3 NL2 NL1 NL0
3rd Parameter 1 ↑ 1 - 0 0 0 1 0 SM 0 GS
…
0x27 320 gate line
0x01 Gate 1
…
Status Availability
Sleep In Yes
SPI2EN 0 ↑ 1 - 1 1 1 0 0 1 1 1 (E7h)
Note:
It needs one dummy clock if commands in command table 2 need to be read in serial interface.
Status Availability
Sleep In Yes
PWCTRL2 0 ↑ 1 - 1 1 1 0 1 0 0 0 (E8h)
Status Availability
Sleep In Yes
EQCTRL 0 ↑ 1 - 1 1 1 0 1 0 0 1 (E9h)
st
1 Parameter 1 ↑ 1 - 0 0 0 SEQ4 SEQ3 SEQ2 SEQ1 SEQ0
Status Availability
Sleep In Yes
PROMCTRL 0 ↑ 1 - 1 1 1 0 1 1 0 0 (ECh)
Parameter 1 ↑ 1 - 0 0 0 0 0 0 0 1
Status Availability
Sleep In Yes
PROMEN 0 ↑ 1 - 1 1 1 1 1 0 1 0 (FAh)
st
1 Parameter 1 ↑ 1 - 0 1 0 1 1 0 1 0 (5Ah)
PROMEN:
Description “0”: Program mode disable
“1”: Program mode enable
Status Availability
Sleep In Yes
NVMSET 0 ↑ 1 - 1 1 1 1 1 1 0 0 (FCh)
st
1 Parameter 1 ↑ 1 - ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
2nd Parameter 1 ↑ 1 - D7 D6 D5 D4 D3 D2 D1 D0
Status Availability
Sleep In Yes
PROMACT 0 ↑ 1 - 1 1 1 1 1 1 1 0 (FEh)
st
1 Parameter 1 ↑ 1 - 0 0 1 0 1 0 0 1 (29h)
Status Availability
Sleep In Yes
DUMMY
DUMMY
VCOM
VCOM
VCOM
VCOM <10ohm VCOM DUMMY
VCOM DUMMY
VCOM
VCOM DUMMY
VCOM G1
DUMMY G3
VAG
VAG G5
VDDS G7
VDDS G9
VDDGX
VDDGX G 11
DUMMY G 13
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VGL
VGL
VGL
VGL
VGL
VGL
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD G303
AVDD G305
AVCL
AVCL G307
AVCL G309
AVCL G311
AVCL
AVCL G313
AVCL G315
VAN G317
VAN
DUMMY G319
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY S1
DUMMY S2
VAP
VAP S3
V20 S4
V20 S5
V20
V20 S6
V20
V20
V20
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
VDD
VDD
VDD
VDD
VDD <10ohm VDD
VDD
VDD
VDD
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
<10ohm AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND S353
DGND
DGND S354
<10ohm DGND S355
DGND S356
DGND S357
DGND
DGND S358
TEST3 S359
DUMMY
DUMMY S360
EXTC <100ohm EXTC
IM3 <100ohm IM3
IM2 <100ohm IM2
IM1
Y
<100ohm IM1
IM0 <100ohm IM0
RESX <100ohm RESX
CSX <100ohm CSX
DCX <100ohm DCX
WRX <100ohm WRX S361
RDX <100ohm RDX
S362
TEST2
VSYNC <100ohm VSYNC S363
HSYNC <100ohm HSYNC S364
ENABLE <100ohm ENABLE S365
DOTCLK <100ohm DOTCLK
DUMMY S366
SDA <100ohm SDA S367
DB0 <100ohm DB0
S368
DB1 <100ohm DB1
DB2 <100ohm DB2
DB3 <100ohm DB3
TEST1
DB4 <100ohm DB4
DB5 <100ohm DB5
DB6
DB9
DB11
DB7
DB8
DB10
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
<100ohm
DB6
DB7
DUMMY
DB8
DB9
DB10
DB11
X
DUMMY
DB12 <100ohm DB12
DB13 <100ohm DB13
DB14 <100ohm DB14
DB15 <100ohm DB15
DUMMY
DB16 <100ohm DB16
DB17 <100ohm DB17
TEST0
TE <100ohm TE
SDO <100ohm SDO
LED_PWM <100ohm LED_PWM
LED_EN <100ohm LED_EN
VDDI_LED <100ohm VDDI_LED
VDDI_LED
TE2
TESTO1
TESTO2
TESTO3
TESTO4
TESTO5
TESTO6
VDDI
VDDI S712
VDDI
VDDI <10ohm VDDI S713
VDDI S714
VDDI
VDDI S715
VCC S716
VCC
S717
VCC S718
VCC
VCC S719
VCC
VCC
S720
VCC
VCC
VCC
VCC
VCC
VCC
VCC
DUMMY
VPP
VPP
VPP <10ohm VPP
VPP
DUMMY
DUMMY G320
VGH G318
VGH G316
VGH
VGH G314
VGH G312
VGH G310
VGH
VGH G308
DUMMY
DUMMY
G306
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
AGND
AGND
AGND
AGND
<10ohm AGND
AGND
AGND
AGND
DUMMYR1
DUMMYR2
DUMMY
DUMMY G12
DUMMY G10
DUMMY
DUMMY G8
G6
DUMMY
DUMMY G4
VCOM G2
VCOM DUMMY
VCOM
VCOM DUMMY
VCOM <10ohm VCOM DUMMY
VCOM
VCOM
VCOM
DUMMY
DUMMY
VAP VAP
VP0
VP0
VP1
VAP VP1
VP0
VP1
VP62
VP63
VP62
VBP
VP63
VP62 VBP
VP63
VBP VBN
VBN VN63
VN63
VN62
VN62
VBN
VN63
VN62
VN1
VN0
VN1
VAN
VN0
VN1
VAN
VN0
VAN