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Synthesis of Digital Systems - - Unit 7 - Week 5 https://onlinecourses.nptel.ac.in/noc18_cs11/uni...

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Unit 7 - Week 5

Course
outline
Assessment 5
The due date for submitting this assignment has passed. Due on 2018-02-28, 23:59 IST.
How to access
the portal Submitted assignment

Pre-Course Multiple options can be correct.

1) Which of the following is true about the Constant Folding transformation? 1 point
Week 1
It could lead to a smaller datapath circuit
Week 2
It could lead to a circuit with lower cycle count
Week 3 It could lead to a smaller datapath circuit AND lower cycle count
It is possible that the resulting datapath is not smaller
Week 4
No, the answer is incorrect.
Week 5 Score: 0
Accepted Answers:
Compiler It could lead to a smaller datapath circuit
Transformations It could lead to a circuit with lower cycle count
in High-level
It could lead to a smaller datapath circuit AND lower cycle count
Synthesis
It is possible that the resulting datapath is not smaller
Memory
2) Which of the following is true about the Dead Code Elimination transformation? 1 point
Modelling and
Compiler
Transformations It results in a smaller CDFG
in High-level
It results in a circuit that always requires fewer cycles for execution
Synthesis
It results in a circuit that sometimes requires fewer cycles for execution
Quiz :
Assessment 5 It may result in a larger CDFG sometimes
No, the answer is incorrect.
Week 6
Score: 0
Accepted Answers:
Week 7
It results in a smaller CDFG
It results in a circuit that sometimes requires fewer cycles for execution
Week 8
3) Which of the following is true about the Constant Propagation transformation? 1 point
Week 9
It may lead to opportunities for Constant Folding
Week 10
It may lead to opportunities for Dead Code Elimination
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1 of 3 Wednesday 16 May 2018 11:02 AM


Synthesis of Digital Systems - - Unit 7 - Week 5 https://onlinecourses.nptel.ac.in/noc18_cs11/uni...

It may leadPowered
to opportunities
by for Constant Folding
It may lead to opportunities for Dead Code Elimination
4) Which of the following is true about the Strength Reduction transformation? 1 point

It results in a smaller CDFG


It could lead to a smaller datapath circuit
It could lead to a circuit with lower cycle count
It may result in a larger CDFG sometimes
No, the answer is incorrect.
Score: 0
Accepted Answers:
It could lead to a smaller datapath circuit
It could lead to a circuit with lower cycle count
5) It is possible to apply the Strength Reduction transformation to realise the 1 point
statement "y = a * 7;" using what resources? [Assume that it is possible to implement a
subtraction operation with one adder, and that no resources are required to shift an
operand by a constant.]

Zero adders and Zero multipliers


One adder and Zero multipliers
Two adders and Zero multipliers
Strength Reduction does not apply to this statement
No, the answer is incorrect.
Score: 0
Accepted Answers:
One adder and Zero multipliers
Two adders and Zero multipliers
6) The Common Subexpression Elimination transformation in High-level 1 point
Synthesis always results in reduced cycle count

TRUE
FALSE
No, the answer is incorrect.
Score: 0
Accepted Answers:
FALSE
7) The Common Subexpression Elimination transformation in results in reduced 1 point
node count in the CDFG

TRUE
FALSE
No, the answer is incorrect.
Score: 0
Accepted Answers:
TRUE
8) Which of the following is true about the Loop Invariant Code Motion 1 point
transformation?

It directly leads to opportunities for Constant Folding


It always leads to lower datapath area
It directly results in a smaller CDFG
It could lead to lower cycle count
No, the answer is incorrect.
Score: 0

2 of 3 Wednesday 16 May 2018 11:02 AM


Synthesis of Digital Systems - - Unit 7 - Week 5 https://onlinecourses.nptel.ac.in/noc18_cs11/uni...

Accepted Answers:
It could lead to lower cycle count
9) A node in HLS that represents a Memory Write operation: 1 point

Has an address input


Has a data input
Has a data output
Has an address output
No, the answer is incorrect.
Score: 0
Accepted Answers:
Has an address input
Has a data input
10)A node in HLS that represents a Memory Read operation: 1 point

Has an address input


Has a data input
Has a data output
Has an address output
No, the answer is incorrect.
Score: 0
Accepted Answers:
Has an address input
Has a data output

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