N Inputs M Outputs: Combinational Circuit
N Inputs M Outputs: Combinational Circuit
N Inputs M Outputs: Combinational Circuit
n inputs m outputs
⭈⭈ circuit ⭈⭈
⭈ ⭈
A T1
B
C
T3
F⬘2
A
B
A
F2
C
B
C
00 1 1 00 1 1
01 1 1 01 1 1
B B
11 X X X X 11 X X X X
A A
10 1 X X 10 1 X X
D D
z D y CD CD
CD C CD C
AB 00 01 11 10 AB 00 01 11 10
00 1 1 1 00
01 1 01 1 1 1 B
B
11 X X X X 11 X X X X
A A
10 1 X X 10 1 1 X X
D D
X BC BD BCD w A BC BD
© 2002 Prentice Hall, Inc.
M. Morris Mano Fig. 4-3 Maps for BCD to Excess-3 Code Converter
DIGITAL DESIGN, 3e.
D⬘ z
D CD y
C
(C ⫹D)⬘
C ⫹D
B
x
w
A
x
C C
y
x 1 1 1 x 1 1 1 1
z z
S xyz xyz xyz xyz S xy xz yz
xy xyz xyz
Fig. 4-8 Implementation of Full Adder with Two Half Adders and an OR Gate
C3 C2 C1
FA FA FA FA C0
C4 S3 S2 S1 S0
Gi
Ci ⫹ 1
Ci
P2
G2
C2
P1
G1
P0 C1
G0
C0
Fig. 4-11 Logic Diagram of Carry Lookahead Generator
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
C4 C4
B3
P3
A3
P3
S3
C3
G3
B2
P2
A2 P2
S2
C2
G2
Carry
Look ahead
B1 generator
P1
A1 P1
S1
C1
G1
B0
P0
A0 P0
S0
G0
C0 C0
© 2002 Prentice Hall, Inc. Fig. 4-12 4-Bit Adder with Carry Lookahead
M. Morris Mano
DIGITAL DESIGN, 3e.
B3 A3 B2 A2 B1 A1 B0 A0
C4 C3 C2 C1 C0
C FA FA FA FA
S3 S2 S1 S0
V
Carry Carry
K 4- bit binary adder
out in
Z8 Z4 Z2 Z1
Output
carry
S8 S4 S2 S1
© 2002 Prentice Hall, Inc.
M. Morris Mano Fig. 4-14 Block Diagram of a BCD Adder
DIGITAL DESIGN, 3e.
B1 B0 A0
B1 B0
A1 A0
A0B1 A 0B 0
A1B1 A1B0
A1
C3 C2 C1 C0 B1 B0
HA HA
C3 C2 C1 C0
A1
B3 B2 B1 B0
Addend Augend
4-bit adder
Sum and output carry
A2
B3 B2 B1 B0
Addend Augend
4-bit adder
Sum and output carry
C6 C5 C4 C3 C2 C1 C0
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e. Fig. 4-16 4-Bit by 3-Bit Binary Multiplier
A3
x3
B3
A2
x2
B2
(A ⬍ B)
A1
x1
B1
A0
x0 (A ⬎ B)
B0
(A ⫽ B)
D 1 xyz
z
D 2 xyz
y
D 3 xyz
D 4 xyz
x
D 5 xyz
D 6 xyz
D 7 xyz
© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e. Fig. 4-18 3-to-8-Line Decoder
D0
E A B D0 D1 D2 D3
D1
1 X X 1 1 1 1
A 0 0 0 0 1 1 1
0 0 1 1 0 1 1
D2 0 1 0 1 1 0 1
B 0 1 1 1 1 1 0
D3
E
38
D 8 to D 15
decoder
E
1
S
x 22 2
3⫻8 3
y 21 decoder 4
z 20 5 C
6
00 X 1 1 1 00 X 1 1 1
01 1 1 1 01 1 1 1 1
D1 D1
11 1 1 1 11 1 1 1 1
D0 D0
10 1 1 1 10 1 1 1
D3 D3
x D2 D 3 y D3 D1D2
y
D2
D1
V
D0
I0 0
Y MUX Y
I1 1
I1
S
S
I3
s1
s0
A1
Y1
A2
Y2
A3
Y3
B0
Function table
E S Output Y
B1
1 X all 0's
0 0 select A
B2 0 1 select B
B3
S
(select)
E
(enable)
I1
I2
A Y I3
0
S1
Select 1
B S0 2⫻4
decoder 2
Enable EN
Select 3
control control
bufifl bufif0
in out in out
control control
notifl notif0
select
T2
T4
D
F2
Fig. P4-1
B
C
G
D
Fig. P4-2
f b
g
b
e c c
d
Fig. P4-9
B0
S0
A0
C0