Effects and Compensation of Dead-Time and Minimum Pulse-Width Limitations in Two-Level PWM Voltage Source Inverters
Effects and Compensation of Dead-Time and Minimum Pulse-Width Limitations in Two-Level PWM Voltage Source Inverters
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1-4244-0365-0/06/$20.00 (c) 2006 IEEE
0.5 1
SVPWM
Desired Duty Cycle dclipH
0
Actual Duty Cycle
Maximum
Modulator (a)
-0.5 Pulse Width
0 50 100 150 200 250 300 350
0.5
DPWM0
Minimum
Pulse Width
dclipL
Phase a (pu x Vdc)
0 0
(a) (b) (c)
Zero Sequence (b)
-0.5 Fig. 3. Methods of rounding to avoid minimum pulse-widths.
0 50 100 150 200 250 300 350
0.5
DPWM1 complementary manner, maximum achievable pulse duration
is effectively induced. The converse is also true if the upper
0 switch is limited to maximum on-time duration, introducing
Fundamental (c) an effective minimum pulse-width on the lower switch. Such
-0.5
0 50 100 150 200 250 300 350
limitations may have to be enforced to prevent damage to the
0.5
DPWM2
semiconductor switches, as are typically found in very high
power applications. MPW limitations can also result from
0 constraints in the gate driver circuit whose possible causes
(d) include transformer reset times or component tolerance drift.
-0.5 Gate driver limitations are often found in cost sensitive
0 50 100 150 200 250 300 350
Electrical Angle (degrees)
applications operating over a very wide temperature range.
Fig. 2. Modulation waveforms of modern PWM methods (Mi = 0.7). Traditionally, pulses less than a minimum width were
prevented from passing to the gate driver circuit and hence,
output. A key difference is that DPWM1 is switching loss dropped [4]. Dropping pulses results in the rounding of the
optimized for unity power factor loads while DPWM0 is phase duty cycle as shown in Fig. 3a. It is possible to hold
optimized for 30° leading power factor loads and DPWM2 is pulses which are too small to be achievable, to the minimum
optimized for 30° lagging power factor loads [9]. The achievable pulse-width, resulting in duty cycles shown in Fig.
fundamental, zero sequence, and resultant modulation waves 3b. Either dropping pulses or holding them at some minimum
for a carrier based implementation of SVPWM and the three value will result in a discontinuity in the achievable output
DPWM methods are shown in Fig. 2 with the waveforms voltage because the average value of the applied volt-seconds
referenced to the center point of the dc link. over a switching period is not accurately reproduced. It is
The modulation index of the PWM signal relates the also possible to round the pulses with an intermediate method
amplitude of the fundamental component of the output as shown in Fig. 3c. In Fig. 3c, pulses are dropped if they are
voltage referenced to the fundamental output voltage very small, but held to the minimum pulse-width value if
produced in six-step operation. The modulation index is then only slightly smaller. As shown in the figure, the break point
given as in deciding whether to round up or round down the desired
V 1* duty cycle is given by dclipL and dclipH.
Mi = (1)
(2/π)Vdc B. Dead-time effects
Dead-time or inverter lock-out time is necessary to prevent
where V 1* is the commanded amplitude of the fundamental a shoot-through failure by gating on both switches in an
component. Employing (1), SVPWM, DPWM0, DPWM1, inverter phase leg. During the dead-time period, both of the
and DPWM2 can ideally reproduce any fundamental output inverter switches in a phase leg are gated off. As a result, the
up to a modulation index, MLmax = π/(2 3 ) ≈ 0.907 [9]. output voltage of the phase (i.e, point a in Fig. 1) is
determined by the direction of the phase current flowing
III. SOURCES OF INVERTER NON-LINEARITY through the inverter antiparallel diodes. As a result the dead-
time effect can be thought of as a parasitic resistance [15].
The two main sources of inverter non-linearity are MPW An efficient way to compensate for dead-time effects is the
effects and dead-time effects. They are discussed along with pulse based dead-time compensator (PBDTC) method shown
their practical impact on system operation as follows; in Fig. 4 [11]. It should be noted that the PBDTC preserves
A. Minimum pulse-width effects the center based pulses which result in superior high
frequency harmonic performance compared to non-centered
Minimum pulse-width limitations result when small on-
pulses [16]. With reference to Fig. 4, PBDTC works as
time duration of the lower switch in a phase leg cannot be
follows; (a) shows the triangular carrier and modulating
achieved. Since the upper switch in the phase leg is gated in a
function while (b) shows the ideal phase a switching pulse.
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+Vdc/2 Maximum achievable pulse width for ia > 0
Triangular Carrier
(a) 1
Phase a modulating actual Sa ouptut
Ts Ts (a) dmax
function switching pulse
-Vdc/2 0
2 2
1 1 Upper switch gate signal
(b) ideal Sa switching pulse (b)
with correction
0 0 TDead
1 1
actual Sa resultant switching Lower switch gate signal
(c) (c) TMPW
error ia > 0 pulse without correction with correction
0 0
1 Minimum achievable pulse width for ia < 0
added actual Sa switching pulse with
(d) ia > 0 1
pulse time correction actual Sa output
0 (d) dmin
1 switching pulse
actual Sa resultant switching 0
(e) ia > 0 1
pulse with correction Upper switch gate
0 (e) TMPW
1 signal with correction
actual Sa resultant switching 0
(f) ia < 0 error 1 TDead
pulse without correction Lower switch gate
0 (f)
1 signal with correction
actual Sa switching pulse with 0
(g) ia < 0 subtracted Ts Ts
pulse time correction
0
2 2
1
actual Sa resultant switching
(h) ia < 0 Fig. 5. Gate signals for maximum and minimum achievable pulse-widths.
pulse with correction
0
phase system. In addition to the achievable duty cycles after
Fig. 4. Pulses for ideal and PBDTC with effects of current direction. compensation given by (2) and (3), the discrete clamped duty
When the current is positive (c) shows that part of the pulse- cycles of d = 0, and d = 1 are also achievable by leaving one
width is lost due to the dead-time effect. Adding pulse-width of the switches in a phase leg always on.
as in (d) will produce the correct, desired pulse (e). When the Dead-time compensation corrects for distortion voltages
current is negative (f), shows that pulse-width is gained due produced by the hardware. Since the dead-time compensation
to the dead-time effect. Subtracting pulse-width as in (g) will occurs after the PWM modulator signal, different limits on
produce the correct, desired pulse (h). duty cycle for the modulator are induced. In effect, this
further shifts the limits in (2) and (3) towards the center, d =
C. Practical limitations 0.5 by one dead-time period. Hence, the practical limits on
The function of any PWM algorithm is to faithfully duty cycle at the output of the PWM modulator are given as
produce the voltage to apply to the load which is requested by
the system controller. As a result, the voltage should be dmax = 1 − (1/Ts)(3Tdead + TMPW) . (4)
distortion free, and independent of the system states (i.e. dmin = (1/Ts)(3Tdead + TMPW) . (5)
current polarity). The system non-linearity’s of MPW and
dead-time compensation limit the achievable pulse-width, or When the limits of (4) – (5) are imposed upon the PWM
duty cycle as seen by the load. modulator, the limits of (2) – (3) will be the resultant limits as
Fig. 5 illustrates the limiting cases for the achievable seen by the load. The discrete clamped duty cycles of d = 1
output duty cycles seen by the load after proper dead-time and d = 0 are also allowable at the modulator limit as they do
compensation is applied. The maximum achievable duty not require any dead-time compensation.
cycle when the load current is positive is given by
IV. EFFECTS OF NON-LINEARITY ON PWM METHODS
dmax_post_dtc = 1 − (1/Ts)(2Tdead + TMPW) . (2)
The inability of the system to produce non-distorted duty
The minimum achievable duty cycle when the phase current cycles which are very small or very large will affect the
is negative is given as PWM modulator. Fig. 6 shows the impact of the duty cycle
limits in space vector diagram format for the four considered
dmin_post_dtc = (1/Ts) (2Tdead + TMPW) . (3) PWM methods. In the figure, the shaded areas indicate where
the duty cycle limits cannot be properly compensated; they
It should be noted that the values given in (2) and (3) are
will be referred to as distortion regions.
the most restrictive cases. For example, if the current is
By considering the distortion regions shown in Fig. 6 for
negative, the achievable dmax_post_dtc is larger than given by
the various PWM methods, several observations can be made.
(2). Likewise, the value of dmin_post_dtc is less than given by All of the PWM methods have distortion at high modulation
(3) if the current is positive. However, the values given by (2) indexes when the commanded voltage vector is in the outer
and (3) are always achievable, and are symmetric about d = portions of the hexagon. In effect, the linear modulation
0.5, which will complement the natural symmetry of a three- range has been reduced. Also, SVPWM has a distortion
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q-axis q-axis
0.5
V*dq V*dq 0
V4=011 V1=100 V4=011 V1=100
θ θ
d-axis d-axis v a1 θ
dmin-0.5
-0.5
200 250 300 350
V5=001 V6=101 V5=001 V6=101 Electrical Angle (degrees)
(a) SVPWM (b) DPWM0 Fig. 7. Expanded view of DPWM2 modulation waveforms (Mi = 0.7).
q-axis q-axis
V3=010 V2=110 V3=010 V2=110
V. COMPENSATING INVERTER NON-LINEAR EFFECTS
V*dq V*dq
With the identification of the distortion regions, it is
V4=011 V1=100 V4=011 V1=100
θ θ possible to develop a compensation method such that the
d-axis d-axis regions are avoided, or their impact reduced. Since all of the
DPWM methods suffer from distortion at undermodulation, a
continuous PWM method such as SVPWM must be chosen if
V5=001 V6=101 V5=001 V6=101
the distortion induced in the phase currents with a DPWM
(c) DPWM1 (d) DPWM2 method is unacceptable.
Fig. 6. Distortion regions for various PWM methods.
A. Middle modulation regions
region at high modulation indexes which is twice as large as
the DPWM methods due to the fact that it has two zero In the middle modulation regions, it is simple enough to
vectors applied during each PWM cycle compared to one for avoid any distortion regions when using a DPWM method by
the DPWM methods. Both of these observations have been choosing the DPWM1 method. However, the DPWM2
previously reported [17]. The DPWM methods also distort method would produce fewer losses for load power factor
the voltages at very low modulation indexes, which will be angles between 15° and 30° [9]. As a result, it is
referred to as an undermodulation region. In the advantageous to use DPWM2 whenever possible and switch
undermodulation region, the load phase voltages are to DPWM1 when the commanded voltage is in the distortion
comprised mainly of a zero sequence component and hence region of DPWM2. Likewise for leading power factor loads,
the individual phase legs will be switching with either a very DPWM0 will produce fewer losses than DPWM1 so
small or very large duty cycle [17]. switching between DPWM0 and DPWM1 is advantageous. It
The DPWM0 and DPWM2 methods shown in Fig. 6b and should be noted that dynamically switching between two
Fig. 6d contain distortion regions at the sector transitions. As DPWM methods does not change the active voltage vector or
a result, they will introduce a distortion voltage term at the increase the number of switching transitions; it merely selects
sixth harmonic under all modulation indexes. Interestingly, a different zero vector (111 or 000).
the distortion regions at the sector transitions may not be an The distortion region is a function of both the modulation
issue for some applications. When the power factor of the index and time (electrical angle). Since the pulse-width limits
load is less then 3 /2 (angle greater than 30°), the dead-time were symmetric, the angle at which the distortion region
compensation adjusts the duty cycle in favor of the limit. For begins needs only be calculated for one sixth of the cycle.
example consider the DPWM2 method in the region of 100 − Symmetry can be used to determine the angle in the
120° as seen in Fig. 2d. This region consists of small duty remaining sectors. Likewise, symmetry properties apply such
cycles, which may be impacted by the limit of (3). However, that the distortion region is the same size for both DPWM2
for lower power factor loads, the current would be positive in and DPWM0; only the location on the space vector diagram
this region. As a result, the dead-time compensator would is changed. With reference to an expanded view of the
increase the duty cycle. Also, the limit of (3) is reduced for modulation waveforms of DPWM2 shown in Fig. 7, the
positive current. Thus, the combined increase in duty cycle phase a fundamental, and zero sequence, between 240° and
and smaller achievable pulse limit would typically eliminate 300° are given as
the distortion region at the sector transitions in its entirety. va1(ωt) = (2/π) Mi cos(ωt) (6)
For higher power factor loads, such as a permanent magnet
motor, the distortion region becomes a factor since the v0(ωt) = (1/2) − (2/π) Mi cos(ωt + (2π/3)) (7)
current would be negative. Thus, the dead-time compensator
would decrease the duty cycle and exceed the limit of (3). The angle, θ, which marks the start of the distortion region,
The interested reader is referred to [18] and [19] which can be found by solving
have explored similar distortion region issues for three-level dmax − (1/2) = va1(θ) + v0(θ) . (8)
inverters.
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Substituting (6) and (7) into (8) yields, after simplification,
It should be noted that the limit given in (12) is also the The DPWM1 adjustment angle, θ1, which marks the start
upper limit on modulation index for which the proposed of the modifications, is given from
method to switch between DPWM methods will be
undistorted. As a result, it represents the transition point dmax − (1/2) = va1(θ1) + v0(θ1) . (15)
between the proposed middle modulation and high Substituting (13) and (14) into (15) yields, after
modulation compensation methods. simplification,
In order to compensate while in the distortion region which
begins at (12), the rounding method shown in Fig. 3c will be
used to preserve the desired fundamental component and
[
dmax = (Mi /π) 3 cos(θ1) − 3 sin(θ1) . ] (16)
maintain the input-output voltage gain of the modulator as in Equation (16) can be solved numerically to yield the angle
the linear region. A similar method for various PWM which indicates the start of the modifications. Applying
algorithms operating in the overmodulation region is Fourier analysis techniques to the waveform of Fig. 8b yields
discussed in [21]. The proposed compensation for DPWM1 a complicated expression for the fundamental component of
in the high modulation regions is shown in Fig. 8. Only the the modified waveform. This is given as
positive half cycle of phase a is shown in the figure as the
remaining signals can be found from symmetry.
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2
[
dclipH = (Mi /π) 3 cos(θ2) − 3 sin(θ2) . ] (18) -40
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i qe , 25 A/div
(a) (b)
i de , 25 A/div da , 0.4/div 5th, 2.34%
7th, 1.78%
~
Te_ripple , 8 Nm/div
1.12 Nm rms
Fig. 12. Baseline case, ωr = 1800 rpm, Mi = 0.45. (a) Motor currents, estimated torque ripple, phase a duty cycle; (b) Phase a current spectrum.
i qe , 25 A/div
(a) (b)
i de , 25 A/div da , 0.4/div
5th, 1.51% 7th, 1.02%
~
Te_ripple , 8 Nm/div
0.73 Nm rms
Fig. 13. Middle mod. comp. method, ωr = 1800 rpm, Mi = 0.45. (a) Motor currents, estimated torque ripple, phase a duty cycle; (b) Phase a current spectrum.
i qe , 75 A/div
5th, 2.88%
(a) (b)
i de , 75 A/div da , 0.4/div 7th, 1.12%
~
Te_ripple , 16 Nm/div
4.58 Nm rms
Fig. 14. Baseline case, ωr = 2500 rpm, Mi = 0.78. (a) Motor currents, estimated torque ripple, phase a duty cycle; (b) Phase a current spectrum.
i qe , 75 A/div
Fig. 15. High mod. comp. method, ωr = 1800 rpm, Mi = 0.89. (a) Motor currents, estimated torque ripple, phase a duty cycle; (b) Phase a current spectrum.
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