MITSUBISHI

MITSUBISHI
SEMICONDUCTOR
SEMICONDUCTOR
<Dual-In-Line
<Dual-In-Line
Package
Package
Intelligent
Intelligent
Power
Power
Module>
Module>

PS22056
PS22056
TRANSFER-MOLD
TRANSFER-MOLDTYPE
TYPE
INSULATED
INSULATED
TYPE
TYPE

PS22056
INTEGRATED POWER FUNCTIONS
1200V/25A low-loss 4 th generation IGBT inverter bridge
for 3 phase DC-to-AC power conversion

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS

• For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.
• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC).
• Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply).
• Input interface : 5V line CMOS/TTL compatible (High active logic).

APPLICATION
AC400V 0.2kW~3.7kW inverter drive for small power motor control.

Fig. 1 PACKAGE OUTLINES Dimensions in mm

30✕2.54(=76.2)
2.54±0.3
Heat sink side
1. VUFS 22. P
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
2. VUFB 23. U
3. VP1 24. V
27.4±0.5

4. UP 25. W
Type name , Lot No. 5. VVFS 26. NU
42.6±0.5
48.6±0.6

34±0.5

6. VVFB 27. NV
44±0.5

QR 7. VP1 28. NW
Code 8. VP
20.4±0.5

2-φ4.5±0.2
18.5±0.5

9. VWFS
10. VWFB
22 23 24 25 26 27 28
11. VP1
12. VPC
A 13. WP
8±0.3 10.16±0.3
14. VN1
67±0.3 15. VNC
79±0.5 16. CIN
17. CFO
18. FO
16.1±0.3

19. UN
20. VN
21. WN
(0.3)
(1.7)
(0.3)
8.2±0.5

(2)

(2.5)
Heat sink side
(2)

Detail : A
All external terminals are treated with lead free solder (ingredient : Sn-Cu) plating.

May 2005
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS22056
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)

CBW+
CBW–
CBV+
CBU–

CBV–
CBU+
C1 : Tight tolerance, temp-compensated electrolytic type High-side input (PWM)
(5V line) (Note 1,2)
(Note : The capacitance depends on the PWM control C2
scheme used in the applied system.) C1
Input signal Input signal Input signal
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering conditioning conditioning conditioning

Level shifter Level shifter Level shifter

Protection Protection Protection
(Note 6)
circuit (UV) circuit (UV) circuit (UV)

DIP-IPM
Drive circuit Drive circuit Drive circuit
Inrush current
limiter circuit
P

AC line input
H-side IGBTS
U
V
(Note 4)
W
M
C
AC line output
Z
NU
(Note 8) NV L-side IGBTS
NW
N1 VNC CIN

Drive circuit
Z : ZNR (Surge absorber)
C : AC filter (Ceramic capacitor 2.2~6.5nF) Protection Control supply
Input signal conditioning Fo logic Under-Voltage
(Protection against common-mode noise) circuit
protection (UV)

(Note 7)
Low-side input (PWM) FO CFO
(5V line) (Note 1, 2) Fault output (5V line)
(Note 3, 5)
VNC VD
(15V line)

Note1: To prevent input signals oscillation, an RC coupling at each input terminal is recommended.
2: By virtue of integrating HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible.
3: Fo output is open drain type. The signal line should be pulled up to the positive side of a 5V supply with an approximate 10kΩ resistor.
4: The wiring between the power DC-link capacitor and the P/N1 terminals should be as short as possible to protect DIP-IPM against catastrophic high
surge voltage. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to mount closely to the
P and N1 terminals.
5: Fo output pulse width (t FO) should be determined by connecting external capacitor between CFO and VNC terminals. (Example : t FO=2.4ms(typ.)
at CFO=22nF)
6: High voltage (1200V or more) and fast recovery type (less than 100ns) diodes should be used for the bootstrap circuit.
7: It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
8: To prevent LVIC from surge destruction, it is recommended to mount a fast recovery type diode between VNC and NU, NV, NW terminals.

Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT

DIP-IPM

Drive circuit IC (A)

P
SC protection
trip level

H-side IGBTS
U
V
W
L-side IGBTS
External protection circuit

Shunt
NU
N1 resistor A NV Collector current
(Note 1) NW waveform

R 0
C Drive circuit 2 tw (µs)
B CIN
Short Circuit Protective Function (SC) :
Protection circuit SC protection is achieved by sensing the L-side DC-Bus current (through the external
C VNC
(Note 2) shunt resistor) with a suitable filtering time (defined by the RC circuit).
Note1: In the recommended external protection circuit, please select the RC time When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
constant in the range 1.5~2.0µs. OFF and a fault signal (Fo) is output.
2: To prevent erroneous protection operation, the wiring of A, B, C should be Since the SC fault may be repetitive, it is recommended to stop the system and check the fault,
as short as possible. when the Fo signal is received.

May 2005
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS22056
TRANSFER-MOLD TYPE
INSULATED TYPE

MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)

INVERTER PART
Symbol Parameter Condition Ratings Unit
VCC Supply voltage Applied between P-NU, NV, NW 900 V
VCC(surge) Supply voltage (surge) Applied between P-NU, NV, NW 1000 V
VCES Collector-emitter voltage 1200 V
±IC Each IGBT collector current TC = 25°C 25 A
±ICP Each IGBT collector current (peak) TC = 25°C, less than 1ms 50 A
PC Collector dissipation TC = 25°C, per 1 chip 78.1 W
Tj Junction temperature (Note 1) –20~+125 °C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ T C ≤ 100°C) however, to en-
sure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C).

CONTROL (PROTECTION) PART

Symbol Parameter Condition Ratings Unit
VD Control supply voltage Applied between V P1-VPC, V N1-VNC 20 V
VDB Control supply voltage Applied between V UFB-VUFS, VVFB -VVFS, 20 V
VWFB-VWFS
Applied between UP, VP, WP-VPC,
VIN Input voltage –0.5~VD+0.5 V
UN, V N, WN-VNC
VFO Fault output supply voltage Applied between FO-VNC –0.5~VD+0.5 V
IFO Fault output current Sink current at F O terminal 1 mA
VSC Current sensing input voltage Applied between CIN-V NC –0.5~VD+0.5 V

TOTAL SYSTEM
Symbol Parameter Condition Ratings Unit
VD = 13.5~16.5V, Inverter part
VCC(PROT) Self protection supply voltage limit 800 V
(short circuit protection capability) Tj = 125°C, non-repetitive, less than 2 µs
TC Module case operation temperature (Note 2) –20~+100 °C
Tstg Storage temperature –40~+125 °C
60Hz, Sinusoidal, AC 1 minute, connection
Viso Isolation voltage 2500 Vrms
pins to heat-sink plate

Note 2 : TC MEASUREMENT POINT

Control terminals

Heat sink boundary

Heat-sink
TC

Power terminals TC

May 2005
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS22056
TRANSFER-MOLD TYPE
INSULATED TYPE

THERMAL RESISTANCE
Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
Rth(j-c)Q Junction to case thermal Inverter IGBT part (per 1/6 module) — — 1.28 °C/W
Rth(j-c)F resistance (Note 3) Inverter FWDi part (per 1/6 module) — — 1.70 °C/W
Rth(c-f) Contact thermal resistance Case to fin, (per 1 module) thermal grease applied — — 0.047 °C/W
Note 3: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100µm~+200µm on the con-
tacting surface of DIP-IPM and heat-sink.

ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)

INVERTER PART
Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
Collector-emitter saturation VD = VDB = 15V Tj = 25°C — 2.7 3.4
VCE(sat) V
voltage VIN = 5V, I C = 25A Tj = 125°C — 2.5 3.2
VEC FWDi forward voltage –I C = 25A, V IN = 0V — 2.5 3.0 V
ton 0.8 1.5 2.2 µs
trr VCC = 600V, VD = VDB = 15V — 0.3 — µs
tc(on) Switching times IC = 25A, Tj = 125°C, VIN = 0 ↔ 5V — 0.6 0.9 µs
toff Inductive load (upper-lower arm) — 2.8 3.8 µs
tc(off) — 0.6 0.9 µs
Collector-emitter cut-off Tj = 25°C — — 1
ICES VCE = VCES mA
current Tj = 125°C — — 10

CONTROL (PROTECTION) PART

Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
VD = VDB = 15V Total of V P1-VPC, VN1-VNC — — 3.70 mA
VIN = 5V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS — — 1.30 mA
ID Circuit current
VD = VDB = 15V Total of V P1-VPC, VN1-VNC — — 3.50 mA
VIN = 0V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS — — 1.30 mA
VFOH VSC = 0V, F O circuit pull-up to 5V with 10kΩ 4.9 — — V
Fault output voltage
VFOL VSC = 1V, I FO = 1mA — — 1.10 V
VSC(ref) Short circuit trip level T j = 25°C, VD = 15V (Note 4) 0.43 0.48 0.53 V
I IN Input current VIN = 5V 0.7 1.5 2.0 mA
UVDBt Trip level 10.0 — 12.0 V
UVDBr Supply circuit under-voltage Reset level 10.5 — 12.5 V
protection T j ≤ 125°C
UVDt Trip level 10.3 — 12.5 V
UVDr Reset level 10.8 — 13.0 V
t FO Fault output pulse width CFO = 22nF (Note 5) 1.6 2.4 — ms
Vth(on) ON threshold voltage 2.0 3.0 4.2 V
Applied between UP, VP, WP-VPC, UN, VN, WN-VNC
Vth(off) OFF threshold voltage 0.8 1.4 2.0 V
Note 4 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC trip-
level is less than 1.7 times device current rating.
5 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulse-
width tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 9.3 ✕ 10-6 ✕ tFO [F].

May 2005
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS22056
TRANSFER-MOLD TYPE
INSULATED TYPE

MECHANICAL CHARACTERISTICS AND RATINGS

Limits
Parameter Condition Unit
Min. Typ. Max.
Mounting torque Mounting screw : M4 Recommended 1.18 N·m 0.98 — 1.47 N·m
Weight — 77 — g
Heat-sink flatness (Note 6) –50 — 100 µm

Note 6: Measurement point of heat-sink flatness

+ – 3.25mm
Measurement location

Heat-sink side

–
+
Heat-sink side

RECOMMENDED OPERATION CONDITIONS

Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
VCC Supply voltage Applied between P-NU, NV, NW 350 600 800 V
VD Control supply voltage Applied between V P1-VPC, V N1-VNC 13.5 15.0 16.5 V
VDB Control supply voltage Applied between V UFB-VUFS, VVFB -VVFS, V WFB-VWFS 13.5 15.0 16.5 V
∆VD, ∆VDB Control supply variation –1 — 1 V/µs
tdead Arm shoot-through blocking time For each input signal, TC ≤ 100°C 3.3 — — µs
fPWM PWM input frequency T C ≤ 100°C, Tj ≤ 125°C — — 15 kHz
VCC = 600V, VD = 15V, fC = 15kHz
IO Allowable r.m.s. current P.F = 0.8, sinusoidal PWM — — 9.2 Arms
T j ≤ 125°C, TC ≤ 100°C (Note 7)
PWIN(on) (Note 8) 1.5 — —
350 ≤ VCC ≤ 800V,
13.5 ≤ VD ≤ 16.5V, Ic ≤ 25A 2.1 — —
Minimum input pulse width 13.5 ≤ VDB ≤ 16.5V, µs
PWIN(off) –20°C ≤ TC ≤ 100°C,
N line wiring inductance less than 25 < Ic ≤ 42.5A 2.3 — —
10nH (Note 9)
VNC VNC variation Between VNC-NU, NV, NW (including surge) –5.0 — 5.0 V
Note 7 : The output r.m.s. current value depends on the actual application conditions.
8 : DIP-IPM might not make response to the input on signal with pulse width less than PWIN (on).
9 : DIP-IPM might not make response or work properly if the input off signal pulse width is less than PWIN (off).

May 2005
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS22056
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 4 THE DIP-IPM INTERNAL CIRCUIT

VUFB DIP-IPM
VUFS P
HVIC1
VP1 VCC VB IGBT1 Di1

UP IN HO

COM VS U
VVFB
VVFS
HVIC2
VP1 VCC VB IGBT2 Di2

VP IN HO

COM VS V
VWFB
VWFS
HVIC3
VP1 VCC VB IGBT3 Di3

WP IN HO

VPC COM VS W

LVIC IGBT4
Di4
UOUT

UVNO NU
VN1 VCC
IGBT5
Di5
VOUT

VVNO NV
UN UN IGBT6
Di6
VN VN WOUT
WN WN
WVNO NW
Fo Fo
CIN
VNC GND
CFO

CFO CIN

May 2005
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS22056
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS

[A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit current detection (SC trigger).
a3. IGBT gate hard interruption.
a4. IGBT turns OFF.
a5. FO output with a fixed pulse width determined by the external capacitor C FO.
a6. Input = “L ” : IGBT OFF
a7. Input = “H” :
a8. IGBT OFF state in spite of input “H”.

Lower-arms control a6 a7
input

Protection circuit state SET RESET

Internal IGBT gate

a3
a2

SC a4
a1
Output current Ic a8
SC reference voltage
Sense voltage of the
shunt resistor

CR circuit time
constant DELAY
Error output Fo a5

[B] Under-Voltage Protection (Lower-arm, UVD)

b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO keeps output during the UV period, however, F O pulse is not less than the fixed width for very short UV interval.
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.

Control input

Protection circuit state RESET SET

RESET

UVDr
Control supply voltage VD b1 UVDt b6
b3

b4
b2 b7

Output current Ic

Error output Fo
b5

May 2005
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS22056
TRANSFER-MOLD TYPE
INSULATED TYPE

[C] Under-Voltage Protection (Upper-side, UVDB)

c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input signal level, but there is no FO signal output.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.

Control input

Protection circuit state RESET SET RESET

UVDBr
Control supply voltage VDB c1 UVDBt c5
c3

c2 c4 c6
Output current Ic

High-level (no fault output)

Error output Fo

Fig. 6 MCU I/O INTERFACE CIRCUIT

5V line

10kΩ DIP-IPM

UP,VP,WP,UN,VN,WN

MCU
Fo

VNC(Logic)

Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in
the application and the wiring impedance of the application’s printed circuit board.
The DIP-IPM input signal section integrates a 2.5kΩ(min) pull-down resistor. Therefore, when using a external
filtering resistor, pay attention to the turn-on threshold voltage requirement.

Fig. 7 WIRING CONNECTION WITH 1 SHUNT RESISTOR

Using low inductance chip resistor and reducing

DIP-IPM wiring length to minimize the wiring inductance.

NU Shunt resistor
NV
VNC NW Please make the wiring connection
of shunt resistor to GND as short as
Please insert fast
recovery type diode possible.
between VNC and
NU, NV, NW terminals.

For 3 shunt resistors connection, please refer to Fig.9.

May 2005
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS22056
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 8 AN EXAMPLE OF TYPICAL DIP-IPM APPLICATION CIRCUT WITH 1 SHUNT RESISTOR

C1:Tight tolerance temp-compensated electrolytic type
C2,C3: 0.1~0.22µF R-category ceramic capacitor for noise filtering.
(Note: The capacitance value depends on the PWM control used in the applied system.)
C2 VUFB
DIP-IPM
C1 VUFS P
HVIC1
VP1
VCC VB
C3
UP
IN HO

COM VS U
C2 VVFB
C1 VVFS
HVIC2
VP1
VCC VB
C3
VP
IN HO
V
C2
COM VS M
VWFB
C1 VWFS
HVIC3
VP1
VCC VB
C3
WP
IN HO
MCU

VPC
COM VS W

LVIC

UOUT

VN1 UVNO NU
VCC
C3

5V line
VOUT
VVNO NV
UN
UN
VN
VN WOUT
WN
WN WVNO NW If this wiring is too
Fo long, short circuit
Fo might be caused.
CIN
VNC
GND CFO C

CFO CIN
C4(CFO )
R1 B
15V line
Shunt
C5 resistor
A N1

The long wiring of GND might generate noise If this wiring is too long, the SC level fluctuation
on input and cause IGBT to be malfunction. might be larger and cause SC malfunction.

Note 1 : To avoid malfunction, the wiring of each input should be as short as possible. (less than 2-3cm)
2: By virtue of integrating HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible.
3: Fo output is open drain type. The signal line should be pulled up to the positive side of a 5V supply with an approximate 10kΩ resistor.
4: Fo output pulse width (tFO) should be determined by connecting external capacitor C4 between CFO and VNC terminals. (Example :
tFO=2.4ms(typ.) at CFO=22nF)
5: Input signal is High-Active type. There is a 2.5kΩ (Min.) resistor inside IC to pull down each input signal line to GND.
When employing RC coupling circuits at each input, set up RC couple such that input signal agree with turn-off/turn-on threshold voltage.
6: To prevent errors of the protection function, the wiring of A, B, C should be as short as possible.
7: The time constant R5C1 of the protection circuit should be selected in the range of 1.5~2µs. SC interrupting time might vary with the
wiring pattern.
8: All capacitors should be mounted as close to the terminals of the DIP-IPM as possible.
9: To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 terminals should be as short as possible.
Generally a 0.1~0.22µF snubber between the P&N1 terminals is recommended.
10: It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
11: To prevent LVIC from surge destruction, it is recommended to mount a fast recovery type diode between VNC and NU, NV, NW
terminals.
Fig. 9 EXAMPLE OF EXTERNAL PROTECTION CIRCUIT WITH 3 SHUNT RESISTORS
DIP-IPM
• The time constant RC of external comparator should be selected in the range
Drive circuit
of 1.5~2µs. SC interrupting time might vary with the wiring pattern.
• The threshold voltage Vref should be set up the same rating of short circuit
P trip level (VSC(ref) typ. 0.48V).
• Please select the external shunt resistance such that the SC trip-level is less

than 1.7 times of the current rating.

• To avoid malfunction, the wiring of each input should be as short as possible.
H-side IGBTS • OR circuit output level should be set up the rating of short circuit trip level
U
V (VSC(ref) typ. 0.48V).
W • For extra precaution, please refer to Fig.8

L-side IGBTS
External protection circuit
R
+
NW
C
NV Vref – OR logic
NU circuit
Drive circuit R
+
C
Protection circuit Vref –
VNC CIN
R
+
Shunt
resistor C
Vref – Comparator

May 2005