Host-Controlled Multi-Chemistry Battery Charger With Low Input Power Detect
Host-Controlled Multi-Chemistry Battery Charger With Low Input Power Detect
REGN
PGND
PVCC
BTST
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq24740 www.ti.com
SLUS736 – DECEMBER 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The bq24740 features Dynamic Power Management (DPM) and input power limiting. These features reduce
battery charge current when the input power limit is reached to avoid overloading the AC adapter when
supplying the load and the battery charger simultaneously. A highly-accurate current-sense amplifier enables
precise measurement of input current from the AC adapter to monitor the overall system power. If the adapter
current is above the programmed low-power threshold, a signal is sent to host so that the system optimizes its
power performance according to what is available from the adapter.
TYPICAL APPLICATION
C16 C17 C18
10 mF 10 mF 10 mF
ADAPTER+ SYSTEM
C1 RAC C6 C7
10 mF P P 0.010 W 10 mF 10 mF
ADAPTER-
Q1 (ACFET) Q2 (ACFET)
SI4435 SI4435
Controlled by
HOST C2 C3
R1 0.1 mF 0.1 mF ACN PVCC
432 kW C8
1% ACP 1 mF
Q3(BATFET)
SI4435
Controlled by
ACDET HOST
R2 Q4 P
AGND HIDRV FDS6680A
66.5 kW VREF N
1%
R3 bq24740 PH R SR
10 kW C9 L1 0.010 W
BTST PACK+
EXTPWR EXTPWR
D1 BAT54 0.1 mF 8.2 mH C12
10 mF PACK-
REGN C11
SRSET C10 10 mF
DAC 1 mF
ACSET C13 C14
0.1 mF
LODRV Q5
VREF FDS6680A 0.1 mF
N
C4
R4 R5 1 mF PGND
10 kW 10 kW
IADSLP
HOST SRP
DPMDET
SRN
LPMD
BAT
CELLS VREF C15
R7 0.1 mF
CHGEN 200 kW
LPREF
VDAC R8
DAC ISYNSET 24.9 kW
VADJ R6
33 kW
ADC IADAPT PowerPad
C5 100 pF
R9 1.8 MW
ADAPTER+ SYSTEM
C1 RAC C6 C7
10 mF P P 0.010 W 10 mF 10 mF
ADAPTER-
Q1 (ACFET) Q2 (ACFET)
SI4435 SI4435
Controlled by
HOST C2 C3
R1 0.1 mF 0.1 mF ACN PVCC
432 kW C8
1% ACP 1 mF
Q3(BATFET)
SI4435
Controlled by
ACDET HOST
R2 Q4 P
AGND HIDRV FDS6680A
66.5 kW VREF N
1%
R3 bq24740 PH R SR
10 kW C9 L1 0.010 W
BTST PACK+
EXTPWR EXTPWR
D1 BAT54 0.1 mF 8.2 mH C12
10 mF PACK-
SRSET REGN C11
R9 C10 10 mF
R10
R11 42 kW 1 mF
100 kW C13 C14
66.5 kW 0.1 mF
ACSET Q5
R12 100 kW LODRV 0.1 mF
N FDS6680A
VREF
HOST C4 PGND
R4 R5 1 mF
10 kW 10 kW
IADSLP SRP
DPMDET SRN
GPIO
LPMD BAT
VREF C15
CELLS R7 0.1 mF
200 kW
CHGEN LPREF
R8
ISYNSET 24.9 kW
VDAC
R6
33 kW
VADJ
R9 1.8 MW
ADAPTER + SYSTEM
C1 RAC C7
C6
10 mF P P 0.010 W 10 mF
ADAPTER - 10 mF
Q1 (ACFET) Q2 (ACFET)
SI4435 SI4435
Controlled by
HOST C2 C3
432 kW 0.1 mF ACN PVCC
R1 0.1 mF
1% C8 1 mF
ACP
Q3(BATFET)
SI4435
Controlled by
ACDET
P
HOST
HIDRV Q4
66.5 kW AGND FDS6680A
R2 1% VREF N
RSR
R3 10 kW bq24740 PH
L1 0.010 W
BTST C9 PACK+
/EXTPWR EXTPWR 0.1 mF 8.2 mH C12
D1 BAT54
PACK-
REGN C11 10 mF
SRSET 10 mF
C10 1 mF
DAC C13
ACSET C14
0.1 mF
LODRV Q5
VREF FDS6680A 0.1 mF
N
C4 1 mF PGND
R4 10 kW R5 10 kW
IADSLP
HOST DPMDET
SRP
SRN
LPMD
BAT
CELLS VREF
C15
R7 0.1 mF
CHGEN 200 kW
LPREF
VDAC R8
DAC ISYNSET
24.9 kW
VADJ R6
33 kW
ADC IADAPT PowerPad
C5 100 pF
R9
(1) Pull-up rail could be either VREF or other system rail 1.8 MW
.
(2) SRSET/ACSET could come from either DAC or resistor dividers .
Figure 3. Typical System Schematic: Sensing Battery Discharge Current, When Adapter Removed. (Set
IADSLP at logic high)
ORDERING INFORMATION
Part number Package Ordering Number Quantity
(Tape and Reel)
bq24740RHDR 3000
bq24740 28-PIN 5 x 5 mm QFN
bq24740RHDT 250
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
ELECTRICAL CHARACTERISTICS
7.0 V ≤ VPVCC≤ 24 V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING CONDITIONS
VPVCC_OP PVCC Input voltage operating range 5.0 24.0 V
CHARGE VOLTAGE REGULATION
VBAT_REG_RNG BAT voltage regulation range 4V-4.512V per cell, times 2,3,4 cell 8 18 V
VVDAC_OP VDAC reference voltage range 2.6 3.6 V
VADJ_OP VADJ voltage range 0 REGN V
Charge voltage regulation accuracy 8 V, 8.4 V, 9.024 V –0.5 0.5
12 V, 12.6 V, 13.536 V –0.5 0.5 %
16 V, 16.8 V, 18.048 V –0.5 0.5
Charge voltage regulation set to default to VADJ connected to REGN, 8.4 V, –0.5 0.5
%
4.2 V per cell 12.6 V, 16.8 V
CHARGE CURRENT REGULATION
VIREG_CHG Charge current regulation differential VIREG_CHG = VSRP– VSRN 0 100
mV
voltage range
VSRSET_OP SRSET voltage range 0 VDAC V
VIREG_CHG = 40–100 mV –3 3
VIREG_CHG = 20 mV –5 5
Charge current regulation accuracy %
VIREG_CHG = 5 mV –25 25
VIREG_CHG = 1.5 mV –33 33
TYPICAL CHARACTERISTICS
(1) Test results based on Figure 2 application schematic. VIN = 20 V, VBAT = 3-cell LiIon, ICHG = 3 A, IADAPTER_LIMIT = 4 A, TA = 25°C, unless
otherwise specified.
VREF LOAD AND LINE REGULATION REGN LOAD AND LINE REGULATION
vs vs
Load Current LOAD CURRENT
0.50 0
0.40
-0.50
Regulation Error - %
Regulation Error - %
0.30
-1
PVCC = 10 V
0.20
-1.50
0.10 PVCC = 10 V
-2
0
PVCC = 20 V
-0.10 -2.50
PVCC = 20 V
-0.20 -3
0 10 20 30 40 50 0 10 20 30 40 50 60 70 80
VREF - Load Current - mA REGN - Load Current - mA
Figure 4. Figure 5.
17.6
7
17.4
6
17.2
5
17
4
16.8
3
16.6
16.4 2
16.2 1
16 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VADJ/VDAC Ratio SRSET/VDAC Ratio
Figure 6. Figure 7.
8
0.1
Regulation Error - %
6
0
5
4
3
-0.1
2
1
-0.2
0 0 2000 4000 6000 8000
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Charge Current - mA
ACSET/VDAC Ratio
Figure 8. Figure 9.
0.04
Regulation Error - %
4-Cell, no load -2
0.02 -3
0 -4
-0.02 -5
-6
-0.04
-7
-0.06
-8
-0.08 -9
-0.10 -10
16.5 17 17.5 18 18.5 19 0 2 4 6 8
V(BAT) - Setpoint - V I(CHRG) - Setpoint - A
INPUT CURRENT REGULATION (DPM) ACCURACY VIADAPT INPUT CURRENT SENSE AMPLIFIER ACCURACY
10 5
9 ACSET Varied
8 0
7
VI = 20 V, CHG = EN
Regulation Error - %
6 4-Cell, VBAT = 16 V -5
Percent Error
5 VI = 20 V, CHG = DIS
-10
4
3
2 -15
1
0 -20
Iadapt Amplifier Gain
-1
-2 -25
0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10
Input Current Regulation Setpoint - A I(ACPWR) - A
Charge Current
2
0
0 1 2 3 4
System Current - A
4
Charge Current - A
Vreg = 12.6 V
90 Vreg = 8.4 V
Efficiency - %
2
80
1
Ichrg_set = 4 A
0 70
0 2 4 6 8 10 12 14 16 18 0 2000 4000 6000 8000
Battery Voltage - V Battery Charge Current - mA
3.3V ENA_BIAS
V(IADAPT) + AC IGOOD
VREF EAI EAO
LDO - CHGEN
PVCC
/IADSLP 250mV +-
IADSLP
ACP
FBO PVCC
+ V(ACP-ACN)
- IIN_ER
- IIN_REG
+ COMP
ACN ERROR BTST
AMPLIFIER CHGEN
-
+
1V
BAT_ER LEVEL HIDRV
BAT -
SHIFTER
10mA VBAT_REG
+
CHRG_ON 20 mA BAT_SHORT
SRP ACOP PH
DC-DC
+ V(SRP-SRN) CONVERTER
20X - ICH_ER PWM LOGIC
-
IBAT_ REG +
PVCC 6V LDO
SRN 20 mA REGN
SYNCH
V(SRP - SRN) +
SYNCH ENA_BIAS
-
REFRESH
ISYNSET BTST - C BTST LODRV
+
BAT – 4V +
_
BAT_SHORT
ACSET PH
+ PGND
2.9 V/Cell +-
IC Tj + TSHUT
155°C –
ACP + V(IADAPT)
SRSET 20x IADAPT
BAT ACN -
VBATSET + BAT_OVP
VBAT_REG
IBATSET
IINSET 104% X VBAT_REG –
IBAT_REG
VADJ RATIO
IIN_REG V(SRP-SRN) +
CHG_OCP
PROGRAM
145% X IBAT_REG –
VDAC ACDET +
DPM_LOOP_ON DPMDET
ACOV
–
CELLS 3.1V +-
2, 3, 4
bq24740
TYPICAL APPLICATIONS
DETAILED DESCRIPTION
The per-cell battery termination voltage is function of the battery chemistry. Consult the battery manufacturer to
determine this voltage.
The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the
battery as possible, or directly on the output capacitor. A 0.1-µF ceramic capacitor from BAT to AGND is
recommended to be as close to the BAT pin as possible to decouple high frequency noise.
V 0.10
I ADAPTER + ACSET
VVDAC R AC (3)
The input voltage range of ACSET is between 0 and VDAC, up to 3.6 V.
The ACP and ACN pins are used to sense RAC with default value of 10mΩ. However, resistors of other values
can also be used. For a larger the sense resistor, you get a larger sense voltage, and a higher regulation
accuracy; but, at the expense of higher conduction loss.
CONVERTER OPERATION
The synchronous buck PWM converter uses a fixed frequency (300 kHz) voltage mode with feed-forward control
scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 8–12.5 kHz nominal.
fo + 1
Where resonant frequency, fo, is given by: 2p ǸLoC o where (from Figure 1 schematic)
• CO = C11 + C12
• LO = L1
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is one-fifteenth of the input adapter voltage making it always directly proportional to
the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and
simplifies the loop compensation. The ramp is offset by 250 mV in order to allow zero percent duty-cycle, when
the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order
to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while
ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin
voltage falls below 4 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and
the low-side n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor.
Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low
again due to leakage current discharging the BTST capacitor below the 4 V, and the reset pulse is reissued.
The 300 kHz fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input
voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of
the audible noise region. The charge current sense resistor RSR should be placed with at least half or more of
the total output capacitance placed before the sense resistor contacting both sense resistor and the output
inductor; and the other half or remaining capacitance placed after the sense resistor. The output capacitance
should be divided and placed onto both sides of the charge current sense resistor. A ratio of 50:50 percent gives
the best performance; but the node in which the output inductor and sense resistor connect should have a
minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching
noise and give better current sense accuracy. The type III compensation provides phase boost near the
cross-over frequency, giving sufficient phase margin.
During the DCM mode the loop response automatically changes and has a single pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage. At very low currents during non-synchronous operation, there may be
a small amount of negative inductor current during the 80 ns recharge pulse. The charge should be low enough
to be absorbed by the input capacitance.
Whenever the converter goes into 0% duty-cycle mode, and BTST – PH < 4 V, the 80-ns recharge pulse occurs
on LODRV, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (no 80-ns
recharge pulse), and there is no discharge from the battery.
ǒVIN_MAX * VBAT_MINǓ ǒ
VBAT_MIN
VIN_MAX
Ǔ ǒǓ
1
fs
and I RIPPLE_MAX +
LMIN (4)
where
VIN_MAX: maximum adapter voltage
VBAT_MIN: minimum BAT voltage
fS: switching frequency
LMIN: minimum output inductor
The ISYNSET comparator, or charge under-current comparator, compares the voltage between SRP-BAT and
internal threshold on the cycle-to-cycle base. The threshold is set to 13 mV on the falling edge with 8 mV
hysteresis on the rising edge with 10% variation.
EXT_PWR_DG EXTPWR
ACP Adaptor
Current Sense
1 kW Amplifier
+
LOIAC
ACN - Comparator
250 mV - LOIAC_DET
+
IADAPT Error
Amplifier
20 kW Disable
- IADAPT
+
IADAPT
Disable
LOPWRMODE
Comparator
+ LOPWR_DET LPMD
LPREF -
Program Hysteresis of comparator
by putting a resistor in feedback
from LPMD pin to LPREF pin.
APPLICATION INFORMATION
Ii
Ri Li
Vi C1 C8 Ci Vc
A. Ri and Li are the equivalent input inductance and resistance. C1 and C8 are the input capacitance.
20 20
15 15
10 10
5 5
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time - ms Time - ms
(a) Vc with various Ci values (b) Vc with various Li values
35
Ri = 0.15 W Li = 9.3 mH,
30 Ci = 40 mF
Ri = 0.50 W
Input Capacitor Voltage - V
25
20
15
10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time - ms
(c) Vc with various Ri values
Minimizing the input stray inductance, increasing the input capacitance and using high-ESR input capacitors
helps to suppress the input voltage spike.
Ci = 20 mF Ci = 40 mF
( c ) C i = 4 9 mF ( 4 7 mF e l e c t r o l y t i c a n d 2 x mF ceramic)
Figure 31. Adapter DC Side Hot Plug-In With Various Input Capacitances
Since the input voltage to the IC is PVCC which is 0.7 V (diode voltage drop) lower than Vc during the adapter
insertion, a 40-µF input capacitance is normally adequate to keep the PVCC voltage well below the maximum
voltage rating under normal conditions. In case of a higher input stray inductance, the input capacitance may be
increased accordingly. An electrolytic capacitor will help reduce the input voltage spike due to its high ESR.
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