Mediatek Confidential: Mt7688 Datasheet
Mediatek Confidential: Mt7688 Datasheet
US AL
EO
om TI
c.c N
ele IDE
ink F
z-l ON
MT7688 DATASHEET
C
ng EK
.ya AT
@
fan DI
E
R M
LY
Confidential B
N
Overview
MT7688 family integrates a 1T1R 802.11n Wi-Fi radio, a 580MHz MIPS® 24KEc™ CPU, 1-port fast Ethernet PHY,
US AL
EO
USB2.0 host, PCIe, SD-XC, I2S/PCM and multiple slow IOs. MT7688 provides two operation modes – IoT
gateway mode and IoT device mode. In IoT gateway mode, the PCI Express interface can connect to 802.11ac
chipset for 11ac dual-band concurrent gateway. The high performance USB 2.0 allows MT7688 to add 3G/LTE
modem support or add a H.264 ISP for wireless IP camera. For the IoT device mode, MT7688 supports eMMC,
om TI
SD-XC and USB 2.0. MT7688 can support the WiFi high quality audio via 192Kbps/24bits I2S interface and VoIP
rd
application through PCM. In IoT device mode, it further supports PWM, SPI slave, 3 UART and more GPIOs.
For IoT gateway, it can connect to touch panel and BLE, Zigbee/Z-Wave and sub-1G RF for smart home control.
c.c N
Features
Embedded MIPS24KEc (575/580 MHz) with 64 KB I- Green AP/STA
ele IDE
Cache and 32 KB D-Cache Intelligent Clock Scaling (exclusive)
1T1R 2.4 GHz with 150 Mbps PHY data rate DDRII: ODT off, Self-refresh mode
Legacy 802.11b/g and HT 802.11n modes QoS: WMM, WMM-PS
20/40 MHz channel bandwidth 16 Multiple BSSID
802.11v iPA/iLNA and ePA/eLNA
Space Time Block Coding (STBC)
ink F
24 STA-Proxy
16-bit DDR1/2 up to 128/256 Mbytes AES128/256-CBC
x1 USB 2.0 Host, x1 PCIe Root Complex
z-l ON
WEP64/128, TKIP, AES, WPA, WPA2, WAPI
1-port 10/100 FE PHY WPS: PBC, PIN
SD-XC, eMMC, I2C, PCM, I2S(192K/24bits), PWM, SPI AP/STA Firmware: Linux 2.6.36 SDK, OpenWrt 3.10
master/slave, UART lite, JTAG, GPIO SDK, eCOS with IPv6
Internet Of Thing
Embedded PMU
C
To CPU
interrupts
EJTAG 16-Bit DDR1/DDR2
INTC
DRAM
.ya AT
64 KB I-Cache Controller
SPI-M x2 SPI Device
32 KB D-Cache OCP_IF
(575/580 MHz) OCP Bridge Arbiter
SPI-S SPI Host
PBUS
PCM PCM
fan DI
N
US AL
EO
IoT Gateway Mode
om TI
interrupts
MIPS 24KEc DRAM INTC
64 KB I-Cache Controller
32 KB D-Cache OCP_IF Timer
c.c N
(575/580 MHz) OCP Bridge Arbiter SPI-M x 2 SPI
PBUS
PCM PCM
ele IDE
RBUS (SYS_CLK) UART x2 UART
GPIO
PBUS GPIO
/LED
Single Port PCIe 1.1 WLAN Switch I2C I2C
SDXC GDMA
USB 2.0 PHY PHY 11n 1x1 (5FE)
I2S I2S
5-Port
ink F
Host X1 PCIe x1 EPHY PWM x2 PWM
SD Card 2.4 GHz RJ45 x 5
z-l ON
C
ng EK
.ya AT
@
fan DI
Ordering Information
E
M
N
US AL
EO
Table of Contents
1. MAIN FEATURES 7
2. PINS 8
om TI
2.1 MT7688AN DR-QFN (12 MM X 12 MM) 156-PIN PACKAGE DIAGRAM 8
2.1.1 UP-LEFT SIDE 8
2.1.2 DOWN-LEFT SIDE 9
c.c N
2.1.3 DOWN-RIGHT SIDE 10
2.1.4 UP-RIGHT SIDE 11
ele IDE
2.1.5 PIN DESCRIPTION 12
2.2 MT7688KN DR-QFN (10 MM X 10 MM) 120-PIN PACKAGE DIAGRAM 18
2.2.1 LEFT SIDE VIE 18
2.2.2 RIGHT SIDE VIEW 20
2.2.3 PIN DESCRIPTION 21
2.3 PIN SHARING SCHEMES 24
ink F
2.3.1 GPIO PIN SHARE SCHEME 24
z-l ON
2.3.2 UART1 PIN SHARE SCHEME 26
2.3.3 MT7688AN EPHY LED PIN SHARE SCHEME 26
2.3.4 MT7688AN WLAN LED PIN SHARE SCHEME 26
2.3.5 MT7688KN EPHY LED PIN SHARE SCHEME 26
2.3.6 MT7688KN WLAN LED PIN SHARE SCHEME 27
C
N
US AL
EO
3.8 AC ELECTRICAL CHARACTERISTICS 34
3.8.1 DDR2 SDRAM INTERFACE 35
3.8.2 SPI INTERFACE 37
2
3.8.3 I S INTERFACE 38
om TI
3.8.4 PCM INTERFACE 39
3.8.5 POWER ON SEQUENCE 40
3.9 PACKAGE PHYSICAL DIMENSIONS 41
c.c N
3.9.1 DR-QFN (10 MM X 10 MM) 128 PINS 41
3.9.2 DR-QFN (12 MM X 12 MM) 156 PINS 43
ele IDE
3.9.3 MT7688 AN/KN MARKING 45
3.9.4 REFLOW PROFILE GUIDELINE 47
4. ABBREVIATIONS 48
5. REVISION HISTORY 51
ink F
Table of Figures
z-l ON
FIGURE 2-1 MT7688AN DR-QFN PIN DIAGRAM (UP-LEFT VIEW) ...................................................................................... 8
FIGURE 2-2 MT7688AN DR-QFN PIN DIAGRAM (DOWN-LEFT VIEW) ................................................................................. 9
FIGURE 2-3 MT7688AN DR-QFN PIN DIAGRAM (DOWN-RIGHT VIEW) ............................................................................. 10
FIGURE 2-4 MT7688AN DR-QFN PIN DIAGRAM (UP-RIGHT VIEW) .................................................................................. 11
FIGURE 2-5 MT7688KN DR-QFN PIN DIAGRAM (LEFT VIEW) ......................................................................................... 19
C
FIGURE 2-6 MT7688KN DR-QFN PIN DIAGRAM (RIGHT SIDE VIEW) ................................................................................. 20
FIGURE 3-1 DDR2 SDRAM COMMAND ....................................................................................................................... 35
FIGURE 3-2 DDR2 SDRAM WRITE DATA ...................................................................................................................... 35
FIGURE 3-3 DDR2 SDRAM READ DATA ....................................................................................................................... 35
ng EK
List of Tables
TABLE 1-1 MAIN FEATURES........................................................................................................................................... 7
TABLE 3-1 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 32
TABLE 3-2 MAXIMUM TEMPERATURES .......................................................................................................................... 32
R
N
US AL
EO
TABLE 3-4 THERMAL CHARACTERISTICS ......................................................................................................................... 33
TABLE 3-5 EXTERNAL XTAL SPECIFICATIONS .................................................................................................................... 33
TABLE 3-6 DC ELECTRICAL CHARACTERISTICS .................................................................................................................. 33
TABLE 3-7 VDD 2.5V ELECTRICAL CHARACTERISTICS ........................................................................................................ 34
om TI
TABLE 3-8 VDD 1.8V ELECTRICAL CHARACTERISTICS ........................................................................................................ 34
TABLE 3-9 VDD 3.3V ELECTRICAL CHARACTERISTICS ........................................................................................................ 34
TABLE 3-10 DDR2 SDRAM INTERFACE DIAGRAM KEY .................................................................................................... 36
c.c N
TABLE 3-11 SPI INTERFACE DIAGRAM KEY ..................................................................................................................... 37
TABLE 3-12 I2S INTERFACE DIAGRAM KEY ..................................................................................................................... 38
TABLE 3-13 PCM INTERFACE DIAGRAM KEY .................................................................................................................. 39
ele IDE
TABLE 3-14 POWER ON SEQUENCE DIAGRAM KEY.......................................................................................................... 40
ink F
z-l ON
C
ng EK
.ya AT
@
fan DI
E
R M
N
US AL
EO
1. Main Features
The following table covers the main features offered by the MT7688KN and MT7688AN. Overall, the
om TI
MT7688KN supports the requirements of an entry-level AP/router, while the more advanced MT7688AN
supports a number of interfaces together with a large maximum RAM capacity.
c.c N
CPU MIPS24KEc (580 MHz) MIPS24KEc (580 MHz)
ele IDE
Total DMIPs 580 x 1.6 DMIPs 580 x 1.6 DMIPs
I-Cache, D-Cache 64 KB, 32 KB 64 KB, 32 KB
L2 Cache n/a n/a
Memory
DRAM Device width support 16 bits 16 bits
ink F
DDR1 64 Mb (MCM), 193 MHz 2 Gb, 193 MHz
DDR2 n/a 2 Gb, 193 MHz
z-l ON
SPI Flash 3B addr mode (max 128Mbit) 3B addr mode (max 128Mbit)
4B addr mode (max 512Mbit) 4B addr mode (max 512Mbit)
SD n/a SD-XC (class 10)
RF 1T1R 802.11n 2.4 GHz 1T1R 802.11n 2.4 GHz
C
PCIe 1 1
USB 2.0 1 1
ng EK
Switch 5p FE SW 5p FE SW
I2S 1 1
PCM 1 1
.ya AT
I2C 1 1
@
N
US AL
EO
2. Pins
om TI
2.1.1 Up-left side
c.c N
AVDD33_WF_RFDIG
XTALIN
WLED_N
UART_RXD1
UART_TXD1
PORST_N
EPHY_LED1_N_JTDI
EPHY_LED2_N_JTMS
WDT_RST_N
PERST_N
REF_CLK0
EPHY_LED0_N_JTDO
CLKOUTP
AVSS33_XTAL
AVDD33_XTAL
EPHY_LED4_N_JTRST_N
WF0_LNA_EXT
SOC_IO_V33D_2
SOC_CO_V12D_5
AVDD33_PCIE
EPHY_LED3_N_JTCLK
AVDD33_WF0_TRX
AVDD33_WF_SX
ele IDE
DR-QFN 12X12
156 pin
156 154 152 150 148 146 144 142 140 138 136 134
155 153 151 149 147 145 143 141 139 137 135
ink F
DIG
AVSS33_RF_1 1
z-l ON
AVSS33_RF_2 2
WF0_RFION_1 3
WF0_RFION_2 4
WF0_RFIOP_1 5
WF0_RFIOP_2 6 RF
AVSS33_RF_3 7
C
AVDD33_WF0_TX 8
NC 9
AVSS33_RF_4 10
NC 11
ng EK
NC 12
AVSS33_RF_5 13
AVDD33_WF1_TX 14
AVDD33_WF1_TRX 15
I2S_SDI 16
I2S_SDO 17
.ya AT
I2S_WS 18
@
I2S_CLK 19
N
US AL
EO
2.1.2 Down-left side
om TI
I2C_SCLK 20
I2C_SD 21 DIG
SOC_CO_V12D_1 22
SOC_IO_V33D_1 23
c.c N
SPI_CS1 24
SPI_CLK 25
SPI_MISO 26
ele IDE
SPI_MOSI 27
SPI_CS0 28
GPIO0 29
UART_TXD0 30
UART_RXD0 31
AVDD33_TX_P0 32
MDI_RP_P0 33
ink F
MDI_RN_P0 34
MDI_TP_P0 35
MDI_TN_P0 36
z-l ON
NC1 37
AVDD33_COM 38
EPHY_VRT 39
EPHY USB
41 43 45 47 49 51 53 55 57 59 61
40 42 44 46 48 50 52 54 56 58 60 62
C
AVDD33_TX_P1234_1
AVDD33_TX_P1234_2
SOC_CO_V12D_2
AVDD33_USB
MDI_RN_P1
MDI_RN_P2
MDI_RN_P3
MDI_RN_P4
MDI_TN_P1
MDI_TN_P2
MDI_TN_P3
MDI_TN_P4
MDI_RP_P1
MDI_RP_P2
MDI_RP_P3
MDI_RP_P4
MDI_TP_P1
MDI_TP_P2
MDI_TP_P3
MDI_TP_P4
USB_VRT
USB_DM
USB_DP
ng EK
N
US AL
EO
2.1.3 Down-right side
98 DDR_IO_1V8D_2 DDR_IO_1V8D_2
om TI
97 MA3 MBA1
96 MA12 MBA0
95 MA7 MCS
94 MA9 MRAS
c.c N
93 MA5 MCAS
92 MA10 MWE
91 SOC_CO_V12D_4 SOC_CO_V12D_4
ele IDE
90 DDR_IO_VREF_1 DDR_IO_VREF_1
89 SOC_CO_V12D_3 SOC_CO_V12D_3
88 MA1 MA13
87 MA2 MCKE
86 MA6 MA12
85 MA11 MA11
84 MA8 MA9
83 MA13 MA8
ink F
82 MA4 MA7
81 MRAS MA6
z-l ON
80 MA0 MA5
79 DDR_IO_1V8D_1 DDR_IO_1V8D_1
DDR
63 65 67 69 71 73 75 77
64 66 68 70 72 74 76 78
C
DDR_IO_VSS_1
MDQM1
MDQS1
MCK_N
MCK_P
MODT
MD15
MD13
MD10
MCAS
MD8
MD2
MD7
MD0
MD5
MCS
[ DDR2 ]
ng EK
DDR_IO_VSS_1
DDR_IO_VSS_2
DDR_IO_VSS_3
MDQM1
MDQS1
MCK_N
MCK_P
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MA4
[ DDR1 ]
.ya AT
@
Note: DR-QFN support DDR1 and DDR2 pin shuffle depend on the bootstrap.
E
R M
N
US AL
EO
2.1.4 Up-right side
om TI
PCIE_RXP0
VOUT_FB
LXBK_2
LXBK_1
PCIE_CKP0
PCIE_CKN0
PCIE_RXN0
PCIE_TXP0
PCIE_TXN0
DDRLDO
AVDD12_PCIE
AVDD33_DDRLDO_2
AVDD33_DDRLDO_1
AVSS33_SMPS_2
AVSS33_SMPS_1
PCIE_IO_VSS
c.c N
[ DDR2 ] [ DDR1 ]
ele IDE
132 130 128 126 124 122 120 118
133 131 129 127 125 123 121 119
PCIE PMU
117 AVDD33_SMPS
116 DDR_IO_1V8D_3 DDR_IO_1V8D_3
115 DDR_IO_VSS_2 DDR_IO_VSS_4
ink F
114 MD14 MD0
113 MDQS0 MDQS0
z-l ON
112 MD9 MD1
111 MD12 MD2
110 MD11 MD3
109 MD6 MD4
108 MDQM0 MD5
107 MD1 MD6
C
MWE MA2
101 MBA2 MA1
DDR 100 MBA0 MA0
99 MBA1 MA10
N
US AL
EO
2.1.5 Pin Description
Pins Name Type Driv. Description
RF
om TI
3,4 WF0_RFION_1 A WF0 main path RF I/O
WF0_RFION_2
5,6 WF0_RFIOP_1 A WF0 main path RF I/O
c.c N
WF0_RFIOP_2
11 NC
ele IDE
12 NC
9 NC
156 WF0_LNA_EXT A WF0 aux. path LNA input
151 XTALIN I Crystal oscillator input
153 CLKOUTP O XO reference clock output
ink F
152 AVDD33_XTAL P 3.3V XTAL Power Supply Pin
z-l ON
150 AVSS33_XTAL G 3.3V XTAL Ground Pin
8 AVDD33_WF0_TX P 3.3V RF Channel 0 Suppoly Power
14 AVDD33_WF1_TX P 3.3V RF Channel 1 Suppoly Power
15 AVDD33_WF1_TRX P 1.65V to 3.3V RF Channel 1 Suppoly Power
C
UART0 Lite
31 RXD0 I 4 mA UART0 Lite RXD
30 TXD0 O, IPD 4 mA UART0 Lite TXD
fan DI
UART1 Lite
147 TXD1 O, IPU 4 mA UART1 Lite TXD
148 RXD1 I 4 mA UART1 Lite RXD
E
I2S
16 I2S_SDI O 4 mA I2S data input
M
N
US AL
EO
Pins Name Type Driv. Description
20 I2C_SCLK I/O 4 mA I2C Clock
SPI
om TI
26 SPI_MISO I/O 4 mA SPI Master input/Slave output
27 SPI_MOSI I/O, IPD 4 mA SPI Master output/Slave input
25 SPI_CLK O, IPU 4 mA SPI clock
c.c N
28 SPI_CS0 O 4 mA SPI chip select0
24 SPI_CS1 O, IPD 4 mA SPI chip select1
ele IDE
GPIO
29 GPIO0 I/O, IPD 4 mA General Purpose I/O
5-Port EPHY
143 EPHY_LED0 _N_JTDO I/O 4 mA 10/100 PHY Port #0 activity LED, JTAG_TDO
ink F
142 EPHY_LED1 _N_JTDI I/O 4 mA 10/100 PHY Port #1 activity LED, JTAG_TDI
141 EPHY_LED2 _N_JTMS I/O 4 mA 10/100 PHY Port #2 activity LED, JTAG_TMS
z-l ON
140 EPHY_LED3 _N_JTCLK I/O 4 mA 10/100 PHY Port #3 activity LED, JTAG_CLK
139 EPHY_LED4 I/O, 4 mA 10/100 PHY Port #4 activity LED, JTAG_TRST_N
_N_JTRST_N
39 EPHY_VRT A Connect to an external resistor to provide accurate bias
C
current
33 MDI_RP_P0 A 10/100 PHY Port #0 RXP
34 MDI_RN_P0 A 10/100 PHY Port #0 RXN
ng EK
N
US AL
EO
Pins Name Type Driv. Description
57 MDI_TN_P4 A General purpose IO (SD-XC, eMMC…etc)
32 AVDD33_TX_P0 P 3.3V Supply Power for P0
om TI
38 AVDD33_COM P 3.3V Supply Power for EPHY COM
41 AVDD33_TX_P1234_1 P 3.3V Supply Power for P1 ~ P4
AVDD33_TX_P1234_2
c.c N
Misc.
136 REF_CLKO O, IPD 4 mA Reference Clock Ouptut
ele IDE
138 PORST_N I, IPU 4 mA Power on reset
137 WDT_RST_N O 4 mA Watchdog timeout reset
USB PHY
129 AVDD33_USB P 3.3 V USB PHY analog power supply
130 USB _VRT I/O Connect to an external 5.1 kΩ resistor for band-gap
ink F
reference circuit
z-l ON
62 USB_DM I/O USB Port0 data pin Data-
61 USB _DP I/O USB Port0 data pin Data+
PCIe PHY
135 PERST_N O, IPD 4mA PCIe device reset
C
N
US AL
EO
Pins Name Type Driv. Description
73 MD5 I/O 8 mA DDR2 Data bit #5
106 MD4 I/O 8 mA DDR2 Data bit #4
om TI
105 MD3 I/O 8 mA DDR2 Data bit #3
69 MD2 I/O 8 mA DDR2 Data bit #2
107 MD1 I/O 8 mA DDR2 Data bit #1
c.c N
71 MD0 I/O 8 mA DDR2 Data bit #0
83 MA13 O 8 mA DDR2 Address bit #13
ele IDE
96 MA12 O 8 mA DDR2 Address bit #12
85 MA11 O 8 mA DDR2 Address bit #11
92 MA10 O 8 mA DDR2 Address bit #10
94 MA9 O 8 mA DDR2 Address bit #9
ink F
84 MA8 O 8 mA DDR2 Address bit #8
95 MA7 O 8 mA DDR2 Address bit #7
z-l ON
86 MA6 O 8 mA DDR2 Address bit #6
93 MA5 O 8 mA DDR2 Address bit #5
82 MA4 O 8 mA DDR2 Address bit #4
97 MA3 O 8 mA DDR2 Address bit #3
C
N
US AL
EO
Pins Name Type Driv. Description
79 DDR_IO_1V8D_1 P DDR io Supply power
98 DDR_IO_1V8D_2
om TI
116 DDR_IO_1V8D_3
90 DDR_IO_VREF_1 A DDR reference voltage
104 DDR_IO_VREF_2
c.c N
DDR1
64 MD15 I/O 8 mA DDR1 Data bit #15
ele IDE
65 MD14 I/O 8 mA DDR1 Data bit #14
66 MD13 I/O 8 mA DDR1 Data bit #13
67 MD12 I/O 8 mA DDR1 Data bit #12
68 MD11 I/O 8 mA DDR1 Data bit #11
69 MD10 I/O 8 mA DDR1 Data bit #10
ink F
70 MD9 I/O 8 mA DDR1 Data bit #9
71 MD8 I/O 8 mA DDR1 Data bit #8
z-l ON
106 MD7 I/O 8 mA DDR1 Data bit #7
107 MD6 I/O 8 mA DDR1 Data bit #6
108 MD5 I/O 8 mA DDR1 Data bit #5
C
N
US AL
EO
Pins Name Type Driv. Description
96 MBA0 O 8 mA DDR1 MBA #0
94 MRAS O 8 mA DDR1 MRAS_N
om TI
93 MCAS O 8 mA DDR1 MCAS_N
92 MWE O 8 mA DDR1 MWE_N
77 MCK_P O 8 mA DDR1 MCK_P
c.c N
76 MCK_N O 8 mA DDR1 MCK_N
73 MDQM1 O 8 mA DDR1 MDQM#1
ele IDE
105 MDQM0 O 8 mA DDR1 MDQM#0
95 MCS O 8 mA DDR1 MCS
72 MDQS1 I/O 8 mA DDR1 MDQS#1
113 MDQS0 I/O 8 mA DDR1 MDQS#0
ink F
87 MCKE O 8 mA DDR1 MCKE
63 DDR_IO_VSS_1 G DDR IO Ground pins
z-l ON
75 DDR_IO_VSS_2
78 DDR_IO_VSS_3
115 DDR_IO_VSS_4
79 DDR_IO_1V8D_1 P DDR IO Supply power
98 DDR_IO_1V8D_2
C
116 DDR_IO_1V8D_3
90 DDR_IO_VREF_1 A DDR reference voltage
104 DDR_IO_VREF_2
ng EK
PMU
118 LXBK_1 O Buck Switching node
119 LXBK_2
122 VOUT_FB A Buck vout feedback pin
.ya AT
@
N
US AL
EO
Pins Name Type Driv. Description
om TI
IPD : Internal pull-down
IPU : Internal pull-up
I : Input
c.c N
O : Output
IO : Bi-directional
P : Power
ele IDE
G : Ground
NC : Not connected
ink F
2.2 MT7688KN DR-QFN (10 mm x 10 mm) 120-Pin Package Diagram
UART_RXD1
UART_TXD1
PORST_N
WDT_RST_N
PERST_N
REF_CLK0
AVSS33_XTAL_2
AVSS33_XTAL_1
AVDD33_XTAL
SOC_IO_V33D_3
SOC_CO_V12D_8
AVDD33_WF0_TRX
AVDD33_WF_SX
CLKOUTP
DR-QFN 10X10
120 pin
C
DIG
WF0_LNA_EXT 1
WF0_RFION_1 2
WF0_RFION_2 3
WF0_RFIOP_1 4
WF0_RFIOP_2 5
AVDD33_WF0_TX 6 RF
.ya AT
7
@
NC
NC 8
NC 9
NC 10
NC 11
AVDD33_WF1_TX 12
fan DI
AVDD33_WF1_TRX 13
I2S_SDI 14
I2S_SDO 15
I2S_WS 16
I2S_CLK 17
E
I2C_SCLK 18
I2C_SD 19
SOC_CO_V12D_1 20
M
SOC_IO_V33D_1 21 DIG
SPI_CS1 22
SPI_CLK 23
SPI_MISO 24
SPI_MOSI 25
SPI_CS0 26
GPIO0 27
UART_TXD0 28
R
UART_RXD0 29
N
US AL
EO
AVDD33_TX_P0 30
EPHY
32 34 36 38 40 42 44 46
31 33 35 37 39 41 43 45
om TI
AVDD33_TX_P1234_1
AVDD33_COM
MDI_RN_P0
MDI_RN_P1
MDI_RN_P2
MDI_TN_P0
MDI_TN_P1
MDI_TN_P2
MDI_RP_P0
MDI_RP_P1
MDI_RP_P2
MDI_TP_P0
MDI_TP_P1
MDI_TP_P2
MDI_TP_P3
EPHY_VRT
c.c N
ele IDE
Figure 2-5 MT7688KN DR-QFN Pin Diagram (left view)
ink F
z-l ON
C
ng EK
.ya AT
@
fan DI
E
R M
N
US AL
EO
2.2.2 Right side view
PCIE_RXP0
VOUT_FB
PCIE_CKP0
PCIE_CKN0
PCIE_RXN0
PCIE_TXP0
PCIE_TXN0
DDRLDO
AVDD33_PCIE
AVDD12_PCIE
AVDD33_DDRLDO
AVSS33_SMPS_2
AVSS33_SMPS_1
PCIE_IO_VSS
om TI
c.c N
104 102 100 98 96 94 92
ele IDE
103 101 99 97 95 93 91
PCIE PMU
90 LXBK_2
PMU 89 LXBK_1
88 AVDD33_SMPS_2
87 AVDD33_SMPS_1
86 SOC_IO_V33D_2
85 WLED_N
ink F
84 EPHY_LED0_N_JTDO
83 EPHY_LED1_N_JTDI
DIG 82 EPHY_LED2_N_JTMS
z-l ON
81 EPHY_LED3_N_JTCLK
80 EPHY_LED4_N_JTRST_N
79 DDR_IO_1V8D_4
78 DDR_IO_1V8D_3
77 DDR_IO_VREF_3
76 DDR_IO_VREF_2
C
75 SOC_CO_V12D_7
74 SOC_CO_V12D_6
DDR 73 DDR_IO_VREF_1
72 SOC_CO_V12D_5
71 SOC_CO_V12D_4
ng EK
70 NC5
69 NC4
68 NC3
67 DDR_IO_1V8D_2
66 DDR_IO_1V8D_1
65 NC2
.ya AT
64 NC1
@
63 DDR_IO_VSS_3
62 DDR_IO_VSS_2
61 DDR_IO_VSS_1
USB
fan DI
48 50 52 54 56 58
47 49 51 53 55 57 59 60
AVDD33_TX_P1234_2
SOC_CO_V12D_2
SOC_CO_V12D_3
AVDD33_USB
MDI_RN_P3
MDI_RN_P4
MDI_TN_P3
MDI_TN_P4
MDI_RP_P3
MDI_RP_P4
MDI_TP_P4
USB_VRT
USB_DM
USB_DP
E
M
N
US AL
EO
2.2.3 Pin Description
Pins Name Type Driv. Description
RF
om TI
2 WF0_RFION_1 A WF0 main path RF I/O
3 WF0_RFION_2
4 WF0_RFIOP_1 A WF0 main path RF I/O
c.c N
5 WF0_RFIOP_2
8 NC
ele IDE
9 NC
10 NC
11 NC
7 NC
1 WF0_LNA_EXT A WF0 aux. path LNA input
ink F
116 XTALIN I Crystal oscillator input
118 CLKOUTP O XO reference clock output
z-l ON
114 AVDD33_XTAL P 3.3V XTAL Power Supply Pin
115 AVS33_XTAL_1 G 3.3V XTAL Ground Pin
117 AVS33_XTAL_2
6 AVDD33_WF0_TX P 3.3V RF Channel 0 Suppoly Power
C
UART0 Lite
28 TXD0 O, IPD 4 mA UART0 Lite TXD
29 RXD0 I UART0 Lite RXD
fan DI
UART1 Lite
111 TXD1 O, IPU 4 mA UART1 Lite TXD
112 RXD1 I UART1 Lite RXD
E
I2S
14 I2S_SDI I/O 4 mA I2S data input
M
N
US AL
EO
Pins Name Type Driv. Description
18 I2C_SCLK I/O 4 mA I2C Clock
SPI
om TI
24 SPI_MISO I/O 4 mA SPI Master input/Slave output
25 SPI_MOSI I/O, IPD 4 mA SPI Master output/Slave input
22 SPI_CLK O, IPU 4 mA SPI clock
c.c N
26 SPI_CS0 O 4 mA SPI chip select0
22 SPI_CS1 O, IPD 4 mA SPI chip select1
ele IDE
GPIO
27 GPIO0 I/O, IPD 4 mA General Purpose I/O
5-Port EPHY
84 EPHY_LED0 _N_JTDO I/O 4 mA 10/100 PHY Port #0 activity LED, JTAG_TDO
ink F
83 EPHY_LED1 _N_JTDI I/O 4 mA 10/100 PHY Port #1 activity LED, JTAG_TDI
82 EPHY_LED2 _N_JTMS I/O 4 mA 10/100 PHY Port #2 activity LED, JTAG_TMS
z-l ON
81 EPHY_LED3 _N_JTCLK I/O 4 mA 10/100 PHY Port #3 activity LED, JTAG_CLK
80 EPHY_LED4 I/O, 4 mA 10/100 PHY Port #4 activity LED, JTAG_TRST_N
_N_JTRST_N
35 EPHY_VRT A Connect to an external resistor to provide accurate bias
C
current
31 MDI_RP_P0 A 10/100 PHY Port #0 RXP
32 MDI_RN_P0 A 10/100 PHY Port #0 RXN
ng EK
N
US AL
EO
Pins Name Type Driv. Description
54 MDI_TN_P4 A General purpose IO (SD-XC, eMMC…etc)
30 AVDD33_TX_P0 P 3.3V Supply Power for P0
om TI
36 AVDD33_COM P 3.3V Supply Power for EPHY COM
38 AVDD33_TX_P1234_1 P 3.3V Supply Power for P1 ~ P4
50 AVDD33_TX_P1234_2
c.c N
Misc.
106 REF_CLKO O, IPD 4 mA Reference Clock Ouptut
ele IDE
108 PORST_N I Power on reset
107 WDT_RST_N O 4 mA Watchdog Reset
USB PHY
58 AVDD33_USB P 3.3 V USB PHY analog power supply
57 USB _VRT A Connect to an external 5.1 kΩ resistor for band-gap
ink F
reference circuit
z-l ON
60 USB_DM I/O USB Port0 data pin Data-
59 USB _DP I/O USB Port0 data pin Data+
PCIe PHY
105 PERST_N O, IPD 4mA PCIe device reset
C
N
US AL
EO
Pins Name Type Driv. Description
21 SOC_IO_V33D_1 P 3.3 V digital I/O power supply
86 SOC_IO_V33D_2
om TI
110 SOC_IO_V33D_3
20 SOC_CO _V12D_1 P 1.2 V digital core power supply
55 SOC_CO _V12D_2
56 SOC_CO _V12D_3
c.c N
71 SOC_CO _V12D_4
72 SOC_CO _V12D_5
ele IDE
74 SOC_CO _V12D_6
75 SOC_CO _V12D_7
109 SOC_CO _V12D_8
EPAD GND G Ground pin
G : Ground
NC : Not connected
ng EK
Programmer’s Guide. Unless specified explicitly, all the GPIO pins are in input mode after reset.
@
N
US AL
EO
I/O Pad Group Normal Mode GPIO Mode
PERST PERST_N GPIO#36
WLED_KN WLED_N (7688KN) GPIO#35
om TI
P0_LED_KN EPHY_LED0_N_JTDO (7688KN) GPIO#34
P1_LED_KN EPHY_LED1_N_JTDI (7688KN) GPIO#33
P2_LED_KN EPHY_LED2_N_JTMS (7688KN) GPIO#32
c.c N
P3_LED_KN EPHY_LED3_N_JTCLK (7688KN) GPIO#31
P4_LED_KN EPHY_LED4_N_JTRST_N (7688KN) GPIO#30
ele IDE
SD / eMMC MDI_TN_P4 GPIO#29
MDI_TP_P4 GPIO#28
MDI_RN_P4 GPIO#27
MDI_RP_P4 GPIO#26
ink F
MDI_RN_P3 GPIO#25
MDI_RP_P3 GPIO#24
z-l ON
MDI_TN_P3 GPIO#23
MDI_TP_P3 GPIO#22
UART2 / eMMC MDI_TN_P2 GPIO#21
MDI_TP_P2 GPIO#20
C
UART_TXD0 GPIO#12
GPIO GPIO0 GPIO#11
SPI SPI_CS0 GPIO#10
fan DI
SPI_MISO GPIO#9
SPI_MOSI GPIO#8
SPI_CLK GPIO#7
E
I2S_SDI GPO#0
MediaTek © 2014 MediaTek Inc. Page 25 of 52
Confidential
FO
N
US AL
EO
2.3.2 UART1 pin share scheme
Controlled by the UART1_MODE register.
om TI
Pin Name 2’b00 2’b01 2’b10 2’b11
UART-Lite #1 GPIO PWM TRX_SW
UART1_RXD UART1_RXD GPIO#46 PWM_CH1
c.c N
UART1_TXD UART1_TXD GPIO#45 PWM_CH0
ele IDE
2.3.3 MT7688AN EPHY LED pin share scheme
Controlled by the P#_LED_AN_MODE registers
Pin Name Bootstrapping Bootstrapping
(DBG_JTAG_MODE=1) (DBG_JTAG_MODE=0)
P4_LED_AN_MODE P4_LED_AN_MODE
ink F
=2’b00 =2’b01
z-l ON
EPHY_LED4_N_JTRST_N JTAG_RST_N EPHY_LED4_N GPIO#39
P3_LED_AN_MODE P3_LED_AN_MODE
=2’b00 =2’b01
EPHY_LED3_N_JTCLK JTAG_CLK EPHY_LED3_N GPIO#40
P2_LED_AN_MODE P2_LED_AN_MODE
C
=2’b00 =2’b01
EPHY_LED2_N_JTMS JTAG_TMS EPHY_LED2_N GPIO#41
ng EK
P1_LED_AN_MODE P1_LED_AN_MODE
=2’b00 =2’b01
EPHY_LED1_N_JTDI JTAG_TDI EPHY_LED1_N GPIO#42
P0_LED_AN_MODE P0_LED_AN_MODE
=2’b00 =2’b01
.ya AT
@
N
US AL
EO
Pin Name Bootstrapping Bootstrapping
(DBG_JTAG_MODE=1) (DBG_JTAG_MODE=0)
P4_LED_KN_MODE P4_LED_KN_MODE
om TI
=2’b00 =2’b01
EPHY_LED4_N_JTRST_N JTAG_RST_N EPHY_LED4_N GPIO#30
P3_LED_KN_MODE P3_LED_KN_MODE
c.c N
=2’b00 =2’b01
EPHY_LED3_N_JTCLK JTAG_CLK EPHY_LED3_N GPIO#31
ele IDE
P2_LED_KN_MODE P2_LED_KN_MODE
=2’b00 =2’b01
EPHY_LED2_N_JTMS JTAG_TMS EPHY_LED2_N GPIO#32
P1_LED_KN_MODE P1_LED_KN_MODE
=2’b00 =2’b01
ink F
EPHY_LED1_N_JTDI JTAG_TDI EPHY_LED1_N GPIO#33
P0_LED_KN_MODE P0_LED_KN_MODE
z-l ON
=2’b00 =2’b01
EPHY_LED0_N_JTDO JTAG_TDO EPHY_LED0_N GPIO#34
N
US AL
EO
2.3.10 UART0 pin share scheme
Controlled by the UART0 _MODE register.
Pin Name 1’b0 1’b1
om TI
UART_TXD0 UART_TXD0 GPIO#12
UART_TXD0 UART_RXD0 GPIO#13
c.c N
2.3.11 GPIO0 pin share scheme
ele IDE
Controlled by GPIO_MODE register.
Pin Name 2’b00 2’b01 2’b10 2’b11
GPIO0 GPIO#11 GPIO#11 REF_CLKO PERST_N
N
US AL
EO
2.3.16 SD pin share scheme
Controlled by the EPHY_APGIO_AIO_EN[4:1] and SD_MODE registers
om TI
EPHY_APGIO_AIO_EN[4:1] EPHY_APGIO_AIO_EN[4:1]
=4’b0000 =4’b1111
Pin Name SD_MODE SD_MODE
c.c N
=2’b00 =2’b01
MDI_TP_P3 MDI_TP_P3 SD_WP GPIO#22
ele IDE
MDI_TN_P3 MDI_TN_P3 SD_CD GPIO#23
MDI_RP_P3 MDI_RP_P3 SD_D1 GPIO#24
MDI_RN_P3 MDI_RN_P3 SD_D0 GPIO#25
MDI_RP_P4 MDI_RP_P4 SD_CLK GPIO#26
MDI_TN_P4 MDI_TN_P4 SD_D2 GPIO#27
ink F
MDI_RN_P4 MDI_RN_P4 SD_CMD GPIO#28
z-l ON
MDI_TP_P4 MDI_TP_P4 SD_D3 GPIO#29
EPHY_APGIO_AIO_EN[4:1] EPHY_APGIO_AIO_EN[4:1]
=4’b0000 =4’b1111
Pin Name SD_MODE SD_MODE
ng EK
=2’b00 =2’b01
MDI_TP_P3 MDI_TP_P3 eMMC_WP GPIO#22
MDI_TN_P3 MDI_TN_P3 eMMC_CD GPIO#23
MDI_RP_P3 MDI_RP_P3 eMMC_D1 GPIO#24
.ya AT
@
4’b0000 4’b1111
Pin Name 2’b00 2’b01 2’b10 2’b11
MDI_TP_P2 MDI_TP_P2 UART_TXD2 GPIO#20 PWM_CH2 eMMC_D5
MDI_TN_P2 MDI_TN_P2 UART_RXD2 GPIO#21 PWM_CH3 eMMC_D4
R
N
US AL
EO
2.3.19 PWM_CH1 pin share scheme
Controlled by the EPHY_APGIO_AIO_EN[4:1] and PWM1_MODE registers
4’b0000 4’b1111
om TI
Pin Name 2’b00 2’b01 2’b10 2’b11
MDI_RN_P2 MDI_RN_P2 PWM_CH1 GPIO#19 eMMC_D6
c.c N
Controlled by the EPHY_APGIO_AIO_EN[4:1] and PWM0_MODE registers
4’b0000 4’b1111
ele IDE
Pin Name 2’b00 2’b01 2’b10 2’b11
MDI_RP_P2 MDI_RP_P2 PWM_CH0 GPIO#18 eMMC_D7
ink F
2.3.21 SPIS pin share scheme
Controlled by the EPHY_APGIO_AIO_EN[4:1] and SPIS_MODE registers
z-l ON
4’b0000 4’b1111
Pin Name 2’b00 2’b01 2’b10 2’b11
MDI_TP_P1 MDI_TP_P1 SPIS_CS GPIO#14 PWM_CH0
MDI_TN_P1 MDI_TN_P1 SPIS_CLK GPIO#15 PWM_CH1
C
DATA signal sent from the PCM host to the external codec.
@
The clock signal can be generated by the PCM host (Output direction), or
provided by an external clock (input direction). The clock frequency should match
the slot configuration of the PCM host.
e.g.
E
N
US AL
EO
Pin Share Name I/O Pin Share Function description
PWM_CH0 O Pulse Width Modulation Channle 0
PWM_CH1 O Pulse Width Modulation Channle 1
om TI
PWM_CH2 O Pulse Width Modulation Channle 2
PWM_CH3 O Pulse Width Modulation Channle 3
c.c N
2.4 Bootstrapping Pins Description
ele IDE
Pin Name Boot Strapping Signal Description
Name
UART_TXD1 DBG_JTAG_MODE 0: JTAG_MODE
1: EPHY_LED (default)
PERST_N XTAL_FREQ_SEL 0: 25 MHz DIP
ink F
1: 40 MHz SMD
I2S_SDO DRAM_TYPE 1: DDR1
z-l ON
0: DDR2
[note] This pin is valid for MT7688AN only. It needs to be pull-low for
7688KN which only supports DDR1.
{SPI_MOSI CHIP_MODE[2:0] A vector to set chip function/test/debug modes.
SPI_CLK,
C
N
US AL
EO
3. Maximum Ratings and Operating Conditions
om TI
I/O supply voltage 3.63 V
Input, Output, or I/O Voltage GND -0.3 V to Vcc +0.3 V
c.c N
Table 3-1 Absolute Maximum Ratings
ele IDE
3.2 Maximum Temperatures
MT7688KN:
Thermal Resistance θJA (°C /W) for JEDEC 2L system PCB 26.1°C/W
Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB 17.72°C/W
fan DI
MT7688AN:
M
Thermal Resistance θJA (°C /W) for JEDEC 2L system PCB 27.01°C/W
Thermal Resistance θJA (°C /W) for JEDEC 4L system PCB 18.15°C/W
Thermal Resistance θJC (°C /W) for JEDEC 6.9°C/W
Thermal Resistance ψJt (°C /W) for JEDEC 2L system PCB 2.41 °C/W
Thermal Resistance ψJt (°C /W) for JEDEC 4L system PCB 1.51 °C/W
R
N
US AL
EO
Table 3-4 Thermal Characteristics
om TI
The calculated shelf life in a sealed bag is 12 months if stored between 0 °C and 40 °C at less than 90% relative
humidity (RH). After the bag is opened, devices that are subjected to solder reflow or other high temperature
processes must be handled in the following manner:
c.c N
Mounted within 168 hours of factory conditions, i.e. < 30 °C at 60% RH.
Storage humidity needs to maintained at < 10% RH.
Baking is necessary if the customer exposes the component to air for over 168 hrs, baking conditions: 125
ele IDE
°C for 8 hrs.
Vdd=2.5V Typ
Min Max
M
(DDR2)
Vdd 2.375 2.5 2.625
VIH VREF+0.15 Vdd25+0.3
VIL -0.3 VREF-0.15
VOH 0.8*Vdd25
R
VOL 0.2*Vdd25
MediaTek © 2014 MediaTek Inc. Page 33 of 52
Confidential
FO
N
US AL
EO
IOL
IOH
om TI
Vdd=1.8V Typ
Min Max
(DDR2)
c.c N
Vdd 1.71 1.8 1.89
VIH VREF+0.125 Vdd18+0.3
ele IDE
VIL -0.3 VREF-0.125
VOH 1.42
VOL 0.28
IOL
ink F
IOH
IOL
IOH
N
US AL
EO
3.8.1 DDR2 SDRAM Interface
The DDR2 SDRAM interface complies with 200 MHz timing requirements for standard DDR2 SDRAM. The
interface drivers are SSTL_18 drivers matching the EIA/JEDEC standard JESD8-15A.
om TI
tCH tCL
CLK
CLK#
c.c N
tIS tIH
MCS_N
ele IDE
tIS tIH
MRAS_N
tIS tIH
MCAS_N
ink F
tIS tIH
MWE_N
z-l ON
tIS tIH
MA0 to MA13
tIS tIH
MBA0, MBA1
C
MDQS
tDS tDH
.ya AT
@
MD D1 D2 D3 D4
tDS tDH
MDQM
fan DI
tRPRE tRPST
MDQS
M
MD D1 D2 D3
N
US AL
EO
Symbol Description Min Max Unit Remark
om TI
tCK(avg) Clock cycle time 5 - ns
tAC DQ output access time from SDRAM CLK -0.6 0.6 ns
tDQSCK DQS output access time from SDRAM CLK -0.5 0.5 ns
c.c N
tCH SDRAM CLK high pulse width 0.48 0.52 tCK(avg)
tCL SDRAM CLK low pulse width 0.48 0.52 tCK(avg)
ele IDE
tHP SDRAM CLK half period Min(tCH,tCL) - ns
tIS Address and control input setup time 0.75 - ns
tIH Address and control input hold time 0.75 - ns
tDQSQ Data skew of DQS and associated DQ - 0.4 ns
tQH DQ/DQS output hold time from DQS tHP-0.5 - ns
ink F
tRPRE DQS read preamble 0.9 1.1 tCK
z-l ON
tRPST DQS read postamble 0.4 0.6 tCK
tDQSS DQS rising edge to CK rising edge -0.25 0.25 tCK
tDQSH DQS input-high pulse width 0.35 - tCK
tDQSL DQS input-low pulse width 0.35 - tCK
C
tDSS DQS falling edge to SDRAM CLK setup time 0.2 - tCK
tDSH DQS falling edge hold time from SDRAM CLK 0.2 - tCK
tWPRE DQS write preamble 0.35 - tCK
ng EK
NOTE: Depends on slew rate of DQS and DQ/DQM for single ended DQS.
fan DI
E
R M
N
US AL
EO
3.8.2 SPI Interface
om TI
SPI_CLK
SPI_CS
c.c N
SPI_MOSI
ele IDE
t_SPI_OVLD (max) T_SPI_OVLD (min)
Read operation (Driven by clock rising edge (slave-device) and latched by clock rising edge)
ink F
SPI_CLK
SPI_CS
z-l ON
SPI_MISO
t_SPI_IS t_SPI_IH
C
N
US AL
EO
2
3.8.3 I S Interface
Transmitter
om TI
SCK
c.c N
WS & SD
ele IDE
t_I2S_OVLD (min) t_I2S_OVLD (max)
Receiver
ink F
SCK
z-l ON
WS & SD
t_I2S_IS t_I2S_IH
C
N
US AL
EO
3.8.4 PCM Interface
PCMCLK
om TI
DTX
c.c N
ele IDE
t_PCM_OVLD
PCMCLK
ink F
DRX &
FSYNC
z-l ON
t_PCM_IS t_PCM_IH
C
fall
@
t_PCM_OVLD PCM_CLK rise to PCM output valid 10.0 35.0 ns output load: 5 pF
N
US AL
EO
3.8.5 Power On Sequence
om TI
c.c N
ele IDE
ink F
z-l ON
N
US AL
EO
3.9 Package Physical Dimensions
om TI
3.9.1.1 Top View
c.c N
ele IDE
ink F
z-l ON
C
ng EK
N
US AL
EO
Figure 3-10 “B” Expanded
om TI
c.c N
ele IDE
3.9.1.5 Package Diagram Key
3.9.1.4 Bottom View
ink F
z-l ON
C
N
US AL
EO
3.9.2 DR-QFN (12 mm x 12 mm) 156 pins
om TI
c.c N
ele IDE
ink F
z-l ON
C
ng EK
N
US AL
EO
3.9.2.4 Bottom View
om TI
c.c N
ele IDE
ink F
z-l ON
C
N
US AL
EO
3.9.2.5 Package Diagram Key
om TI
c.c N
ele IDE
ink F
z-l ON
C
ng EK
.ya AT
@
fan DI
N
US AL
EO
MEDIATEK
om TI
MT7688AN
YYWW-XXXX
LLLLLLLLL
c.c N
ele IDE
YYWW: Date code
LLLLLLLLL : Lot number
“.” : Pin #1 dot
Figure 3-16 MT7688AN top marking
ink F
z-l ON
MEDIATEK
MT7688KN
YYWW-XXXX
C
LLLLLLLLL
ng EK
N
US AL
EO
3.9.4 Reflow profile guideline
om TI
c.c N
ele IDE
ink F
Figure 3-18 Reflow profile for MT7688
z-l ON
Notes;
1. Reflow profile guideline is designed for SnAgCulead-free solder paste.
2. Reflow temperature is defined at the solder ball of package/or the lead of package.
C
3. MTK would recommend customer following the solder paste vendor’s guideline to design a profile
appropriate your line and products.
4. Appropriate N2 atmosphere is recommended since it would widen the process window and mitigate the risk
ng EK
LY
Confidential B
N
4. Abbreviations
US AL
EO
Abbrev. Description Abbrev. Description
AC Access Category CPU Central Processing Unit
ACK Acknowledge/ Acknowledgement CRC Cyclic Redundancy Check
om TI
ACPR Adjacent Channel Power Ratio CSR Control Status Register
AD/DA Analog to Digital/Digital to Analog CTS Clear to Send
converter CW Contention Window
c.c N
ADC Analog-to-Digital Converter CWmax Maximum Contention Window
AES Advanced Encryption Standard CWmin Minimum Contention Window
ele IDE
AGC Auto Gain Control DAC Digital-To-Analog Converter
AIFS Arbitration Inter-Frame Space DCF Distributed Coordination Function
AIFSN Arbitration Inter-Frame Spacing DDONE DMA Done
Number
DDR Double Data Rate
ALC Asynchronous Layered Coding
DFT Discrete Fourier Transform
ink F
A-MPDU Aggregate MAC Protocol Data Unit
DIFS DCF Inter-Frame Space
A-MSDU Aggregation of MAC Service Data
z-l ON
DMA Direct Memory Access
Units
DSP Digital Signal Processor
AP Access Point
DW DWORD
ASIC Application-Specific Integrated Circuit
EAP Expert Antenna Processor
ASME American Society of Mechanical
C
LY
Confidential B
N
Abbrev. Description Abbrev. Description
HCCA HCF Controlled Channel Access NAV Network Allocation Vector
US AL
EO
HCF Hybrid Coordination Function NAS Network-Attached Server
HT High Throughput NAT Network Address Translation
HTC High Throughput Control NDP Null Data Packet
om TI
ICV Integrity Check Value NVM Non-Volatile Memory
IFS Inter-Frame Space ODT On-die Termination
iNIC Intelligent Network Interface Card Oen Output Enable
c.c N
IV Initialization Vector OFDM Orthogonal Frequency-Division
2
IC Inter-Integrated Circuit Multiplexing
ele IDE
2
IS Integrated Inter-Chip Sound OSC Open Sound Control
I/O Input/Output PA Power Amplifier
IPI Idle Power Indicator PAPE Provider Authentication Policy
Extension
IQ In phase/Quadrature phase
PBC Push Button Configuration
JEDEC Joint Electron Devices Engineering
ink F
Council PBF Packet Buffer
PCB Printed Circuit Board
z-l ON
JTAG Joint Test Action Group
kbps kilo (1000) bits per second PCF Point Coordination Function
KB Kilo (1024) Bytes PCM Pulse-Code Modulation
LDO Low-Dropout Regulator PHY Physical Layer
PIFS PCF Interframe Space
C
MCS Modulation and Coding Scheme PSDU Physical layer Service Data Unit
MDC Management Data Clock PSI Power supply Strength Indication
MDIO Management Data Input/Output PSM Power Save Mode
PTN Packet Transport Network
fan DI
MEM Memory
MFB MCS Feedback QoS Quality of Service
MFS MFB Sequence RDG Reverse Direction Grant
E
MLNA Monolithic Low Noise Amplifier RGMII Reduced Gigabit Media Independent
Interface
MM Mixed Mode
RH Relative Humidity
MOSFET Metal Oxide Semiconductor Field
Effect Transistor RoHS Restriction on Hazardous Substances
MPDU MAC Protocol Data Units ROM Read-Only Memory
R
LY
Confidential B
N
Abbrev. Description Abbrev. Description
RSSI Received Signal Strength Indication TSSI Transmit Signal Strength Indication
US AL
EO
(Indicator) Tx Transmit
RTS Request to Send TxBF Transmit Beamforming
RvMII Reverse Media Independent Interface TXD Transmitted Data
Rx Receive
om TI
TXDAC Transmit Digital-Analog Converter
RXD Received Data TXINFO Transmit Information
RXINFO Receive Information TXOP Opportunity to Transmit
c.c N
RXWI Receive Wireless Information TXWI Tx Wireless Information
S Stream UART Universal Asynchronous Rx/ Tx
ele IDE
SDXC Secure Digital eXtended Capacity USB Universal Serial Bus
SDIO Secure Digital Input Output UTIF Universal Test Interface
SDRAM Synchronous Dynamic Random Access VGA Variable Gain Amplifier
Memory
VCO Voltage Controlled Amplifier
SEC Security
VIH High Level Input Voltage
ink F
SGI Short Guard Interval
VIL Low Level Input Voltage
SIFS Short Inter-Frame Space
z-l ON
VoIP Voice over IP
SoC System-on-a-Chip
WCID Wireless Client Identification
SPI Serial Peripheral Interface
WEP Wired Equivalent
SRAM Static Random Access Memory
WI Wireless Information
SSCG Spread Spectrum Clock Generator
C
TA Transmitter Address
WPDMA Wireless Polarization Division Multiple
TBTT Target Beacon Transmission Time Access
TDLS Tunnel Direct Link Setup WS Word Select
TKIP Temporal Key Integrity Protocol
.ya AT
@
N
US AL
EO
5. Revision History
om TI
Rev Date Description
1.0 2012/07/09 Initial Release
1.1 2012/07/18 Update SPI_WP/SPI_HOLD GPO table
c.c N
1.2 2012/08/20 Fix DRQFN internal pad size typo
1.3 2012/09/12 Add IR reflow guideline
ele IDE
ink F
z-l ON
C
ng EK
.ya AT
@
fan DI
E
M
This product is not designed for use in medical and/or life support applications. Do not use this product in these
R
types of equipment or applications. This document is subject to change without notice and Ralink assumes no
MediaTek © 2014 MediaTek Inc. Page 51 of 52
Confidential
FO
N
US AL
EO
responsibility for any inaccuracies that may be contained in this document. Ralink reserves the right to make
changes in its products to improve function, performance, reliability, and to attempt to supply the best product
possible.
om TI
c.c N
ele IDE
ink F
z-l ON
C
ng EK
.ya AT
@
fan DI
E
R M