Synchronous-Rectified Buck MOSFET Drivers: General Description Features
Synchronous-Rectified Buck MOSFET Drivers: General Description Features
BOOT 8 UGATE
PWM 2 7 PHASE
NC 3 6 PGND
VCC 4 5 LGATE
SOP-8
L1
2.2uH
ATX_12V VIN
Typical Application Circuit
C2
R2 1uF
D1 1
1
R1 BOOT R3
10 8 2.2
ATX_12V 4 VCC
UGATE Q1
C1
1uF L2
RT9619/A
7 1uH
3 PHASE VCORE
+
+
+
+
NC
R4 R5
2 5 0 2.2 C4 C5 C6 C7
PWM PWM LGATE Q2 2200uF 2200uF 10uF 10uF
C3
PGND 3.3nF
6
Internal
5V
POR
R
BOOT
Tri-State
PWM Detect Shoot-Through
UGATE
Protection
R
VCC
Shoot-Through
Protection LGATE
PGND
Timing Diagram
PWM
tpdlLGATE
LGATE 90%
tpdlUGATE
2V 2V
90%
2V 2V
UGATE
tpdhUGATE tpdhLGATE
Electrical Characteristics
(Recommended Operating Conditions, TA = 25°C unless otherwise specified)
To be continued
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
PWM
(5V/Div)
PWM
(5V/Div)
UGATE UGATE
(20V/Div) (20V/Div)
LGATE LGATE
(10V/Div) (10V/Div)
PHASE PHASE
(10V/Div) (10V/Div)
No Load No Load
UGATE UGATE
PHASE PHASE
(5V/Div) (5V/Div)
LGATE LGATE
UGATE UGATE
PHASE PHASE
(5V/Div) (5V/Div)
LGATE LGATE
0.05
UGATE
0.04
Current (A)
PHASE
LGATE
0.03
0.02
(5V/Div)
0.01
0.00
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Time (20ns/Div)
Voltage (V)
d1 s1 L
around 2.4V by the internal divider and provide the PWM VIN VOUT
controller with a recognizable level. Cgd1 Cgs1
GND
Non-overlap Control
Vg1
To prevent the overlap of the gate drives during the UGATE VPHASE +12V
turn low and the LGATE turn high, the non-overlap circuit
monitors the voltages at the PHASE node and high side
gate drive (UGATE-PHASE). When the PWM input signal t
800
L1 D1 R1
700 12V
VIN C4 10
600 12V 1.2uH
+
C2 1 4 1uF
C1 1uF
BOOT VCC
500 1000uF CB
CU=CL=2nF 1uF 2
400 Q1 8 VIN PWM
RT9619/A
UGATE
L2
300 VCORE 7
CU=CL=1nF PHASE
2uH PHB83N03LT
200
+
C3
1500uF Q2 PHB95N03LT 5 6
100 LGATE PGND
0
0 200 400 600 800 1000
Frequency (kHz) Figure 5. Two-Phase Synchronous Buck Converter Circuit
Figure 4. Power Dissipation vs. Frequency
H
A
J B
C
I
D
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specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.