1.

In memory-mapped I/O ____________

a) The I/O devices and the memory share the same address space
b) The I/O devices have a separate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation
View Answer

Answer: a
Explanation: Its the different modes of accessing the i/o devices.
2. The usual BUS structure used to connect the I/O devices is ___________
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure
View Answer

Answer: c
Explanation: BUS is a collection of address, control and data lines used to connect
the various devices of the computer.
3. In intel�s IA-32 architecture there is a separate 16 bit address space for the
I/O devices.
a) False
b) True
View Answer

Answer: b
Explanation: This type of access is called as I/O mapped devices.
4. The advantage of I/O mapped devices to memory mapped is ___________
a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a bigger buffer space
c) The devices have to deal with fewer address lines
d) No advantage as such
View Answer

Answer: c
Explanation: Since the I/O mapped devices have a separate address space the address
lines are limited by the amount of the space allocated.
5. The system is notified of a read or write operation by ___________
a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) Sending a special signal along the BUS
View Answer

Answer: d
Explanation: It is necessary for the processor to send a signal intimating the
request as either read or write.
6. To overcome the lag in the operating speeds of the I/O device and the processor
we use ___________
a) BUffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions
View Answer

Answer: b
Explanation: The processor operating is much faster than that of the I/O devices,
so by using the status flags the processor need not wait till the I/O operation is
done. It can continue with its work until the status flag is set.
7. The method of accessing the I/O devices by repeatedly checking the status flags
is ___________
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None of the mentioned
View Answer

Answer: a
Explanation: In this method, the processor constantly checks the status flags, and
when it finds that the flag is set it performs the appropriate operation.
8. The method of synchronising the processor with the I/O device in which the
device sends a signal when it is ready is?
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA
View Answer

Answer: c
Explanation: This is a method of accessing the I/O devices which gives the complete
power to the devices, enabling them to intimate the processor when they�re ready
for transfer.
9. The method which offers higher speeds of I/O transfers is ___________
a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA
View Answer

Answer: d
Explanation: In DMA the I/O devices are directly allowed to interact with the
memory without the intervention of the processor and the transfers take place in
the form of blocks increasing the speed of operation.
10. The process wherein the processor constantly checks the status flags is called
as ___________
a) Polling
b) Inspection
c) Reviewing
d) Echoing
View Answer

Answer: a
Explanation: None

� PrevNext �
This set of Computer Organization and Architecture Multiple Choice Questions &
Answers (MCQs) focuses on �Interrupts � 1�.

1. The interrupt-request line is a part of the ___________

a) Data line
b) Control line
c) Address line
d) None of the mentioned
View Answer

Answer: b
Explanation: The Interrupt-request line is a control line along which the device is
allowed to send the interrupt signal.
2. The return address from the interrupt-service routine is stored on the
___________
a) System heap
b) Processor register
c) Processor stack
d) Memory
View Answer

Answer: c
Explanation: The Processor after servicing the interrupts as to load the address of
the previous process and this address is stored in the stack.
3. The signal sent to the device from the processor to the device after receiving
an interrupt is ___________
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal
View Answer

Answer: a
Explanation: The Processor upon receiving the interrupt should let the device know
that its request is received.
4. When the process is returned after an interrupt service ______ should be loaded
again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
a) i, iv
b) ii, iii and iv
c) iii, iv
d) i, ii
View Answer

Answer: d
Explanation: None.
5. The time between the receiver of an interrupt and its service is ______
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time
View Answer

Answer: b
Explanation: The delay in servicing of an interrupt happens due to the time is
taken for contact switch to take place.
6. Interrupts form an important part of _____ systems.
a) Batch processing
b) Multitasking
c) Real-time processing
d) Multi-user
View Answer

Answer: c
Explanation: This forms an important part of the Real time system since if a
process arrives with greater priority then it raises an interrupt and the other
process is stopped and the interrupt will be serviced.
7. A single Interrupt line can be used to service n different devices.
a) True
b) False
View Answer

Answer: a
Explanation: None.
8. ______ type circuits are generally used for interrupt service lines.
i) open-collector
ii) open-drain
iii) XOR
iv) XNOR
a) i, ii
b) ii
c) ii, iii
d) ii, iv
View Answer

Answer: a
Explanation: None.
9. The resistor which is attached to the service line is called _____
a) Push-down resistor
b) Pull-up resistor
c) Break down resistor
d) Line resistor
View Answer

Answer: b
Explanation: This resistor is used to pull up the voltage of the interrupt service
line.
10. An interrupt that can be temporarily ignored is ___________
a) Vectored interrupt
b) Non-maskable interrupt
c) Maskable interrupt
d) High priority interrupt
View Answer

Answer: c
Explanation: The maskable interrupts are usually low priority interrupts which can
be ignored if a higher priority process is being executed.
11. The 8085 microprocessor responds to the presence of an interrupt ___________
a) As soon as the trap pin becomes �LOW�
b) By checking the trap pin for �high� status at the end of each instruction fetch
c) By checking the trap pin for �high� status at the end of execution of each
instruction
d) By checking the trap pin for �high� status at regular intervals
View Answer

Answer: c
Explanation: The 8085 microprocessor are designed to complete the execution of the
current instruction and then to service the interrupts.
12. CPU as two modes privileged and non-privileged. In order to change the mode
from privileged to non-privileged.
a) A hardware interrupt is needed
b) A software interrupt is needed
c) Either hardware or software interrupt is needed
d) A non-privileged instruction (which does not generate an interrupt)is needed
View Answer

Answer: b
Explanation: A software interrupt by some program which needs some CPU service, at
that time the two modes can be interchanged.
13. Which interrupt is unmaskable?
a) RST 5.5
b) RST 7.5
c) TRAP
d) Both RST 5.5 and 7.5
View Answer

Answer: c
Explanation: The trap is a non-maskable interrupt as it deals with the ongoing
process in the processor. The trap is initiated by the process being executed due
to lack of data required for its completion. Hence trap is unmaskable.
14. From amongst the following given scenarios determine the right one to justify
interrupt mode of data transfer.
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
a) i and ii
b) ii
c) i, ii and iv
d) iv
View Answer

Answer: d
Explanation: None.
15. How can the processor ignore other interrupts when it is servicing one
___________
a) By turning off the interrupt request line
b) By disabling the devices from sending the interrupts
c) BY using edge-triggered request lines
d) All of the mentioned
View Answer

Answer: d
Explanation: None.

cuses on �Interrupts � 2�.

1. When dealing with multiple devices interrupts, which mechanism is easy to

implement?
a) Polling method
b) Vectored interrupts
c) Interrupt nesting
d) None of the mentioned
View Answer

2. The interrupt servicing mechanism in which the requesting device identifies

itself to the processor to be serviced is ___________
a) Polling
b) Vectored interrupts
c) Interrupt nesting
d) Simultaneous requesting
View Answer

3. In vectored interrupts, how does the device identify itself to the processor?
a) By sending its device id
b) By sending the machine code for the interrupt service routine
c) By sending the starting address of the service routine
d) None of the mentioned
View Answer

Answer: c
Explanation: By sending the starting address of the routine the device ids the
routine required and thereby identifying itself.
4. The code sent by the device in vectored interrupt is _____ long.
a) upto 16 bits
b) upto 32 bits
c) upto 24 bits
d) 4-8 bits
View Answer

Answer: d
Explanation: None.
5. The starting address sent by the device in vectored interrupt is called as
__________
a) Location id
b) Interrupt vector
c) Service location
d) Service id
View Answer

Answer: b
Explanation: None.
6. The processor indicates to the devices that it is ready to receive interrupts
________
a) By enabling the interrupt request line
b) By enabling the IRQ bits
c) By activating the interrupt acknowledge line
d) None of the mentioned
View Answer

Answer: c
Explanation: When the processor activates the acknowledge line the devices send
their interrupts to the processor.
7. We describe a protocol of input device communication below:
i) Each device has a distinct address.
ii) The BUS controller scans each device in a sequence of increasing address value
to determine if the entity wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the
following.
a) Programmed mode of data transfer
b) DMA
c) Interrupt mode
d) Polling
View Answer

Answer: d
Explanation: In polling, the processor checks each of the devices if they wish to
perform data transfer and if they do it performs the particular operation.
8. Which one of the following is true with regard to a CPU having a single
interrupt request line and single interrupt grant line?
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is
possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not
possible.
iv) Both vectored and multiple interrupting devices are possible.
a) iii
b) i, iv
c) ii, iii
d) iii, iv
View Answer

Answer: a
Explanation: None.
9. Which table handle stores the addresses of the interrupt handling sub-routines?
a) Interrupt-vector table
b) Vector table
c) Symbol link table
d) None of the mentioned
View Answer

Answer: a
Explanation: None.
10. _________ method is used to establish priority by serially connecting all
devices that request an interrupt.
a) Vectored-interrupting
b) Daisy chain
c) Priority
d) Polling
View Answer

Answer: b
Explanation: In the Daisy chain mechanism, all the devices are connected using a
single request line and they�re serviced based on the interrupting device�s
priority.
11. In daisy chaining device 0 will pass the signal only if it has _______
a) Interrupt request
b) No interrupt request
c) Both No interrupt and Interrupt request
d) None of the mentioned
View Answer

Answer: b
Explanation: In daisy chaining since there is only one request line and only one
acknowledges line, the acknowledge signal passes from device to device until the
one with the interrupt is found.
12. ______ interrupt method uses register whose bits are set separately by
interrupt signal for each device.
a) Parallel priority interrupt
b) Serial priority interrupt
c) Daisy chaining
d) None of the mentioned
View Answer

Answer: a
Explanation: None.
13. ______________ register is used for the purpose of controlling the status of
each interrupt request in parallel priority interrupt.
a) Mass
b) Mark
c) Make
d) Mask
View Answer

Answer: d
Explanation: None.
14. The added output of the bits of the interrupt register and the mask register is
set as an input of ______________
a) Priority decoder
b) Priority encoder
c) Process id encoder
d) Multiplexer
View Answer

Answer: b
Explanation: In a parallel priority system, the priority of the device is obtained
by adding the contents of the interrupt register and the mask register.
15. Interrupts initiated by an instruction is called as _______
a) Internal
b) External
c) Hardware
d) Software
View Answer

Answer: b
Explanation: None.

1. If during the execution of an instruction an exception is raised then __________

a) The instruction is executed and the exception is handled
b) The instruction is halted and the exception is handled
c) The processor completes the execution and saves the data and then handle the
exception
d) None of the mentioned
View Answer

Answer: b
Explanation: Since the interrupt was raised during the execution of the
instruction, the instruction cannot be executed and the exception is served
immediately.
2. _____ is/are types of exceptions.
a) Trap
b) Interrupt
c) System calls
d) All of the mentioned
View Answer

Answer: d
Explanation: None.
3. The program used to find out errors is called __________
a) Debugger
b) Compiler
c) Assembler
d) Scanner
View Answer

Answer: a
Explanation: Debugger is a program used to detect and correct errors in the
program.
4. The two facilities provided by the debugger is __________
a) Trace points
b) Break points
c) Compile
d) Both Trace and Break points
View Answer

Answer: d
Explanation: The debugger provides us with the two facilities to improve the
checking of errors.
5. In trace mode of operation is ________
a) The program is interrupted after each detection
b) The program will not be stopped and the errors are sorted out after the complete
program is scanned
c) There is no effect on the program, i.e the program is executed without
rectification of errors
d) The program is halted only at specific points
View Answer

Answer: a
Explanation: In trace mode, the program is checked line by line and if errors are
detected then exceptions are raised right away.
6. What is the operation in Breakpoint mode?
a) The program is interrupted after each detection
b) The program will not be stopped and the errors are sorted out after the complete
program is scanned
c) There is no effect on the program, i.e the program is executed without
rectification of errors
d) The program is halted only at specific points
View Answer

Answer: d
Explanation: The Breakpoint mode of operation allows the program to be halted at
only specific locations.
7. What are the different modes of operation of a computer?
a) User and System mode
b) User and Supervisor mode
c) Supervisor and Trace mode
d) Supervisor, User and Trace mode
View Answer

Answer: b
Explanation: The user programs are in the user mode and the system crucial programs
are in the supervisor mode.
8. The instructions which can be run only supervisor mode are?
a) Non-privileged instructions
b) System instructions
c) Privileged instructions
d) Exception instructions
View Answer

Answer: c
Explanation: These instructions are those which can are crucial for the system�s
performance and hence cannot be adultered by user programs, so is run only in
supervisor mode.
9. A privilege exception is raised __________
a) When a process tries to change the mode of the system
b) When a process tries to change the priority level of the other processes
c) When a process tries to access the memory allocated to other users
d) All of the mentioned
View Answer
Answer: d
Explanation: None.
10. How is a privilege exception dealt with?
a) The program is halted and the system switches into supervisor mode and restarts
the program execution
b) The Program is stopped and removed from the queue
c) The system switches the mode and starts the execution of a new process
d) The system switches mode and runs the debugger
View Answer

Answer: a
Explanation: None

�Direct Memory Access�.

1. The DMA differs from the interrupt mode by __________

a) The involvement of the processor for the operation
b) The method of accessing the I/O devices
c) The amount of data transfer possible
d) None of the mentioned
View Answer

Answer: d
Explanation: DMA is an approach of performing data transfers in bulk between memory
and the external device without the intervention of the processor.
2. The DMA transfers are performed by a control circuit called as __________
a) Device interface
b) DMA controller
c) Data controller
d) Overlooker
View Answer

Answer: b
Explanation: The Controller performs the functions that would normally be carried
out by the processor.
3. In DMA transfers, the required signals and addresses are given by the __________
a) Processor
b) Device drivers
c) DMA controllers
d) The program itself
View Answer

Answer: c
Explanation: The DMA controller acts as a processor for DMA transfers and overlooks
the entire process.
4. After the completion of the DMA transfer, the processor is notified by
__________
a) Acknowledge signal
b) Interrupt signal
c) WMFC signal
d) None of the mentioned
View Answer

Answer: b
Explanation: The controller raises an interrupt signal to notify the processor that
the transfer was complete.
5. The DMA controller has _______ registers.
a) 4
b) 2
c) 3
d) 1
View Answer

Answer: c
Explanation: The Controller uses the registers to store the starting address, word
count and the status of the operation.
6. When the R/W bit of the status register of the DMA controller is set to 1.
a) Read operation is performed
b) Write operation is performed
c) Read & Write operation is performed
d) None of the mentioned
View Answer

Answer: a
Explanation: None.
7. The controller is connected to the ____
a) Processor BUS
b) System BUS
c) External BUS
d) None of the mentioned
View Answer

Answer: b
Explanation: The controller is directly connected to the system BUS to provide
faster transfer of data.
8. Can a single DMA controller perform operations on two different disks
simultaneously?
a) True
b) False
View Answer

Answer: a
Explanation: The DMA controller can perform operations on two different disks if
the appropriate details are known.
9. The technique whereby the DMA controller steals the access cycles of the
processor to operate is called __________
a) Fast conning
b) Memory Con
c) Cycle stealing
d) Memory stealing
View Answer

Answer: c
Explanation: The controller takes over the processor�s access cycles and performs
memory operations.
10. The technique where the controller is given complete access to main memory is
__________
a) Cycle stealing
b) Memory stealing
c) Memory Con
d) Burst mode
View Answer

Answer: d
Explanation: The controller is given full control of the memory access cycles and
can transfer blocks at a faster rate.
11. The controller uses _____ to help with the transfers when handling network
interfaces.
a) Input Buffer storage
b) Signal enhancers
c) Bridge circuits
d) All of the mentioned
View Answer

Answer: a
Explanation: The controller stores the data to transfer in the buffer and then
transfers it.
12. To overcome the conflict over the possession of the BUS we use ______
a) Optimizers
b) BUS arbitrators
c) Multiple BUS structure
d) None of the mentioned
View Answer

Answer: b
Explanation: The BUS arbitrator is used to overcome the contention over the BUS
possession.
13. The registers of the controller are ______
a) 64 bits
b) 24 bits
c) 32 bits
d) 16 bits
View Answer

Answer: c
Explanation: None.
14. When the process requests for a DMA transfer?
a) Then the process is temporarily suspended
b) The process continues execution
c) Another process gets executed
d) process is temporarily suspended & Another process gets executed
View Answer

Answer: d
Explanation: The process requesting the transfer is paused and the operation is
performed, meanwhile another process is run on the processor.
15. The DMA transfer is initiated by _____
a) Processor
b) The process being executed
c) I/O devices
d) OS
View Answer

Answer: c
Explanation: The transfer can only be initiated by an instruction of a program
being execut
ed.

1. To resolve the clash over the access of the system BUS we use ______
a) Multiple BUS
b) BUS arbitrator
c) Priority access
d) None of the mentioned
View Answer
Answer: b
Explanation: The BUS arbitrator is used to allow a device to access the BUS based
on certain parameters.
2. The device which is allowed to initiate data transfers on the BUS at any time is
called _____
a) BUS master
b) Processor
c) BUS arbitrator
d) Controller
View Answer

Answer: a
Explanation: The device which is currently accessing the BUS is called as the BUS
master.
3. ______ BUS arbitration approach uses the involvement of the processor.
a) Centralised arbitration
b) Distributed arbitration
c) Random arbitration
d) All of the mentioned
View Answer

Answer: a
Explanation: In this approach, the processor takes into account the various
parameters and assigns the BUS to that device.
4. The circuit used for the request line is a _________
a) Open-collector
b) EX-OR circuit
c) Open-drain
d) Nand circuit
View Answer

Answer: c
Explanation: None.
5. The Centralised BUS arbitration is similar to ______ interrupt circuit.
a) Priority
b) Parallel
c) Single
d) Daisy chain
View Answer

Answer: d
Explanation: None.
6. When the processor receives the request from a device, it responds by sending
_____
a) Acknowledge signal
b) BUS grant signal
c) Response signal
d) None of the mentioned
View Answer

Answer: b
Explanation: The Grant signal is passed from one device to the other until the
device that has requested is found.
7. In Centralised Arbitration ______ is/are is the BUS master.
a) Processor
b) DMA controller
c) Device
d) Both Processor and DMA controller
View Answer

Answer: d
Explanation: The BUS master is the one that decides which will get the BUS.
8. Once the BUS is granted to a device ___________
a) It activates the BUS busy line
b) Performs the required operation
c) Raises an interrupt
d) All of the mentioned
View Answer

Answer: a
Explanation: The BUS busy activated indicates that the BUS is already allocated to
a device and is being used.
9. The BUS busy line is made of ________
a) Open-drain circuit
b) Open-collector circuit
c) EX-Or circuit
d) Nor circuit
View Answer

Answer: b
Explanation: None.
10. After the device completes its operation _____ assumes the control of the BUS.
a) Another device
b) Processor
c) Controller
d) None of the mentioned
View Answer

Answer: b
Explanation: After the device completes the operation it releases the BUS and the
processor takes over it.
11. The BUS busy line is used __________
a) To indicate the processor is busy
b) To indicate that the BUS master is busy
c) To indicate the BUS is already allocated
d) None of the mentioned
View Answer

Answer: c
Explanation: None.
12. Distributed arbitration makes use of ______
a) BUS master
b) Processor
c) Arbitrator
d) 4-bit ID
View Answer

Answer: d
Explanation: The device uses a 4bit ID number and based on this the BUS is
allocated.
13. In Distributed arbitration, the device requesting the BUS ______
a) Asserts the Start arbitration signal
b) Sends an interrupt signal
c) Sends an acknowledge signal
d) None of the mentioned
View Answer
Answer: a
Explanation: None.
14. How is a device selected in Distributed arbitration?
a) By NANDing the signals passed on all the 4 lines
b) By ANDing the signals passed on all the 4 lines
c) By ORing the signals passed on all the 4 lines
d) None of the mentioned
View Answer

Answer: c
Explanation: The OR output of all the 4 lines is obtained and the device with the
larger value is assigned the BUS.
15. If two devices A and B contesting for the BUS have ID�s 5 and 6 respectively,
which device gets the BUS based on the Distributed arbitration.
a) Device A
b) Device B
c) Insufficient information
d) None of the mentioned
View Answer

Answer: b
Explanation: The device Id�s of both the devices are passed on the lines and since
the value of B is greater after the Or
operation it gets the BUS.

1. The primary function of the BUS is __________

a) To connect the various devices to the cpu
b) To provide a path for communication between the processor and other devices
c) To facilitate data transfer between various devices
d) All of the mentioned
View Answer

Answer: a
Explanation: The BUS is used to allow the passage of commands and data between cpu
and devices.
2. The classification of BUSes into synchronous and asynchronous is based on
__________
a) The devices connected to them
b) The type of data transfer
c) The Timing of data transfers
d) None of the mentioned
View Answer

Answer: c
Explanation: The BUS is classified into different types for the convenience of use
and depending on the device.
3. The device which starts data transfer is called __________
a) Master
b) Transactor
c) Distributor
d) Initiator
View Answer

Answer: d
Explanation: The device which starts the data transfer is called an initiator.
4. The device which interacts with the initiator is __________
a) Slave
b) Master
c) Responder
d) Friend
View Answer

Answer: a
Explanation: The device which receives the commands from the initiator for data
transfer.
5. In synchronous BUS, the devices get the timing signals from __________
a) Timing generator in the device
b) A common clock line
c) Timing signals are not used at all
d) None of the mentioned
View Answer

Answer: b
Explanation: The devices receive their timing signals from the clock line of the
BUS.
6. The delays caused in the switching of the timing signals is due to __________
a) Memory access time
b) WMFC
c) Propagation delay
d) Processor delay
View Answer

Answer: c
Explanation: The time taken for the signal to reach the BUS from the device or the
circuit accounts for this delay.
7. The time for which the data is to be on the BUS is affected by __________
a) Propagation delay of the circuit
b) Setup time of the device
c) Memory access time
d) Propagation delay of the circuit & Setup time of the device
View Answer

Answer: d
Explanation: The time for which the data is held is larger than the time taken for
propagation delay and setup time.
8. The Master strobes the slave at the end of each clock cycle in Synchronous BUS.
a) True
b) False
View Answer

Answer: a
Explanation: None.
9. Which is fed into the BUS first by the initiator?
a) Data
b) Address
c) Commands or controls
d) Address, Commands or controls
View Answer

Answer: d
Explanation: None.
10. _____________ signal is used as an acknowledgement signal by the slave in
Multiple cycle transfers.
a) Ack signal
b) Slave ready signal
c) Master ready signal
d) Slave received signal
View Answer

Answer: b
Explanation: The slave once it receives the commands and address from the master
strobes the ready line indicating to the master that the commands are received

1. The master indicates that the address is loaded onto the BUS, by activating
_____ signal.
a) MSYN
b) SSYN
c) WMFC
d) INTR
View Answer

Answer: a
Explanation: The signal activated by the master in the asynchronous mode of
transmission is used to intimate the slave the required data is on the BUS.
2. The devices with variable speeds are usually connected using asynchronous BUS.
a) True
b) False
View Answer

Answer: a
Explanation: The devices with variable speeds are connected using asynchronous BUS,
as the devices share a master-slave relationship.
3. The MSYN signal is initiated __________
a) Soon after the address and commands are loaded
b) Soon after the decoding of the address
c) After the slave gets the commands
d) None of the mentioned
View Answer

Answer: b
Explanation: This signal is activated by the master to tell the slave that the
required commands are on the BUS.
4. In IBM�s S360/370 systems _____ lines are used to select the I/O devices.
a) SCAN in and out
b) Connect
c) Search
d) Peripheral
View Answer

Answer: a
Explanation: The signal is used to scan and connect to input or output devices.
5. The meter in and out lines are used for __________
a) Monitoring the usage of devices
b) Monitoring the amount of data transferred
c) Measure the CPU usage
d) None of the mentioned
View Answer

Answer: a
Explanation: The line is used to monitor the usage of the device for a process.
6. MRDC stands for _______
a) Memory Read Enable
b) Memory Ready Command
c) Memory Re-direct Command
d) None of the mentioned
View Answer

Answer: b
Explanation: The command is used to initiate a read from memory operation.
7. The BUS that allows I/O, memory and Processor to coexist is _______
a) Attributed BUS
b) Processor BUS
c) Backplane BUS
d) External BUS
View Answer

Answer: c
Explanation: None.
8. The transmission on the asynchronous BUS is also called _____
a) Switch mode transmission
b) Variable transfer
c) Bulk transfer
d) Hand-Shake transmission
View Answer

Answer: d
Explanation: The asynchronous transmission is termed as Hand-Shake transfer because
the master intimates the slave after each step of the transfer.
9. Asynchronous mode of transmission is suitable for systems with multiple
peripheral devices.
a) True
b) False
View Answer

Answer: a
Explanation: This mode of transmission is suitable for multiple device situation as
it supports variable speed transfer.
10. The asynchronous BUS mode of transmission allows for a faster mode of data
transfer.
a) True
b) False
View Answer

Answer: b
Explanation: None.

1. ______ serves as an intermediary between the device and the BUSes.

a) Interface circuits
b) Device drivers
c) Buffers
d) None of the mentioned
View Answer

Answer: a
Explanation: The interface circuits act as a hardware interface between the device
and the software side.
2. The side of the interface circuits, that has the data path and the control
signals to transfer data between interface and device is _____
a) BUS side
b) Port side
c) Hardwell side
d) Software side
View Answer

Answer: b
Explanation: This side connects the device to the motherboard.
3. What is the interface circuit?
a) Helps in installing of the software driver for the device
b) Houses the buffer that helps in data transfer
c) Helps in the decoding of the address on the address BUs
d) None of the mentioned
View Answer

Answer: c
Explanation: Once the address is put on the BUS the interface circuit decodes the
address and uses the buffer space to transfer data.
4. The conversion from parallel to serial data transmission and vice versa takes
place inside the interface circuits.
a) True
b) False
View Answer

Answer: a
Explanation: By doing this the interface circuits provide a better interconnection
between devices.
5. The parallel mode of communication is not suitable for long devices because of
______
a) Timing skew
b) Memory access delay
c) Latency
d) None of the mentioned
View Answer

Answer: a
Explanation: None.
6. The Interface circuits generate the appropriate timing signals required by the
BUS control scheme.
a) True
b) False
View Answer

Answer: a
Explanation: The interface circuits generate the required clock signal for the
synchronous mode of transfer.
7. The status flags required for data transfer is present in _____
a) Device
b) Device driver
c) Interface circuit
d) None of the mentioned
View Answer

Answer: c
Explanation: The circuit holds the flags which are required for data transfers.
8. User programmable terminals that combine VDT hardware with built-in
microprocessor is _____
a) KIPs
b) Pc
c) Mainframe
d) Intelligent terminals
View Answer
Answer: d
Explanation: None.
9. Which most popular input device is used today for interactive processing and for
the one line entry of data for batch processing?
a) Mouse
b) Magnetic disk
c) Visual display terminal
d) Card punch
View Answer

Answer: a
Explanation: In batch processing systems the processes are grouped into batches and
they�re executed in batches.
10. The use of spooler programs or _______ Hardware allows PC operators to do the
processing work at the same time a printing operation is in progress.
a) Registers
b) Memory
c) Buffer
d) CPU
View Answer

Answer: c
Explanation: When the processor is busy with the process the data to be printed is
stored
in the buffer.

1. ______ is used as an intermediate to extend the processor BUS.

a) Bridge
b) Router
c) Connector
d) Gateway
View Answer

Answer: a
Explanation: The bridge circuit is basically used to extend the processor BUS to
connect devices.
2. ________ is an extension of the processor BUS.
a) SCSI BUS
b) USB
c) PCI BUS
d) None of the mentioned
View Answer

Answer: c
Explanation: The PCI BUS is used as an extension of the processor BUS and devices
connected to it, is like connected to the Processor itself.
3. What is the full form of ISA?
a) International American Standard
b) Industry Standard Architecture
c) International Standard Architecture
d) None of the mentioned
View Answer

Answer: b
Explanation: The ISA is an architectural standard developed by IBM for its PC�s.
4. What is the full form of ANSI?
a) American National Standards Institute
b) Architectural National Standards Institute
c) Asian National Standards Institute
d) None of the mentioned
View Answer

Answer: a
Explanation: The ANSI is one of the standard architecture used by companies in
designing the systems.
5. The video devices are connected to ______ BUS.
a) PCI
b) USB
c) HDMI
d) SCSI
View Answer

Answer: d
Explanation: The SCSI BUS is used to connect the video devices to a processor by
providing a parallel BUS.
6. SCSI stands for ___________
a) Signal Computer System Interface
b) Small Computer System Interface
c) Small Coding System Interface
d) Signal Coding System Interface
View Answer

Answer: b
Explanation: The SCSI BUS is used to connect disks and video controllers.
7. ISO stands for __________
a) International Standards Organisation
b) International Software Organisation
c) Industrial Standards Organisation
d) Industrial Software Organisation
View Answer

Answer: a
Explanation: The ISO is yet another architectural standard, used to design systems.
8. The system developed by IBM with ISA architecture is ______
a) SPARC
b) SUN-SPARC
c) PC-AT
d) None of the mentioned
View Answer

Answer: c
Explanation: None.
9. IDE disk is connected to the PCI BUS using ______ interface.
a) ISA
b) ISO
c) ANSI
d) IEEE
View Answer

Answer: a
Explanation: None.
10. IDE stands for _________
a) Integrated Device Electronics
b) International Device Encoding
c) Industrial Decoder Electronics
d) International Decoder Encoder
View Answer
Answer: a
Explanation: The IDE interface is used to connect the hard disk to the processor in
most of the Pentium processors.

1. The _____ circuit enables the generation of the ASCII code when the key is
pressed.
a) Generator
b) Debouncing
c) Encoder
d) Logger
View Answer

Answer: c
Explanation: The signal generated upon the pressing of a button is encoded by the
encoder circuit into the corresponding ASCII value.
2. To overcome multiple signals being generated upon a single press of the button,
we make use of ______
a) Generator circuit
b) Debouncing circuit
c) Multiplexer
d) XOR circuit
View Answer

Answer: b
Explanation: When the button is pressed, the contact surfaces bounce and hence it
might lead to the generation of multiple signals. In order to overcome this, we use
Debouncing circuits.
3. The best mode of connection between devices which need to send or receive large
amounts of data over a short distance is _____
a) BUS
b) Serial port
c) Parallel port
d) Isochronous port
View Answer

Answer: c
Explanation: The parallel port transfers around 8 to 16 bits of data simultaneously
over the lines, hence increasing transfer rates.
4. The output of the encoder circuit is/are ______
a) ASCII code
b) ASCII code and the valid signal
c) Encoded signal
d) None of the mentioned
View Answer

Answer: b
Explanation: The encoder outputs the ASCII value along with the valid signal which
indicates that a key was pressed.
5. The disadvantage of using a parallel mode of communication is ______
a) It is costly
b) Leads to erroneous data transfer
c) Security of data
d) All of the mentioned
View Answer

Answer: a
Explanation: The parallel mode of data transfer is costly as it involves data being
sent over parallel lines.
6. In a 32 bit processor, the A0 bit of the address line is connected to _____ of
the parallel port interface.
a) Valid bit
b) Idle bit
c) Interrupt enable bit
d) Status or data register
View Answer

Answer: d
Explanation: None.
7. The Status flag circuit is implemented using _____
a) RS flip flop
b) D flip flop
c) JK flip flop
d) Xor circuit
View Answer

Answer: b
Explanation: The circuit is implemented using the edge triggered D flip flop, that
is triggered on the rising edge of the valid signal.
8. In the output interface of the parallel port, along with the valid signal ______
is also sent.
a) Data
b) Idle signal
c) Interrupt
d) Acknowledge signal
View Answer

Answer: b
Explanation: The idle signal is used to check if the device is idle and ready to
receive data.
9. DDR stands for __________
a) Data Direction Register
b) Data Decoding Register
c) Data Decoding Rate
d) None of the mentioned
View Answer

Answer: a
Explanation: This register is used to control the flow of data from the DATAOUT
register.
10. In a general 8-bit parallel interface, the INTR line is connected to _______
a) Status and Control unit
b) DDR
c) Register select
d) None of the mentioned
View Answer

Answer: a
Explanation: None

1. The mode of transmission of data, where one bit is sent for each clock cycle is
______
a) Asynchronous
b) Parallel
c) Serial
d) Isochronous
View Answer
Answer: d
Explanation: In the isochronous mode of transmission, each bit of the data is sent
per each cycle.
2. The transformation between the Parallel and serial ports is done with the help
of ______
a) Flip flops
b) Logic circuits
c) Shift registers
d) None of the mentioned
View Answer

Answer: c
Explanation: The Shift registers are used to output the data in the desired format
based on the need.
3. The serial port is used to connect basically _____ and processor.
a) I/O devices
b) Speakers
c) Printer
d) Monitor
View Answer

Answer: a
Explanation: The serial port is used to connect the keyboard and other devices
which input or output one bit at a time.
4. The double buffer is used for _________
a) Enabling retrieval of multiple bits of input
b) Combining the input and output operations
c) Extending the buffer capacity
d) None of the mentioned
View Answer

Answer: a
Explanation: None.
5. ______ to increase the flexibility of the serial ports.
a) The wires used for ports is changed
b) The ports are made to allow different clock signals for input and output
c) The drivers are modified
d) All of the mentioned
View Answer

Answer: b
Explanation: The ports are made more flexible by enabling the input or output of
different clock signals for different devices.
6. UART stands for ________
a) Universal Asynchronous Relay Transmission
b) Universal Accumulator Register Transfer
c) Universal Asynchronous Receiver Transmitter
d) None of the mentioned
View Answer

Answer: c
Explanation: The UART is a standard developed for designing serial ports.
7. The key feature of UART is _________
a) Its architectural design
b) Its simple implementation
c) Its general purpose usage
d) Its enhancement of connecting low speed devices
View Answer
Answer: d
Explanation: None.
8. The data transfer in UART is done in ______
a) Asynchronous start stop format
b) Synchronous start stop format
c) Isochronous format
d) EBDIC format
View Answer

Answer: a
Explanation: This basically means that the data transfer is done in asynchronous
mode.
9. The standard used in serial ports to facilitate communication is _____
a) RS-246
b) RS-LNK
c) RS-232-C
d) Both RS-246 and RS-LNK
View Answer

Answer: c
Explanation: This is a standard that acts as a protocol for message communication
involving serial ports.
10. In a serial port interface, the INTR line is connected to _____
a) Status register
b) Shift register
c) Chip select
d) None of the mentioned
View Answer

Answer: a
Explanation: None.