Digital System Module 4 PDF

Digital System Design-18EC34
Regulation – 2018
Module 4
Module 4:
Simple Flip-Flops Applications : Registers, Binary Ripple Counters, Synchronous Binary Counters,
Counters Based on Shift Registers, Design of a Synchronous Counters, Design of a Synchronous
Mod-n Counters using clocked T, JK, D and SR Flip-Flops (Text 2, Chapter 3).
REGISTERS:
➢ A register is simply a collection of flip-flops taken as an entity. The basic function of a register is
to hold information within a digital system so as to make it available to the logic elements during
computing process.
➢ Since a register consists of finite number of flip-flops and since each flip-flop is capable of storing
a 0 or a 1 symbol, there are only a finite number of 0-1 combinations that can be stored in a
register. Each of these combinations is known as the state or content of the register.
➢ Registers that are capable of moving information position-wise upon the occurrence of a clock
signal are called shift registers. These registers are normally classified by weather they can move
the information in one direction or two directions, ie unidirectional or bidirectional.
Classification of registers:
Based on information can move in one direction or two directions:
1. Unidirectional
2. Bidirectional
Based on how information is entered into and outputted from a register:

➢ There are two basic ways of transfers: Serially, Parallel.
➢ In parallel transfer, all 0-1 symbols that comprise the information are simultaneously transferred
as an entity in a single unit of time. Such transfer requires as many lines as symbols being
transferred.
➢ In serial transfer, the information is transferred symbol by symbol in a time sequence. Such
transfer requires only a single line.
➢ Thus, there are four possible ways registers can transfer information:
1. Serial-in/Serial-out 2. Serial-in/Parallel-out
3. Parallel-in/Parallel-out 4. Parallel-in/Serial-out
1. With a neat logic diagram, explain the operation of 4-bit SISO unidirectional shift register.
Dec. 2014/Jan.2015, 10ES33, 06 Marks
2. Explain SIPO and PISO shift registers with relevant diagrams.
Dec.2017/Jan.2018, 15EC33, 06 Marks
3. Explain with suitable logic and timing diagram.
i. Serial – in serial – out shift register.
ii. Parallel – in parallel – out shift register. June/July 2009, 06ES33, 10 Marks
Serial-in/Serial out Register:

➢ The below figure illustrate the serial-in, serial-out unidirectional shift register constructed from
positive-edge-triggered D flip-flops.
Availaible at: VTU Fig:

HUB (Android
Serial-in, App)
Serial-out Unidirectional Shift Register
Prepared by: Halesha H R & Aruna R Sri Sairam College of Engineering Anekal. Page | 1
Regulation – 2018
Module 4
➢ The Q output each flip-flop is connected to the D input of the flip-flop to its right. The control
inputs of all the flip-flops are connected together to a common synchronizing signal called the
clock.
➢ Thus, upon the occurrence of a positive edge of the clock signal, the content of each flip-flop is
shifted one position to the right. The content of the leftmost flip-flop after the clock signal
depends upon the signal value on the serial-data-in line, and the content of the rightmost flip-flop
prior to the clock signal is lost.
➢ The output from the shift register occurs at the right most flip-flop on the serial-data-out line.
Example:
Clock Serial-in Content of Flip-Flops
Signal Data line Q0 Q1 Q2 Q3
0 1 0 1 1
(Initial Contents)
1 1 1 1 0 1
2 0 0 1 1 0
3 1 1 0 1 1
4 1 1 1 0 1
➢ The serial data shifted in i.e., 1101, becomes available as an output on the serial-data-out line after
four clock pulses.
Fig: Timing Diagram

Serial-in Parallel Out:
➢ Outputs are provided from each flip-flop. Once the information is shifted into the register, ie
serial-in, the information is available as a single entity, ie parallel-out, at the flip-flops output
terminals.
Availaible at: VTU HUB Parallel-out

Fig: Serial-in, (AndroidUnidirectional
App) Shift Register
Regulation – 2018
Module 4
➢ Since the information is transferred into this register serially, after an appropriate number of shifts
the information is available in parallel. These provides for serial-to-parallel conversion of
information.
➢ By taking the outputs from the individual flip-flops, the register functions as a parallel-in,
parallel-out unidirectional shift register.
Parallel-in/Parallel-out Register:
➢ The parallel-in, parallel-out unidirectional shift register is illustrated in below figure.
Fig: Parallel-In, Parallel-Out Register
Availaible at: VTU HUB (Android App)Diagram

Fig: Timing
Regulation – 2018
Module 4
Parallel-in Serial-out Unidirectional Shift Register:

4. Explain PIPO and SIPO operations using single diagram.
Dec.2016/Jan.2017, 15EC33, 06 Marks
➢ The operation of the register is controlled by the Load/Shift line.
When Load/Shift = 0; the signals on the parallel-data-in lines IA IB IC ID are transferred into the
register upon the occurrence of a positive-edge clock signal.
When Load/Shift = 1; the D flip-flops become a cascade connection that functions as a
unidirectional shift register providing the serial output.
➢ This register is provides for parallel-to-serial conversion of information.
➢ By taking the outputs from the individual flip-flops, the register functions as a parallel-in,
parallel-out unidirectional shift register.
➢ It can also function as a serial-in, parallel-out unidirectional shift register, and as a serial-in, serial-
out unidirectional shift register.
Fig: Parallel-In, Serial-Out Unidirectional Register
Bidirectional Shift Register:

1. Explain 4 bit universal shift register using 4:1 MUX with help of logic diagram. Write a mode
control table. Dec.2015/Jan.2016, 10ES33, 10 Marks
2. Draw the logic diagram of a 4-bit universal shift register using 4:1 multiplexers. Write its mode
control table. Dec. 2011, 06ES33, 06 Marks
3. Design a 4-bit universal shift register using positive edge triggered D flip-flops to operate as
shown in the table below Q6(a) Dec.08/Jan.09, 06ES33, 12 Marks
Select line Data line Register
S0 S1 selected operation
0 0 I0 HOLD
0 1 I1 Shift RIGHT
1 0 I2 Shift LEFT
1 1 I3 Parallel load
Table Q6(a)
4. Explain 4 bit universal shift register using negative edge triggered D – flip flops.
Dec. 2011, 10ES33, 08 Marks
5. Explain the operation of universal shift register with a neat diagram.
Dec.2017/Jan.2018, 15EC33, 08 Marks
6. Explain the working of universal shift register with the help of logic diagram and mode control
Availaible at: VTU HUB (Android App)
table. June/July.2014, 10ES33, 10 Marks
Regulation – 2018
Module 4
7. Explain universal shift register with the help of logic diagram, mode control table.
Dec. 2012, 10ES33, 10 Marks
8. Explain universal shift register with the help of logic diagram, mode control table and symbol.
May/June 10, 06ES33, 09 Marks
9. With a neat circuit diagram, explain the working of a universal shift register.
Dec.07/Jan.08, 06ES33, 08 Marks
10. Describe the working principle of universal shift register with the help of logic diagram and mode
control table. June/July.2017, 15EC33, 08 Marks
➢ These registers are capable of shifting their contents either left or right depending upon the signals
present on appropriate control input lines. This register is also known as universal shift register as
shown below.
Fig: Universal Shift Register
Table: Mode Control Table

Select Lines Register
S1 S0 operation
0 0 Hold
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load
➢ Each of these operations is the result of the occurrence of positive edge on the clock line. In
addition, the register is cleared asynchronously if a logic-0 is applied to the line labeled CLEAR.
Shift Right Operation:

➢ The logic values to the select lines 𝑆1 𝑆0 of the multiplexer are 01, with this 𝐼1 input of each
multiplexer is connected to its f output.
From figure,
The input to the leftmost D flip-flop is the signal on the serial-input-for-shift-right line,
The input to the 2nd leftmost D flip-flop is the output of the leftmost D flip-flop.
The input to the 3rd leftmost D flip-flop is the output of the 2nd leftmost D flip-flop.
Availaible at: TheVTU inputHUB
to the 4th(Android App)is the output of the 3rd leftmost D flip-flop.
leftmost D flip-flop
Regulation – 2018
Module 4
➢ Upon the occurrence of the positive-edge signal on the clock line, the register shifts its contents
one position to the right.
➢ Similarly, the remaining three operations can be verified.
➢ Registers are available commercially as MSI components. In these circuits, the control lines for
the clock inputs of the flip-flops are connected together and appropriate logic is included to
provide various capabilities. Eg: unidirectional or bidirectional shifting,
1. Design a 4-bit register using positive edge triggered D flip flops to operate as indicated in the table
below: June. 2012, 10ES33, 06 Marks
Mode Select:
Register Operation:
𝐚𝟏 𝐚𝟎
0 0 Hold
0 1 Clear
1 0 Complement contents
1 1 Circular right shift
2. Design a 4-bit register using positive edge triggered D flip-flops to operate as indicated in the
table below: Dec. 2013/Jan.2014, 10ES33, 08 Marks
Mode Select:
Register Operation:
a1 a0
0 0 Hold
0 1 Synchronous clear
1 0 Complement contents
1 1 Circular shift right
Fig: Universal Shift Register

Regulation – 2018
Module 4
COUNTERS:
➢ A counter is another example of a register. Its primary function is to produce a specified output
pattern sequence, so it is also called as pattern generator.
➢ This pattern sequence might correspond to the number of occurrences of an event or it might be
used to control various portions of a digital system.
➢ Each of the 0-1 combinations that are stored in flip-flops that comprise the counter, ie output
pattern, is known as a state of the counter.
➢ The total number of states is called its modulus. Thus, if a counter has m distinct states, then it is
called a modulus-m counter or mod-m counter.
➢ The order in which the states appear is referred to as its counting sequence. The counting sequence
is often depicted by a directed graph.
Binary Ripple Counters:

➢ The counters, whose counting sequence is corresponds to that of binary numbers are called
binary counters. The modulus of a binary counter is 2𝑛 , where n is the number flip-flops in the
counter.
➢ For binary up-counter, the counting sequence is 00 … 0(2) to 11 … 1(2) . After reaching its
maximum count, the counting sequence is then repeated.
➢ For binary down-counter, the counting sequence is in reverse order 11 … 1(2) to 00 … 0(2) . After
reaching its minimum count, the counting sequence is then repeated.
Four-bit Binary Up-Counter:

1. Explain the working of 4 – bit asynchronous counter. June/July 2013, 10ES33, 04 Marks
2. Explain the working of 4-bit asynchronous counter. June/July 2009, 06ES33, 06 Marks
3. Explain the working of four-bit binary ripple up counter, configure using positive edge triggered
flip-flop. Also draw the timing diagram. Dec. 2014/Jan.2015, 10ES33, 08 Marks
4. Explain the working principle of four-bit binary ripple counter, with help of logic diagram, timing
diagram and counting sequence. Dec. 2010, 06ES33, 10 Marks
5. Explain the working principle of 4 bit binary ripple counter configured using +ve edge triggered T
– F/F. Also draw timing diagram. Dec.2017/Jan.2018, 15EC33, 08 Marks
6. Write timing diagrams, counting sequence and the logic diagram for 4-bit ripple counter and
briefly explain. Dec.2016/Jan.2017, 15EC33, 06 Marks
7. Illustrate the operation of 4-bit binary ripple counter using logic diagram and timing diagram.
June/July.2017, 15EC33, 08 Marks
8. Design a 4 bit binary ripple up counter using negative edge triggered JK flip-flops. Draw the
timing diagram with respect to the input clock pulses. Explain the operation.
June/July.2015, 10ES33, 10 Marks
➢ The below figure shows a four-bit binary up-counter implemented with positive-edge triggered T
flip-flop. Each positive transition ie from 0 to 1, on the C terminal causes the flip-flop to toggle.
Fig: Four-bit Asynchronous Up Counter Using Positive Edge Triggered T Flip-Flops.

Regulation – 2018
Module 4
Fig: 4 – Bit Ripple Up Counter Using Negative Edge Triggered JK Flip Flops
➢ Since this is a 4-bit up-counter, its modulus is 24 = 16 and its counting sequence is from 0000(2)
to 1111(2) . The output of the counter appears at the Q output terminals of the four flip-flops.
➢ The input to the counter is count enable signal and a series of count pulses applied to the flip-flop
associated with the lowest-order binary digit.
➢ As long as count enable signal is logic-1, the Q0 flip-flop changes state on each positive-edge of a
count pulse. The control input C, of the remaining flip-flops is connected to Q output of its
previous-order flip-flop.
➢ Thus, when the Qi−1 flip-flop output changes from 1 to 0, then Qi−1 output changes from 0 to 1, a
positive triggering edge occurs at the control input of the Qi flip-flop causing it to toggle.
Operation: Counting Sequence:
➢ The counter is assumed to be initially in its 0000 state and the count Q 3 Q 2 Q1 Q 0
enable signal is logic-1. 0 0 0 0
➢ Upon the occurrence of the positive edge of the first count pulse, Q0 0 0 0 1
changes from 0 to 1, Q0 output changes from 1 to 0 ie negative edge, 0 0 1 0
hence Q1 flip-flop is not affected. Then, the state of the counter is now 0 0 1 1
0 1 0 0
0001.
0 1 0 1
➢ Upon the occurrence of the positive edge of the 2nd count pulse, Q0 0 1 1 0
changes from 1 to 0, Q0 output changes from 0 to 1 ie positive edge, 0 1 1 1
hence Q1 flip-flop changes from 0 to 1, Q1 output changes from 1 to 0 1 0 0 0
ie., negative edge, hence Q2 flip-flop is not affected. Then, the state of 1 0 0 1
the counter is now 0010. 1 0 1 0
rd
➢ Upon the occurrence of the positive edge of the 3 count pulse, Q0 1 0 1 1
1 1 0 0
flip-flop changes from 0 to 1, Q0 output changes from 1 to 0 ie., 1 1 0 1
negative edge, hence Q1 flip-flop is not affected, Q2 flip-flop is also 1 1 1 0
not affected, since no transition in Q1 flip-flop. Then, the state of the 1 1 1 1
counter is now 0011.
➢ Similarly, other states can be analyzed and the counting sequence and timing diagram is given
below.

Regulation – 2018
Module 4
Fig: Timing Diagram of Four-bit binary ripple Up-counter – Positive Edge Triggered
Fig: Timing Diagram of Four-bit binary ripple Up-counter – Negative Edge Triggered
➢ The propagation delays are associated with each flip-flops, these delays are not included in timing
diagram for simplicity.
➢ The above binary counter is also called as ripple counter since a change in state of the Qi−1 flip-
flop is used to toggle Qi flip-flop. Thus, the effect of a count pulse must ripple through the
counter. Ripple counters are also referred as asynchronous counters.
➢ There is a propagation delay between the input and output of a flip-flop, this rippling behavior
affects the overall time delay between the occurrence of a count pulse and the stabilized count
appears at the output terminals.
➢ The worst case occurs when the counter goes from its 11…1-state to its 00…0-state, since toggle
signals must propagate through the entire length of the counter.
➢ For an n-stage binary ripple counter, the worst case settling time becomes n x 𝑡𝑝𝑑 , where 𝑡𝑝𝑑 : is
the propagation delay time associated with each flip-flop.
Four-bit Binary Down-Counter:
Fig: Four-bit Binary Ripple Down Counter.

Regulation – 2018
Module 4
Fig: Timing Diagram of Four-bit binary ripple down-counter – Positive Edge Triggered
9. Draw the circuit of a 3 BIT, asynchronous, down counter using negative edge triggered JK flip
flops and draw the timing waveforms. Dec. 2011, 10ES33, 05 Marks
Solution:
Fig: 3 – Bit Asynchronous Counter Using Negative Edge Triggered JK Flip Flops
Fig: Timing Diagram of 3-Bit Binary Ripple Down-Counter – Negative Edge Triggered
10. Explain the working principle of a mod-8 binary ripple counter, configured using positive edge
triggered T-FF. Also draw the timing diagram. Dec.08/Jan.09, 06ES33, 08 Marks
Solution:

Fig: Mod – 8 Ripple Counter Using Positive Edge Triggered T Flip Flops
Regulation – 2018
Module 4
Fig: Timing Diagram of 3-Bit Binary Ripple Down-Counter – Positive Edge Triggered
11. Design mod-11 asynchronous counter using JK flip flops. June. 2012, 10ES33, 06 Marks
Solution:
Fig: Mod – 11 Asynchronous Counter Using Negative Edge Triggered JK Flip Flops
Counting Sequence:
Q3 Q2 Q1 Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0 Fig: Timing Diagram of Mod – 11 Asynchronous Counter– Negative Edge
0 0 0 0 Triggering
12. Design and implement a divide-by-10 asynchronous counter using T FFS.

Dec. 2012, 10ES33, 10 Marks
Solution:

Regulation – 2018
Module 4
Fig: Mod – 10 Asynchronous Counter Using Negative Edge Triggered T Flip Flops
Counting Sequence:
Q3 Q2 Q1 Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0
0 0 0 1 Fig: Timing Diagram of Divide – by – 10 Counter – Negative Edge
Triggered
13. Design mod-6 ripple counter using T flip-flops. June/July 2018, 15EC33, 06 Marks
Solution:
Fig: Mod – 6 Ripple Counter Using Negative Edge Triggered T Flip Flops
Counting Sequence:
Q2 Q1 Q0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
0 0 0
0 0 1
Fig: Timing Diagram of Mod – 6 Counter – Negative
Edge Triggered
Regulation – 2018
Module 4
Synchronous Binary Counters:

➢ The settling time problem with the asynchronous counters is avoided in synchronous counters.
The count pulses are applied directly to the control inputs of all the clocked flip-flops. Hence all
the flip-flops change simultaneously after the appropriate delay associated with single flip-flop.
➢ Referring to binary counting sequence, for each count pulse the lowest order flip-flop Q0 must
toggle.
For remaining flip-flops, a flip-flop Qi must toggle upon the occurrence of a count pulse, if all its
lower order flip-flops ie Qi−p for p = 1, 2,……,i are in their 1-state.
Example: For i = 3, p = 1, 2, 3
Q3 must toggle if Q2 , Q1 , Q0 are in 1-state
➢ The below figure shows a binary up-counter. The count pulses are applied to the control input (C),
of each clocked flip-flop.
Fig: 4 – Bit Synchronous Up Counter

➢ As long as the counter is enabled, ie CE = 1, the counter follows the binary counting sequence.
The lowest order flip-flop Q0 , toggles on the positive-edge of the each count pulse.
➢ The AND-gate preceding each T input terminal of the remaining flip-flop detects if all the low-
order flip-flops are in their 1-state. If this condition is satisfied, then the flip-flop toggles upon the
occurrence of the positive-edge of the count pulse.
➢ Since the count pulses are applied directly to each flip-flop, the only delay incurred between the
application of a count pulse and the availability of the new count output is the propagation delay
time of a flip-flop.
Drawbacks:
➢ There are p inputs to the AND-gate connected to the pth flip-flop. Thus, if the counter consists of
a large number of flip-flops, then AND-gates having large number of inputs are required. If there
are n-stages to the counter, then output of the pth must appear as input to the (n − p) AND-gates.
➢ Again, if the number flip-flops is large, then the low-order flip-flop must drive a large number of
gates, which may introduce loading complications.
➢ Also, the output of the AND-gate preceding the Qi flip-flop consists of precisely inputs to the
AND-gate preceding the Qi−1 plus the output of the Qi−1 flip-flop.
Availaible at: VTU HUB Fig:

(Android App) Up Counter
4 – Bit Synchronous
Regulation – 2018
Module 4
➢ This observation leads the variation of synchronous counter as shown above. Each AND-gate
requires only two inputs, and the output of each flip-flop is needed as input to the next stage
AND-gate. The propagation delays are incurred between the positive-edges of the count pulses
due-to serial connection of AND-gates. All the flip-flops change state simultaneously after the
propagation delay time of a flip-flop.
➢ The counter speed is based on the availability of the next count at the output terminals, hence
synchronous counters are faster than asynchronous counter.
➢ In synchronous counter, the rate at which the count pulses can be applied is determined by the
gate delays and the flip-flop propagation delay time, and in asynchronous counter, the allowable
count pulse rate is determined by simply the 1st stage of the counter.
➢ This implies that an asynchronous counter is very fast relative to its inputs, ie once the 1st stage
flip-flop changes the state it can accept the next count pulse, even the change has not propagated
through the rest of the counter. However, until the rippling effect is completed the count is not
available for use.
Counter With Parallel Load:

➢ The provisions can be made to load initial count value in parallel before counting operation, then
mod − 2n counter can be used as a mod-m counter, where m < 2n , as shown below.
Fig: Logic Diagram

Fig: Circuit Diagram
Regulation – 2018
Module 4
➢ As shown in fig, JK flip-flops, rather than T flip-flops, are used to facilitate the handling of the
parallel inputs.
➢ Two enable signals are utilized. One to allow the parallel loading of the data inputs D0 , D1 , D2 ,
and D3 , and second to provide for counting. Both are synchronized with the positive edges of the
count pulses.
➢ If Load Enable = 1, regardless of the value on count enable line, the signal values on the data
inputs D0 , D1 , D2 , and D3 are entered into the flip-flops upon the occurrence of the positive edge
of the count pulse.
➢ If Load Enable = 0, and Count Enable = 1; the network behaves as a binary counter. If Load
Enable=0, and Count Enable = 0; the count pulses are ignored and counter retain its current state,
since both J = K = 0. The below figure shows the logic diagram.
➢ The below figure shows a mod-10 counter and its counting sequence.
➢ AND-gate is used to detect the count 1001, and output is connected to the load enable, the counter
is loaded with 0000 ie signal values on the Di inputs upon the occurrence of the next positive edge
of count pulse.
➢ The carry out (CO) = 1, whenever the counter state is 1111 and the counter is in count mode, ie
Count Enable=1, and Load Enable=0, is used for constructing larger binary counters by cascading
two or more 4-bit binary counters.
Counting Sequence:
Q3 Q2 Q1 Q1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0
0 0 0 1
Fig: Logic Diagram
➢ The below fig shows an 8-bit counter, CO corresponds to the least significant digits is used as
count enable input to the counter for most significant digits.
Fig: 8 – Bit Synchronous Counter constructed from Two 4 – Bit Synchronous Counter.
➢ Many different types of MSI Counters are commercially available.

Regulation – 2018
Module 4
Counters Based on Shift Registers:

➢ The overall operation of a digital system is divided into a sequence of time periods. In order to
determine the various time periods, assign them to the states of a binary counter, then by
incorporating a decoder along with counter, the various states, and correspondingly time periods
are identified.
➢ Rather than using a decoder, a non-binary counter could be used, whose counting sequence
provides a series of patterns that simplifies the detection of its states, at the cost of increasing
number of flip-flops used.
Example: Counters based on the structure of shift register: Ring counter and Switch-tail counter.
Ring-counter:
1. Explain Mod-4 ring counter using D flip-flop. June/July.2017, 15EC33, 06 Marks
➢ It is a circular shift register, with only one flip-flop is in 1-state, while the others are in 0-states.
Upon the occurrence of each count pulse, the single 1 is shifted to its adjacent flip-flop.
➢ A ring counter consists of n flip-flops has only n-states in its counting sequence. The below figure
shows the mod-4 ring counter and its counting sequence.
Counting Sequence:
QA QB QC QD
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
1 0 0 0
Fig: Mod – 4 Ring Counter

➢ To detect any particular states, it is only necessary to interrogate the output of a single flip-flop.
Eg: The 0001 state is detected by QD output terminal.
Switch-tail Counter:
2. Explain Johnson counter with its circuit diagram and timing diagram.
June/July 2009, 06ES33, 08 Marks
3. Explain Jonson counter, with its circuit diagram, and timing diagram.
May/June 10, 06ES33, 08 Marks
4. With the help of a schematic diagram, explain how a serial shift register can be transformed into a
i) Ring counter ii) Johnson counter. June/July.2016, 10ES33, 04 Marks
5. Give the circuit of a 4 bit JOHNSON counter using negative edge triggered D – flip flops. Draw
the timing waveforms with respect to clock starting with an initial state of Q3 Q2 Q1 Q0 = 0000.
What is the modulus of this counter. Dec. 2011, 10ES33, 08 Marks
6. Draw the logic diagram of mod-8 twisted ring counter. Write its counting sequence.
Dec. 2011, 06ES33, 06 Marks
7. Design mod 8 counter using shift register. Use D flip-flop to built register circuit. Explain the
operation using function table. Dec.2016/Jan.2017, 15EC33, 06 Marks
8. With the help of a diagram, explain the following with respect to shift register.
i. Parallel in serial out
ii. Ring counter and twisted ring counter. June/July 2013, 10ES33, 08 Marks
9. With help of a diagram, explain the following with respect to shift register:
i. Parallel in serial out
ii. Ring counter and twisted ring counter. Dec.09/Jan.10, 06ES33, 08 Marks
10. With the help of a suitable example, explain the following operations in a shift register. i) SISO ii)
Availaible
PISO iii)at:Twisted
VTUring HUB (Android App)
counter. June/July 2008, 06ES33, 10 Marks
Regulation – 2018
Module 4
Solution:
➢ It is a variation of the ring counter, it is also called as Johnson counter or twisted ring counter, as
shown below.
Counting Sequence:
AND-gate
QA QB QC QD
Inputs:
0 0 0 0 QA QD
1 0 0 0 QA QD
1 1 0 0 QB QC
1 1 1 0 QC QD
1 1 1 1 QA QD
0 1 1 1 QA QB
Fig: Mod – 8 JOHNSON Counter
0 0 1 1 QB QC
0 0 0 1 QC QD
0 0 0 0
➢ The complement of the right most flip-flop serves as the input to the left most flip-flop in the shift
register configuration. There are 2n states occur in the counting sequence of an n-state counter.
➢ In counting sequence, the underlined pair of bits uniquely determine a state. Only 2-input AND-
gate, whose logic expression is also given in the figure, is required to obtain a decoded output.
This counter having even number of states.
➢ The below figure shows a ring counter having odd number of states. It is achieved by connecting
QC QD to the input of the left most flip-flop. Again, each state is detectable by use of a single 2-
input AND-gate.
Fig: Timing Diagram of 4-bit Johnson Counter
11. Describe the block diagram of a MOD-7 twisted ring counter and explain its operation with the
count sequence table and decoding logic used to identify the various states.
Dec.2015/Jan.2016, 10ES33, 08 Marks
12. Describe the block diagram of a mod 7 twisted ring counter and explain its operation. Give the
count sequence table and the decoding logic used to identify the various states.

Regulation – 2018
Module 4
Counting Sequence:
AND-gate
QA QB QC QD
Inputs:
0 0 0 0 QA QD
1 0 0 0 QA QD
1 1 0 0 QB QC
1 1 1 0 QC QD
0 1 1 1 QA QB
0 0 1 1 QB QC
Fig: Mod – 7 JOHNSON Counter 0 0 0 1 QC QD
0 0 0 0
Design of Synchronous Counters:

➢ Depending on application, other types counters might be desirable. Example, one that counts
according to gray code.
➢ Now we develop a general procedure for designing synchronous counters having a pre-specified
output pattern sequence.
Design of a Synchronous Mod-6 Counter Using Clocked JK Flip-Flops:

1. Explain the design of a synchronous mod – 6 counter, using clocked flip – flops. Clearly indicate
the application table, excitation table and minimal sum expressions.
Dec. 2010, 06ES33, 10 Marks
2. Design synchronous mod-6 counter using D flip-flop to generate the sequence 0, 2, 3, 6, 5, 1, 0…..
Dec. 2014/Jan.2015, 10ES33, 10 Marks
3. Design synchronous mod-6 counter using D flip-flops to generate the count sequence, (0, 2, 3, 6,
5, 1, 0). June/July 2018, 15EC33, 08 Marks
4. Design a mod-6 synchronous counter using clocked JK flip flops, the count sequence being 0, 2,
3, 6, 5, 1, 0, 2…… Dec.2015/Jan.2016, 10ES33, 12 Marks
5. Design a synchronous counter using clocked JK flip-flop for the counting sequence shown below:
Q2 Q1 Q0
0 0 0
0 1 0
0 1 1
1 1 0
1 0 1
0 0 1
0 0 0
Solution:
Fig: State Diagram for the Synchronous Mod – 6 Counter

Regulation – 2018
Module 4
➢ The general structure is given below. The 3 clocked JK flip-flops have common count pulse
applied to their control inputs, C. The count pulse may be clock signal or they may originate from
some other source.
➢ The current state of the counter is applied to the logic network. The function of the logic network
is to generate the appropriate signals for J & K terminals of the clocked flip-flops, so that the
specified next-state in the counting sequence results upon the occurrence of the triggering-edge of
the count pulse.
➢ So the appropriate logic network is to be designed. The logic network can be described by six
Boolean expressions one for each of the six inputs to the 3 clocked flip-flops in terms of Boolean
variables Q1 , Q2 , and Q3 , that corresponds to current state of the counter.
➢ To obtain these expressions, a truth table for logic network, called excitation table is to be
developed first, and then simplified Boolean expressions are obtained using K-Map.
Fig: General structure of a synchronous mod-6 counter using positive edge triggered JK flip-
flops.
Excitation Table:
➢ It has 3 sections labeled as, Present-State, Next-State, and Flip-Flop inputs. The counting
sequence is listed in the present-state section, the desired next-state for each present-state is
entered in the next-state section. The 3rd section requires to develop a application table of a flip-
flop.
Present-State Next-State Flip-Flop inputs
+ + +
Q1 Q2 Q3 Q1 Q2 Q3 J1 K1 J2 K 2 J3 K 3
0 0 0 0 0 1 0 0 X 1 X 0 X
2 0 1 0 0 1 1 0 X X 0 1 X
3 0 1 1 1 1 0 1 X X 0 X 1
6 1 1 0 1 0 1 X 0 X 1 1 X
5 1 0 1 0 0 1 X 1 0 X X 0
1 0 0 1 0 0 0 0 X 0 X X 1
Application Table of JK Flip-Flop:

➢ There are four distinct actions that a flip-flop can undergo as a consequence of a triggering signal
at its control input. They are;
1. The flip-flop should remain in its 0-state, ie the transition from 0 to 0.
2. The flip-flop should remain in its 1-state, ie the transition from 1 to 1.
3. The flip-flop should go from 1-state to its 0-state, ie the transition from 1 to 0.
4. The flip-flop should go from 0-state to its 1-state, ie the transition from 0 to 1.
Regulation – 2018
Module 4
➢ It is necessary to consider the flip-flop next-state table as given below in Table (a), and application
table of JK flip-flop is given in Table (b).
(a) Next State Table
J K Q Q+
0 0 0 0 (b) Application Table:
0 0 1 1 Q Q+ J K
0 1 0 0 0 0 0 X
0 1 1 0 0 1 1 X
1 0 0 1 1 0 X 1
1 0 1 1 1 1 X 0
1 1 0 1
1 1 1 0
➢ Now it is simple to determine the logic signals that must be applied to 3 JK Flip-Flops, in order to
produce the present-state to next-state transition specified in each row.
Example: Q1 Q2 Q3 = 000, Q+ + +
1 Q 2 Q 3 = 010
Q1 must remains in 0-state, hence J1 = 0, K1 = X
Q2 must go from its 0-state to 1-state, hence J2 = 1, K 2 = X
Q3 must remains in 0-state, hence J3 = 0, K 3 = X
➢ The inputs to the logic network corresponds to present-section of the excitation table, and the
outputs from the network correspond to the flip-flop inputs section of the excitation table.
➢ Thus, 1st and 3rd sections of the excitation table becomes the truth table for the logic network.
Using these two sections, the six k-maps can be drawn as shown below. These six maps
corresponds to the six flip-flop input functions, and a cell of the map corresponds to the present-
state of the counter.
Boolean Expressions for Inputs to Flip-Flops Using K-Map:
J1 = Q 2 Q 3 K1 = Q 2
J2 = Q 3 K 2 = Q1

Regulation – 2018
Module 4
J3 = Q 2 K 3 = Q1
Fig: Logic Diagram

Self-Correcting Counters:
➢ The counting sequence did not include the states 100 and 111. Once the counter is designed,
definite next states result if either of these states occur.
➢ When a system is initially started, ie when power is applied to the network, the initial states of the
flip-flops are unpredictable. Consequently, either of the two states can occur.
➢ As a solution to this problem, the counter could be initialized prior to its use. One way, this can be
done by applying appropriate signals to the asynchronous input terminals of the flip-flops to force
them into the first state of the counting sequence. Noise signals can also cause the counter to enter
into one of its initially unused states.
➢ A counter in which all the states are not included in the original counting sequence eventually lead
to the normal counting sequence after one or more count pulses are applied to the control inputs,
C, is said to be self-correcting. To avoid having the counter “hang up”, it should always be
designed as self-correcting.
Analysis:
Flip-Flop Inputs Equations: J1 = Q2 Q3 & K1 = Q2 , J2 = Q3 & K 2 = Q1 , J3 = Q2 & K 3 = Q1
Unused State: Q1 Q2 Q3 = 100
Flip-Flop Inputs: J1 = 0 & K1 = 1, J2 = 1 & K 2 = 1, J3 = 0 & K 3 = 0
➢ Upon the occurrence of count pulse; Q1 = 0(reset), Q2 = 1(toggles), Q3 = 0(same state). The
next state of the counter is Q+ + +
1 Q 2 Q 3 = 010. Hence, a valid state of the counting sequence is
reached.
Similarly, for Unused State: Q1 Q2 Q3 = 111
Flip-Flop Inputs: J1 = 1 & K1 = 0, J2 = 0 & K 2 = 1, J3 = 1 & K 3 = 0
➢ Upon the occurrence of count pulse; Q1 = 1(set), Q2 = 0(reset), Q3 = 1(set). The next state of
the counter is Q+ + +
1 Q 2 Q 3 = 101. Hence, a valid state of the counting sequence is reached.

Regulation – 2018
Module 4
Fig: Complete State Diagram for the Synchronous Mod – 6 Counter

➢ Counters having no unused states are always self-correcting. If assignment is done to the don’t
cares associated with the unused states when the logic expressions are obtained then the counter is
not to be self-correcting.
➢ By specifying the next states for each of the unused sates in the counting sequence prior to
constructing the K-maps, a self-correcting counter realization can be guaranteed.
Application Table for a Clocked SR Flip-Flop:

Next State Table:
S R Q Q+
0 0 0 0 Application Table:
0 0 1 1 Q Q+ S R
0 1 0 0 0 0 0 X
0 1 1 0 0 1 1 0
1 0 0 1 1 0 0 1
1 0 1 1 1 1 X 0
1 1 0 X
1 1 1 X
Excitation table for a synchronous mod-6 counter using clocked SR flip-flops:

Excitation Table:
Present-State Next-State Flip-Flop inputs
+ + +
Q1 Q2 Q3 Q1 Q2 Q3 S1 R1 S2 R 2 S3 R 3
0 0 0 0 0 1 0 0 X 1 0 0 X
2 0 1 0 0 1 1 0 X X 0 1 0
3 0 1 1 1 1 0 1 0 X 0 0 1
6 1 1 0 1 0 1 X 0 0 1 1 0
5 1 0 1 0 0 1 0 1 0 X X 0
1 0 0 1 0 0 0 0 X 0 X 0 1
Boolean Expressions Using K-Map:

S1 = Q 2 Q 3 R1 = Q 2
Regulation – 2018
Module 4
S2 = Q 2 Q 3 R 2 = Q1
S3 = Q 2 Q 3 R 3 = Q1 Q 3
Fig: Logic Diagram

Analysis for Self-Correcting:
Flip-Flop Inputs Equations: S1 = Q2 Q3 & R1 = Q2 , S2 = Q2 Q3 /Q1 Q3 & R 2 = Q1 , S3 = Q2 Q3 & R 3 =
Q1 Q 3
Flip-Flop Inputs: S1 = 0 & R1 = 1, S2 = 0 & R 2 = 1, S3 = 0 & K 3 = 0
➢ Upon occurrence of count pulse; Q1 = 0(reset), Q2 = 0(reset), Q3 = 0(same state). The next
state of the counter is Q+ + +
Flip-Flop Inputs: S1 = 1 & R1 = 0, S2 = 0 & R 2 = 1, S3 = 0 & K 3 = 0
➢ Upon the occurrence of count pulse; Q1 = 1(set), Q2 = 0(reset), Q3 = 1(same state). The next
Availaiblestateat:of VTU HUB
the counter is Q+
1Q(Android
+ +
App)a valid state of the counting sequence is reached.
2 Q 3 = 101. Hence,
Regulation – 2018
Module 4
Design of a Synchronous Mod-6 counter Using Clocked D Flip-Flops:

Excitation Table:
Present-State Next-State Flip-Flop Inputs Next State Application
+
Q1 Q2 Q3 Q1 Q2 Q3 D1 + +
D2 D3 Table Table
0 0 0 0 0 1 0 0 1 0 D Q Q+ Q Q+ D
2 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0
3 0 1 1 1 1 0 1 1 0 0 1 0 0 1 1
6 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0
5 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1
1 0 0 1 0 0 0 0 0 0
D1 = Q 2 Q 3 + Q1 Q 2 D2 = Q 2 Q 3 + Q 1 Q 2
D3 = Q1 + Q2 Q3

Regulation – 2018
Module 4
Fig: Logic Diagram

Flip-Flop Inputs Equations: D1 = Q2 Q3 + Q1 Q2 , D2 = Q2 Q3 + Q1 Q2 , D3 = Q1 + Q2 Q3
Flip-Flop Inputs: D1 = 0, D2 = 1, D3 = 1
➢ Upon occurrence of count pulse; Q1 = 0(reset), Q2 = 1(set), Q3 = 1(set). The next state of the
counter is Q+ + +
Flip-Flop Inputs: D1 = 1, D2 = 0, D3 = 1
➢ Upon the occurrence of count pulse; Q1 = 1(set), Q2 = 0(reset), Q3 = 1(set). The next state of
the counter is Q+ + +
Design of a Synchronous Mod-6 counter Using Clocked T Flip-Flops:

Excitation table:
+
Q1 Q2 Q3 Q1 Q2 Q3 T1 + +
T2 T3 Table: Table:
0 0 0 0 0 1 0 0 1 0 T Q Q+ Q Q+ T
2 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0
3 0 1 1 1 1 0 1 0 1 0 1 1 0 1 1
6 1 1 0 1 0 1 0 1 1 1 0 1 1 0 1
5 1 0 1 0 0 1 1 0 0 1 1 0 1 1 0
1 0 0 1 0 0 0 0 0 1

Regulation – 2018
Module 4
T1 = Q 2 Q 3 + Q1 Q 2 T2 = Q 2 Q 3 + Q1 Q 2
T3 = Q2 + Q1 Q3
Fig: Logic Diagram

Flip-Flop Inputs Equations: T1 = Q2 Q3 + Q1 Q2 , T2 = Q2 Q3 + Q1 Q2 , T3 = Q2 + Q1 Q3
Flip-Flop Inputs: T1 = 1, T2 = 1, T3 = 0
➢ Upon occurrence of count pulse; Q1 = 0(toggle), Q2 = 1(toggle), Q3 = 0(same state). The
next state of the counter is Q+ + +
1 Q 2 Q 3 = 010. Hence, a valid state of the counting sequence is
reached.
Flip-Flop Inputs: T1 = 1, T2 = 1, T3 = 1
➢ Upon the occurrence of count pulse; Q1 = 0(toggle), Q2 = 0(toggle), Q3 = 0(toggle). The next
state of the counter is Q+ + +

Regulation – 2018
Module 4
University Questions:
1. Design a synchronous Mod – 6 counter using JK flip – flop.
Dec. 2013/Jan.2014, 10ES33, 08 Marks
2. Design a synchronous Mod-6 counter using clocked JK flip flop.
3. Design a cyclic mod 6 synchronous binary counter using JK flip flop. Give the state diagram,
transition table and excitation table. Dec.08/Jan.09, 06ES33, 10 Marks
4. Design mod-6 synchronous counter using D flip-flops. June/July.2016, 10ES33, 10 Marks
5. Design divide by 6 synchronous counter using T flip-flops. Write state table and reduce the
expression using K-map. June/July 2018, 15EC33, 06 Marks
6. Design a synchronous Mod-6 counter using clocked T flip-flop.
June/July.2017, 15EC33, 10 Marks
Solution:
State Table:
Present Next
State State
S0 S1
S1 S2
S2 S3
S3 S4
S4 S5
S5 S0
Fig: State Diagram
Using JK Flip – Flops:

Transition and Excitation Table: Application
PS NS Flip-Flop Inputs Table:
Q2 + + +
Q1 Q0 Q2 Q1 Q0 J2 K 2 J1 K1 J0 K0 Q Q+ J K
0 0 0 0 0 0 1 0 X 0 X 1 X 0 0 0 X
1 0 0 1 0 1 0 0 X 1 X X 1 0 1 1 X
2 0 1 0 0 1 1 0 X X 0 1 X 1 0 X 1
3 0 1 1 1 0 0 1 X X 1 X 1 1 1 X 0
4 1 0 0 1 0 1 X 0 0 X 1 X
5 1 0 1 0 0 0 X 1 0 X X 1

Regulation – 2018
Module 4
J2 = Q1 Q 0 K 2 = Q0
J1 = Q 2 Q 0 K1 = Q 0
J0 = 1 K0 = 1
Fig: Logic Diagram

Regulation – 2018
Module 4
Using D Flip – Flops:

Transition and Excitation Table:
+
Q2 Q1 Q0 Q2 Q1 Q0 D2 + +
D1 D0 Table Table
0 0 0 0 0 0 1 0 0 1 D Q Q+ Q Q+ D
1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0
2 0 1 0 0 1 1 0 1 1 0 1 0 0 1 1
3 0 1 1 1 0 0 1 0 0 1 0 1 1 0 0
4 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1
5 1 0 1 0 0 0 0 0 0
D2 = Q 1 Q 0 + Q 2 Q 0 D1 = Q1 Q 0 + Q 2 Q1 Q 0
D0 = Q1 Q0 + Q2 Q1 Q0
Fig: Logic Diagram

Regulation – 2018
Module 4
Using T Flip – Flops:

+
Q2 Q1 Q0 Q2 Q1 Q0 T2 + +
T1 T0 Table Table
0 0 0 0 0 0 1 0 0 1 T Q Q+ Q Q+ T
1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0
2 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1
3 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1
4 1 0 0 1 0 1 0 0 1 1 1 0 1 1 0
5 1 0 1 0 0 0 1 0 1
T2 = Q 2 Q 0 + Q1 Q 0 T1 = Q 2 Q 0 + Q1 Q 0
T0 = 1
Fig: Logic Diagram
7. Design a synchronous mod-5 counter using JK flip-flops and implement it.

June/July 2018, 15EC33, 08 Marks
8. Design a mod – 5 synchronous counter using JK flip flop. Dec.09/Jan.10, 06ES33, 12 Marks
9. Design a mod – 5 synchronous binary counter using clocked JK flip – flops.
Solution:
Regulation – 2018
Module 4

+
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0
+ +
K0 Q Q+ J K
0 0 0 0 0 0 1 0 X 0 X 1 X 0 0 0 X
1 0 0 1 0 1 0 0 X 1 X X 1 0 1 1 X
2 0 1 0 0 1 1 0 X X 0 1 X 1 0 X 1
3 0 1 1 1 0 0 1 X X 1 X 1 1 1 X 0
4 1 0 0 0 0 0 X 1 0 X 0 X
J2 = Q1 Q 0 K2 = 1
J1 = Q 0 K1 = Q 0
J0 = Q 2 K0 = 1
Fig: Logic Diagram

Regulation – 2018
Module 4
10. Realize a 3 bit synchronous up counter using JK flip-flop. Write excitation table, transition table
and logic diagram. Dec.2017/Jan.2018, 15EC33, 10 Marks
11. Design a cyclic mod 8 synchronous binary counter using JK flip-flop. Give state diagram,
transition table and excitation table. Dec.2017/Jan.2018, 15EC33, 08 Marks
Solution:
+
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
+ +
Q Q+ J K
0 0 0 0 0 0 1 0 X 0 X 1 X 0 0 0 X
1 0 0 1 0 1 0 0 X 1 X X 1 0 1 1 X
2 0 1 0 0 1 1 0 X X 0 1 X 1 0 X 1
3 0 1 1 1 0 0 1 X X 1 X 1 1 1 X 0
4 1 0 0 1 0 1 X 0 0 X 1 X
5 1 0 1 1 1 0 X 0 1 X X 1
6 1 1 0 1 1 1 X 0 X 0 1 X
7 1 1 1 0 0 0 X 1 X 1 X 1
J2 = Q1 Q 0 K 2 = Q1 Q 0
J1 = Q 0 K1 = Q 0
J0 = 1 K0 = 1

Regulation – 2018
Module 4
Fig: Logic Diagram
11. Design a cyclic modulo – 8 synchronous binary counter, using JK flip flops, to count the number
of occurrences of an input, i.e, the number of times it is a 1. The input variable x must be
coincident with the clock to be counted. The counter is to count in binary. The design should
clearly indicating the following:
i. State diagram and state table. Dec. 2010, 06ES33, 05 Marks
ii. Transition table and excitation table. Dec. 2010, 06ES33, 05 Marks
iii. Karnaugh maps. Dec. 2010, 06ES33, 05 Marks
iv. Logic diagram. Dec. 2010, 06ES33, 05 Marks
12. Design a cyclic modulo-8 synchronous counter using JK flip flop that will count the number of
occurrences of a input; that is, the number times it is a 1. The input variable X must be coincident
with the clock to be counted. The counter is to count in binary.
Solution:
State Table: Application Table:
Present Next Q Q+ J K
State State 0 0 0 X
S0 S1 0 1 1 X
S1 S2 1 0 X 1
S2 S3 1 1 X 0
S3 S4
S4 S5
S5 S6
S6 S7
S7 S0
Fig: State Diagram

NS Flip-Flop Inputs
PS
X=0 X=1 X=0 X=1
+ +
Q2 Q1 Q0 Q+2 Q+1 Q 0 Q +
2 Q +
1 Q 0 J 2 K 2 J 1 K1 J 0 K0 J 2 K2 J 1 K1 J 0 K0
0 0 0 0 0 0 0 0 0 1 0 X 0 X 0 X 0 X 0 X 1 X
1 0 0 1 0 0 1 0 1 0 0 X 0 X X 0 0 X 1 X X 1
2 0 1 0 0 1 0 0 1 1 0 X X 0 0 X 0 X X 0 1 X
3 0 1 1 0 1 1 1 0 0 0 X X 0 X 0 1 X X 1 X 1
4 1 0 0 1 0 0 1 0 1 X 0 0 X 0 X X 0 0 X 1 X
5 1 0 1 1 0 1 1 1 0 X 0 0 X X 0 X 0 1 X X 1
6 1 1 0 1 1 0 1 1 1 X 0 X 0 0 X X 0 X 0 1 X
7 1 1 1 1 1 1 0 0 0 X 0 X 0 X 0 X 1 X 1 X 1
Regulation – 2018
Module 4
Input PS NS Flip-Flop Inputs

X Q2 Q1 Q0 Q+
2 Q+1 Q+
0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 0 0 0 X 0 X 0 X
1 0 0 0 1 0 0 1 0 X 0 X X 0
2 0 0 1 0 0 1 0 0 X X 0 0 X
3 0 0 1 1 0 1 1 0 X X 0 X 0
4 0 1 0 0 1 0 0 X 0 0 X 0 X
5 0 1 0 1 1 0 1 X 0 0 X X 0
6 0 1 1 0 1 1 0 X 0 X 0 0 X
7 0 1 1 1 1 1 1 X 0 X 0 X 0
8 1 0 0 0 0 0 1 0 X 0 X 1 X
9 1 0 0 1 0 1 0 0 X 1 X X 1
10 1 0 1 0 0 1 1 0 X X 0 1 X
11 1 0 1 1 1 0 0 1 X X 1 X 1
12 1 1 0 0 1 0 1 X 0 0 X 1 X
13 1 1 0 1 1 1 0 X 0 1 X X 1
14 1 1 1 0 1 1 1 X 0 X 0 1 X
15 1 1 1 1 0 0 0 X 1 X 1 X 1
J2 = XQ1 Q0 K 2 = XQ1 Q 0
J1 = XQ 0 K1 = XQ 0

Regulation – 2018
Module 4
J0 = X K0 = X
Fig: Logic Diagram
13. Design a counter circuit for the following sate table. Follow the standard steps for design.
Dec.2016/Jan.2017, 15EC33, 10 Marks

Regulation – 2018
Module 4
Solution: Using D Flip-Flops

State Table: Transition and Excitation Table:
Present Next State Input PS NS FF Inputs
+ + +
State X=0 X=1 X Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
A A B 0 0 0 0 0 0 0 0 0 0 0
B B C 2 0 0 1 0 0 1 0 0 1 0
C C D 3 0 0 1 1 0 1 1 0 1 1
D D E 5 0 1 0 1 1 0 1 1 0 1
E E F 6 0 1 1 0 1 1 0 1 1 0
F F A 7 0 1 1 1 1 1 1 1 1 1
8 1 0 0 0 0 1 0 0 1 0
Application Table: 10 1 0 1 0 0 1 1 0 1 1
Q Q+ D 11 1 0 1 1 1 0 1 1 0 1
0 0 0 13 1 1 0 1 1 1 0 1 1 0
0 1 1 14 1 1 1 0 1 1 1 1 1 1
1 0 0 15 1 1 1 1 0 0 0 0 0 0
1 1 1 D2 = ∑m (5, 6, 7, 11, 13, 14) + ∑d(1, 4, 9, 12)
D1 = ∑m (2, 3, 6, 7, 8, 10, 13, 14) + ∑d(1, 4, 9, 12)
D0 = ∑m (3, 5, 7, 10, 11, 14) + ∑d(1, 4, 9, 12)
D2 = Q1 Q 0 + XQ 2 + Q 2 Q 0 + XQ 2 Q 0 D1 = XQ1 + XQ1 + Q1 Q 0
Availaible at: VTU HUB D(Android App)

0 = Q 2 Q 0 + XQ 0 + XQ1 Q 0
Regulation – 2018
Module 4
Fig: Logic Diagram

Using JK Flip-Flops:
Input PS NS Flip-Flop Inputs Table
X + + +
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 Q Q+ J K
0 0 0 0 0 0 0 0 0 X 0 X 0 X 0 0 0 X
2 0 0 1 0 0 0 1 0 X X 1 1 X 0 1 1 X
3 0 0 1 1 0 1 0 0 X X 0 X 1 1 0 X 1
5 0 1 0 1 0 1 1 X 1 1 X X 0 1 1 X 0
6 0 1 1 0 1 0 0 X 0 X 1 0 X
7 0 1 1 1 1 0 1 X 0 X 1 X 0
8 1 0 0 0 1 1 0 1 X 1 X 0 X
10 1 0 1 0 1 1 1 1 X X 0 1 X
11 1 0 1 1 0 0 1 0 X X 1 X 0
13 1 1 0 1 0 1 0 X 1 1 X X 1
14 1 1 1 0 0 1 1 X 1 X 0 1 X
15 1 1 1 1 0 0 0 X 1 X 1 X 1
J2 = ∑m(8, 10) + ∑d(5, 6, 7, 13, 14, 15, 1, 4, 9, 12)

K 2 = ∑m(5, 13, 14, 15) + ∑d(0, 2, 3, 8, 10, 11, 1, 4, 9, 12)
J1 = ∑m(5, 8, 13) + ∑d(2, 3, 6, 7, 10, 11, 14, 15, 1, 4, 9, 12)
K1 = ∑m(2, 6, 7, 11, 15) + ∑d(0, 5, 8, 13, 1, 4, 9, 12)
J0 = ∑m(2, 10, 14) + ∑d(3, 5, 7, 11, 13, 15, 1, 4, 9, 12)
K 0 = ∑m(3, 13, 15) + ∑d(0, 2, 6, 8, 10, 14, 1, 4, 9, 12)

Regulation – 2018
Module 4
J2 = XQ 0 K 2 = X + Q1
J1 = X + Q 0 K1 = XQ 0 + XQ 2 + X Q 0
J0 = XQ1 + Q 2 Q1 K 0 = X Q 2 + XQ 2

Regulation – 2018
Module 4
Fig: Logic Diagram
14. Design and implement a synchronous 3 bit up/down counter using J-K flip-flops.
Solution:
State Table: Application Table:
Present Next State Q Q+ J K
State X=0 X=1 0 0 0 X
S0 S7 S1 0 1 1 X
S1 S0 S2 1 0 X 1
S2 S1 S3 1 1 X 0
S3 S2 S4
S4 S3 S5
S5 S4 S6
S6 S5 S7
S7 S6 S0
Fig: State Diagram

Input PS NS Flip-Flop Inputs
+ + +
X Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 1 1 1 X 1 X 1 X
1 0 0 0 1 0 0 0 0 X 0 X X 1
2 0 0 1 0 0 0 1 0 X X 1 1 X
3 0 0 1 1 0 1 0 0 X X 0 X 1
4 0 1 0 0 0 1 1 X 1 1 X 1 X
5 0 1 0 1 1 0 0 X 0 0 X X 1
6 0 1 1 0 1 0 1 X 0 X 1 1 X
7 0 1 1 1 1 1 0 X 0 X 0 X 1
8 1 0 0 0 0 0 1 0 X 0 X 1 X
9 1 0 0 1 0 1 0 0 X 1 X X 1
10 1 0 1 0 0 1 1 0 X X 0 1 X
11 1 0 1 1 1 0 0 1 X X 1 X 1
12 1 1 0 0 1 0 1 X 0 0 X 1 X
13 1 1 0 1 1 1 0 X 0 1 X X 1
Availaible at: VTU HUB (Android App) 1 X 0 X 0 1
14 1 1 1 0 1 1 X
Regulation – 2018
Module 4
15 1 1 1 1 0 0 0 X 1 X 1 X 1
J2 = ∑m(0, 11) + ∑d(4, 5, 6, 7, 12, 13, 14, 15)
K 2 = ∑m(4, 15) + ∑d(0, 1, 2, 3, 8, 9, 10, 11)
J1 = ∑m(0, 4, 9, 13) + ∑d(2, 3, 6, 7, 10, 11, 14, 15)
K1 = ∑m(2, 6, 11, 15) + ∑d(0, 1, 4, 5, 8, 9, 12, 13)
J0 = ∑m(0, 2, 4, 6, 8, 10, 12, 14) + ∑d(1, 3, 5, 7, 9, 11, 13, 15)
K 0 = ∑m(1, 3, 5, 7, 9, 11, 13, 15) + ∑d(0, 2, 4, 6, 8, 10, 12, 14)
J2 = X Q1 Q 0 + XQ1 Q 0 K 2 = X Q1 Q 0 + XQ1 Q 0
J1 = X Q 0 + XQ 0 K1 = X Q 0 + XQ 0

Regulation – 2018
Module 4
J0 = 1 K0 = 1
Fig: Logic Diagram
15. Design a synchronous counter using JK flip flops to count the sequence 0, 1, 2, 4, 5, 6, 0, 1, 2 use
the state diagram and state table. June/July 2013, 10ES33, 10 Marks
16. Design a synchronous counter using JK flip-flops to count the sequence 0, 1, 2, 4, 5, 6, 0, 1, 2.
Use state diagram and state table. June/July 2018, 15EC33, 08 Marks
17. Design a synchronous counter using JK flip flops to count in the sequence 0, 1, 2, 4, 5, 6, 0, 1, 2…
Use state diagram and state table. June/July 2009, 06ES33, 12 Marks
Solution:S0
State Diagram: State Table: Application Table:
Present Next Q Q+ J K
State State 0 0 0 X
S0 S1 0 1 1 X
S1 S2 1 0 X 1
S2 S4 1 1 X 0
S4 S5
S5 S6
S6 S0

Regulation – 2018
Module 4

PS NS Flip-Flop Inputs
+ + +
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
2 0 1 0 1 0 0 1 X X 1 0 X
4 1 0 0 1 0 1 X 0 0 X 1 X
5 1 0 1 1 1 0 X 0 1 X X 1
6 1 1 0 0 0 0 X 1 X 1 0 X
J2 = ∑m(2) + ∑d(3, 4, 5, 6, 7) K 2 = ∑m(6) + ∑d(0, 1, 2, 3, 7)

J1 = ∑m(1, 5) + ∑d(2, 3, 6, 7) K 1 = ∑m(2, 6) + ∑d(0, 1, 3, 4, 5, 7)
J0 = ∑m(0, 4) + ∑d(1, 3, 5, 7) K 0 = ∑m(1, 5) + ∑d(0, 2, 3, 4, 6, 7)
Boolean Expressions:
J2 = Q1 K 2 = Q1
J1 = Q 0 K1 = 1
J0 = Q1 K0 = 1

Regulation – 2018
Module 4
Fig: Logic Diagram
18. Design a counter using JK flip flops whose sequence is {0, 1, 4, 6, 7, 5, 0, …..} by obtaining
minimal sum equations. June. 2012, 10ES33, 10 Marks
19. Design a counter using JK – flip flops whose counting sequence is 000, 001, 100, 110, 111, 101,
000 etc. by obtaining its minimal sum equations. June/July 2008, 06ES33, 08 Marks
20. Design a counter using JK flip flops whose counting sequence is 000, 001, 100, 110, 111, 101,
000 etc., by obtaining its minimal sum equations. May/June 10, 06ES33, 10 Marks
Solution:
PS NS Flip-Flop Inputs Table of JK Flip-
Q2 + + +
Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 Flop:
0 0 0 0 0 0 1 0 X 0 X 1 X Q Q+ J K
1 0 0 1 1 0 0 1 X 0 X X 1 0 0 0 X
4 1 0 0 1 1 0 X 0 1 X 0 X 0 1 1 X
6 1 1 0 1 1 1 X 0 X 0 1 X 1 0 X 1
7 1 1 1 1 0 1 X 0 X 1 X 0 1 1 X 0
5 1 0 1 0 0 0 X 1 0 X X 1
J2 = ∑m(1) + ∑d(2, 3, 4, 5, 6, 7) K 2 = ∑m(5) + ∑d(0, 1, 2, 3)

J1 = ∑m(4) + ∑d(2, 3, 6, 7) K1 = ∑m(7) + ∑d(0, 1, 2, 3, 4, 5)
J0 = ∑m(0, 6) + ∑d(1, 2, 3, 5, 7) K 0 = ∑m(1, 5) + ∑d(0, 2, 3, 4, 6)
J2 = Q 0 K 2 = Q1 Q 0

Regulation – 2018
Module 4
J1 = Q 2 Q 0 K1 = Q 0
J0 = Q1 K 0 = Q1
Fig: Logic Diagram
21. Design and implement a synchronous counter to count the sequence 0 – 3 – 2 – 5 – 1 – 0 using
negative edge triggered JK flip flops. Dec. 2011, 10ES33, 12 Marks
Solution:
Transition and Excitation Table: Application Table
PS NS Flip-Flop Inputs of JK Flip-Flop:
Q2 Q1 Q0 Q+ 2 Q +
1 Q +
0 J2 K2 J1 K1 J0 K0 Q Q+ J K
0 0 0 0 0 1 1 0 X 1 X 1 X 0 0 0 X
3 0 1 1 0 1 0 0 X X 0 X 1 0 1 1 X
2 0 1 0 1 0 1 1 X X 1 1 X 1 0 X 1
5 1 0 1 0 0 1 X 1 0 X X 0 1 1 X 0
1 0 0 1 0 0 0 0 X 0 X X 1
J2 = ∑m(2) + ∑d(4, 5, 6, 7) K 2 = ∑m(5) + ∑d(0, 1, 2, 3, 4, 6, 7)

J1 = ∑m(0) + ∑d(2, 3, 4, 6, 7) K1 = ∑m(2) + ∑d(0, 1, 4, 5, 6, 7)
J0 = ∑m(0, 2) + ∑d(1, 3, 4, 5, 6, 7) K 0 = ∑m(1, 3) + ∑d(0, 2 4, 6, 7)

Regulation – 2018
Module 4
J2 = Q1 Q 0 K2 = 1
J1 = Q 0 K1 = Q 0
J0 = 1 K 0 = Q2
Fig: Logic Diagram

Regulation – 2018
Module 4
22. Design Mod-6 synchronous counter using JK flip-flop. The sequence is 000, 001, 011, 100, 101,
111, .. 000. Dec.2016/Jan.2017, 15EC33, 07 Marks
Solution:
Q2 Q1 + + +
Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 Flop:
0 0 0 0 0 0 1 0 X 0 X 1 X Q Q+ J K
1 0 0 1 0 1 1 0 X 1 X X 0 0 0 0 X
3 0 1 1 1 0 0 1 X X 1 X 1 0 1 1 X
4 1 0 0 1 0 1 X 0 0 X 1 X 1 0 X 1
5 1 0 1 1 1 1 X 0 1 X X 0 1 1 X 0
7 1 1 1 0 0 0 X 1 X 1 X 1
J2 = ∑m(3) + ∑d(2, 4, 5, 6, 7) K 2 = ∑m(7) + ∑d(0, 1, 2, 3, 6)

J1 = ∑m(1, 5) + ∑d(2, 3, 6, 7) K1 = ∑m(3, 7) + ∑d(0, 1, 2, 4, 5, 6)
J0 = ∑m(0, 4) + ∑d(1, 2, 3, 5, 6, 7) K 0 = ∑m(3, 7) + ∑d(0, 4, 2, 6)
J2 = Q1 K 2 = Q1
J1 = Q 0 K1 = 1
J0 = 1 K 0 = Q1

Regulation – 2018
Module 4
Fig: Logic Diagram
23. Design and implement a synchronous BCD counter using J-K FFS.
Dec. 2012, 10ES33, 10 Marks
24. Design a synchronous counter to count from 0000 to 1001 using JK flip-flops.
Solution:
+ + + +
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0 Flop:
0 0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X Q Q+ J K
1 0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1 0 0 0 X
2 0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X 0 1 1 X
3 0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1 1 0 X 1
4 0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X 1 1 X 0
5 0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
6 0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
7 0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
8 1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
9 1 0 0 1 0 0 0 0 X 1 0 X 0 X X 1
J3 = Q 2 Q1 Q 0 K 3 = Q0

Regulation – 2018
Module 4
J2 = Q1 Q 0 K 2 = Q1 Q 0
J1 = Q 3 Q 0 K1 = Q 0
J0 = 1 K0 = 1

Regulation – 2018
Module 4
Fig: Logic Diagram
25. Design a synchronous 5421 code sequence using positive edge triggered D flip flop with
minimum combinational circuits. June. 2012, 10ES33, 10 Marks
Solution:
Present State Next State FF Inputs Table:
+ + +
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 D3 D2 D1 +
D0 Q Q+ D
0(0) 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0
1(1) 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1
2(2) 0 0 1 0 0 0 1 1 0 0 1 1 1 0 0
3(3) 0 0 1 1 0 1 0 0 0 1 0 0 1 1 1
4(4) 0 1 0 0 1 0 0 0 1 0 0 0
5(8) 1 0 0 0 1 0 0 1 1 0 0 1
6(9) 1 0 0 1 1 0 1 0 1 0 1 0
7(10) 1 0 1 0 1 0 1 1 1 0 1 1
8(11) 1 0 1 1 1 1 0 0 1 1 0 0
9(12) 1 1 0 0 0 0 0 0 0 0 0 0
D3 = Q 3 Q 2 + Q 3 Q 2 = Q 3 ⊕ Q 2 D2 = Q 1 Q 0

Regulation – 2018
Module 4
D1 = Q1 Q 0 + Q1 Q 0 = Q1 ⊕ Q 0 D0 = Q 2 Q 0
Fig: Logic Diagram
26. Design a synchronous mod – 6 counter whose counting sequence is 0, 1, 2, 4, 6, 7 and repeat, by
obtaining its minimal – sum equations. Use positive – edge – triggered D flip – flops.
Dec. 2011, 06ES33, 10 Marks
Solution:
Transition and Excitation Table: Application Table of
PS NS Flip-Flop Inputs D Flip-Flop:
Q2 Q1 Q0 Q+ 2
+
Q1 Q0 +
D2 D1 D0 Q Q+ D
0 0 0 0 0 0 1 0 0 1 0 0 0
1 0 0 1 0 1 0 0 1 0 0 1 1
2 0 1 0 1 0 0 1 0 0 1 0 0
4 1 0 0 1 1 0 1 1 0 1 1 1
6 1 1 0 1 1 1 1 1 1
7 1 1 1 0 0 0 0 0 0
D2 = ∑m(2, 4, 6) + ∑d(3, 5) D1 = ∑m(1, 4, 6) + ∑d(3, 5) D0 = ∑m(0, 6) + ∑d(3, 5)

Regulation – 2018
Module 4
D2 = Q 2 Q 1 + Q 1 Q 0 D1 = Q 2 Q 0 + Q 2 Q 0 = Q 2 ⊕ Q 0
D0 = Q 2 Q 1 Q 0 + Q 2 Q 1 Q 0
Fig: Logic Diagram
27. In the figure shown in Fig.Q.6(c) sketch the counting sequence. Assume both the flip flops are
cleared initially. Dec. 2011, 06ES33, 04 Marks
Solution:
CLK Q2 Q1 J2 = Q1 K 2 = Q1 J1 = Q2 K1 = Q2
0 0 0 1 1 0 0
1 1 0 1 1 1 1
2 0 1 0 0 0 0
3 0 1 0 0 0 0
Availaible at: VTU HUB
4 0 (Android
1 0 App) 0 0 0
Regulation – 2018
Module 4
28. Compare synchronous and ripple counters. Dec. 2011, 10ES33, 03 Marks
29. Compare synchronous and asynchronous counter. Dec. 2014/Jan.2015, 10ES33, 04 Marks
30. Compare synchronous and asynchronous counters. June/July 2018, 15EC33, 04 Marks
Solution:
Asynchronous Counter (Ripple counter): Synchronous Counter:
1. Clock input is applied to LSB FF. The 1. Clock input is common to all FF.
output of1st FF is connected as clock to
next FF.
2. All flip-flops are toggle flip-flop. 2. Any flip-flop can be used.
3. Speed depends upon number flip-flops 3. Speed is independent of number of flip-
1 1
used for n bit. 𝑓𝑚𝑎𝑥 = n x t flops used. 𝑓𝑚𝑎𝑥 = t
p p
4. No extra logic gates are required. 4. Logic gates are required based on
design.
5. Cost is less. 5. Cost is more.
Self-Correcting Counters:
31. Write the state diagram for Mod-5 self correcting counter and briefly explain. The sequence is
000, 001, 101, 110, 111, 000. Dec.2016/Jan.2017, 15EC33, 03 Marks


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Digital System Design-18EC34

Based on how information is entered into and outputted from a register:

Serial-in/Serial out Register:

Availaible at: VTU Fig:

Fig: Timing Diagram

Availaible at: VTU HUB Parallel-out

Fig: Parallel-In, Parallel-Out Register

Availaible at: VTU HUB (Android App)Diagram

Parallel-in Serial-out Unidirectional Shift Register:

Fig: Parallel-In, Serial-Out Unidirectional Register

Bidirectional Shift Register:

Fig: Universal Shift Register

Table: Mode Control Table

Shift Right Operation:

Fig: Universal Shift Register

Availaible at: VTU HUB (Android App)

Binary Ripple Counters:

Four-bit Binary Up-Counter:

Fig: Four-bit Asynchronous Up Counter Using Positive Edge Triggered T Flip-Flops.

Availaible at: VTU HUB (Android App)

Availaible at: VTU HUB (Android App)

Four-bit Binary Down-Counter:

Fig: Four-bit Binary Ripple Down Counter.

Availaible at: VTU HUB (Android App)

12. Design and implement a divide-by-10 asynchronous counter using T FFS.

Availaible at: VTU HUB (Android App)

Synchronous Binary Counters:

Fig: 4 – Bit Synchronous Up Counter

Availaible at: VTU HUB Fig:

Counter With Parallel Load:

Fig: Logic Diagram

Availaible at: VTU HUB (Android App)

Availaible at: VTU HUB (Android App)

Counters Based on Shift Registers:

Fig: Mod – 4 Ring Counter

Fig: Timing Diagram of 4-bit Johnson Counter

Availaible at: VTU HUB (Android App)

Design of Synchronous Counters:

Design of a Synchronous Mod-6 Counter Using Clocked JK Flip-Flops:

Fig: State Diagram for the Synchronous Mod – 6 Counter

Application Table of JK Flip-Flop:

Availaible at: VTU HUB (Android App)

Fig: Logic Diagram

Availaible at: VTU HUB (Android App)

Fig: Complete State Diagram for the Synchronous Mod – 6 Counter

Application Table for a Clocked SR Flip-Flop:

Excitation table for a synchronous mod-6 counter using clocked SR flip-flops:

Boolean Expressions Using K-Map:

Availaible at: VTU HUB (Android App)

Fig: Logic Diagram

Fig: Complete State Diagram for the Synchronous Mod – 6 Counter

Design of a Synchronous Mod-6 counter Using Clocked D Flip-Flops:

Boolean Expressions Using K-Map:

Availaible at: VTU HUB (Android App)

Fig: Logic Diagram

Fig: Complete State Diagram for the Synchronous Mod – 6 Counter

Design of a Synchronous Mod-6 counter Using Clocked T Flip-Flops:

Availaible at: VTU HUB (Android App)

Boolean Expressions Using K-Map:

Fig: Logic Diagram

Availaible at: VTU HUB (Android App)

Fig: Complete State Diagram for the Synchronous Mod – 6 Counter