Microcomputer Components: 8-Bit CMOS Single-Chip Microcontroller
Microcomputer Components: 8-Bit CMOS Single-Chip Microcontroller
SAB 80C517A/83C517A-5
www.DataSheet4U.com
Preliminary
SAB 83C517A-5 Microcontroller with factory mask-programmable ROM
SAB 80C517A Microcontroller for external ROM
The SAB 80C517A/83C517A-5 is a high-end member of the Siemens SAB 8051 family of
microcontrollers. It is designed in Siemens ACMOS technology and based on SAB 8051
architecture. ACMOS is a technology which combines high-speed and density characteristics
with low-power consumption or dissipation.
While maintaining all the SAB 80C517 features and operating characteristics the
SAB 80C517A is expanded in its "fail-safe" characteristics and timer capabilities.The
SAB 80C517A is identical with the SAB 83C517A-5 except that it lacks the on-chip program
memory. The SAB 80C517A/83C517A-5 is supplied in a 84-pin plastic leaded chip carrier
package (P-LCC-84) and in a 100-pin plastic quad flat package (P-MQFP-100-2).
SAB 80C517A/83C517A-5
Revision History 05.94
Previous Releases 01.94/08.93/11.92/10.91/04.91
Page Subjects (changes since last revision 04.91)
6 – Pin configuration P-MQFP-100-2 added
4 – Pin differences updated
7-15 – Pin numbers for P-MQFP-100-2 package added
several – Correction of P-MRFP-100 into P-MQFP-100-2
3 – Ordering information for -40 to +110°C versions
26, 27, 31 – Correction of register names S0RELL, SCON, ADCON, ICRON,
and SBUF
34 – Figure 4 corrected
41 – Figure 8 corrected
49 – PE/SWD function description completed
60 – Correct ordering numbers
62 – Test condition for VOH, VOH1 corrected
65 – tPXIZ name corrected
tAVIV, tAZPL values corrected
several – Minimum clock frequence is now 3.5 MHz
66 – tQVWH (data setup before WR) corrected and added
66 – tLLAX2 corrected
Page Subjects (changes since last revision 08.93)
26 – Corrected SFR name S0RELL
51 – Below "Termination of HWPD Mode": 4th paragraph with ident
www.DataSheet4U.com
corrected
65 – Description of tLLIV corrected
65 – Program Memory Read Cycle: tPXAV added
74 – Oscillator circuit drawings: MQFP-100-2 pin numbers added.
Page Subjects (changes since last revision 01.94)
– Minor changes on several pages
47 – Table 6 corrected
Ordering Information
www.DataSheet4U.com
Logic Symbol
The pin functions of the SAB 80C517A are identical with those of the SAB 80C517/80C537 with
one exception:
P-LCC-84, Pin 60
HWPD N.C.
P-MQFP-100-2, Pin 36
www.DataSheet4U.com
Pin Configuration
(P-LCC-84)
www.DataSheet4U.com
Pin Configuration
(P-MQFP-100-2)
www.DataSheet4U.com
– INT4/CC1 (P1.1): interrupt 4 input /
compare 1 output /capture 1 input
– INT5/CC2 (P1.2): interrupt 5 input /
compare 2 output /capture 2 input
– INT6/CC3 (P1.3): interrupt 6 input /
compare 3 output /capture 3 input
– INT2/CC4 (P1.4): interrupt 2 input /
compare 4 output /capture 4 input
– T2EX (P1.5): timer 2 external
reload trigger input
– CLKOUT (P1.6): system clock output
– T2 (P1.7): counter 2 input
* I = Input
O = Output
www.DataSheet4U.com
www.DataSheet4U.com
Figure 1
Block Diagram
Functional Description
The SAB 80C517A is based on 8051 architecture. It is a fully compatible member of the
Siemens SAB 8051/80C51 microcontroller family being an significantly enhanced
SAB 80C517. The SAB 80C517A is therefore compatible with code written for the
SAB 80C517.
Having an 8-bit CPU with extensive facilities for bit-handling and binary BCD arithmetics the
SAB 80C517A is optimized for control applications. With a 18 MHz crystal, 58 % of the
instructions are executed in 666.67 ns.
Being designed to close the performance gap to the 16-bit microcontroller world, the
SAB 80C517A’s CPU is supported by a powerful 32-/16-bit arithmetic unit and a more flexible
addressing of external memory by eight 16-bit datapointers.
Memory Organisation
According to the SAB 8051 architecture, the SAB 80C517A has separate address spaces for
program and data memory. Figure 2 illustrates the mapping of address spaces.
www.DataSheet4U.com
Figure 2
Memory Map
Accesses to XRAM
Because the XRAM is used in the same way as external data memory the same instruction
types must be used for accessing the XRAM.
Note: If a reset occurs during a write operation to XRAM, the effect on XRAM depends on the
cycle which the reset is detected at (MOVX is a 2-cycle instruction):
Reset detection at cycle 1: The new value will not be written to XRAM. The old value
is not affected.
Reset detection at cycle 2: The old value in XRAM is overwritten by the new value.
www.DataSheet4U.com
Bit Function
XMAP0 Global enable/disable bit for XRAM memory.
XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is en-
abled.
XMAP0 = 1: The access to XRAM is disabled. All MOVX accesses are per-
formed by the external bus (reset state).
XMAP1 Control bit for RD/WR signals during accesses to XRAM; this bit has no
effect if XRAM is disabled (XMAP0 = 1) or if addresses exceeding the
XRAM address range are used for MOVX accesses.
XMAP1 = 0: The signals RD and WR are not activated during accesses
to XRAM.
XMAP1 = 1: The signals RD and WR are activated during accesses to
XRAM.
Table 1:
Behaviour of P0/P2 and RD /WR during MOVX accesses
=0 EA =1
EA
XMAP1, XMAP0 XMAP1, XMAP0
00 10 X1 00 10 X1
DPTR < XRAM a) P0/P2ÝBus a) P0/P2ÝBus a) P0/P2ÝBus a) P0/P2ÝBus a) P0/P2ÝBus a) P0/P2ÝBus
address
b) RD /WR active b) RD /WR active b) RD /WR active b) RD /WR active b) RD /WR active b) RD /WR active
range
c) ext. memory is c) ext. memory is c) ext. memory is c) ext. memory is c) ext. memory is c) ext. memory is
MOVX used used used used used used
@DPTR
DPTR ≥ XRAM a) P0/P2ÝBUS a) P0/P2ÝBUS a) P0/P2ÝBus a) P0/P2ÝI/0 a) P0/P2ÝBUS a) P0/P2ÝBus
address ( WR -Data only) ( WR -Data only) b) RD /WR active b) RD /WR inactive ( WR -Data only) b) RD /WR active
range
b) RD /WR inactive b) RD /WR active c) ext. memory is c) XRAM is used b) RD /WR active c) ext. memory is
c) XRAM is used c) XRAM is used used c) XRAM is used used
24
SAB 80C517A/83C517A-5
addr. page ( WR -Data only) ( WR -Data only) P2ÝI/0 b) RD /WR inactive ( WR -Data only) P2ÝI/0
range P2ÝI/0 P2ÝI/0 b) RD /WR active c) XRAM is used P2ÝI/0 b) RD /WR active
b) RD /WR inactive b) RD /WR active c) ext. memory is b) RD /WR active c) ext. memory is
c) XRAM is used c) XRAM is used used c) XRAM is used used
Multiple Datapointers
As a functional enhancement to standard 8051 controllers, the SAB 80C517A contains eight
16-bit datapointers. The instruction set uses just one of these datapointers at a time. The
selection of the actual datapointer is done in special function register DPSEL (data pointer
select, addr. 92H). Figure 3 illustrates the addressing mechanism.
- - - - - .2 .1 .0
DPSEL(92 H) DPTR7
DPSEL Selected
Data-
.2 .1 .0 pointer
0 0 0 DPTR 0
DPTR0
0 0 1 DPTR 1
0 1 0 DPTR 2 DPH(83 H ) DPL(82 H)
0 1 1 DPTR 3
1 0 0 DPTR 4
External Data Memory
1 0 1 DPTR 5
MCD00779
1 1 0 DPTR 6
1 1 1 DPTR 7
w w w . D a t a S h e e t 4 U . c o m
Figure 3
Addressing of External Data Memory
Table 2
Special Function Register
Table 2
Special Function Register (cont’d)
Table 2
Special Function Register (cont’d)
www.DataSheet4U.com
Table 3
Special Function Registers - Functional Blocks
Table 3
Special Function Registers - Functional Blocks (cont’d)
Table 3
Special Function Registers - Functional Blocks (cont’d)
Table 3
Special Function Registers - Functional Blocks (cont’d)
www.DataSheet4U.com
A/D Converter
In the SAB 80C517A a new high performance / high-speed 12-channel 10-bit A/D-Converter is
implemented. Its successive approximation technique provides 7 µs con-version time (fOSC= 16
MHz). The conversion principle is upward compatible to the one used in the SAB 80C517. The
main functional blocks are shown in figure 4.
The comparator is a fully differential comparator for a high power supply rejection ratio and very
low offset voltages. The capacitor network is binary weighted providing genuine 10-bit
resolution.
The table below shows the sample time T S and the conversion time T C, which are dependend
on f OSC and a new prescaler (see also Bit ADCL in SFR ADCON 1).
www.DataSheet4U.com
www.DataSheet4U.com
Figure 4
Block Diagram A/D Converter
www.DataSheet4U.com
Table 4
CCU Compare Configuration
www.DataSheet4U.com
Figure 5
Block Diagram of the Compare/Capture Unit
Compare
In compare mode, the 16-bit values stored in the dedicated compare registers are compared
to the contents of the timer 2 register or the compare timer register. If the count value in the
timer registers matches one of the stored value, an appropriate output signal is generated at
the corresponding pin(s) and an interrupt is requested. Three compare modes are provided:
Mode 0: Upon a match the output signal changes from low to high.
It returns to low level at timer overflow.
Mode 1: The transition of the output signal can be determined by software.
A timer overflow signal does not affect the compare-output.
Mode 2: In compare mode 2 the concurrent compare output pins on Port 5 are used
as follows (see figure 9)
– When a compare match occurs with register COMSET, a high level
appears at the pins of port 5 whose corresponding bits in the mask
register SETMSK (address 0A5H) are set.
– When a compare match occurs in register COMCLR, a low level
appears at the pins of port 5 whose corresponding bits in the mask
register CLRMSK (address 0A6H) are set.
Additionally the Port 5 pins used for compare mode 2 may also be
directly written to by write instructions to SFR P5. Of course, the pins
can also be read under program control.
Compare registers CM0 to CM7 use additional compare latches when operated in mode 0.
Figure 8 shows the function of these latches. The latches are implemented to prevent from loss
of compare matches which may occur when loading of the compare values is not correlated
with the timer count. The compare latches are automatically loaded from the compare registers
at every timer overflow.
www.DataSheet4U.com
Capture
This feature permits saving of the actual timer/counter contents into a selected register upon
an external event or a software write operation. Two modes are provided to 'freeze' the current
16-bit value of timer 2 registers into a dedicated capture register.
Mode 0: Capture is performed in response to a transition at the corresponding
port 1 pins CC0 to CC3.
Mode 1: Write operation into the low-order byte of the dedicated capture register
causes the timer 2 contents to be latched into this register.
Reload of Timer 2
A 16-bit reload can be performed with the 16-bit CRC register, which is a concatenation of the
8-bit registers CRCL and CRCH. There are two modes from which to select:
Mode 0: Reload is caused by a timer overflow (auto-reload).
Mode 1: Reload is caused in response to a negative transition at pin T2EX (P1.5),
which can also request an interrupt.
Timer/Counters 0 and 1
These timer/counters are fully compatible with timer/counter 0 or 1 of the SAB 8051 and can
operate in four modes:
Mode 0: 8-bit timer/counter with 32:1 prescaler
Mode 1: 16-bit timer/counter
Mode 2: 8-bit timer/counter with 8-bit auto reload
Mode 3: Timer/counter 0 is configured as one 8-bit timer;
timer/counter 1 in this mode holds its count.
External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters
0 and 1 to facilitate pulse width measurements.
www.DataSheet4U.com
www.DataSheet4U.com
Figure 6
Block Diagram of Timer 2
f OSC /2
3-Bit Prescaler Compare Timer
Control (CTCON)
16
To Compare
Circuitry
To Interrupt
16-Bit Compare Timer CTF
Circuitry
Overflow
MCB00783
Figure 7
Block Diagram of the Compare Timer
www.DataSheet4U.com
Figure 8
Compare-Mode 0 with Registers CM0 to CM7
www.DataSheet4U.com
Figure 9
Compare-Mode 2 (Port 5 only)
Interrupt Structure
The SAB 80C517A has 17 interrupt vectors with the following vector addresses and request
flags.
Table 5
Interrupt Sources and Vectors
Each interrupt vector can be individually enabled/disabled. The response time to an interrupt
request is more than 3 machine cycles and less than 9 machine cycles.
External interrupts 0 and 1 can be activated by a low-level or a negative transition (selectable)
at their corresponding input pin, external interrupts 2 and 3 can be programmed for triggering
on a negative or a positive transition. The external interrupts 2 to 6 are combined with the
corresponding alternate functions compare (output) and capture (input) on port 1.
For programming of the priority levels the interrupt vectors are combined to pairs or triples.
Each pair or triple can be programmed individually to one of four priority levels by setting or
clearing one bit in special function register IP0 and one in IP1. Figure 9 shows the interrupt
request sources, the enabling and the priority level structure.
www.DataSheet4U.com
Figure 10
Interrupt Structure of the SAB 80C517A
www.DataSheet4U.com
Figure 10
Interrupt Structure of the SAB 80C517A (cont'd)
www.DataSheet4U.com
Figure 10
Interrupt Structure of the SAB 80C517A (cont'd)
Multiplication/Division Unit
This on-chip arithmetic unit provides fast 32-bit division, 16-bit multiplication as well as shift
and normalize features. All operations are integer operation.
32-bit normalize – – 6 t cy 2)
The MDU consists of six registers used for operands and results and one control register.
Operation of the MDU can be divided in three phases:
www.DataSheet4U.com
To start an operation, register MD0 to MD5 (or ARCON) must be written to in a certain se-
quence according to table 5 or 6. The order the registers are accessed determines the type of
the operation. A shift operation is started by a final write operation to register ARCON (see also
the register description).
I/O Ports
The SAB 80C517A has seven 8-bit I/O ports and two input ports (8-bit and 4-bit wide).
Port 0 is an open-drain bidirectional I/O port, while ports 1 to 6 are quasi-bidirectional I/O ports
with internal pull-up resistors. That means, when configured as inputs, ports 1 to 6 will be
pulled high and will source current when externally pulled low. Port 0 will float when configured
as input.
Port 0 and port 2 can be used to expand the program and data memory externally. During an
access to external memory, port 0 emits the low-order address byte and reads/writes the data
byte, while port 2 emits the high-order address byte. In this function, port 0 is not an open-drain
port, but uses a strong internal pull-up FET. Port 1, 3, 4, 5 and port 6 provide several alternate
functions. Please see the "Pin Description" for details.
Port pins show the information written to the port latches, when used as general purpose port.
When an alternate function is used, the port pin is controlled by the respective peripheral unit.
Therefore the port latch must contain a "one" for that function to operate. The same applies
when the port pins are used as inputs. Ports 1, 3, 4 and 5 are bit- addressable.
The SAB 80C517A has two dual-purpose input ports. The twelve port lines at port 7 and port
8 can be used as analog inputs for the A/D converter. If input voltages at P7 and P8 meet the
specified digital input levels (VIL and VIH) the port can also be used as digital input port.
In Hardware Power Down Mode the port pins and several control lines enter a floating state.
For more details see the section about Hardware Power Down Mode.
www.DataSheet4U.com
Idle Mode
During idle mode all peripherals of the SAB 80C517A (except for the watchdog timer) are still
supplied by the oscillator clock. Thus the user has to take care which peripheral should
continue to run and which has to be stopped during Idle.
The procedure to enter the idle mode is similar to the one entering the power down mode. The
two bits IDLE and IDLS must be set by two consecutive instructions to minimize the chance of
www.DataSheet4U.com
unintentional activating of the idle mode.
There are two ways to terminate the idle mode:
– The idle mode can be terminated by activating any enabled interrupt. This interrupt will
be serviced and the instruction to be executed following the RETI instruction will be the
one following the instruction that set the bit IDLS.
– The other way to terminate the idle mode, is a hardware reset. Since the oscillator is
still running, the hardware reset must be held active only for two machine cycles for
a complete reset.
Normally the port pins hold the logical state they had at the time idle mode was activated. If
some pins are programmed to serve their alternate functions they still continue to output during
idle mode if the assigned function is on. The control signals ALE and hold at logic high levels
PSEN (see table 8).
– First the pins leave their floating condition and enter their default reset state
(as they had immediately before going to float state).
– Both oscillators are enabled (only if OWE = high). The oscillator watchdog’s RC
oscillator starts up very fast (typ. less than 2 microseconds)
microseconds).
– Because the oscillator watchdog is active it detects a failure condition if the
on-chip oscillator hasn’t yet started. Hence, the watchdog keeps the part in reset
and supplies the internal clock from the RC oscillator.
– Finally, when the on-chip oscillator has started, the oscillator watchdog releases
the part from reset with oscillator watchdog status flag not set
set.
When automatic start of the watchdog was enabled (PE/SWD connected to VCC),
the Watchdog Timer will start, too (with its default reload value for time-out period).
– The Reset pin overrides the Hardware Power Down function, i.e. if reset gets active
during Hardware Power Down it is terminated and the device performs the normal
reset function. (Thus, pin Reset has to be inactive during Hardware Power Down Mode).
Table 8
Status of all pins during Idle Mode, Power Down Mode and Hardware Power
Down Mode
Table 8
Status of all pins during Idle Mode, Power Down Mode and Hardware Power
Down Mode (cont’d)
Serial Interfaces
The SAB 80C517A has two serial interfaces. Both interfaces are full duplex and receive
buffered. They are functionally identical with the serial interface of the SAB 8051 when working
as asynchronous channels. Serial interface 0 additionally has a synchronous mode. Table 9
shows possible configurations and the according baud rates.
Table 9
Baud Rate Generation
Mode Mode 0 –
Serial Interface 0
Serial Interface 0 can operate in 4 modes:
The default value after reset in the reload registers S0RELL and S0RELH provide a baud rate
of 4.8 kBaud (SMOD = 0) or 9.6 kBaud (SMOD = 1) at 12 MHz oscillator frequency. This guar-
antees full compatibility to the SAB 80C517.
Serial Interface 1
Serial interface 1 can operate in two asynchronous modes:
www.DataSheet4U.com
Watchdog Units
The SAB 80C517A offers two enhanced fail safe mechanisms, which allow an automatic
recovery from hardware failure or software upset:
– programmable watchdog timer (WDT), variable from 512 µs up to appr. 1.1 s time-out
period @12 MHz. Upward compatible to SAB 80515 watchdog.
– oscillator watchdog (OWD), monitors the on-chip oscillator and forces the micro-
controller into reset state, in case the on-chip oscillator fails, controls the restart from
the Hardware Power Down Mode and provides clock for a fast internal reset after power-on.
www.DataSheet4U.com
Figure 11
Block Diagram of the Programmable Watchdog Timer
Oscillator Watchdog
The unit serves three functions:
– Monitoring of the on-chip oscillator’s function.
The watchdog supervises the on-chip oscillator’s frequency; if it is lower than the
frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is
supplied by the RC oscillator and the device is forced into reset; if the failure condition
disappears (i.e. the on-chip oscillator has again a higher frequency than the RC oscillator),
the part executes a final reset phase of appr. 0.25 ms in order to allow the oscillator
to stabilize; then the oscillator watchdog reset is released and the part starts
program execution again.
– Restart from the Hardware Power Down Mode.
If the Hardware Power Down Mode is terminated the oscillator watchdog has to control
the correct start-up of the on-chip oscillator and to restart the program. The oscillator
watchdog function is only part of the complete Hardware Power Down sequence; however,
the watchdog works identically to the monitoring function.
– Fast internal reset after power-on.
In this function the oscillator watchdog unit provides a clock supply for the reset before
the on-chip oscillator has started. In this case the oscillator watchdog unit also
works identically to the monitoring function.
If the oscillator watchdog unit is to be used it must be enabled (this is done by applying high
level to the control pin OWE).
Figure 12 shows the block diagram of the oscillator watchdog unit. It consists of an internal RC
oscillator which provides the reference frequency of the on-chip oscillator. The RC oscillator
can be enabled/disabled by the control pin OWE. If it is disabled the complete unit has no
function.
www.DataSheet4U.com
Figure 12
Functional Block Diagram of the Oscillator Watchdog
www.DataSheet4U.com
Instruction Set
The SAB 80C517A / 83C517A-5 has the same instruction set as the industry standard 8051
microcontroller.
A pocket guide
www.DataSheet4U.com is available which contains the complete instruction set in functional and
hexadecimal order. Furtheron it provides helpful information about Special Function Registers,
Interrupt Vectors and Assembler Directives.
Literature Information
Note Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (VIN > VCC or V IN <
VSS) theVoltage on VCC pins with respect to ground (VSS) must not exeed the values
definded by the absolute maximum ratings.
DC Characteristics
VCC = 5 V + 10 %, – 15 %; VSS = 0 V
TA= 0 to 70 oC for the SAB 80C517A/83C517A-5
T A = – 40 to 85 oC for the SAB 80C517A-T3/83C517A-5-T3
T A = – 40 to 110 oC for the SAB 80C517A-T4/83C517A-5-T4
min. max.
www.DataSheet4U.com
Input low voltage VIL – 0.5 0.2 VCC – V –
(except EA, RESET, HWPD) 0.1
Input low voltage (EA) VIL1 – 0.5 0.2 VCC – V –
0.3
Input low voltage (HWPD, VIL2 – 0.5 0.2 V C C V –
RESET) + 0.1
Input high voltage (except VIH 0.2 VCC VCC + 0.5 V –
RESET, XTAL2 and HWPD + 0.9
Input high voltage to XTAL2 VIH1 0.7 VCC VCC + 0.5 V –
Input high voltage to RESET VIH2 0.6 VCC VCC + 0.5 V –
and HWPD
DC Characteristics (cont’d)
min. max.
2) Capacitive loading on ports 0 and 2 may cause the V OH on ALE and PSEN to momentarily
fall below the 0.9 V C C specification when the address lines are stabilizing.
5) ICC (Idle mode) is measured with all output pins disconnected and with all peripherals
disabled; XTAL2 driven with tCLCH, t CHCL = 5 ns, V IL = VSS + 0.5 V, VIH = VCC – 0.5 V;
XTAL1 = N.C.; RESET = VCC; HWPD = VCC; Port0 = Port7 = Port8 =VCC ;
EA = PE/SWD = VSS; all other pins are disconnected;
www.DataSheet4U.com
6) ICC (slow down mode) is measured with all output pins disconnected and with all peripher-
als disabled; XTAL2 driven with tCLCH, t CHCL = 5 ns, VIL = VSS + 0.5 V, VIH =VCC – 0.5 V;
XTAL1 = N.C.;RESET= VCC; HWPD = VCC; Port7 = Port8 = VCC; EA = PE/SWD = VSS ;
all other pins are disconnected;
ADCL ADCL
1) ) /f
t CY = (8*2 OSC; (tCY = 1/fADC; fADC = fOSC/(8*2 ))
2)
This parameter specifies the time during the input capacitance CI, can be charged/discharged by the
external source. It must be guaranteed, that the input capacitance CI,, is fully loaded within this time.
4TCY is 2 µs at the fOSC= 16 MHz. After the end of the sample time T S, changes of the analog input
voltage have no effect on the conversion result.
3)
This parameter includes the sample time T S. 14TCY is 7 µs at fOSC = 16 MHz.
www.DataSheet4U.com
4)
The differencial impedance rD of the analog reference source must be less than 1 KΩ at reference supply
voltage.
AC Characteristics
V CC = 5 V + 10 %, – 15 %; V SS = 0 V
TA= 0 to 70 oC for the SAB 80C517A/83C517A-5
T A = – 40 to 85 oC for the SAB 80C517A-T3/83C517A-5-T3
T A = – 40 to110 o C for the SAB 80C517A-T4/83C517A-5-T4
(C L for port 0, ALE and PSEN outputs = 100 pF; C L for all other outputs = 80 pF)
AC Characteristics (cont’d)
t LHLL
ALE
t AVLL t PLPH
t LLPL
t LLIV
t PLIV
PSEN
t AZPL t PXAV
t LLAX t PXIZ
t PXIX
Port 0 A0 - A7 Instr.IN A0 - A7
t AVIV
MCT00096
www.DataSheet4U.com
t WHLH
ALE
PSEN
t LLWL t WLWH
WR
t QVWX
t AVLL t WHQX
t LLAX2
t QVWH
A0 - A7 from A0 - A7 Instr.IN
Port 0 Data OUT
Ri or DPL from PCL
t AVWL
MCT00098
www.DataSheet4U.com
Data Memory Write Cycle
AC Characteristics (cont'd)
Variable clock
Frequ. = 3.5 MHz to 18 MHz
min. max.
www.DataSheet4U.com
AC Characteristics (cont'd)
www.DataSheet4U.com
min. max.
ROM Verification Mode 1 (Standard Verify Mode for not Read Protected ROM)
www.DataSheet4U.com
ROM Verification Mode 2 (New Verify Mode for Protected and not Protected ROM)
www.DataSheet4U.com
www.DataSheet4U.com
AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measure-
ments are made at VIHmin for a logic ’1’ and VILmax for a logic ’0’.
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and
begins to float when a 100 mV change from the loaded V OH/V OL level occurs. IOL/IOH ≥ ± 20 mA.
www.DataSheet4U.com
GPM05623
www.DataSheet4U.com
Figure 1
P-MQFP-100-2 Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device Dimensions in mm
GPM05623
www.DataSheet4U.com
Figure 2
P-LCC-84-2 Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device Dimensions in mm