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UNIT-4 The Memory System
Memory Hierarchy, Main Memory, Auxiliary Memory, Associative Memory, Cache Memory, Virtual
Memory.
4.1 Memory Hierarchy
The memory unit is an essential component in any digital computer since it is needed for storing
programs and data. The memory unit is communicates directly with the CPU is called “Main Memory”.
Only programs and data which are currently needed by the processor is reside in main memory. Initially
programs are stored in auxiliary memory that means all the information is stored in auxiliary memory
and transferred into main memory when needed.
The devices that provide backup storage are called “Auxiliary Memory”. The most commonly
used auxiliary memory devices in digital computers are magnetic disks and magnetic tapes. They are
used for storing system programs, large data files and other backup information.
Cache is a fast access and small capacity memory that should hold those information which are most
likely to be accessed. I/O processor is an interface between auxiliary memory and main memory. The
main memory and cache memory are directly connected to CPU. The block diagram is shown below:
Block diagram for different memories
Suppose a typical cache memory may have an access time of 100ns, while main memory access
time may be 700. i. e 1:7 ratio between cache and main memory. Auxiliary memory access time is
usually 1000 times that of main memory. Block size in cache memory is 1 to 16 words and auxiliary
memory is 256 to 2048 words.
In a memory hierarchy system, programs and data are first stored in auxiliary memory. Portions
of a programs or data are brought into main memory when they are needed by the CPU. Many
operating systems performs multiple operation in CPU at a time is called as “Multiprogramming”.
Memory hierarchy block diagram is shown below:
Computer Organization(R13) DEPT OF CSE Page 1

Memory hierarchy block diagram
4.2 Main Memory:
The main memory is a central storage unit in a computer system. It is relatively large and fast access
time memory used to store programs and data during computer operations. The principal technology
used for main memory is based on semiconductor integrated circuits. The integrated circuits RAM chips
are two types:
1) Static RAM
2) Dynamic RAM
The Static RAM consists of an internal flip-flop that stores the binary information. The stored
information is valid as long as power is applied to the unit.
The Dynamic RAM stores the binary information in Capacitors. The capacitors are inside chips by MOS
transistors. So they need electrical charges sequentially or periodically.
Most of the main memories in general purpose computers made up of RAM integrated circuit chips, but
a portion of the memory may be constructed with ROM chips.
The ROM portion of main memory is needed for storing an initial program called “Boot Strap loader”. It
is an initial program to start the computer software operating when power is turned on.

Differences between SRAM and DRAM:
Static RAM Dynamic RAM
Binary information is stored in internal flip-flops. Binary information is stored in capacitors.
It does not require electrical charge. It requires electrical charges to charge periodically.
The information is valid until the power supply is The information is valid before computer is turn
applied to unit. off.
It is easier to use and has shorter read and write It is a large storage capacity in a single memory
cycles. Because size of SRAM is less. unit. It's access time is slow.
It implements cache memory It implements main memory. Most of PC's are
DRAMs
RAM and ROM Chips:
RAM chip is better suited for communication with the CPU. If it has one or more control inputs
that select the chips (CS1, CS2) when needed. One feature is bidirectional data bus that allows the
transfer of data either from memory to CPU during read operation; or from CPU to Memory during
“write operation”. RAM and ROM chips are available in a variety of sizes. The block diagram for RAM
and its list of functional operations is shown below

The capacity of RAM memory is 128 bytes * 8 bits. This requires 7 bit address and an 8 bit bidirectional
data bus. The read and write inputs specify the memory operation and two chips select (CS1, CS2’)
control inputs are for enabling the chip only when it is selected by the microprocessor. The function
table specifies the operation of the RAM when CS1=1 and CS2’=0.
The capacity of ROM is 512 Bytes * 8 bits and ROM has nine address lines, two chips (CS1, CS2’).
The ROM have only one directional data transfer. The block diagram of ROM is shown below
Typical ROM chip
Memory Address Map
The memory address map table consists of RAM, ROM, chips, and hexadecimal address. The memory
address table is shown in below with different operations:
Memory connection to CPU
RAM and ROM chips are connected to a CPU through the data and address buses. The RAM selects
seven low-order bits of the address bus to select one of 128 possible bytes. The particular RAM chip
selected is determined from lines 8 and 9 are equal to 00, the first RAM chip is selected. When 01, the
second RAM chip is selected, and so on. The RD and WR outputs from the micro processor are applied to
the inputs of each RAM chip. The selection between RAM and ROM is achieved through bus line10. The
diagram for memory connection to CPU is below:

Memory connection to CPU

4.3 Auxiliary Memory:
The most common auxiliary memory devices used in computer systems are magnetic disks and magnetic
tapes. Other components used in computer systems are magnetic drums, magnetic bubble memory and
optical disks are not frequently used. The important characteristics of any device are Access mode,
Access Time, Transfer Rate, and capacity of cost.
Access Time: The average time required to reach a storage location in memory and obtain its contents is
called as “access time”.
Seek Time: Time to position heads over cylinder containing target sector.
Typical Tavg seek time is 3 – 9 ms.
Rotational Time: Waiting time for rotation from first bit of target sector to pass under read write head.
Tavg Rotational time= 1/2 * 1/RPM * 60 sec.
Transfer Time: The time to read bits in the target time while transferring data.
Tavg Transfer Time= 1/ RPM * 1/ (avg no.of sectors/track) * 60 sec.
Therefore, Taccess time= Tavg seek time + Tavg rotational time + Tavg transfer time
Example:
What is the access time from given data Tavg seek time = 6ms; Rotation per minute (RPM)=7200;
avg number of sectors is = 400.
Solution: Given that Tavg seek time=6ms; RPM=7200; and avg number of sectors = 400
Tavg rotational time = 1/2 * 1/RPM * 60 sec
= 1/2 * 1/7200 * 60 sec
= 0.041 sec (1 sec = 1000ms)
= 4.1 ms
Tavg Transfer time = 1/ RPM * 1/ (avg no.of sectors/track) * 60 sec
= 1/7200 * 1/400 * 60 sec
= 0.02 ms
therefore Taccess = Tavg seek time + Tavg rotational time + Tavg transfer time;
= 6 ms + 4.1 ms + 0.02ms => 10.12 ms

4.3.1 Magnetic Disks:
 A magnetic disk consists of magnetic, electronics and electromechanical systems.
 A magnetic disk is a circular plate constructed of metal or plastic coated with magnetic material
often both sides of the disk are used and several disks may be stacked on one spindle with
read/write heads available on each surface.
 Disk consists of Platters, each platter have 2 Surfaces.
 Each surface consists of concentric rings called Tracks.
 Each track consists of sectors separated by gaps. Sectors store byte of information.
 Bits are stored in the magnetized surface in spots along concentric circles called “Tracks”
 The tracks are commonly sub divided into sectors. Each sector consists of bytes of information.
 Disks follows only anti-clockwise-direction.
 Disks are permanently attached to the unit are called “Hard Disk”.
 Flash memory is a USB device like “Pendrive”.
 A disk drive with removable disk is called as “Floppy Disk, CD-Disk”. The block diagram for magnetic
disk is shown below
Block diagram for magnetic disk

4.3.2 Magnetic Tapes:
 A magnetic tape transport consists of the magnetic, electrical and electronics components to
provide parts and control mechanism for a magnetic tape unit.
 The magnetic tape is coated with plastic with a magnetic recording medium.
 Bits are stored in recorded magnetic spots on the tape along several tracks.

 Records may be fixed or variable in length. Each record store group of characters. The records are
accessed sequentially one after another.
 The record information is automatically removed after some period of when not in use.
 Magnetic tapes data can be stopped, started to move forward or in reverse, or can be rewound.
 The information is recorded in blocks.
4.4 Associative Memory

The associative memory is used to search an items in a table stored in memory. A
memory unit accessed by the contents is called an “associative memory or content
addressable memory”. This type of memory is accessed simultaneously and in parallel on the
basis of data content rather than by specific address or location. The searches can be done on
an entire word or an specific field in a word. Each word in memory is compared in parallel with
the content of the argument registers. The key register provides a mask for choosing or
identifying a particular field or key in the argument register word.
Hardware Organization
The block diagram of an associative memory consists of a memory array and logic for w words
with n bits per word. The argument register A and key register K each have n bits, one for each
bit of a word. The match register M has m bits, one for each memory word. Each word in
memory is compared in parallel with the content of the argument register. The words that
match the bits of the argument register set a corresponding bit in the match register depends
on key register.
If the key register contains one then the entire word is compared with argument
register; suppose both the values are equal match found else match not found. Otherwise (k=0)
it will not perform search operation on argument register and word.
Associative memory of m words and n cells
The block diagram for associative memory is below
The relation between the memory array and external registers in an associative memory with
individual cell representation is shown below. Each cell have n number of bits and m number of
words. The word is denoted by C symbol. Each cell in m words is denoted by C ij where j is a
middle bit in word i. The match logic is denoted by Mi, where i=1,2,3…….n.
Associative memory of m word, n cells per word

Match Logic:
The match logic for each word can be derived from the comparision algorithm for two
binary numbers. Here compare the argument register A with the bits stored in the cells of the

words. The formula for match logic of individual bits is : where
j=1,2,3……n. Two bits are equal if they are both 1 or both 0. Where Xj=1 if the pair of bits in
position j are equal; otherwise, Xj=0. It consists of two AND gates, one NOT gate and one OR
gate. It is explained in match logic for one word of associative memory diagram is shown below.
For a word I to be equal to the argument in A we must have all X j variables equal to 1.
This is the condition for setting the corresponding match bit Mi to 1. The boolean function for
this entire word is: and constitutes the AND operation
of all pairs of matched bits in a word. One cell of associative memory is shown below.
One cell of associative memory
Match logic for one word of associative memory
Draw backs of Associative memory:
 It takes more time for searching word.

 It takes entire match logic circuit, so it wastes memory.
 It is more expensive than a random access memory because each cell must have storage
capacity and as well as match logic circuit.

4.5 Cache memory
Cache is a fast accessing and small capacity memory that should hold those information
which are most likely to be accessed.
Locality of Reference: The reference to memory at any given interval of time tends to be
confined within a few localized areas in memory. This phenomenon is called as “Property of
locality of reference”.
Cache Hit: When the CPU refers to memory and finds the word in cache memory.
Cache Miss When the CPU refers to memory and the word is not found in cache memory.
Cache memory diagram
In the above diagram, the CPU communicates with both memories. It first sends a 15-bit
address to cache. If there is a hit, the CPU accepts the 12-bit data from cache. If there is a miss,
the CPU reads the word from main memory and the word is then transferred to cache. All the
memory accesses are directly communicates with cache.
Therefore hit ratio = hit / (hit + miss);
The cache memory mapping techniques are classified into 3 types:

4.5.1. Associative Mapping
4.5.2. Direct Mapping
4.5.3. Set associative Mapping
4.5.1 Associative Mapping:
The associative memory implements a mapping table stored in memory. The mapping table
consists of both address and content of the memory. The cache memory represents bits in octal
format. The size of cache memory is 512 * 12; here it contains 12 data lines and 512 is the
address lines. So 512 = 2^9 i.e 9 address lines in cache memory. The octal format of 12 data bits
takes 4 digits and 9 address lines takes 3 digits.

The size of main memory is 32 KB * 12; here it consists of 12 bits of data and 32 * 1024 bytes of
the address lines. So 32 * 1024 = 2^15 i.e 15 address bits in main memory. The octal format of
12 data bits takes 4 digits and 15 address lines takes 5 digits.
If the address is found, the corresponding 12 bit data is read and sent to the CPU. If no match
occurs, the main memory is accessed for the word. The address-data pair is then transferred to
the associative cache memory.
Associative mapping cache

Drawback:
It is more expensive than a random access memory because each cell must have storage
capacity and as well as entire match logic circuit is needed.
4.5.2 Direct Mapping:

The CPU address is divided into 2 parts. They are Tag field and index field. The nine least
significant bits constitute the index field and the remaining six bits constitute the tag field. The
below figure shows that the main memory needs an address bits that includes both the tag and
the index bits. The number of bits in the index field is equal to the number of address bits
required to access the cache memory. In general case, there are 2k words in the cache memory
and 2n words in the main memory. The n-bit memory address is divided into two fields: k bits
for the index field and n-k bits for the tag field are shown in below diagram.

Addressing relationships between main and cache memories. CPU Address
Direct mapping cache organization Direct mapping cache with block size of 8 words
In the Direct mapping cache diagram, the index is divided into two parts: the block field and the
word field. In a 512-word cache there are 64 blocks of 8 words each, since 64 * 8 = 512. The
block number is specified with a 6-bit field and the word within the block is specified with a 3-
bit field.
Drawback:
It is not allowed two words with the same index in their address but with different tag
values cannot reside in cache memory at the same time.
4.5.3 Set Associative Mapping

It is an improvement over the direct mapping organization in that each word of cache
can store two or more words of memory under the same index address. Each data word is

stored together with the its tag and the number tag-data items in one word of cache is said to
form a set. Set Associative Mapping is classified into 3 types:
4.5.3.1 2-way Set Associative Mapping.


In 2-way Set Associative Mapping, single index contains only two tags at a time. If we
need third tag data then it takes data from main memory and removes one tag-data in the
given tag value. It is shown in diagram below.
2-way Set Associative Mapping.

4.5.3.2 4-way Set Associative Mapping:
In 4-way Set Associative Mapping, single index contains four tags at a time. If we need
th
5 tag-data then it removes one tag-data from the given tag value.
4.5.3.3 4-way Set Associative Mapping:

In 8-way Set Associative Mapping, single index contains eight tags at a time. It stores
entire tag-data once.
4.5.4 Writing into cache
An important aspect of cache organization is concerned with memory write requests. When the
CPU finds a word in cache during a read operation, the main memory is not involved in the
transfer. However, if the operation is a write, there are two ways that the system can proceed.
Write Through Policy: In this method, both cache memory and main memory areas are
updated at a same time that means operations are performed parallel.

Write Back Policy: In this method, First cache memory is updated next main memory is
updated.
Cache Initialization: In cache memory initially cache memory is empty, that means no valid
data. After some operations it has some valid data.
4.6 Virtual Memory:

Virtual memory is a concept used in some large computer systems that permit the user to
construct programs as though a large memory space were available, equal to the auxiliary
memory. A virtual memory system provides a mechanism for translating program generated
address into correct main memory locations.
4.6.1 Address Space and Memory Space:

In Virtual Memory, an address used by a programmer will be called as virtual address,
and the set of virtual addresses is called as Address Space. An address space consists of
programs and data.
In Main Memory, an address used by a programmer will be called as location or physical
address, and the set of such addresses is called a Memory Space. The memory space consists of
the actual main memory locations directly addressable for processing. In most computers both
address space and memory space are identical.
Relation between address and memory space in a virtual memory system.

In a multiprogramming computer system, programs and data are transferred to and
from auxiliary memory and main memory based on demands imposed by the CPU. Suppose
program 1 is currently being executed in the CPU. Program 1 and a portion of its associative
data are moved from auxiliary memory into main memory as shown in below diagram. Portions
of programs and data need not be in contiguous locations in memory since information is
moved in and out, empty spaces may be available in scattered locations in memory.
In virtual memory system, programmers use a main-memory capacity of 32KB and

virtual memory capacity is 1024KB. Programmers told that they have 20-bit address from virtual

memory and 15 bit address main memory. Thus data transfer in CPU will reference instruction
and data with 20 bits to 15-bits at a time is not possible. So we are using memory mapping
table to overcome this problem. It is shown memory table for mapping in virtual address in
below diagram.
Address mapping using pages

The table implementation of the address mapping is simplified if the information in the
address space and the memory space are each divided into groups of fixed size. The physical
memory (Main Memory) is broken down into groups of equal size called blocks and page refers
to groups of address space (Virtual Memory). It is shown in address space and memory space
split into groups of 1KB words. Consider a computer with an address space of 8KB and memory
space of 4KB and split each into groups of 1K words. We obtain 8 pages and 4 blocks as shown
in below diagram
Address space and memory space split into groups of 1KB words
The memory-page table consists of eight words, one for each page. The address in the page
table denotes the page number and the content of the word gives the block number where that
page is stored in main memory. The table shows that pages 1,2,5 and 6 are now available in
main memory in blocks 3,0,1, and 2 respectively. A presence bit in each location indicates
whether data is present or not in pages. In virtual memory, 10 bits are used for page data and 3
bits are used for size of pages. Similarly in main memory, 10 bits for data block and 2 bits for
block size. The organization of the memory mapping table in a paged system is shown in below.

Mapping table in a paged system
Associative Memory Page Table

A random-access memory page table is inefficient with respect to storage utilization. In the
example of memory table in a page table, we observe that eight words of memory are needed,
one for each page, but at least four words will always be marked empty because of main
memory cannot accommodate more than four blocks. This problem is rectified in associative
memory with each word in memory containing a page number together with its corresponding
block number. The page field in each word is compared with the page number in the virtual
address. If a match occurs, the word is read from memory and its corresponding block number
is extracted. It is shown in below diagram.
An associative memory page table

In the above diagram, each entry in the associative memory array consists of two fields. The
first three bits specify a field for storing the page number. The last two bits constitute a field for
storing the block number.

Page Replacement
A virtual memory system is a combination of hardware and software techniques. The

memory management software system handles all the software operations for the efficient
utilization of memory space. It checks 3 conditions:
1: which page in main memory ought to be removed to make room for a new page.
2: when a new page is to be transferred from auxiliary memory to main memory.
3: where the page is to be placed in main memory.
Suppose a page is not in main memory is called “page fault”. Then we brought data
from auxiliary memory. It is followed 2 page replacement algorithms LRU and FIFO.
The FIFO (First in first out) algorithm selects for replacement the page that has been in memory
the longest time. Each time page is loaded into memory, its identification number is pushed
into a FIFO stack. When FIFO stack is full then remove first inserted page element first.
The LRU (least recently used) policy is more difficult to implement but has been more
attractive on the assumption that the least recently page as in FIFO. When LRU stack is full then
remove least element first.
Differences between Cache Memory and Virtual Memory:
Cache Memory Virtual Memory
Cache memory stores data in block or line Virtual memory stores data in Pages
In cache memory, if data is found- cache hit Here, If data is found – Page hit else data is
else cache miss. not found – Page fault.
Block size is: Bytes Block size is: Kbytes
It has Associative mapping, Direct mapping, It have only Fully Associative mapping.
and set-Associative mapping.
Cache memory follows LRU Page replacement Virtual memory follows LRU and FIFO Page
algorithms. replacement algorithms.
It uses write through and write back policy. It uses only write back policy.

It is hardware managed. It is both hardware and software managed.
A.SUNEETHA M.Tech(Ph.D)
Asst.Professor
CSE Department

UNIT IV
CHAPTER-2 Input – output organization: peripheral devices, Input – output interface,

Asynchronous data transfer, Modes of Transfer, Priority Interrupts, Direct memory access.
4.1 Peripheral Devices

 The input output devices connected to the computer is called as peripherals. Among the most
common peripherals are keyboards, display units, and printers. Peripherals that provide auxiliary
storage for the system are magnetic disks and tapes.
 The input-output subsystem of a computer, referred to as I/O, provides an efficient mode of
communication between the central system and the outside environment. The most familiar input
device is keyboard that allows a person to enter alphanumeric information directly. Every time a key
is pressed and released, the terminal sends a binary coded character to the computer.
 Monitor: Video monitors are the most commonly used peripherals. The keyboard is an input device
and a display unit is the output device. There are different types of monitors, but the most popular
use a cathode ray tube (CRT). The CRT contains an electronic gun that sends an electronic beam to a
phosphorescent screen in front of tube. The beam can be deflected horizontally and vertically.
 Printer: Printers provide a permanent record on paper of computer output data or text. There are 3
types of character printers: daisywheel, dot matrix, and laser printers.
 The daisywheel printer contains a wheel with the characters placed along the
circumference. To print a character, the wheel rotates to the proper position.
 The dot matrix printer contains a set of dots along the printing mechanism.
 The laser printer uses a rotating photographic drum that is used to imprint the character
images. This pattern transferred onto paper in the same manner as a copying machine.
 Magnetic tape: Magnetic tapes are used mostly for storing files of data. For example, a company's
payroll record. Access is sequential and consists of records that can be accessed one after another as
the tape moves along a stationary read write mechanism. It is one of the cheapest and slowest
methods for storage. Magnetic tapes automatically removed when not in use.
 Magnetic disk: Magnetic disks have high speed rotational surfaces coated with plastic material.
Access is achieved by moving a read write mechanism to a track in the magnetized surface. Disks are
used mostly for bulk storage of programs and data.
4.2 Input-Output Interface
Input-output interface provides a method for transferring information between internal storage
and external I/O devices. Peripherals connected to computer need special communication links for
interfacing them with the central processing unit. Some differences between peripherals and CPU and
memory unit is below:
1: Peripherals are electromechanical and electromagnetic devices and their manner of
operation is different from the operation of the CPU and memory, which are electronic devices.
2: The data transfer rate of peripheral is usually slower than the transfer rate of CPU.
3: Data codes and formats in peripherals differ from the word format in CPU and memory.
4: The operating modes of peripherals are different from each other and each must be
controlled by the CPU.
To resolve these differences, computer systems include special hardware components between
the CPU and peripherals to supervise all input and output transfers. These components are called
interface units because they interface between the processor bus and the peripheral device.
4.2.1 I/O Bus and Interface Modules
A typical communication link between the processor and several peripherals is shown below.
The I/O bus consists of data bus/lines, address bus/lines, and control bus/lines. The I/O bus from the
processor is attached to all peripheral interfaces.
Connection of I/O bus to input output device
The I/O command is a function code and is in essence an instruction that is executed in the
interface and it is attached to peripheral unit. There are 4 types of interfaces: control command, status
command, data output, and input.
Control command: To control the peripheral and interface operations.
Status command: To test the various status conditions in the interface and peripherals.
Data output command: To transfer the data from the bus into one of its registers.
Input command: It is opposite of the data output.
4.2.2 I/O versus Memory Bus

In addition to communicating with I/O, the processor must communicate the memory unit. Like
the I/O bus, the memory bus contains data, address and read/write control lines with IOP. The computer
has independent sets of data, address, and control buses, one for accessing memory and the other for
I/O. This operates done at separate I/O processor(IOP) in addition to the CPU. There are 3 ways to
communicate with memory and I/O:
1: Use two separate buses, one for memory and the other for I/O.
2: Use one common bus for both memory and I/O but have separate control lines for each.
3: Use one common bus for both memory and I/O with common control lines.
The purpose of IOP is to provide an independent pathway for the transfer of information between
external devices and internal memory is shown in below diagram.

Block diagram of computer with IO processor
4.2.3 Isolated versus Memory mapped I/O
Many computers use one common bus to transfer information between memory or I/O and the
CPU. The distinction between a memory transfer and I/O transfer is made through separate read and
write lines. The I/O read and I/O write control lines are enabled during an I/O transfer. The memory read
and memory write control lines are enabled during a memory transfer. This configuration isolates all I/O
interface addresses from the addresses assigned to memory and is referred to as the isolated I/O
method for assigning addresses in a common bus.
In the isolated I/O configuration, the CPU has distinct inputs and output instructions, and each
of these instructions is associated with the address of an interface register. The isolated I/O method
isolates memory and I/O addresses so that memory address values are not affected by the interface
register. The other alternative is to use the same address space for both memory and I/O. This is the
case in computers that employ only one set for read and write signals and do not distinguish between
memory the and I/O address. This configuration is called as memory-mapped I/O. This reduces the
memory address without using an interface register. The CPU can manipulate I/O instructions and
memory reference instructions data directly within memory unit.
4.2.4 Example of I/O interface:

An example of an I/O interface unit consists of two data registers called ports, a control register,
a status register, and timing and control circuits. The interface communicates with the CPU through the
data bus. The chip select and register select inputs determine the address assigned to the interface. The
I/O read and I/O write are two control lines that specify an input or output operations. The four registers
communicate directly with the I/O device attached to the interface. The I/O data to and from the device
can be transferred into either port A or Port B. The control register receives control information from
the CPU. By loading appropriate bits into the control register, the interface and the I/O device. It is
shown in below diagram.

An example of Interface unit
4.3 Asynchronous Data Transfer
The internal operations in a digital system are synchronized by means of clock pulses
supplied by a common pulse generator. That means a single clock pulse for all the devices.
Clock pulses are applied to all registers within a unit and all data transfers among internal
registers occur simultaneously during the occurrence of a clock pulse.
Two units such as a CPU and an I/O interface are designed independently of each other.
If the registers in the interface share a common clock with the CPU registers, the transfer
between the two units is said to be synchronous.
Asynchronous data transfer between two independent units requires that control
signals for transferring between the communicating units to indicate the time at which data is
being transmitted. Asynchronous data transfer can be classified into two types: 1. Strobe pulse
and 2. Hand shaking pulse.

4.3.1 Strobe pulse
The strobe pulse and handshaking method of asynchronous data transfer are not
restricted to I/O transfers. The timing diagram pass timing control signals to asynchronous data
transfer. Initially data is on data bus, before going to transfer data from one unit to other unit it
is checking whether given data is valid data or not with strobe pulse. It is shown in below
diagrams. The first diagrams transfer data from source unit to destination unit. The second
diagram transfer data from source unit to destination but strobe pulse is from destination unit
to source unit. Both the diagrams follow timing signals.
Source initiated strobe for data transfer

Strobe controlled
The strobe control method of asynchronous data transfer employs a single control line
to time each transfer. The strobe may be activated by either source or the destination unit.
Destination initiated strobe for data transfer

The data bus carries the binary information from source unit to the destination unit. Typically, the bus
has multiple lines to transfer an entire byte or word. The strobe is a single line that informs the
destination unit when a valid data word is available in the bus. The source removes the data from the
bus a brief period after it disables its strobe pulse. The data transfer initiated by the destination unit
activates the strobe pulse, informing the source to provide the data. The source unit responds
by placing the requested binary information on the data bus. The data must be valid and
remain in the bus long enough for the destination unit to accept it.

4.3.2 Handshaking
The disadvantage of the strobe method is that the source unit sent the data but it does
not know whether the destination unit has actually received the data item or not. The
handshaking method solves this problem by introducing a second control signal that provides a
reply to the unit that initiates the transfer. This basic principle of the two-wire handshaking
method of data transfer is as follows. One control line is in the same direction as the data flow
in the bus from the source to the destination. It is used by the source unit to inform the
destination unit whether there are valid data in the bus. The other control line is in the other
direction from the destination to the source for accepting data. The two handshaking lines are
data valid and data accepted. The diagrams for source to destination and destination to source
unit is shown below.
Sequence of events
Source initiated data transfer using handshaking
Destination initiated transfer using hand shaking
In the destination initiated transfer using hand shaking method, first ready for data is
active then data on data bus and check whether data is valid or not. Later it transfers data from
source to destination after it disables ready for data and data valid. It is shown in below
diagrams.

(b) Timing diagram
(c) Sequence events

Destination initiated transfer using hand shaking
4.3.3 Asynchronous serial transfer
The transfer of data between two units may be done in parallel or serial. In parallel data
transmission, each bit of the message has its own path and the total message is transmitted at
the same time. This means that an n-bit message must be transmitted through n separate
conductor paths.
In serial data transmission, each bit in the message is sent in sequence one at a time.
This method requires the use of one pair of conductors or one conductor and a common
ground. Parallel transmission is faster but requires many wires. So it is used for short distances
and where speed is important.
Serial transmission can be synchronous or asynchronous. In synchronous transmission,
the two units share a common clock frequency and bits are transmitted continuously at the rate
dictated by the clock pulses. A serial asynchronous data transmission technique used in
many interactive terminals employs special bits that are inserted at both ends of the
character code. With this technique, each character consists of three parts: a start bit,
the character bits, and stop bits.

Asynchronous serial data transfer
The baud rate is defined as the rate at which serial information is transmitted and is equivalent
to the data transfer in bits per second. The circuit representation of data transfer is called as
asynchronous communication interface or a universal asynchronous receiver transmitter
(UART).
4.3.4 Asynchronous Communication Interface
The block diagram of an asynchronous communication interface is shown in below. It
functions as both a transmitter and a receiver. The interface is initialized for a particular mode
of transfer by mean of a control byte that is loaded into its control register.
In asynchronous communication data transfer circuit consists of bus buffer, 4 registers
(transmitter register, receiver register, control register and status register), and timing control.
The transmitter register accepts a data byte from the CPU through the data bus. This byte is
transferred to a shift register for serial transmission. The receiver receives serial information
from other shift register. The bits in the status register to check the status of the flag bits and
for recording certain errors that may occur during transmission.
The chip selection and the read and write control lines communicate with the CPU.
When chip selection (CS) input is 1 then it performs operations. The register selection (RS) is
associated with the read (RD) and write (WR) controls. Two registers are write-only and two are
read-only. It is listed in below diagram.

Asynchronous communication data transfer
4.3.5 First-in, First-out buffer
A first in first out buffer is a memory unit that stores information in such a manner that
the item first in is the item first out. A FIFO buffer comes with separate input and output
terminals. The important feature of this buffer is that it can input data and output data at two
different rates and the output data are always in the same order in which the data entered the
buffer.
The logic diagram of a typical 4 * 4 FIFO buffer is shown in below figure. It consists of
four registers R1,R2,R3,R4 and a control register with flip-flops Fi, i=1,2,3,4 one for each
register. The FIFO can store four words of four bits each. The master clear is a clock pulse to
clear the devices. A flip-flop Fi in the control register that is set to 1 indicates that a 4-bit data
word is stored in the corresponding register RI. Suppose a flip-flop Fi is 0 that indicates
corresponding register does not contain valid data. The control register directs the movement
of data through the registers.
Data are inserted into the buffer provided that the input ready signal is enabled. When
register R1 empty; then data is loaded input lines by enabling the clock in R1 through the insert
control line. This procedure is continuing until four registers full. Later it deletes the data from
first register first and repeats same procedure from register R1 to R4.

Circuit diagram of 4 * 4 FIFO
4.4 Modes of Transfer
Binary information received from an external device is usually stored in memory for
later processing. Information transferred from the central computer into an external device
originates in the memory unit. Data transfer between the central computer and I/O devices
may be handled in a variety of modes. Some modes of transfer are
1. Programmed I/O
2. Interrupt Initiated or driven I/O
3. Direct memory Access (DMA)
4.4.1 Programmed I/O
Programmed I/O operations are the result of I/O instructions written in the computer
program. Each data item transfer is initiated by an instruction in the program. Usually, the
transfer is to and from a CPU register and peripheral. Other instructions are needed to transfer
the data to and from CPU and memory.
4.4.1.2 Example of Programmed I/O
In the programmed I/O method, the I/O device does not have direct access to memory.
A transfer from an I/O device to memory requires the execution of several instructions by the
CPU, including an input instruction to transfer the data from the device to the CPU and a store
instruction to transfer the data from the CPU to memory.
The transfer of each byte from I/O device to CPU requires three instructions:
1. Read the data register

2. Check the status of the flag bit and branch to step1 if not set else go to step3
3. Read the status register.
It is shown in below diagram. It consists of data on data bus and transfer from I/O device to
CPU with an interface while transferring data it is checking whether valid data or not. If data is
valid then send acceptance to I/O device.
Data transfer from I/O device to CPU

Each byte is read into a CPU register and then transferred to memory with a store
instruction. A common I/O programming task is to transfer a block of words from an I/O device
and store them in a memory buffer. It is shown in below flowchart:
Flowchart for CPU program into input data

4.4.2 Interrupt Initiated I/O:
In the programmed I/O method, two problems occurred. First, the CPU stays in a
program loop until the I/O unit indicates that it is ready for data transfer. This is a time
consuming process and sometimes the source program loop is repeated infinite times when a
problem occurred in loops. So it can be avoided by using an interrupt facility and special
commands to inform the interface to issue an interrupt request signal when the data are
available from the device. In the mean time CPU can proceed to execute another program.
When an external interrupt signal is detected, then it stops the task it is processing. The
interrupts are classified into two types:
4.4.2.1 Vectored Interrupt
In vectored interrupt, the source program contains an interrupt.
4.4.2.2 Non Vectored Interrupt:
In non vectored interrupt, the branch address assigned to a fixed location in memory.
4.4.3 Direct Memory Access:
Second drawback of programmed I/O, there is no direct data transfer between CPU and
peripherals. In direct memory access (DMA), removing the CPU from the path and letting the
peripheral device manage the memory buses directly. Here interface register is not used for
transferring data into and out of the memory unit through the memory bus. The CPU initiates
the transfer by supplying the interface with the starting address and the number of words
needed to be transferred and then proceeds to execute other tasks. During DMA transfer, the
CPU is idle and has no control of the memory buses. A DMA controller takes over the buses to
manage the transfer directly between the I/O device and memory.
The CPU may be placed in an idle state in a variety of ways. One common method used
in microprocessors is to disable the buses through special control signals: bus request and bus
grant. The bus request (BR) input is used by the DMA controller to request the CPU to
relinquish control of buses. When the CPU is accepted the bus request then it transfer bus
grant (BG) signal to DMA controller. The CPU performs different address bus, data bus, read
and write operations. It is shown in DMA controller block diagram below.
DMA channel: system pathway used by a device to transfer information directly to and from
memory.
DMA controller: Dedicated hardware used for controlling the DMA operation
Single-cycle mode/ Cycle stealing: In DMA data transfer is done one byte at a time.
Burst-mode/ burst transfer: DMA transfer is finished when all data has been moved. That
means, In DMA burst transfer, a block consisting of a number of memory words is transfer
continuous burst while the DMA controller is master of the memory buses. When the request is
granted by the memory controller, the DMA transfers the data directly into memory.

CPU bus signals for DMA transfer
4.4.3.1 DMA controller
The DMA controller needs the usual circuits of an interface to communicate with the
CPU and I/O device. In addition, it needs an address register, a word count register, and a set of
address lines. The address register and address lines are used for direct communication with
the memory. The address register specifies the address of the memory location. The word
count register specifies the number of words that must be transferred. The data transfer may
be done directly between the device and memory under control of the DMA.
The DMA unit communicates with the CPU via the data bus and control lines. The
registers in the DMA are selected by the CPU through the address bus by enabling the DS (DMA
Select) and RS (Register Select) inputs. The Read (RD) and Write (WR) inputs are bidirectional.
When BG=0 then it is communicate with the DMA register through data bus to read or write to
DMA register else BG=1 then CPU sent message to DMA controller to perform operations.
The CPU initializes the DMA by sending the following information through the data bus:
1. The starting address of the memory block where data are available (read) and where
data to store (write).
2. The word count, which is the number of words in the memory block.
3. Control to specify the mode of transfer such as read or write.
4. A control to start the DMA transfer.
Block diagram of DMA controller

4.4.3.2 DMA Transfer
The position of the DMA controller among the other components in a computer system
consists of DMA controller, CPU, Random-access memory and I/O peripheral devices. The CPU
is communicates with the DMA through the address and data buses as with any interface unit.
The DMA has its own address and data buses as with any interface unit. The CPU initializes the
DMA through the data bus. Once the DMA receives the start control command, it can start the
transfer between the peripherals and memory.
When the peripheral device sends a DMA request, the DMA controller activates the BR
line, informing the CPU to relinquish the buses. The CPU responds with its BG line, informing
the DMA that its buses are disabled. The DMA then puts the current value of its address
register into the address bus initiates the RD or WR signal, and sends a DMA acknowledge to
the peripheral device. Note that the RD and WR lines are bidirectional. For each word that is
transferred, the DMA increments its address registers and decrements its word count register.
If the word count reaches to zero, then stops the DMA and removes the bus request. Else the
DMA check the request line coming from the peripheral.
A DMA controller may have more than one channel. In this case, each channel has a
request and acknowledges pair of control signals which are connected with separate peripheral
devices. Each channel also has its own address register and word count register within the DMA
controller. DMA transfer is very useful in many applications. It is used for fast transfer of
information between magnetic disks and memory. The contents of the memory can be
transferred to the screen periodically by means of DMA transfer. It is shown in diagram below.
DMA transfer in a computer system

4.5 Priority Interrupts
Data transfer between the CPU and an I/O device is initiated by the CPU. However, the
CPU cannot start the transfer unless the device is ready to communicate with the CPU. The
readiness of the device can be determined from an interrupt signal. A priority interrupt is a
system that establishes a priority over various source to destination which condition is to be
serviced first when two or more requests arrive simultaneously. The system may also
determine which conditions are permitted to interrupt the computer while another interrupt is
being serviced. Higher order priority interrupt levels are assigned to requests which if delayed
or interrupted, could have serious consequences.
Priority interrupts are classified into two types:

4.5.1 Software priority interrupt
In software priority interrupt, a common memory address is used for entire memory
unit. So it will takes more time for transferring data. A polling procedure is software, which is
used to identify the highest-priority source.
4.5.2 Hardware priority interrupts

Hardware priority interrupts again classified into two types:
4.5.2.1 Daisy-chaining priority (Serial transfer priority interrupt)

The daisy-chaining priority method of establishing priority consists of a serial connection
of all devices that request an interrupt. The device with the highest priority is placed in the first
position, followed by lower-priority devices up to the device with the lowest priority, which is
placed in chain. This method provides a connection between three devices and the CPU. The
interrupt request line is common to all devices and forms a wired logic connection. If any device
has its interrupt signal in the low-level state, the interrupt line goes to the low-level state and
enables the interrupt input in the CPU.
Daisy chain priority interrupt

The one stage of a Daisy chain priority interrupt contains SR-flip-flop, Priority input and priority output.
When priority in (PI) is 0; then it will not perform any operation otherwise it performs Priority output
and enable operation. It is shown in below diagram.
One stage of the daisy chain priority arrangement

4.5.2.2 Parallel priority Interrupt
The parallel priority interrupt method uses a register whose bits are set separately by
the interrupt signal from each device. Priority is established according to the position of the bits
in the register. In addition to the interrupt register, the circuit may include a mask register
whose purpose is to control the status of each interrupt request.
Priority interrupt hardware

4.5.2.3 Priority Encoder:
The priority encoder is a circuit that implements the priority function. The priority
encoder takes two or more inputs arrive at same time. The input having the highest priority will
take high precedence. The truth table of a four input priority encoder is shown in below
diagram. It has *'s in the table designate don't care conditions. Input Io has the highest priority.
4.5.2.4 Interrupt cycle

The interrupt enable flip-flop IEN can be set or cleared by the program instructions.
When IEN is cleared, the interrupt request coming from IST is neglected by the CPU. When IEN
is set, then the interrupt facility will be used while the current program is running. It means an
interrupt signal is repeatedly occurs is known as interrupt cycle.
4.5.2.5 Software Routines
A priority interrupt system is a combination of hardware and software

techniques. So far we have discussed the hardware aspects of a priority interrupt
system. The computer must also have software routines for servicing the interrupt
requests and for controlling the interrupt hardware registers. The diagrammatic
representation is shown below. Each device has its own service program that can be
reached through a jump(JMP) instruction stored at the assigned vector address.
Each interrupt service routine must have an initial and final set of operations for
controlling the registers in the hardware interrupt system like clear lower-level mask
register, clear IST bit, set IEN bit and proceed service routine. Finally save the contents
of process register.

Programs stored in memory for servicing interrupts
A.SUNEETHA M.Tech (Ph.D)

Asst.Professor
CSE Department

www.jntuworldupdates.org
www.specworld.in 1 www.smartzworld.com

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UNIT-4 The Memory System

4.1 Memory Hierarchy

Block diagram for different memories

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Static RAM Dynamic RAM

Binary information is stored in internal flip-flops. Binary information is stored in capacitors.

RAM and ROM Chips:

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Typical ROM chip

Memory Address Map

Memory connection to CPU

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Typical Tavg seek time is 3 – 9 ms.

Tavg Rotational time= 1/2 * 1/RPM * 60 sec.

Tavg Transfer Time= 1/ RPM * 1/ (avg no.of sectors/track) * 60 sec.

Tavg rotational time = 1/2 * 1/RPM * 60 sec

= 1/2 * 1/7200 * 60 sec

= 0.041 sec (1 sec = 1000ms)

Tavg Transfer time = 1/ RPM * 1/ (avg no.of sectors/track) * 60 sec

= 1/7200 * 1/400 * 60 sec

= 6 ms + 4.1 ms + 0.02ms => 10.12 ms

 A magnetic disk consists of magnetic, electronics and electromechanical systems.

 Disk consists of Platters, each platter have 2 Surfaces.

 Each surface consists of concentric rings called Tracks.

 Disks follows only anti-clockwise-direction.

 Flash memory is a USB device like “Pendrive”.

Block diagram for magnetic disk

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4.4 Associative Memory

The block diagram for associative memory is below

Associative memory of m word, n cells per word

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One cell of associative memory

Match logic for one word of associative memory

Draw backs of Associative memory:

 It takes more time for searching word.

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Cache memory diagram

Therefore hit ratio = hit / (hit + miss);

The cache memory mapping techniques are classified into 3 types:

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Associative mapping cache

4.5.2 Direct Mapping:

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4.5.3 Set Associative Mapping

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4.5.3.1 2-way Set Associative Mapping.

4.5.3.1 2-way Set Associative Mapping.

2-way Set Associative Mapping.

4.5.3.3 4-way Set Associative Mapping:

4.5.4 Writing into cache

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4.6 Virtual Memory:

4.6.1 Address Space and Memory Space:

Relation between address and memory space in a virtual memory system.

In virtual memory system, programmers use a main-memory capacity of 32KB and