450 Μa, 5 Mhz Rail-To-Rail Op Amp: Features Description

MCP6281/2/3/4/5
450 µA, 5 MHz Rail-to-Rail Op Amp

Features Description
• Gain Bandwidth Product: 5 MHz (typ.) The Microchip Technology Inc. MCP6281/2/3/4/5
• Supply Current: IQ = 450 µA (typ.) family of operational amplifiers (op amps) provide wide
• Supply Voltage: 2.2V to 5.5V bandwidth for the current. This family has a 5 MHz
Gain Bandwidth Product (GBWP) and a 65° phase
• Rail-to-Rail Input/Output
margin. This family also operates from a single supply
• Extended Temperature Range: -40°C to +125°C voltage as low as 2.2V, while drawing 450 µA (typ.)
• Available in Single, Dual and Quad Packages quiescent current. Additionally, the MCP6281/2/3/4/5
• Single with Chip Select (CS) (MCP6283) supports rail-to-rail input and output swing, with a
• Dual with Chip Select (CS) (MCP6285) common mode input voltage range of VDD + 300 mV to
VSS – 300 mV. This family of operational amplifiers is
Applications designed with Microchip’s advanced CMOS process.
The MCP6285 has a Chip Select (CS) input for dual op
• Automotive
amps in an 8-pin package. This device is manufactured
• Portable Equipment by cascading the two op amps (the output of op amp A
• Photodiode Amplifier connected to the non-inverting input of op amp B). The
• Analog Filters CS input puts the device in Low-power mode.
• Notebooks and PDAs The MCP6281/2/3/4/5 family operates over the
• Battery-Powered Systems Extended Temperature Range of -40°C to +125°C. It
also has a power supply range of 2.2V to 5.5V.
Available Tools
• SPICE Macro Model (at www.microchip.com)
• FilterLab® Software (at www.microchip.com)
Package Types
MCP6281 MCP6281 MCP6281R MCP6282
PDIP, SOIC, MSOP SOT-23-5 SOT-23-5 PDIP, SOIC, MSOP
NC 1 8 NC VOUTA 1 8 VDD
VOUT 1 5 VDD VOUT 1 5 VSS
VIN_ 2 - 7 VDD VINA_ 2 - + 7 VOUTB
VSS 2 VDD 2
+ - +
-
+
VIN+ 3 6 VOUT VINA+ 3 + - 6 VINB_

VIN+ 3 4 VIN– VIN+ 3 4 VIN–
VSS 4 5 NC VSS 4 5 VINB+
MCP6283 MCP6283 MCP6284 MCP6285

PDIP, SOIC, MSOP SOT-23-6 PDIP, SOIC, TSSOP PDIP, SOIC, MSOP
NC 1 8 CS VOUTA 1 14 VOUTD
VOUT 1 6 VDD VOUTA/VINB+ 1 8 VDD
VIN_ 2 - 7 VDD VINA_ 2 - + + - 13 VIND_
+
VSS 2 5 CS VINA_ 2 - + 7 VOUTB
VIN+ 3 6 VOUT -
+
_ VINA+ 3 12 VIND+ _
VIN+ 3 4 VIN VINA+ 3 + - 6 VINB
VSS 4 5 NC VDD 4 11 VSS
VSS 4 5 CS
VINB+ 5 10 VINC+
VINB_ 6 -+ +- 9 V _
INC
VOUTB 7 8 VOUTC
 2004 Microchip Technology Inc. DS21811D-page 1

MCP6281/2/3/4/5
1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
CHARACTERISTICS stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
Absolute Maximum Ratings † operational listings of this specification is not implied. Expo-
sure to maximum rating conditions for extended periods may
VDD – VSS ........................................................................7.0V
affect device reliability.
All Inputs and Outputs ................... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short Circuit Current ................................. Continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature.....................................-65°C to +150°C
Junction Temperature (TJ) . .........................................+150°C
ESD Protection On All Pins (HBM;MM) ................ ≥ 4 kV;400V
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND,
VCM = VDD/2, RL = 10 kΩ to VDD/2 and VOUT ≈ VDD/2.
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -3.0 — +3.0 mV VCM = VSS (Note 1)
Input Offset Voltage VOS -5.0 — +5.0 mV TA= -40°C to +125°C,
(Extended Temperature) VCM = VSS (Note 1)
Input Offset Temperature Drift ∆VOS/∆TA — ±1.7 — µV/°C TA= -40°C to +125°C,
VCM = VSS (Note 1)
Power Supply Rejection Ratio PSRR 70 90 — dB VCM = VSS (Note 1)
Input Bias, Input Offset Current and Impedance
Input Bias Current IB — ±1.0 — pA Note 2
At Temperature IB — 50 200 pA TA= +85°C (Note 2)
At Temperature IB — 2 5 nA TA= +125°C (Note 2)
Input Offset Current IOS — ±1.0 — pA Note 3
Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Note 3
Differential Input Impedance ZDIFF — 1013||3 — Ω||pF Note 3
Common Mode (Note 4)
Common Mode Input Range VCMR VSS − 0.3 — VDD + 0.3 V
Common Mode Rejection Ratio CMRR 70 85 — dB VCM = -0.3V to 2.5V, VDD = 5V
Common Mode Rejection Ratio CMRR 65 80 — dB VCM = -0.3V to 5.3V, VDD = 5V
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 90 110 — dB VOUT = 0.2V to VDD – 0.2V,
VCM = VSS (Note 1)
Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD – 15 mV
Output Short Circuit Current ISC — ±25 — mA
Power Supply
Supply Voltage VDD 2.2 — 5.5 V
Quiescent Current per Amplifier IQ 300 450 570 µA IO = 0
Note 1: The MCP6285’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6285’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6285’s VOUTA/VINB+ pin.
4: The MCP6285’s VINB– pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD – 100 mV.
The MCP6285’s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL.
DS21811D-page 2  2004 Microchip Technology Inc.

MCP6281/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
AC Response
Gain Bandwidth Product GBWP — 5.0 — MHz
Phase Margin at Unity-Gain PM — 65 — °
Slew Rate SR — 2.5 — V/µs
Noise
Input Noise Voltage Eni — 3.5 — µVP-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni — 16 — nV/√Hz f = 1 kHz
Input Noise Current Density ini — 3 — fA/√Hz f = 1 kHz
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.2V to +5.5V and VSS = GND.
Temperature Ranges
Operating Temperature Range TA -40 — +125 °C Note
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W
Thermal Resistance, 6L-SOT-23 θJA — 230 — °C/W
Thermal Resistance, 8L-PDIP θJA — 85 — °C/W
Thermal Resistance, 8L-SOIC θJA — 163 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 14L-PDIP θJA — 70 — °C/W
Thermal Resistance, 14L-SOIC θJA — 120 — °C/W
Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Note: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.

MCP6281/2/3/4/5
MCP6283/MCP6285 CHIP SELECT (CS) SPECIFICATIONS
VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF.
CS Low Specifications
CS Logic Threshold, Low VIL VSS — 0.2 VDD V
CS Input Current, Low ICSL — 0.01 — µA CS = VSS
CS High Specifications
CS Logic Threshold, High VIH 0.8 VDD — VDD V
CS Input Current, High ICSH — 0.7 2 µA CS = VDD
GND Current per Amplifier ISS — -0.7 — µA CS = VDD
Amplifier Output Leakage — — 0.01 — µA CS = VDD

Dynamic Specifications (Note 1)
CS Low to Valid Amplifier tON — 4 10 µs CS Low ≤ 0.2 VDD, G = +1 V/V,
Output, Turn-on Time VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output High-Z tOFF — 0.01 — µs CS High ≥ 0.8 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.1 VDD/2
Hysteresis VHYST — 0.6 — V VDD = 5V
Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6285. The dynamic specification is tested
at the output of op amp B (VOUTB).
CS VIL VIH
tOFF
tON
VOUT Hi-Z Hi-Z
-0.7 µA (typ.) -0.7 µA (typ.)

ISS -450 µA (typ.)
0.7 µA (typ.) 0.7 µA (typ.)
ICS
10 nA (typ.)
FIGURE 1-1: Timing Diagram for the

Chip Select (CS) pin on the MCP6283 and
MCP6285.

MCP6281/2/3/4/5
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 10 kΩ to VDD/2 and CL = 60 pF.
14% 30%
832 Samples
Percentage of Occurrences
832 Samples
12% VCM = VSS VCM = VSS
25%
TA = -40°C to +125°C
10%
20%
8%
15%
6%
4% 10%
2% 5%
0%
0%
-2.8
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
-10 -8 -6 -4 -2 0 2 4 6 8 10
Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C)
FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Offset Voltage Drift.
25% 35%
210 Samples 210 Samples
TA = +85°C 30% TA = +125°C
20%
25%
15% 20%
15%
10%
10%
5% 5%
0%
0
200
400
800
1200
1600
2000
2400
2800
3200
3600
0%
0 10 20 30 40 50 60 70 80 90 100
Input Bias Current (pA) Input Bias Current (pA)
FIGURE 2-2: Input Bias Current at FIGURE 2-5: Input Bias Current at
TA = +85 °C. TA = +125 °C.
300 300
VDD = 2.2V VDD = 5.5V
Input Offset Voltage (µV)
250 250
200 200
150 150
100 100
50 50
TA = +125°C TA = +125°C
0 TA = +85°C 0 TA = +85°C
TA = +25°C -50 TA = +25°C
-50
TA = -40°C TA = -40°C
-100 -100
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-0.5 0.0 0.5 1.0 1.5 2.0 2.5
Common Mode Input Voltage (V) Common Mode Input Voltage (V)
FIGURE 2-3: Input Offset Voltage vs. FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 2.2V. Common Mode Input Voltage at VDD = 5.5V.

MCP6281/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
300 10,000
VCM = VSS VCM = VDD
250
Input Bias, Offset Currents

Representative Part VDD = 5.5V
200 1,000
150
100
(pA)
100 Input Bias Current
50 Input Offset Current

0 VDD = 5.5V
VDD = 2.2V 10
-50
-100
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
25 35 45 55 65 75 85 95 105 115 125
Output Voltage (V) Ambient Temperature (°C)
FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Bias, Input Offset
Output Voltage. Currents vs. Ambient Temperature.
110 120
PSRR-
100 CMRR
110
90 PSRR+ PSRR, CMRR (dB)
CMRR, PSRR (dB)
100 CMRR
80
70
90
60
PSRR
80
50 VCM = VSS
40 70
30
60
20 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
1 10 100 1k 10k 100k 1M -50 -25 0 25 50 75 100 125

Frequency (Hz) Ambient Temperature (°C)
FIGURE 2-8: CMRR, PSRR vs. FIGURE 2-11: CMRR, PSRR vs. Ambient
Frequency. Temperature.
55 2.5
TA = +125°C
45 VDD = 5.5V
2.0
Input Bias Current
35
1.5 Input Bias Current
25
1.0
(pA)
(nA)
15
0.5
5
Input Offset Current 0.0
-5 Input Offset Current
TA = +85°C -0.5
-15 VDD = 5.5V
-25 -1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V) Common Mode Input Voltage (V)
FIGURE 2-9: Input Bias, Offset Currents FIGURE 2-12: Input Bias, Offset Currents
vs. Common Mode Input Voltage at TA = +85°C. vs. Common Mode Input Voltage at TA = +125°C.

MCP6281/2/3/4/5
600 1000
Ouput Voltage Headroom (mV)

500
Quiescent Current
(µA/amplifier)
400 100
300
TA = +125°C
200
TA = +85°C 10
TA = +25°C VOL - VSS
100
TA = -40°C VDD - VOH
0
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.01 0.1 1 10
Power Supply Voltage (V)
Output Current Magnitude (mA)
FIGURE 2-13: Quiescent Current vs. FIGURE 2-16: Output Voltage Headroom
Power Supply Voltage. vs. Output Current Magnitude.
120 0
6 90
VDD = 5.5V
100 -30
Gain Bandwidth Product

5 85
Open-Loop Gain (dB)
Open-Loop Phase (°)
Gain
VDD = 2.2V
Phase Margin (°)

80 -60
4 Gain Bandwidth Product 80
(MHz)
60 -90
Phase
3 VDD = 5.5V 75
40 -120
2 70
20 -150
Phase Margin VDD = 2.2V
1 65
0 -180
0 60
-20 -210
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
1.E-01
0.1 1 10 100 1k 10k 100k 1M 10M 100M -50 -25 0 25 50 75 100 125
FIGURE 2-14: Open-Loop Gain, Phase vs. FIGURE 2-17: Gain Bandwidth Product,
Frequency. Phase Margin vs. Ambient Temperature.
10
4.5
Falling Edge, VDD = 2.2V
Maximum Output Voltage
4.0
VDD = 5.5V Falling Edge, VDD = 5.5V
3.5
Slew Rate (V/µs)
Swing (VP-P)
3.0
VDD = 2.2V
2.5
1
2.0
1.5 Rising Edge, VDD = 5.5V
Rising Edge, VDD = 2.2V
1.0
0.5
0.0
0.1
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1k 10k 100k 1M 10M -50 -25 0 25 50 75 100 125

FIGURE 2-15: Maximum Output Voltage FIGURE 2-18: Slew Rate vs. Ambient
Swing vs. Frequency. Temperature.

MCP6281/2/3/4/5
1,000 30
f = 1 kHz
Input Noise Voltage Density

Input Noise Voltage Density
VDD = 5.0V
25
20
(nV/¥Hz)
(nV/Hz)
100 15
10
10 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

0
0.1 1 10 100 1k 10k 100k 1M 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Frequency (Hz) Common Mode Input Voltage (V)
FIGURE 2-19: Input Noise Voltage Density FIGURE 2-22: Input Noise Voltage Density
vs. Frequency. vs. Common Mode Input Voltage at 1 kHz.
35 140
Channel-to-Channel Separation
Ouptut Short Circuit Current
30
25 130
20
(dB)
(mA)
120
15
TA = +125°C
10 TA = +85°C 110
TA = +25°C
5
TA = -40°C
0 100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100
Power Supply Voltage (V) Frequency (kHz)
FIGURE 2-20: Output Short Circuit Current FIGURE 2-23: Channel-to-Channel

vs. Power Supply Voltage. Separation vs. Frequency (MCP6282 and
MCP6284 only).
500 1000
Op-Amp shuts off here VDD = 5.5V
450 900
Op-Amp turns on here
800
Quiescent Current
400
Quiescent Current
Hysteresis
(µA/Amplifier)
700
(µA/Amplifier)
350
300 600 CS swept
low to high
500
high to low
250
CS swept
Hysteresis
200 400
150 300
CS swept CS swept
100 high to low low to high 200
50 VDD = 2.2V 100
Op Amp toggles On/Off here
0 0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V) Chip Select Voltage (V)
FIGURE 2-21: Quiescent Current vs. FIGURE 2-24: Quiescent Current vs.
Chip Select (CS) Voltage at VDD = 2.2V Chip Select (CS) Voltage at VDD = 5.5V
(MCP6283 and MCP6285 only). (MCP6283 and MCP6285 only).

MCP6281/2/3/4/5
5.0 5.0
G = +1V/V G = -1V/V
4.5 VDD = 5.0V 4.5 VDD = 5.0V
4.0 4.0
Output Voltage (V)

Output Voltage (V)
3.5 3.5
3.0 3.0
2.5 2.5
2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
0.0 0.E+00 2.E-06 4.E -06 6.E-06 8.E-06 1.E-05 1.E-05 1.E-05 2.E-05 2.E-05 2.E -05
0.0 0.E+00 2.E-06 4.E-06 6.E-06 8.E-06 1.E-05 1.E-05 1.E-05 2.E-05 2.E-05 2.E-05
Time (2 µs/div) Time (2 µs/div)
FIGURE 2-25: Large-Signal, Non-inverting FIGURE 2-28: Large-Signal, Inverting

Pulse Response. Pulse Response.
G = +1V/V
Output Voltage (10 mV/div)

Output Voltage (10 mV/div)
G = -1V/V
Time (500 ns/div) Time (500 ns/div)
FIGURE 2-26: Small-Signal, Non-inverting FIGURE 2-29: Small-Signal, Inverting

Pulse Response. Pulse Response.
6.0
2.5
VDD = 2.2V VDD = 5.5V
Chip Select, Output Voltages
5.5
Chip Select, Output Voltages
G = +1V/V CS Voltage G = +1V/V

5.0
CS Voltage VIN = VSS VIN = VSS
2.0 4.5
4.0
1.5 3.5
VOUT
(V)
(V)
VOUT Output On 3.0

2.5
1.0
2.0
1.5
0.5 1.0 Output High-Z Output On
0.5
Output High-Z
0.0 0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05
0.0 0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05 4.0E-05 4.5E-05 5.0E-05
Time (5 µs/div) Time (5 µs/div)
FIGURE 2-27: Chip Select (CS) to FIGURE 2-30: Chip Select (CS) to
Amplifier Output Response Time at VDD = 2.2V Amplifier Output Response Time at VDD = 5.5V
(MCP6283 and MCP6285 only). (MCP6283 and MCP6285 only).

MCP6281/2/3/4/5
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS

MCP6281 MCP6283
MCP6281 MCP6271R MCP6283
(PDIP, SOIC, (PDIP, SOIC, Symbol Description
(SOT-23-5) (SOT-23-5) (SOT-23-6)
MSOP) MSOP)
6 1 1 6 1 VOUT Analog Output
2 4 4 2 4 VIN– Inverting Input
3 3 3 3 3 VIN+ Non-inverting Input
7 5 2 7 6 VDD Positive Power Supply
4 2 5 4 2 VSS Negative Power Supply
— — — 8 5 CS Chip Select
1,5,8 — — 1,5 — NC No Internal Connection
TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
MCP6282 MCP6284 MCP6285 Symbol Description
1 1 — VOUTA Analog Output (op amp A)
2 2 2 VINA– Inverting Input (op amp A)
3 3 3 VINA+ Non-inverting Input (op amp A)
8 4 8 VDD Positive Power Supply
5 5 — VINB+ Non-inverting Input (op amp B)
6 6 6 VINB– Inverting Input (op amp B)
7 7 7 VOUTB Analog Output (op amp B)
— 8 — VOUTC Analog Output (op amp C)
— 9 — VINC– Inverting Input (op amp C)
— 10 — VINC+ Non-inverting Input (op amp C)
4 11 4 VSS Negative Power Supply
— 12 — VIND+ Non-inverting Input (op amp D)
— 13 — VIND– Inverting Input (op amp D)
— 14 — VOUTD Analog Output (op amp D)
— — 1 VOUTA/VINB+ Analog Output (op amp A)/Non-inverting Input (op amp B)
— — 5 CS Chip Select
3.1 Analog Outputs 3.4 CS Digital Input

The output pins are low-impedance voltage sources. This is a CMOS, Schmitt-triggered input that places the
part into a low-power mode of operation.
3.2 Analog Inputs 3.5 Power Supply (VSS and VDD)
The non-inverting and inverting inputs are high-
The positive power supply (VDD) is 2.2V to 5.5V higher
impedance CMOS inputs with low bias currents.
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
3.3 MCP6285’s VOUTA/VINB+ Pin
Typically, these parts are used in a single (positive)
For the MCP6285 only, the output of op amp A is supply configuration. In this case, VSS is connected to
connected directly to the non-inverting input of ground and VDD is connected to the supply. VDD will
op amp B; this is the VOUTA/VINB+ pin. This connection need a local bypass capacitor (typically 0.01 µF to
makes it possible to provide a Chip Select pin for duals 0.1 µF) within 2 mm of the VDD pin. These parts need
in 8-pin packages. to use a bulk capacitor (within 100 mm), which can be
shared with nearby analog parts.

MCP6281/2/3/4/5
4.0 APPLICATION INFORMATION
The MCP6281/2/3/4/5 family of op amps is manufac- –
tured using Microchip's state-of-the-art CMOS
process. This family is specifically designed for low- RIN MCP628X VOUT
cost, low-power and general purpose applications. VIN +
The low supply voltage, low quiescent current and
wide bandwidth makes the MCP6281/2/3/4/5 ideal for
battery-powered applications. ( Maximum expected VIN ) – V DD
R IN ≥ ----------------------------------------------------------------------------------
2 mA
4.1 Rail-to-Rail Inputs V SS – ( Minimum expected V IN )
The MCP6281/2/3/4/5 op amp is designed to prevent R IN ≥ ------------------------------------------------------------------------------
2 mA
phase reversal when the input pins exceed the supply
voltages. Figure 4-1 shows the input voltage exceeding FIGURE 4-2: Input Current Limiting
the supply voltage without any phase reversal.
Resistor (RIN).
6
VDD = 5.0V
4.2 Rail-to-Rail Output
5 G = +2 V/V
Input, Output Voltage (V)
The output voltage range of the MCP6281/2/3/4/5 op

4 amp is VDD – 15 mV (min.) and VSS + 15 mV (max.)
VOUT
3
VIN when RL = 10 kΩ is connected to VDD/2 and
VDD = 5.5V. Refer to Figure 2-16 for more information.
2
1 4.3 Capacitive Loads

0 Driving large capacitive loads can cause stability
-1 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5
problems for voltage feedback op amps. As the load
Time (1 ms/div) capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
FIGURE 4-1: The MCP6281/2/3/4/5 Show reduced. This produces gain peaking in the frequency
No Phase Reversal. response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
The input stage of the MCP6281/2/3/4/5 op amps use sensitive to capacitive loads, though all gains show the
two differential CMOS input stages in parallel. One
same general behavior.
operates at low common mode input voltage (VCM),
while the other operates at high VCM. With this When driving large capacitive loads with these op
topology, the device operates with VCM up to 0.3V amps (e.g., > 100 pF when G = +1), a small series
above VDD and 0.3V below VSS. The Input Offset Volt- resistor at the output (RISO in Figure 4-3) improves the
age (VOS) is measured at VCM = VSS – 0.3V and feedback loop’s phase margin (stability) by making the
VDD + 0.3V to ensure proper operation. output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
Input voltages that exceed the absolute maximum
with no capacitive load.
voltage (VSS – 0.3V to VDD + 0.3V) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally – RISO
limited with a resistor, as shown in Figure 4-2.
MCP628X VOUT
VIN + CL
FIGURE 4-3: Output Resistor, RISO

stabilizes large capacitive loads.
Figure 4-4 gives recommended RISO values for differ-
ent capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

MCP6281/2/3/4/5
1,000 VOUTA/VINB+ VINB–

Recommended RISO (Ω )
1 6
2 7
VINA– VOUTB
B
100 A
3
VINA+
GN = 1 V/V
MCP6285
GN = 2 V/V
GN ≥ 4 V/V
10 5
10 100 1,000 10,000
CS
Normalized Load Capacitance; CL/GN (pF)
FIGURE 4-5: Cascaded Gain Amplifier.

FIGURE 4-4: Recommended RISO Values
for Capacitive Loads. The output of op amp A is loaded by the input imped-
ance of op amp B, which is typically 1013Ω||6 pF, as
After selecting RISO for your circuit, double-check the specified in the DC specification table (Refer to
resulting frequency response peaking and step Section 4.3 “Capacitive Loads” for further details
response overshoot. Modify RISO's value until the regarding capacitive loads).
response is reasonable. Bench evaluation and simula-
tions with the MCP6281/2/3/4/5 SPICE macro model The common mode input range of these op amps is
are helpful. specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
4.4 MCP628X Chip Select (CS) 10 kΩ load), the non-inverting input range of op amp B
The MCP6283 and MCP6285 are single and dual op is limited to the common mode input range of
amps with Chip Select (CS), respectively. When CS is VSS + 20 mV and VDD – 20 mV.
pulled high, the supply current drops to 0.7 µA (typ) and
flows through the CS pin to VSS. When this happens, 4.6 Supply Bypass
the amplifier output is put into a high-impedance state.
By pulling CS low, the amplifier is enabled. If the CS pin With this family of operational amplifiers, the power
is left floating, the amplifier may not operate properly. supply pin (VDD for single-supply) should have a local
Figure 1-1 shows the output voltage and supply current bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
response to a CS pulse. for good, high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
4.5 Cascaded Dual Op Amps shared with other analog parts.
(MCP6285)
The MCP6285 is a dual op amp with Chip Select (CS). 4.7 PCB Surface Leakage
The Chip Select input is available on what would be the
In applications where low input bias current is critical,
non-inverting input of a standard dual op amp (pin 5).
Printed Circuit Board (PCB) surface-leakage effects
This pin is available because the output of op amp A
need to be considered. Surface leakage is caused by
connects to the non-inverting input of op amp B, as
humidity, dust or other contamination on the board.
shown in Figure 4-5. The Chip Select input, which can
Under low humidity conditions, a typical resistance
be connected to a microcontroller I/O line, puts the
between nearby traces is 1012Ω. A 5V difference would
device in Low-power mode. Refer to Section 4.4
cause 5 pA of current to flow, which is greater than the
“MCP6283/5 Chip Select (CS)”.
MCP6281/2/3/4/5 family’s bias current at 25°C (1 pA,
typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.

MCP6281/2/3/4/5
4.8 Application Circuits
VIN– VIN+
VSS
4.8.1 SALLEN-KEY HIGH-PASS FILTER
The MCP6281/2/3/4/5 op amps can be used in active-
filter applications. Figure 4-7 shows a second-order
Sallen-Key high-pass filter with a gain of 1. The output
bias voltage is set by the VDD/2 reference, which can
be changed to any voltage within the output voltage
range.
Guard Ring
FIGURE 4-6: Example Guard Ring Layout

for Inverting Gain. R1
1. For Inverting Gain and Transimpedance VIN +
Amplifiers (convert current to voltage, such as
C1 C2 MCP6281 VOUT
photo detectors):
a. Connect the guard ring to the non-inverting R2 –
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op VDD/2
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB FIGURE 4-7: Sallen-Key High-Pass Filter.
surface. This filter, and others, can be designed using
2. Non-inverting Gain and Unity-Gain Buffer: Microchip’s FilterLab® software, which is available on
a. Connect the non-inverting pin (VIN+) to the our web site (www.microchip.com).
input with a wire that does not touch the
PCB surface. 4.8.2 INVERTING MILLER INTEGRATOR
b. Connect the guard ring to the inverting input Analog integrators are used in filters, control loops and
pin (VIN–). This biases the guard ring to the measurement circuits. Figure 4-8 shows the most
common mode input voltage. common implementation, the inverting Miller integrator.
The non-inverting input is at VDD/2 so that the op amp
properly biases up. The switch (SW) is used to zero the
output in some applications. Other applications use a
feedback loop to keep the output within its linear range
of operation.
SW
R C
VIN VOUT
+
MCP6281
VDD/2 –
VOUT 1
=
VIN sRC
FIGURE 4-8: Miller Integrator.

MCP6281/2/3/4/5
4.8.3 CASCADED OP AMP
APPLICATIONS R4 R3 R2 R1
The MCP6285 provides the flexibility of Low-power
mode for dual op amps in an 8-pin package. The
MCP6285 eliminates the added cost and space in
battery-powered applications by using two single op
B VOUT
amps with Chip Select lines or a 10-pin device with one A
Chip Select line for both op amps. Since the two op VIN
amps are internally cascaded, this device cannot be MCP6285
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with CS
Chip Select line becomes suitable. The circuits below
show possible applications for this device. FIGURE 4-10: Cascaded Gain Circuit
Configuration.
4.8.3.1 Load Isolation
With the cascaded op amp configuration, op amp B can 4.8.3.3 Difference Amplifier
be used to isolate the load from op amp A. In applica- Figure 4-11 shows op amp A configured as a difference
tions where op amp A is driving capacitive or low resis- amplifier with Chip Select. In this configuration, it is
tance loads in the feedback loop (such as an integrator recommended to use well-matched resistors (e.g.,
circuit or filter circuit), the op amp may not have 0.1%) to increase the Common Mode Rejection Ratio
sufficient source current to drive the load. In this case, (CMRR). Op amp B can be used to provide additional
op amp B can be used as a buffer. gain and isolate the load from the difference amplifier.
R4 R3
R2 R1
B VOUTB VIN2
A
Load B VOUT
MCP6285 R2 A
VIN1
MCP6285
CS R1
FIGURE 4-9: Isolating the Load with a CS

Buffer.
FIGURE 4-11: Difference Amplifier Circuit.
4.8.3.2 Cascaded Gain
Figure 4-10 shows a cascaded gain circuit configura-
tion with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this
configuration, it is important to note that the input offset
voltage of op amp A is amplified by the gain of
op amp A and B, as shown below:
V OUT = V IN G A G B + V OSA G A G B + V OSB G B
Where:
GA = op amp A gain
GB = op amp B gain
VOSA = op amp A input offset voltage
VOSB = op amp B input offset voltage
Therefore, it is recommended to set most of the gain

with op amp A and use op amp B with relatively small
gain (e.g., a unity-gain buffer).

MCP6281/2/3/4/5
4.8.3.4 Buffered Non-inverting Integrator 4.8.3.6 Second-Order MFB Low-Pass Filter
Figure 4-12 shows a lossy non-inverting integrator that with an Extra Pole-Zero Pair
is buffered and has a Chip Select input. Op amp A is Figure 4-14 is a second-order multiple feedback low-
configured as a non-inverting integrator. In this config- pass filter with Chip Select. Use the FilterLab® software
uration, matching the impedance at each input is from Microchip to determine the R and C values for the
recommended. RF is used to provide a feedback loop op amp A’s second-order filter. Op amp B can be used
at frequencies << 1/(2πR1C1) and makes this a lossy to add a pole-zero pair using C3, R6 and R7.
integrator (it has a finite gain at DC). Op amp B is used
to isolate the load from the integrator.
R6 C3
R1
R2 C2 C1
R7
R3 R2
RF VIN B VOUT
B VOUT A
R1 A R5
C2
VIN R4 MCP6285
MCP6285
C1
CS
CS
R1 C 1 = ( R 2 || R F )C 2 FIGURE 4-14: Second-Order Multiple
Feedback Low-Pass Filter with an Extra
FIGURE 4-12: Buffered Non-inverting Pole-Zero Pair.
Integrator with Chip Select.
4.8.3.7 Second-Order Sallen-Key Low-Pass
4.8.3.5 Inverting Integrator with Active Filter with an Extra Pole-Zero Pair
Compensation and Chip Select Figure 4-15 is a second-order Sallen-Key low-pass
Figure 4-13 uses an active compensator (op amp B) to filter with Chip Select. Use the FilterLab® software from
compensate for the non-ideal op amp characteristics Microchip to determine the R and C values for the op
introduced at higher frequencies. This circuit uses amp A’s second-order filter. Op amp B can be used to
op amp B as a unity-gain buffer to isolate the integration add a pole-zero pair using C3, R5 and R6.
capacitor C1 from op amp A and drives the capacitor
with low-impedance source. Since both op amps are R2 R1 R5 C3
matched very well, they provide a higher quality
integrator.
R6
B VOUT
R4 R3 A
R1 C1 VIN
VIN MCP6285
C1
B
C2 CS
A VOUT
FIGURE 4-15: Second-Order Sallen-Key
MCP6285
Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.
CS
FIGURE 4-13: Integrator Circuit with Active

Compensation.

MCP6281/2/3/4/5
4.8.3.8 Capacitorless Second-Order 5.0 DESIGN TOOLS
Low-Pass filter with Chip Select
Microchip provides the basic design tools needed for
The low-pass filter shown in Figure 4-16 does not the MCP6281/2/3/4/5 family of op amps.
require external capacitors and uses only three exter-
nal resistors; the op amp's GBWP sets the corner
5.1 SPICE Macro Model
frequency. R1 and R2 are used to set the circuit gain
and R3 is used to set the Q. To avoid gain peaking in The latest SPICE macro model for the
the frequency response, Q needs to be low (lower MCP6281/2/3/4/5 op amps is available on our web site
values need to be selected for R3). Note that the ampli- at www.microchip.com. This model is intended to be an
fier bandwidth varies greatly over temperature and initial design tool that works well in the op amp’s linear
process. However, this configuration provides a low- region of operation at room temperature. See the
cost solution for applications with high bandwidth macro model file for information on its capabilities.
requirements.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
R2 R1 results using this macro model need to be validated by
VIN comparing them to the data sheet specifications and
characteristic curves.
R3
A 5.2 FilterLab® Software

B VOUT
VREF Microchip’s FilterLab software is an innovative tool that
MCP6285 simplifies analog active-filter (using op amps) design.
Available at no cost from our web site at
www.microchip.com, the FilterLab design tool provides
CS full schematic diagrams of the filter circuit with compo-
nent values. It also outputs the filter circuit in SPICE
FIGURE 4-16: Capacitorless Second-Order format, which can be used with the macro model to
Low-Pass Filter with Chip Select. simulate actual filter performance.

MCP6281/2/3/4/5
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
5-Lead SOT-23 (MCP6281 and MCP6281R) Example:
Device Code
XXNN MCP6281 CHNN CH25

MCP6281R EUNN
Note: Applies to 5-Lead SOT-23.
6-Lead SOT-23 (MCP6283) Example:
XXNN CL25
8-Lead MSOP Example:
XXXXXX 6281E
YWWNNN 437256
8-Lead PDIP (300 mil) Example:
XXXXXXXX MCP6281
XXXXXNNN E/P256
YYWW 0437
8-Lead SOIC (150 mil) Example:
XXXXXXXX MCP6281
XXXXYYWW E/SN0437
NNN 256
Legend: XX...X Customer specific information*

YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.

MCP6281/2/3/4/5
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6284) Example:
XXXXXXXXXXXXXX MCP6284-E/P
XXXXXXXXXXXXXX
YYWWNNN 0437256
14-Lead SOIC (150 mil) (MCP6284) Example:
XXXXXXXXXX MCP6284ESL
XXXXXXXXXX
YYWWNNN 0437256
14-Lead TSSOP (MCP6284) Example:
XXXXXX 6284EST
YYWW 0437
NNN 256

MCP6281/2/3/4/5
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
E1
p
B
p1 D
n 1
c
A A2
φ A1
L
β
Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 5 5
Pitch p .038 0.95
Outside lead pitch (basic) p1 .075 1.90
Overall Height A .035 .046 .057 0.90 1.18 1.45
Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30
Standoff A1 .000 .003 .006 0.00 0.08 0.15
Overall Width E .102 .110 .118 2.60 2.80 3.00
Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75
Overall Length D .110 .116 .122 2.80 2.95 3.10
Foot Length L .014 .018 .022 0.35 0.45 0.55
Foot Angle φ 0 5 10 0 5 10
Lead Thickness c .004 .006 .008 0.09 0.15 0.20
Lead Width B .014 .017 .020 0.35 0.43 0.50
Mold Draft Angle Top α 0 5 10 0 5 10
Mold Draft Angle Bottom β 0 5 10 0 5 10
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A

Drawing No. C04-091

MCP6281/2/3/4/5
6-Lead Plastic Small Outline Transistor (CH) (SOT-23)
E1
B
p1 D
n 1
A A2
L A1
β

Pitch p .038 0.95
Outside lead pitch (basic) p1 .075 1.90
Overall Height A .035 .046 .057 0.90 1.18 1.45
Standoff A1 .000 .003 .006 0.00 0.08 0.15
Overall Width E .102 .110 .118 2.60 2.80 3.00
Overall Length D .110 .116 .122 2.80 2.95 3.10
Foot Length L .014 .018 .022 0.35 0.45 0.55
Foot Angle φ 0 5 10 0 5 10
Lead Thickness c .004 .006 .008 0.09 0.15 0.20
Lead Width B .014 .017 .020 0.35 0.43 0.50
Notes:
JEITA (formerly EIAJ) equivalent: SC-74A

Drawing No. C04-120

MCP6281/2/3/4/5
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E1
D
2
B
n 1
A A2
c
φ
A1
(F) L
β
Units INCHES MILLIMETERS*

Pitch p .026 BSC 0.65 BSC
Overall Height A - - .043 - - 1.10
Standoff A1 .000 - .006 0.00 - 0.15
Overall Width E .193 TYP. 4.90 BSC
Molded Package Width E1 .118 BSC 3.00 BSC
Overall Length D .118 BSC 3.00 BSC
Foot Length L .016 .024 .031 0.40 0.60 0.80
Footprint (Reference) F .037 REF 0.95 REF
Foot Angle φ 0° - 8° 0° - 8°
Lead Thickness c .003 .006 .009 0.08 - 0.23
Lead Width B .009 .012 .016 0.22 - 0.40
Mold Draft Angle Top α 5°5° - 15° 5° - 15°
-
Mold Draft Angle Bottom β 5°5° - 15° 5° - 15°
Notes:
JEDEC Equivalent: MO-187
Drawing No. C04-111

MCP6281/2/3/4/5
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
n 1
A A2
L
c
A1
β B1
p
eB B

Pitch p .100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018

MCP6281/2/3/4/5
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E1
D
2
B n 1
h α
45°
c
A A2
φ
β L A1

Pitch p .050 1.27
Overall Height A .053 .061 .069 1.35 1.55 1.75
Standoff § A1 .004 .007 .010 0.10 0.18 0.25
Overall Width E .228 .237 .244 5.79 6.02 6.20
Overall Length D .189 .193 .197 4.80 4.90 5.00
Chamfer Distance h .010 .015 .020 0.25 0.38 0.51
Foot Length L .019 .025 .030 0.48 0.62 0.76
Foot Angle φ 0 4 8 0 4 8
Lead Thickness c .008 .009 .010 0.20 0.23 0.25
Lead Width B .013 .017 .020 0.33 0.42 0.51
Notes:
.010” (0.254mm) per side.
Drawing No. C04-057

MCP6281/2/3/4/5
14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
n 1
α
A A2
c L
A1
β B1
eB
B p

Pitch p .100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Overall Length D .740 .750 .760 18.80 19.05 19.30
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Notes:
.010” (0.254mm) per side.
Drawing No. C04-005

MCP6281/2/3/4/5
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
E1
B n 1
α
h
45°
c
A A2
φ
A1
L
β

Pitch p .050 1.27
Overall Height A .053 .061 .069 1.35 1.55 1.75
Standoff § A1 .004 .007 .010 0.10 0.18 0.25
Overall Width E .228 .236 .244 5.79 5.99 6.20
Overall Length D .337 .342 .347 8.56 8.69 8.81
Chamfer Distance h .010 .015 .020 0.25 0.38 0.51
Foot Length L .016 .033 .050 0.41 0.84 1.27
Lead Thickness c .008 .009 .010 0.20 0.23 0.25
Lead Width B .014 .017 .020 0.36 0.42 0.51
Notes:
.010” (0.254mm) per side.
Drawing No. C04-065

MCP6281/2/3/4/5
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E1
2
n 1
B
α
A
β A1 A2
L
Units INCHES MILLIMETERS*

Pitch p .026 0.65
Overall Height A .043 1.10
Standoff § A1 .002 .004 .006 0.05 0.10 0.15
Overall Width E .246 .251 .256 6.25 6.38 6.50
Molded Package Length D .193 .197 .201 4.90 5.00 5.10
Foot Length L .020 .024 .028 0.50 0.60 0.70
Lead Thickness c .004 .006 .008 0.09 0.15 0.20
Lead Width B1 .007 .010 .012 0.19 0.25 0.30
Notes:
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-087

MCP6281/2/3/4/5
APPENDIX A: REVISION HISTORY
Revision A (June 2003)

Original data sheet release.
Revision B (October 2003)
Revision C (June 2004)
Revision D (December 2004)

The following is the list of modifications:
1. Added SOT-23-5 packages for the MCP6281
and MCP6281R single op amps.
2. Added SOT-23-6 package for the MCP6283
single op amp.
3. Added Section 3.0 “Pin Descriptions”.
4. Corrected application circuits
(Section 4.8 “Application Circuits”).
5. Added SOT-23-5 and SOT-23-6 packages and
corrected package marking information
(Section 6.0 “Packaging Information”).
6. Added Appendix A: Revision History.

MCP6281/2/3/4/5
NOTES:

MCP6281/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. – X /XX Examples:

a) MCP6281-E/SN: Extended Temperature,
Device Temperature Package 8LD SOIC package.
Range b) MCP6281-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6281-E/P: Extended Temperature,
Device: MCP6281: Single Op Amp 8LD PDIP package.
MCP6281T: Single Op Amp d) MCP6281T-E/OT: Tape and Reel,
(Tape and Reel) Extended Temperature,
(SOIC, MSOP, SOT-23-5) 5LD SOT-23 package.
MCP6281RT: Single Op Amp a) MCP6282-E/SN: Extended Temperature,
(Tape and Reel) (SOT-23-5) 8LD SOIC package.
MCP6282: Dual Op Amp b) MCP6282-E/MS: Extended Temperature,
MCP6282T: Dual Op Amp 8LD MSOP package.
(Tape and Reel) (SOIC, MSOP) c) MCP6282-E/P: Extended Temperature,
MCP6283: Single Op Amp with Chip Select 8LD PDIP package.
MCP6283T: Single Op Amp with Chip Select d) MCP6282T-E/SN: Tape and Reel,
(Tape and Reel) Extended Temperature,
(SOIC, MSOP, SOT-23-6) 8LD SOIC package.
MCP6284: Quad Op Amp
MCP6284T: Quad Op Amp a) MCP6283-E/SN: Extended Temperature,
(Tape and Reel) (SOIC, TSSOP) 8LD SOIC package.
MCP6285: Dual Op Amp with Chip Select b) MCP6283-E/MS: Extended Temperature,
MCP6285T: Dual Op Amp with Chip Select 8LD MSOP package.
(Tape and Reel) (SOIC, MSOP) c) MCP6283-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6283T-E/CH: Tape and Reel,
Temperature Range: E = -40°C to +125°C Extended Temperature,
6LD SOT-23 package.
a) MCP6284-E/P: Extended Temperature,
Package: OT = Plastic Small Outline Transistor (SOT-23), 5-lead
14LD PDIP package.
(MCP6281, MCP6281R only)
b) MCP6284T-E/SL: Tape and Reel,
CH = Plastic Small Outline Transistor (SOT-23), 6-lead
Extended Temperature,
(MCP6283 only)
14LD SOIC package.
MS = Plastic MSOP, 8-lead
c) MCP6284-E/SL: Extended Temperature,
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
14LD SOIC package.
SN = Plastic SOIC, (150 mil Body), 8-lead
d) MCP6284-E/ST: Extended Temperature,
SL = Plastic SOIC (150 mil Body), 14-lead
14LD TSSOP package.
ST = Plastic TSSOP (4.4mm Body), 14-lead
a) MCP6285-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6285-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6285-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6285T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office

2. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System

Register on our web site (www.microchip.com) to receive the most current information on our products.

MCP6281/2/3/4/5
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
registered trademarks of Microchip Technology Incorporated
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
in the U.S.A. and other countries.
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, PICMASTER, SEEVAL, SmartSensor and The Embedded
MERCHANTABILITY OR FITNESS FOR PURPOSE. Control Solutions Company are registered trademarks of
Microchip disclaims all liability arising from this information and Microchip Technology Incorporated in the U.S.A.
its use. Use of Microchip’s products as critical components in Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
life support systems is not authorized except with express dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
written approval by Microchip. No licenses are conveyed, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
implicitly or otherwise, under any Microchip intellectual property Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,
rights. MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,
PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,
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Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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E/MS MCP6283T-E/MS MCP6285T-E/MS MCP6281T-E/MS MCP6282T-E/MS MCP6281RT-E/OT MCP6281T-E/OT
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MCP6284T-E/STVAO

450 Μa, 5 Mhz Rail-To-Rail Op Amp: Features Description

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450 Μa, 5 Mhz Rail-To-Rail Op Amp: Features Description

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MCP6281/2/3/4/5

450 µA, 5 MHz Rail-to-Rail Op Amp

VIN+ 3 6 VOUT VINA+ 3 + - 6 VINB_

MCP6283 MCP6283 MCP6284 MCP6285

 2004 Microchip Technology Inc. DS21811D-page 1

DS21811D-page 2  2004 Microchip Technology Inc.

 2004 Microchip Technology Inc. DS21811D-page 3

CS Input Current, Low ICSL — 0.01 — µA CS = VSS

CS Input Current, High ICSH — 0.7 2 µA CS = VDD

GND Current per Amplifier ISS — -0.7 — µA CS = VDD

Amplifier Output Leakage — — 0.01 — µA CS = VDD

VOUT Hi-Z Hi-Z

-0.7 µA (typ.) -0.7 µA (typ.)

FIGURE 1-1: Timing Diagram for the

DS21811D-page 4  2004 Microchip Technology Inc.

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

 2004 Microchip Technology Inc. DS21811D-page 5

Input Bias, Offset Currents

50 Input Offset Current

1 10 100 1k 10k 100k 1M -50 -25 0 25 50 75 100 125

DS21811D-page 6  2004 Microchip Technology Inc.

Ouput Voltage Headroom (mV)

Gain Bandwidth Product

Open-Loop Phase (°)

Phase Margin (°)

1k 10k 100k 1M 10M -50 -25 0 25 50 75 100 125

 2004 Microchip Technology Inc. DS21811D-page 7

Input Noise Voltage Density

10 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

FIGURE 2-20: Output Short Circuit Current FIGURE 2-23: Channel-to-Channel

DS21811D-page 8  2004 Microchip Technology Inc.

Output Voltage (V)

Time (2 µs/div) Time (2 µs/div)

FIGURE 2-25: Large-Signal, Non-inverting FIGURE 2-28: Large-Signal, Inverting

Output Voltage (10 mV/div)

Time (500 ns/div) Time (500 ns/div)

FIGURE 2-26: Small-Signal, Non-inverting FIGURE 2-29: Small-Signal, Inverting

G = +1V/V CS Voltage G = +1V/V

VOUT Output On 3.0

Time (5 µs/div) Time (5 µs/div)

 2004 Microchip Technology Inc. DS21811D-page 9

TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS

3.1 Analog Outputs 3.4 CS Digital Input

DS21811D-page 10  2004 Microchip Technology Inc.

The output voltage range of the MCP6281/2/3/4/5 op

1 4.3 Capacitive Loads

FIGURE 4-3: Output Resistor, RISO

 2004 Microchip Technology Inc. DS21811D-page 11

1,000 VOUTA/VINB+ VINB–

FIGURE 4-5: Cascaded Gain Amplifier.

DS21811D-page 12  2004 Microchip Technology Inc.

FIGURE 4-6: Example Guard Ring Layout

FIGURE 4-8: Miller Integrator.

 2004 Microchip Technology Inc. DS21811D-page 13

FIGURE 4-9: Isolating the Load with a CS

Therefore, it is recommended to set most of the gain

DS21811D-page 14  2004 Microchip Technology Inc.

FIGURE 4-13: Integrator Circuit with Active

 2004 Microchip Technology Inc. DS21811D-page 15

A 5.2 FilterLab® Software

DS21811D-page 16  2004 Microchip Technology Inc.

XXNN MCP6281 CHNN CH25

6-Lead SOT-23 (MCP6283) Example: