Bq2417X 1.6-Mhz Synchronous Switched-Mode Li-Ion and Li-Polymer Stand-Alone Battery Charger With Integrated Mosfets and Power Path Selector
Bq2417X 1.6-Mhz Synchronous Switched-Mode Li-Ion and Li-Polymer Stand-Alone Battery Charger With Integrated Mosfets and Power Path Selector
bq24170, bq24172
SLUSAD2C – NOVEMBER 2010 – REVISED APRIL 2015
– ±4% Charge Current Regulation (1) For all available packages, see the orderable addendum at
the end of the data sheet.
C6
AVCC 1m
C1
R6 1µ PGND
1000 k
OVPSET
SRP
R7 VREF C3: 0.1 m
100 k TTC SRN
R8
5.23 k
TS CELL Float
R9 R10
RT 1.5 k
30.1 k THERMAL
103AT STAT PAD
VREF D3
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24170, bq24172
SLUSAD2C – NOVEMBER 2010 – REVISED APRIL 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.3 Feature Description................................................. 15
2 Applications ........................................................... 1 9.4 Device Functional Modes........................................ 24
3 Description ............................................................. 1 10 Application and Implementation........................ 25
4 Revision History..................................................... 2 10.1 Application Information.......................................... 25
10.2 Typical Application ............................................... 25
5 Description (continued)......................................... 3
10.3 System Examples ................................................. 28
6 Device Comparison Table..................................... 3
11 Power Supply Recommendations ..................... 31
7 Pin Configuration and Functions ......................... 4
12 Layout................................................................... 31
8 Specifications......................................................... 6
12.1 Layout Guidelines ................................................. 31
8.1 Absolute Maximum Ratings ...................................... 6
12.2 Layout Examples................................................... 32
8.2 ESD Ratings.............................................................. 6
8.3 Recommended Operating Conditions....................... 6 13 Device and Documentation Support ................. 33
13.1 Related Links ........................................................ 33
8.4 Thermal Information .................................................. 6
13.2 Trademarks ........................................................... 33
8.5 Electrical Characteristics........................................... 7
13.3 Electrostatic Discharge Caution ............................ 33
8.6 Typical Characteristics ............................................ 11
13.4 Glossary ................................................................ 33
9 Detailed Description ............................................ 14
9.1 Overview ................................................................. 14 14 Mechanical, Packaging, and Orderable
Information ........................................................... 33
9.2 Functional Block Diagram ....................................... 14
4 Revision History
Changes from Revision B (April 2011) to Revision C Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
• Changed FEATURES third bullet to 30-V Input Rating with Adjustable Overvoltage Protection and added sub-bullet:
4.5-V to 17-V Input Operating Voltage Range........................................................................................................................ 1
• Added a new paragraph in DESCRIPTION on page 2, second paragraph ........................................................................... 3
• Deleted last sentence in Pin NO. 19, Description column...................................................................................................... 4
• Added 2nd row in the ABS MAX TABLE, moving AVCC,....STAT from first row to second row and adding -0.3 to 30
in Value column. Also moved ACDRV to this row from next row........................................................................................... 6
• Changed RECOMMENDED OPERATING CONDITIONS Output current row, MIN column from 600 to 0.6 ....................... 6
• Changed MIN and MAX columns from 1.55 to 1.57, and 1.65 to 1.63 in first row under INPUT OVER-VOLTAGE
COMPARATOR (ACOV) section in ELECTRICAL CHARACTERISTICS table..................................................................... 9
• Changed MIN, TYP, MAX column from 0.45 to 0.487, 0.5 to 0.497 and 0.55 to 0.507 in first row under INPUT
UNDER-VOLTAGE COMPARATOR (ACUV) section in ELECTRICAL CHARACTERISTICS table ..................................... 9
• Added paragraph to INPUT FILTER DESIGN section ......................................................................................................... 27
• Added diode between BTST and REGN pins in Figure 23 .................................................................................................. 28
• Added diode between BTST and REGN pins in Figure 25 .................................................................................................. 30
5 Description (continued)
The device charges the battery in three phases: precondictioning, constant current, and constant voltage.
Charge is terminated when the current reaches 10% of the fast charge rate. A programmable charge timer offers
a safety backup. The bq2417x automatically restarts the charge cycle if the battery voltage falls below an internal
threshold, and enters a low-quiescent current sleep mode when the input voltage falls below the battery voltage.
The bq2417x features Dynamic Power Management (DPM) to reduce the charge current when the input power
limit is reached to avoid overloading the adapter. A highly accurate current-sense amplifier enables precise
measurement of input current from adapter to monitor overall system power.
The bq2417x provides power path selector gate driver ACDRV/CMSRC on input NMOS pair ACFET (Q1) and
RBFET (Q2), and BATDRV on a battery PMOS device (Q3). When the qualified adapter is present, the system is
directly connected to the adapter. Otherwise, the system is connected to the battery. In addition, the power path
prevents battery from boosting back to the input.
The bq2417x charges a battery from a DC source as high as 17 V, including a car battery. The input overvoltage
limit is adjustable through the OVPSET pin. The AVCC, ACP, and ACN pins have a 30-V rating. When a high-
voltage DC source is inserted, Q1 and Q2 remain off to avoid high voltage damage to the system.
For 1-cell applications, if the battery is not removable, the system can be directly connected to the battery to
simplify the power path design and reduce the cost. With this configuration, the battery can automatically
supplement the system load if the adapter is overloaded.
The bq2417x is available in a 24-pin, 5.5-mm × 3.5-mm thin VQFN package.
RGY Package
24-Pin VQFN
Top View
SW
SW
1 24
PVCC 2 23 PGND
PVCC 3 22 PGND
AVCC 4 21 BTST
ACN 5 20 REGN
ACP 6 19 BATDRV
CMSRC 7
AGND 18 OVPSET
ACDRV 8 17 ACSET
STAT 9 16 SRP
TS 10 15 SRN
TTC 11 14 CELL/FB
12 13
VREF
ISET
Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
AC adapter to system switch driver output. Connect to 4-kΩ resistor then to the gate of the ACFET N-
channel power MOSFET and the reverse conduction blocking N-channel power MOSFET. Connect both
ACDRV 8 O
FETs as common-source. The internal gate drive is asymmetrical, allowing a quick turnoff and slower
turnon in addition to the internal break-before-make logic with respect to the BATDRV.
Adapter current sense resistor negative input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to
ACN 5 I provide differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND
for common-mode filtering.
Adapter current sense resistor positive input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to
ACP 6 P/I provide differential-mode filtering. A 0.1-µF ceramic capacitor is placed from ACP pin to AGND for
common-mode filtering.
Input current set point. Use a voltage divider from VREF to ACSET to AGND to set this value:
ACSET 17 I VACSET
IDPM =
20 ´ R AC
Exposed pad beneath the IC. Always solder Thermal Pad to the board, and have vias on the Thermal
Thermal
AGND P Pad plane star-connecting to AGND and ground plane for high-current power converter. It dissipates the
Pad
heat from the IC.
IC power positive supply. Place a 1-µF ceramic capacitor from AVCC to AGND and place it as close as
AVCC 4 P possible to IC. Place a 10-Ω resistor from input side to AVCC pin to filter the noise. For 5-V input, a 5-Ω
resistor is recommended.
Battery discharge MOSFET gate driver output. Connect to 1-kΩ resistor to the gate of the BATFET P-
channel power MOSFET. Connect the source of the BATFET to the system load voltage node. Connect
BATDRV 19 O the drain of the BATFET to the battery pack positive node. The internal gate drive is asymmetrical to
allow a quick turnoff and slower turnon, in addition to the internal break-before-make logic with respect to
ACDRV.
BTST 21 P PWM high-side driver positive supply. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
(bq24170) Cell selection pin. Set CELL pin LOW for 1-cell, Float for 2-cell (0.8 V - 1.8 V), and HIGH for 3-
CELL
cell with a fixed 4.2 V per cell.
14 I (bq24172) Charge voltage analog feedback adjustment. Connect the output of a resistor divider powered
FB from the battery terminals to VFB to AGND. Output voltage is regulated to 2.1 V on FB pin during
constant-voltage mode.
Connect to common source of N-channel ACFET and reverse blocking MOSFET (RBFET). Place 4-kΩ
CMSRC 7 O resistor from CMSRC pin to the common source of ACFET and RBFET to control the turnon speed. The
resistance between ACDRV and CMSRC should be 500 kΩ or bigger.
ISET 13 I
VISET
ICHG =
20 ´ RSR
The precharge and termination current is internally as one tenth of the charge current. The charger is
disabled when ISET pin voltage is below 40 mV and enabled when ISET pin voltage is above 120 mV.
Valid input voltage set point. Use a voltage divider from input to OVPSET to AGND to set this voltage.
The voltage above internal 1.6-V reference indicates input overvoltage, and the voltage below internal
OVPSET 18 I
0.5-V reference indicates input undervoltage. In either condition, charge terminates, and input NMOS pair
ACFET/RBFET turn off. LED driven by STAT pin keeps blinking, reporting fault condition.
Power ground. Ground connection for high-current power converter node. On PCB layout, connect
PGND 22,23 P directly to ground connection of input and output capacitors of the charger. Only connect to AGND
through the Thermal Pad underneath the IC.
Charger input voltage. Connect at least 10-µF ceramic capacitor from PVCC to PGND and place it as
PVCC 2,3 P
close as possible to IC.
PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to PGND
REGN 20 P
pin, close to the IC. Generate high-side driver bootstrap voltage by integrated diode from REGN to BTST.
Charge current sense resistor negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to
SRN 15 I provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRN pin to AGND for
common-mode filtering.
Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to
SRP 16 I/P provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to AGND for
common-mode filtering.
Open-drain charge status pin with 10-kΩ pullup to power rail. The STAT pin can be used to drive LED or
communicate with the host processor. It indicates various charger operations: LOW when charge in
STAT 9 O
progress. HIGH when charge is complete or in SLEEP mode. Blinking at 0.5 Hz when fault occurs,
including charge suspend, input overvoltage, timer fault and battery absent.
Switching node, charge current output inductor connection. Connect the 0.047-µF bootstrap capacitor
SW 1,24 P
from SW to BTST.
Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program
TS 10 I the hot and cold temperature window with a resistor divider from VREF to TS to AGND. The temperature
qualification window can be set to 5-40°C or wider. The 103AT thermistor is recommended.
Safety Timer and termination control. Connect a capacitor from this node to AGND to set the fast charge
safety timer(5.6 min/nF). Precharge timer is internally fixed to 30 minutes. Pull the TTC to LOW to disable
TTC 11 I
the charge termination and safety timer. Pull the TTC to HIGH to disable the safety timer but allow the
charge termination.
3.3-V reference voltage output. Place a 1-μF ceramic capacitor from VREF to AGND pin close to the IC.
VREF 12 P This voltage could be used for programming ISET and ACSET and TS pins. It may also serve as the
pullup rail of STAT pin and CELL pin.
8 Specifications
8.1 Absolute Maximum Ratings
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
PVCC –0.3 20
AVCC, ACP, ACN, ACDRV, CMSRC, STAT –0.3 30
BTST –0.3 26
BATDRV, SRP, SRN –0.3 20
Voltage (with respect to
SW –2 20 V
AGND)
FB (bq24172) –0.3 16
OVPSET, REGN, TS, TTC, CELL (bq24170) –0.3 7
VREF, ISET, ACSET –0.3 3.6
PGND –0.3 0.3
Maximum difference voltage SRP–SRN, ACP-ACN –0.5 0.5 V
Junction temperature, TJ –40 155 °C
Storage temperature, Tstg –55 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult packaging
section of the data book for thermal limitations and considerations of packages.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Recharge Threshold, below regulation voltage bq24170, CELL floating, 2 cells, measure on
140 200 260
VRECHG limit, VBAT_REG-VSRN (bq24170), or VFB_REG-VFB SRN mV
(bq24172) bq24170, CELL to VREF, 3 cells, measure on
210 300 390
SRN
bq24172, measure on FB 35 50 65
tRECH_RISE_DEG VRECHG rising deglitch VFB decreasing below VRECHG 10 ms
tRECH_FALL_DEG VRECHG falling deglitch VFB increasing above VRECHG 10 ms
BAT OVERVOLTAGE COMPARATOR
As percentage of VBAT_REG (bq24170) or
VOV_RISE Overvoltage rising threshold 104%
VFB_REG (bq24172)
Wake threshold with respect to VREG To detect Measure on SRN (bq24170) 100 mV/cell
VWAKE
battery absent during WAKE Measure on FB (bq24172) 50 mV
Discharge Threshold to detect battery absent Measure on SRN (bq24170) 2.9 V/cell
VDISCH
during discharge Measure on VFB (bq24172) 1.45 V
INTERNAL PWM
fsw PWM Switching Frequency 1360 1600 1840 kHz
(1) Dead time when switching between LSFET
tSW_DEAD Driver Dead Time 30 ns
and HSFET no load
RDS_HI High-Side MOSFET ON-Resistance VBTST – VSW = 4.5 V 25 45 mΩ
RDS_LO Low-Side MOSFET ON-Resistance 60 110 mΩ
VBTST – VSW when low-side refresh pulse is
3
Bootstrap Refresh Comparator Threshold requested, VAVCC = 4.5 V
VBTST_REFRESH V
Voltage VBTST – VSW when low-side refresh pulse is
4
requested, VAVCC > 6 V
INTERNAL SOFT START (8 steps to regulation current ICHG)
SS_STEP Soft start steps 8 step
TSS_STEP Soft start step time 1.6 3 ms
(1) All waveforms and data are measured on HPA610 and HPA706 EVMs.
ISET
500mV/div
AVCC
10V/div REGN
5V/div
VREF
2V/div STAT
10V/div
ACDRV
5V/div
IL
STAT 1A/div
10V/div
ISET
500mV/div
PH
5V/div
PH
5V/div
IL
IOUT
2A/div
1A/div
4 ms/div 2 ms/div
PH PH
5V/div 5V/div
IL
1A/div
IL
1A/div
Figure 5. Continuous Conduction Mode Switching Figure 6. Discontinuous Conduction Mode Switching
AVCC
10V/div
ACDRV IIN
10V/div 1A/div
ISYS
2A/div
VSYS
10V/div
BATDRV IOUT
10V/div 1A/div
Figure 7. BATFET to ACFET Transition During Power Up Figure 8. System Load Transient (Input Current DPM)
SRN SRN
5V/div 5V/div
PH
10V/div PH
10V/div
IL IL
1A/div 1A/div
Figure 9. Battery Insertion and Removal Figure 10. Battery-to-Ground Short Protection
96
94
SRN
5V/div 92
Efficiency - % 90
IL
1A/div 84
82
4 ms/div
80
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Charge Current - A
Figure 11. Battery-to-Ground Short Transition Figure 12. Efficiency vs Output Current (VIN = 15 V)
94
90
Efficiency - %
88
86
84
82
80
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Charge Current - A
9 Detailed Description
9.1 Overview
The bq2417x device is a stand-alone switched-mode battery charger for Li-ion and Li-Polymer batteries with
power path management and integrated N-channel power MOSFETs. This fixed-frequency synchronous PWM
charger offers high accuracy regulation of input current charge current and battery regulation voltage.
VREF
VREF 12
LDO
2.05V
RCHRG
Thermal PAD
AVCC REGN
BAT_OVP 20 REGN
CE LDO
2.184V
21 BTST
SRN
FBO EAI
2 PVCC
CELL (170) bq24170
14 3 PVCC
FB (172)
2.1V 1V LEVEL
SHIFTER
bq24172 1 SW
IC TJ PWM 24 SW
REGN
120C 20μA CONTROL
EAO PWM
ACP 6 20xIAC
20X 22 PGND
ACN 5
23 PGND
5mV UCP
ACSET 17
CE VSRP-VSRN
VSRP-VSRN OCP
120mV
160%xVISET/20
ISET 13 REFRESH
Fast-Chrg IBAT_REG VSW+4.2V
Pre-Chrg
VBTST
Selection
LOWV 20μA
EN_CHARGE
9 STAT
SRP 16 CE
20xICHG
20X RCHRG
Charge Discharge
SRN 15 Termination
10%xVISET Termination
Qualification VREF
2V STATE
Discharge Termination Fault BAT_SHORT MACHINE LTF
Qualification
VSRN
IDISCHARGE IQUAL IFAULT
SUSPEND HTF
Fast Charge Timer Timer Fault
TTC 11 (TTC)
Precharge Timer 10 TS
OVPSET 18 ACOV (30 mins) ACOV
TCO
1.6V ACUV
IC TJ TSHUT SLEEP
0.5V ACUV
TSHUT UVLO
Charge
Current
Charge
Voltage
VLOWV
10% ICHRG
Precharge
Fast Charge Safety Timer
Timer
The bq24172 uses external resistor divider for voltage feedback and regulate to internal 2.1-V voltage reference
on FB pin. Use the following equation for the regulation voltage for bq24172:
é R2 ù
VBAT = 2.1 V ´ ê1+
ë R1 úû
where
• R2 is connected from FB to the battery.
• R1 is connected from FB to GND. (1)
where
• VISET is the voltage on the ISET pin.
• RSR is the sense resistor. (5)
There is a 25-ms deglitch time during transition between fast charge and precharge.
As a safety backup, the charger also provides an internal fixed 30-minute precharge safety timer and a
programmable fast charge timer. The fast charge time is programmed by the capacitor connected between the
TTC pin and AGND, and is given by the formula:
where
• CTTC is the capacitor connected to TTC.
• KTTC is the constant multiplier. (6)
A new charge cycle is initiated when one of the following conditions occurs:
• The battery voltage falls below the recharge threshold
• A power-on-reset (POR) event occurs
• ISET pin toggled below 40 mV (disable charge) and above 120 mV (enable charge)
Pull the TTC pin to AGND to disable both termination and fast charge safety timer (reset timer). Pull the TTC pin
to VREF to disable the safety timer, but allow charge termination.
9.3.6 Power Up
The charge uses a SLEEP comparator to determine the source of power on the AVCC pin because AVCC can
be supplied either from the battery or the adapter. With the adapter source present, if the AVCC voltage is
greater than the SRN voltage, the charger exits SLEEP mode. If all conditions are met for charging, the charger
then starts charge the battery (see Enable and Disable Charging). If SRN voltage is greater than AVCC, the
charger enters low quiescent current SLEEP mode to minimize current drain from the battery. During SLEEP
mode, the VREF output turns off and the STAT pin goes to high impedance.
If AVCC is below the UVLO threshold, the device is disabled.
POR or RECHARGE
1s timer
VFB < VBATOWV No No
expired
Yes Yes
0.5s timer
VFB > VRECH No No
expired
Yes
Yes
Battery Present,
Disable 125mA Begin Charge
charge current
Battery Absent
Once the device has powered up, an 8-mA discharge current is applied to the SRN terminal. If the battery
voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is
turned on at low charge current (125 mA). If the battery voltage gets up above the recharge threshold within 500
ms, there is no battery present and the cycle restarts. If either the 500-ms or 1-second timer times out before the
respective thresholds are hit, a battery is detected and a charge cycle is initiated.
Battery Battery
Absent Absent
VBAT_RE
VRECH
Battery
VLOW Present
Ensure that the total output capacitance at the battery node is not so large that the discharge current source
cannot pull the voltage below the LOWV threshold during the 1 second discharge time. The maximum output
capacitances can be calculated according to the following equations:
IDISCH ´ tDISCH
CMAX = (for bq24170)
(4.1 V - 2.9 V) ´ Number of cells (7)
IDISCH ´ tDISCH
CMAX = (for bq24172)
é R2 ù
(2.05 V - 1.45 V) ´ ê1+ ú
ë R1 û
where
• CMAX is the maximum output capacitance.
• IDISCH is the discharge current.
• tDISCH is the discharge time.
• R2 and R1 are the voltage feedback resistors from the battery to the FB pin. (8)
9.3.15.1 Example
For a 3-cell Li+ charger, with R2 = 500 kΩ, R1 = 100 kΩ (giving 12.6 V for voltage regulation), IDISCH = 8 mA,
tDISCH = 1 second.
8 mA ´ 1 sec
CMAX = = 2.2 mF
é 500 kW ù
0.6 V ´ ê1+ ú
ë 100 kW û (9)
Based on these calculations, no more than 2200 µF should be allowed on the battery node for proper operation
of the battery detection circuit.
VHTF
VTCO
CHARGE SUSPENDED CHARGE SUSPENDED
AGND AGND
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 18, the values of RT1 and RT2 can
be determined by using Equation 10 and Equation 11:
æ 1 1 ö
VVREF ´ RTHCOLD ´ RTHHOT ´ ç - ÷
V
è LTF VTCO ø
RT2 =
æV ö æV ö
RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷
è VTCO ø è VLTF ø (10)
VVREF
-1
VLTF
RT1 =
1 1
+
RT2 RTHCO LD (11)
Select 0°C to 45°C range for Li-ion or Li-polymer battery,
RTHCOLD = 27.28 kΩ
RTHHOT = 4.911 kΩ
RT1 = 5.23 kΩ
RT2 = 30.1 kΩ
After selecting the closest standard resistor value, by calculating the thermistor resistance at temperature
threshold, the final temperature range can be gotten from thermistor data sheet temperature resistance table.
VREF
bq24170 RT1
bq24172
TS
RT2 RTH
103AT
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
C6
AVCC 1m
C1
R6 1µ PGND
1000 k
OVPSE T
SRP
R7 VREF C3: 0.1 m
100 k TTC SRN
R8
5.23 k
TS CELL Float
R9 R10
RT 1.5k
30.1 k THERMAL
103AT STAT PAD
VREF D3
12-V input, 2-cell battery 8.4 V, 2-A charge current, 0.2-A precharge/termination current, 3-A DPM current, 18-V input
OVP, 0 – 45°C TS
The bq2417x has an internal loop compensator. To achieve good loop stability, the resonant frequency of the
output inductor and output capacitor should be designed from 15 kHz to 25 kHz. The preferred ceramic capacitor
has a 25-V or higher rating, X7R or X5R.
RIN C4 1m CSYS
2 RGS 40?
CIN CGS 499k
2. ?
2.2? CGD PVCC
R12
4.02k CMSRC
R11
4.02k
ACDRV
92%
Efficiency (%)
90%
88%
86%
84%
82%
80%
0 0.5 1 1.5 2 2.5 3 3.5 4
IOUT (A) D001
Figure 22. Charge Efficiency
RevFET Q4
RAC: 20m
Adapter 0.1µ System
Or USB
0.1µ
4.7µ
ACN PVCC
ACP
CMSRC BATDRV
1µ
ACDRV 3.3mH RSR: 10m VBAT
VREF
VREF VREF SW
R2
Selectable input
R4 100k bq24170
current limit 0.1m
100k ISET 0.047m
R3
R5B 32.4k
BTST
R11 0.1m 10m 10m
R5A D1
5 8.06k
32.4k ACSET REGN Optional
ILIM_500mA
1m
R6 C1 AVCC
845k 1µ
PGND
OVPSET
SRP
R7
VREF
100k
R8 TTC SRN
6.81k
R10 TS CELL
RT R9
1.5k THERMAL
133k
103AT STAT PAD
VREF D3
USB or adapter with input OVP 15 V, up to 4-A charge current, 0.4-A precharge current, 2-A adapter current or 500-
mA USB current, 5 – 40°C TS, system connected before sense resistor
Q1 Q2
RAC: 10m System
15-V Adapter C12: 0.1µ
RIN
2 C11: 0.1µ
C4
CIN ACN PVCC 10µ
2.2m Q3
ACP R14
R12 1k
R11 4.02k CMSRC BATDRV
VBAT 4.02k
ACDRV L: 2.2mH RSR:10m
C2: 1µ VBAT
VREF SW
D2 D1
VREF R21
100k
bq24172 C5 C8
R4 ISET 0.047m 0.1m
100k R22 BTST
R20
32.4k C7 C9, C10
10
R5 ACSET 0.1m m 10m
20m
32.4k
REGN
C6
AVCC 1m
C1
R6 1µ
499k PGND
OVPSET
Battery LEARN R7 C3: 0.1m
SRP
VREF
49.9k
R8
TTC SRN R2
VREF LEARN R17
5.23k 499k
R20 FB 49.9k TS
R9 R10 FB
599k RT 30.1k 1.5k THERMAL R1
R21 103AT STAT PAD 100k
499k VREF D3
15-V input, 3-cell battery 12.6 V, 4-A charge current, 0.4-A precharge/termination current, 4-A DPM current, 0 – 45°C
TS
4.7µ
ACN PVCC
ACP
CMSRC BATDRV
ACDRV 3.3mH RSR: 20m VBAT
1µ
VREF SW
VREF VREF
Selectable
current limit
R4 bq24172 0.1m
100k ISET 0.047m
R5B
BTST
R11 0.1m 10m10m
R5A D1
12.1k
12.1
5 12.1k ACSET REGN Optional
ILIM_500mA
1m
R6 C1 AVCC
400k 1µ
PGND
OVPSET
SRP
R7
VREF
100k
R8 TTC SRN R2
5.23k 100k
R10 TS FB
RT R9
1.5k THERMAL R1
30.1k
103AT STAT PAD 100k
VREF D3
USB with input OVP 8 V, selectable charge current limit of 900 mA or 500 mA, 0 – 45°C TS, system connected after
sense resistor
12 Layout
High
Frequency
VIN BAT
Current
C1 Path C2 C3
PGND
Current Direction
R SNS
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
BQ24170RGYR ACTIVE VQFN RGY 24 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24170
& no Sb/Br)
BQ24170RGYT ACTIVE VQFN RGY 24 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24170
& no Sb/Br)
BQ24172RGYR ACTIVE VQFN RGY 24 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24172
& no Sb/Br)
BQ24172RGYT ACTIVE VQFN RGY 24 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ24172
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Aug-2014
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Aug-2014
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGY 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5.5 x 3.5 mm, 0.5 mm pitch
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4203539-5/J
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