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Short Papers: LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
Short Papers: LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
2, FEBRUARY 2007
Short Papers
LFSR-Reseeding Scheme Achieving Low-Power be considered when a seed is computed because they are don’t care
Dissipation During Test bits. Therefore, the size of a seed is much smaller than the size of a
test vector. Consequently, reseeding can significantly reduce test-data
Jinkyu Lee and Nur A. Touba storage and bandwidth.
Several reseeding schemes have been proposed to reduce test stor-
age. The first was introduced in [3], where it was shown that if smax is
Abstract—This paper presents a new low-power test-data-compression
the largest number of specified bits in any test cube, then for an LFSR
scheme based on linear feedback shift register (LFSR) reseeding. A draw-
back of compression schemes based on LFSR reseeding is that the unspec- of length smax + 20 bits, the probability of not being able to find a seed
ified bits are filled with random values, which results in a large number of for some test cube is less than 10−6 . Several techniques were proposed
transitions during scan-in, thereby causing high-power dissipation. A new to improve the encoding efficiency of the basic scheme in [3] including
encoding scheme that can be used in conjunction with any LFSR-reseeding using multiple-polynomial LFSRs [4], test cube concatenation [5], and
scheme to significantly reduce test power and even further reduce test
storage is presented. The proposed encoding scheme acts as the second variable-length seeds [6]. More recent work has focused on dynamic
stage of compression after LFSR reseeding. It accomplishes two goals. LFSR reseeding where the seed is incrementally modified as the LFSR
First, it reduces the number of transitions in the scan chains (by filling the runs [1], [2], [7]. In dynamic LFSR reseeding, the size of a seed does
unspecified bits in a different manner). Second, it reduces the number of not depend on smax and thus can be even smaller than the size of
specified bits that need to be generated via LFSR reseeding. Experimental
an LFSR.
results indicate that the proposed method significantly reduces test power
and in most cases provides greater test-data compression than LFSR While reseeding is a very powerful method for test-data compres-
reseeding alone. sion, it is not good for power consumption. The don’t care bits in each
Index Terms—Reseeding, test-data compression, test power. test cube get filled with random values, thereby resulting in excessive
switching activity when they are shifted into a scan chain. During
normal operation, typically, only a small percentage of flip-flops make
I. I NTRODUCTION transitions during each clock cycle. However, when scanning test
Power dissipation during test is a significant problem as the size vectors whose 95%–99% of the bits have been filled with random
and complexity of systems-on-chip (SOCs) continue to grow. During values, a very large percentage of the flip-flops will make transitions,
scan shifting, more transitions occur in the flip-flops compared to thereby resulting in excessive power consumption during test. The chip
what occurs during normal functional operation. This problem is may be designed to only handle the power consumption during normal
further compounded when pseudorandom filling of the unassigned operation, and thus the excessive power consumption during test can
input values is employed. Excessive power dissipation during test can result in overheating. One solution to this problem is to simply reduce
increase manufacturing costs by requiring the use of a more expensive the scan frequency; however, this results in longer test times.
chip packaging or causing unnecessary yield loss. In this paper, a new Many techniques for reducing power consumption during scan
test-data-compression scheme based on linear feedback shift register testing have been presented and are summarized in [8]. It was only
(LFSR) reseeding that significantly reduces power consumption during recently that work has been done on considering together the problems
test is proposed. of test-data compression and low-power test. Research in this direction
Test-data volume has also increased dramatically as the size and has been presented in [9]–[12] and is summarized in Section II.
the complexity of chips grow. Consequently, there has been a lot of In this paper, we present a new encoding algorithm that can be
work on test-data-compression schemes that can be used to reduce used in conjunction with any LFSR-reseeding scheme to significantly
tester storage and bandwidth requirements. Commercial tools for test- reduce power consumption during test (preliminary results were pre-
data compression, which are based on LFSR reseeding including sented in [13]). A key feature of the proposed approach is that it
TestKompress by Mentor Graphics [1], SOC BIST by Synopsys, and reduces the number of specified bits and the number of transitions at
ELT-Comp by LogicVision, have been introduced. the same time. Since the amount of compression for LFSR reseeding
The basic idea in LFSR reseeding is to generate deterministic test depends on the number of specified bits, the proposed approach
cubes by expanding seeds. A seed is an initial state of the LFSR that exploits this property.
is expanded by running the LFSR. Given a deterministic test cube, In Section II, we review the related work. In Section III, we
a corresponding seed can be computed by solving a set of linear introduce the new encoding scheme. Section IV explains a hardware
equations (one equation for each specified bit) based on the feedback implementation for the proposed scheme. Section V shows the experi-
polynomial of the LFSR. Since typically only 1%–5% of the bits in mental results, and Section VI concludes this paper.
a test vector are specified, most bits in a test cube do not need to
II. R ELATED W ORK
The idea of considering together the problems of test-data com-
pression and low-power test has been previously investigated in a few
Manuscript received August 17, 2005; revised January 11, 2006. This work papers. In [9], a procedure for directing the static compaction process
was supported in part by Intel Corporation and in part by the National Science in a manner that reduces test power and test data was described. In
Foundation under Grant CCR-0306238. This paper was recommended by [10], an encoding algorithm that reduces both test storage and test
Associate Editor S. M. Reddy. power was presented. The test cubes are encoded using a Golomb
The authors are with the Computer Engineering Research Center, Depart-
ment of Electrical and Computer Engineering, University of Texas, Austin, TX
code, which is a run-length code. All don’t care bits are mapped to
78712-1084 USA (e-mail: [email protected]). 0, and the Golomb code is used to encode runs of 0s. The Golomb
Digital Object Identifier 10.1109/TCAD.2006.882509 code compresses the test data, and the mapping of the don’t cares to
all 0s reduces the number of transitions during scan-in and thus power. and not through bypassing. In [14], scan-chain reconfiguration is
One drawback of a Golomb code is that it is very inefficient for runs necessary, which requires inserting design for test (DFT) logic in the
of 1s; thus, an extension based on an alternating run-length code was scan chains themselves to provide the bypass capability, whereas for
described in [11]. the proposed scheme, the DFT logic is inserted only at the inputs
While both Golomb codes and alternating run-length codes are good of the scan chains and is thus compatible with conventional scan
for reducing test power, they are not as efficient as LFSR reseeding for chains. The proposed scheme can be used for hard cores and firm cores.
compressing test data. With LFSR reseeding, only the specified bits,
which generally account for only 1%–5% of the test data, need to be III. E NCODING A LGORITHM
considered.
One previous method has been proposed in [12] for reducing test Let a transition in a test cube be defined as a specified 0 (1), followed
power for LFSR reseeding. Two LFSRs are used. The main LFSR by 0 or more Xs and then by a specified 1 (0). The key idea of the
generates the test cube through conventional reseeding. An extra proposed encoding algorithm is to take advantage of the fact that the
“masking” LFSR is used to generate a set of mask bits. If the number number of transitions in a test cube is always less than the number of
of 1s in a test cube is less than the number of 0s, then the outputs of specified bits in a test cube. Thus, rather than using LFSR reseeding to
the two LFSRs are ANDed together, and the mask cube will have a 1 directly encode the specified bits as in conventional LFSR reseeding,
for each specified 1 in the test cube and an X for each specified 0 or the proposed encoding algorithm divides the test cube into blocks
X in the test cube. If the number of 0s in the test cube is less than the and only uses LFSR reseeding to produce the blocks that contain
number of 1s, then the outputs of the two LFSRs are ORed together, transitions. For the blocks that do not contain transitions, the logic
and the mask cube will have a 0 for each specified 0 in the test cube value fed into the scan chain is simply held constant. This approach
and an X for each specified 1 or X in the test cube. A seed is computed reduces the number of transitions in the scan chains and in most cases
for the extra masking LFSR so that it generates the mask cube. Thus, also reduces the total number of specified bits that must be generated
the effective number of specified bits that must be generated using this by the LFSR as compared with conventional LFSR reseeding.
method is equal to the original number of specified bits in the test cube
plus the number of specified bits in each mask cube (which is equal A. Basic Concepts
to the minimum of the number of 0s or 1s in each test cube). The size
of the main LFSR is the same as that for conventional reseeding, and The proposed encoding scheme encodes each test cube with two
the size of the extra masking LFSR depends on the maximum number kinds of data: “hold flags” and “data bits.” Each test cube is divided
of specified bits in any mask cube. Test power is reduced because the into several blocks, and each block has a 1-bit hold flag. The hold flag
outputs of the two LFSRs are ANDed or ORed, thus reducing the transi- indicates whether a transition occurs in a block. There are three types
tion probability. However, the test-data compression for this scheme is of blocks.
greatly reduced compared with conventional LFSR reseeding because 1) Transition block (hold flag = 0).
it requires storing an extra set of seeds for the extra masking LFSR. One or more transitions exist in the block. Either both 0 and 1
Results in this paper indicate that the test storage was increased by are present in the block (e.g., XX1X0X) or only 0 or 1 is present,
21%–54% compared with conventional LFSR reseeding, while the but the last specified bit from a previous block was the opposite
transition count was reduced by about 24%. The proposed method value.
addresses the problem of reducing test power for LFSR reseeding. 2) Nontransition block (hold flag = 1).
However, a different approach that does not compromise the amount of No transition occurs in the current block. Only 0 or 1 is
test-data compression is taken. Moreover, the number of transitions is present in the block, and the last specified bit from a previous
reduced much more significantly than in [12]. The experimental results block is same (e.g., X0XX0X).
for the proposed method are compared with the previous methods in 3) Don’t care block (hold flag = X).
Section V. No specified bits occur in the block; all are don’t cares.
The proposed scheme has some similarity to the dynamic-scan If the hold flag for a block is 1, then the data bits in the block are
scheme presented in [14]; however, there are a number of significant simply held constant from the last data bit in the previous block. If the
differences. Both schemes use the fact that different test cubes have hold flag is 0, then the data bits are loaded directly from the LFSR.
compatible values for a significant number of scan elements. The If the hold flag is X, then it can be treated either as a nontransition
dynamic-scan scheme identifies scan-chain segments that have com- block or as a transition block with all X data. Both the hold flags
patible values across a set of test cubes and bypasses those segments and the data bits are generated from a single LFSR using reseeding.
in order to reduce test time and test storage. This approach also serves An example of the proposed encoding is shown in Fig. 1. The test
to reduce power, although this is not the focus of this paper. The sequence in the example is composed of four blocks, and each block
proposed scheme also takes advantage of compatible scan segments has one hold flag and four data bits. The hold flags are shown in bold
but in a different way. The proposed scheme exploits the property that along the “Encoded” bit sequence row. In Fig. 1, the original test cube
the number of transitions in a test cube is smaller than the number of contains seven specified bits. However, using the proposed encoding
specified bits. By dividing the scan chains into blocks and identifying scheme, the encoded data only has three specified hold flags and two
blocks that do not contain transitions, the proposed approach is able specified data bits, giving a total of only five specified bits. Thus,
to fill those blocks with constant values. The compatibility of blocks the proposed encoding scheme reduces the number of specified bits
across different test cubes is exploited by reducing control information that need to be generated using LFSR reseeding. As shown in Fig. 1,
398 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007
Fig. 2. Example of conversion procedure (the last bit of blocks 1 and 3 are specified to convert blocks 2 and 4 into nontransition blocks).
B. Conversion Procedure
It is possible to increase the number of nontransition blocks by
converting some transitions blocks into nontransition blocks. There are
two requirements that must be satisfied in order to convert a transition
block into a nontransition block. The first is that it cannot contain
both specified 0s and specified 1s. The second is that the last bit of Fig. 3. Hold-cube regeneration and reordering. (a) Hold cube before parti-
tioning. (b) Hold cube after partitioning.
the previous block must be an X. Two examples of this are shown
in Fig. 2. Block 2 is initially a transition block even though it only
contains specified 0s because the last specified bit in block 1 was a 1.
However, the very last bit of block 1 is a don’t care, so a “conversion
procedure” can be used to specify that don’t care as a 0 and thereby
convert block 2 into a nontransition block. Even though this conversion
required adding an extra specified data bit, the net result is still a
reduction in the total number of specified bits because now block 2 is a
nontransition block; thus, none of its data bits need to be generated by
the LFSR. This same conversion procedure can also be used to convert
block 4 in Fig. 2 into a nontransition block.
By increasing the number of nontransition blocks, the conversion
procedure can help to reduce both test storage (since it can reduce
the total number of specified bits) and test power (since it can reduce
the number of transitions by enabling all the Xs in the converted
nontransition block to be filled with the same logic value).
TABLE I
RESULTS FOR THE PROPOSED ENCODING SCHEME
will typically have a large number of don’t cares. Thus, the test cubes IV. H ARDWARE I MPLEMENTATION
can be generally partitioned into a relatively small number of hold-
cube-compatible sets. The test cubes can then be ordered so that the The hardware implementation of the proposed scheme is shown in
test cubes in each hold-cube-compatible set will occur in succession. Fig. 4. Each scan chain is divided into one or more blocks. Let B be
Thus, the hold flags only need to be loaded once for each hold-cube- the number of blocks per scan chain. Each scan chain has a “hold-flag
compatible set. One extra bit per test cube is required to indicate if the shift register (HF-SR)” whose size is equal to B. LFSR reseeding is
hold flags for the current test cube needs to be updated or not. used to generate all of the data for each test cube, which consists of
Fig. 3 shows an example of partitioning a test set into hold-cube- three components, namely: 1) update flag; 2) hold flags; and 3) test
compatible sets. The original hold cubes for each test cube are shown data. The format for the data coming out of the LFSR for each test
in Fig. 3. Originally, they require 16 specified bits. They are then cube is shown in Fig. 5.
grouped into two hold-cube-compatible sets. The first set contains test There is a small finite-state machine (FSM) controller that controls
cubes 1, 3, and 4, and the second contains test cubes 2 and 5. As where the data coming out from the LFSR is stored. In the first clock
shown in Fig. 3, the test cubes are reordered so that the hold-cube- cycle, the LFSR generates a single bit, which is the update flag. If the
compatible sets are grouped together. An extra update flag bit is added update flag is 1, then in the next B clock cycles, the LFSR generates
to each test cube to indicate if the hold flags need to be updated. This the hold flags for each of the scan chains that are shifted into the HF-
is set only for the first test cube in each hold cube compatible set. In SRs. If the update flag is 0, then the HF-SRs are not loaded. Let the
this example, the total number of specified bits (including the added length of each scan chain be L. Then, for the next L clock cycles,
update flag bits) is reduced to 14. In a typical circuit, the number of the LFSR generates the test data. For each L/B clock cycle, if the
test cubes and the number of don’t care bits are much larger than those corresponding hold flag for a scan chain is 0, then the scan chain
in the example shown in Fig. 3. Thus, the reduction in specified bits is loaded from the LFSR. If the corresponding hold flag is a 1, then
using this approach will be sizable. In fact, in our experiments (shown the last value shifted into the scan chain is repeatedly shifted into the
in Section V), we found that in most cases, this encoding scheme scan chain, and the data from the LFSR is ignored. After each L/B
was capable of reducing the total number of specified bits (including clock cycle, the HF-SR is shifted so that the next hold flag becomes
data bits, hold flags, and update flags) to below that of the original active for its corresponding block and is used as the control signal to
test cubes. a multiplexer (MUX, as shown in Fig. 4). After the scan chains have
400 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007
been filled, the scan vector is applied to the circuit under test, and
the response is loaded back into the scan chain. The process is then
repeated to generate the next scan vector.
The hardware overhead consists of one 2-to-1 MUX and an
HF-SR per scan chain, one 1-bit update flag flip-flop, and a small
FSM controller. The FSM controller consists of a bit counter (which is
present for LFSR reseeding anyway) and some small combinational
logic. The size of the HF-SR dominantly determines the hardware
overhead in this scheme. It depends on the number of scan chains and
the total number of blocks.
V. E XPERIMENTAL R ESULTS
Experimental results for the proposed scheme for the largest
ISCAS’89 benchmark circuits are shown in Table I. Results for
dividing each test cube into different numbers of blocks are shown
(note that there is one hold flag for each block). The test cubes were
partitioned into hold-cube-compatible sets, and the number of such
sets is shown in each case. The total number of specified bits required
for the proposed encoding scheme is shown (including update flags,
hold flags, and data bits). The total number of specified bits and the
total number of transitions (computed as described in [9]) for the
proposed encoding scheme are compared with those for the original
test cubes. When computing the number of transitions, the final values
of the don’t care blocks are taken into consideration. In most cases,
the total number of specified bits is reduced, which will result in less
test-data bits in the test data and hold flags. The more blocks used,
the less specified bits in the test data but the more specified hold flags.
Moreover, the reduction in the number of transitions increases as the
number of blocks in a test pattern increases. Note that the number
of transitions in the HF-SR is included in the number of transitions Fig. 6. Continuous change with 5–100 blocks in s15850. (a) Percentage
shown in the ninth column. The hardware overhead also increases in change in specified bits. (b) Power reduction.
this case as the size of the HF-SRs becomes larger. The hardware
overhead depends on the number of scan chains. In these experiments,
the number of scan chains is chosen depending on the circuit size. The hardware overhead but not as small as hardware overhead with five to
11th column indicates the number of 2-to-1 MUXs required, which is ten blocks.
equal to the number of scan chains because one MUX is located on the The proposed encoding scheme can be used in conjunction with
entrance of each scan chain. The size of the HF-SR is indicated in the any LFSR-reseeding scheme. Experiments were performed for using
last column and depends on the number of blocks. the proposed encoding scheme in conjunction with the partial LFSR-
Fig. 6 shows the percentage change in specified bits and power reseeding scheme described in [7]. The results are shown in Table II.
reduction compared to the original test cubes for one benchmark The exact same set of test cubes that were used for generating the
circuit s15850. It illustrates how to choose the number of blocks for results published in [7] was encoded using the proposed encoding
a corresponding circuit and test set. The number of blocks is a user- scheme in conjunction with the scheme in [7]. As can be seen, in most
defined variable. It is chosen by considering test power, the number cases, both the test storage and the test power are reduced using the
of specified bits, and hardware overhead simultaneously. The number proposed scheme.
of blocks simulated varies from 5 to 100, which is represented on the Table III shows a comparison of the experimental results in [11] and
x axis for both graphs in Fig. 6. With a small number of blocks, the [12] with those of the proposed encoding scheme (used in conjunction
number of specified bits is reduced to less than the number of specified with partial LFSR reseeding as described in [7]). As can be seen, the
bits in the original test cubes. This is also observed in most of the proposed scheme reduces the test-storage requirements much more
other circuits. A small number of blocks are also good with respect than the other schemes. Note that the test storage for the method in
to hardware overhead because it means small hardware overhead. [12] was calculated here by multiplying the size of the primary and
However, the amount of power reduction is almost proportional to the secondary LFSRs by the number of test cubes. In terms of reducing test
number of blocks, as shown in Fig. 6, which means that the power power, the proposed scheme is much more effective than the scheme
consumption with a small number of blocks is small. With five to ten in [12], which is also applicable for LFSR reseeding. Moreover, the
blocks, the power reduction is about 37%, while the average of the compression ratio in the proposed scheme is similar or even higher
power reduction is about 50%. If 37% power reduction is good enough than that in [12] even though 1000 pseudorandom patterns are applied
for a user’s test methodology, a number from five to ten is chosen as first in [12]. Note that the results for both [11] and the proposed scheme
the number of blocks because it causes very small hardware overhead are for encoding the entire deterministic test set. While the test power
and can achieve high test-data compression. If 37% power reduction for the proposed scheme is not reduced as much as for the scheme in
is not good enough, the number of blocks is chosen to be larger while [11], which is based on run-length encoding, much more compression
still trying to minimize the number of specified bits. In Fig. 6, 38 or is achieved. The key advantage of the proposed scheme compared with
39 blocks can be chosen. This can achieve 48% power reduction and [11] is that it is compatible with LFSR reseeding, which is used in
1.8% reduction of the number of specified bits with relatively small commercial tools due to its superior encoding efficiency.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007 401
TABLE II
SIMULATION RESULTS FOR PARTIAL RESEEDING AND THE PROPOSED SCHEME (AFTER A PSEUDO-RANDOM SEQUENCE OF 10 000 PATTERNS)
TABLE III
SIMULATION RESULTS COMPARING THE ALTERNATING RUN-LENGTH CODE AND THE PROPOSED SCHEME