T E C H N O L O G Y AT3263

Current Mode PWM Controller

Description Features
AT3263 is highly integrated current mode PWM ●Frequency jitter function to improve EMI
control IC optimized for high performance low performance of power supply
standby power offline flyback converter applications. ●No-audible-noise green mode Control
To meet the international power conservation ● External Programmable PWM Switching
requirements, optimized green mode is integrated to Frequency
improve the efficiency at light or no load conditions ● Internal Slope Compensation
with no audible noise. Slope compensation is ● Low VDD Startup Current and Low Operating
integrated to ensure the stability at high load. Lead Current
edge blanking is integrated to prevent the false ● Leading Edge Blanking
trigger at the transition of the switch. Soft switching ● UVLO
control at the gate drive can improve the EMI ● Gate Max Output Voltage Clamp at 18V
performance of the power supply. The Gate-drive ● Overload Protection (OLP).
output is clamped at 18V to protect the power MOS. ● Line Compensation Over Current Protection
AT3263 offers many protection functions with auto (OCP)
self-recovery feature, including Cycle-by-Cycle
current limiting, over load protection (OLP) and Applications
under voltage lockout (UVLO). Offline AC/DC flyback converter for
Excellent EMI performance is achieved with ● Battery Charger
frequency jitter technique together with soft switching ● Power Adaptor
control at the totem pole gate driver. ● Set-Top Box Power Supplies
AT3263 is offered in SOT23-6, SOP-8 and DIP-8 ● Open-frame SMPS
packages. ● PC 5V Standby Power

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 T E C H N O L O G Y AT3263

Pin Assignments Ordering Information

S6 Package (SOT23-6)
AT3263□□□

DATE

GND 1 6 GATE
FB 2 5 VDD P: Pb Free with Commercial
Standard (RoHS Compliant)
RI 3 4 SENSE

Package Type
S6:SOT23-6
PD:P-DIP8
Figure 1. Pin Assignment of AT3263 for SOT23-6 SO:SOP(normal)8

PD8&SOP8 Package (P-DIP8&SOP8)

GATE 1 8 GND

VDD 2 7 FB

NC 3 6 NC

SENSE 4 5 RI

Figure 2. Pin Assignment of AT3263 for P-DIP8&SOP8

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 T E C H N O L O G Y AT3263

Typical Application Circuit

Figure3. Typical Application Circuit of AT3263

Functional Pin Description

Pin Name Pin Function

GND Ground
Feedback input pin. The PWM duty cycle is determined by voltage level into this pin and
FB
the current-sense signal at Pin 6.
Internal Oscillator frequency setting pin. A resistor connected between RI and GND sets
RI
the PWM frequency.
SENSE Current sense input pin. Connected to MOSFET current sensing resistor node.
VDD Chip DC power supply pin.
GATE Totem-pole gate drive output for the power MOSFET.

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 T E C H N O L O G Y AT3263

Block Diagram

Figure 4. Block Diagram of AT3263

Absolute Maximum Ratings

● VDD to GND---------------------------------------------------------------------------------------------------- - 0.3V to + 30V

● VDD clamped current---------------------------------------------------------------------------------------- 10mA

● VFB, VSENSE and VRI to GND--------------------------------------------------------------------------- - 0.3V to + 7V

● Junction Temperature---------------------------------------------------------------------------------------- - 20°C to + 150°C

● Storage Temperature Range------------------------------------------------------------------------------- - 55°C to + 160°C

Note：Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device.

Recommended Operating Conditions

● Supply Voltage, VDD---------------------------------------------------------------------------------------- 25V

● RI resistor value----------------------------------------------------------------------------------------------- 100kOhm

● Operation Temperature Range---------------------------------------------------------------------------- - 20°C to + 85°C

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 T E C H N O L O G Y AT3263

Electrical Characteristics
(TA = 25°C, RI=82kOhm, VDD=16V if not otherwise noted)
Parameter Symbol Test Conditions Min Typ Max Units

SUPPLY SECTION
Vdd=12V, measure current into VDD
Chip start up current via VDD pin I_set 5 25 uA
pin
VDD=16V,VFB=3V
Operation current I_op 1.4 mA

VDD UVLO enter UVLO_L 8 9 10 V

VDD UVLO exit UVLO_H 13 14 15 V
VDD clamp voltage VDD_CLP I(VDD)=10mA 34 V
FEEDBACK SECTION
PWM input gain A_PWM ΔVFB/ΔVCS 2
VFB open loop voltage VFB_O 5.3 V
Short FB pin to gnd and measure
FB pin short circuit current VFB_S 0.8 mA
current
Zero duty cycle FB threshold VFB_th_L 0.75 V
Power limiting FB threshold VFB_th_P 3.7 V
Power limiting delay time T_PL_D 35 mS
Input impedance R_FB 6 KΩ
Maxim duty cycle D_MAX VDD=18V, FB=3V,CS=0 80 %
OSCILLATOR
Normal oscillation frequency FOSC 60 65 70 KHz
Frequency temperature stability Δf_Temp TA -20°C to +100°C 5 %
Frequency supply stability Δf_Sup VDD 12-25V 5 %
Operating RI range RI_range 50 82 150 KΩ
RI open load voltage RI_open 2 V
Burst mode base frequency FOSC-BM 22 KΩ
Frequency modulate range (jitter) Δf_OSC -3 3 %
Jitter frequency f_jitter 32 Hz
CURRENT SENSE SECTION
Leading edge blanking time T_blank 300 nS
Sense pin input impedance R_sense 40 kΩ
Over current threshold voltage at
VTH_OC FB=3.3V 0.70 0.75 0.80 V
Sense pin
Over current protect delay T_OC_D CS>VTH_OC, FB=3.3V 75 nS
GATE OUTPUT
Output low level VOL Io=-20mA 0.8 V
Output high level VOH Io=20mA 10V V
Output voltage clamped level VG_CLP 18 V
Output rising time T_r Cl=1nf 220 nS
Output falling time T_f Cl=1nf 70 nS

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T E C H N O L O G Y AT3263

OPERATION DESCRIBTION

Over-view description

The AT3263 includes all necessary function to build

an easy and cost effective solution for low power
supplies to meet the international power conservation
requirements.

Start-up current

Startup current of AT3263 is designed to be very low When VFB decrease further, the power supply will
so that VDD could be charged up above UVLO (exit) enter into burst mode operation to decrease the
threshold level and device starts up quickly. Also a power consumed at no load condition. Besides there
large value startup resistor can be used to minimize is no audible noise in any load condition.
the power loss.
Oscillator Operation
Green Mode Operation （Patent）
A resistor from RI pin to ground will generate a
constant current source for AT3263. This current is
At light load or no load condition, the switch loss
used to charge/discharge an internal capacitor and
become the major loss of the power supply, to reduce
hence the internal clock and switching frequency are
the power wasted in light and no load condition,
determined. Increase the resistance will decrease the
based on a special designed voltage controlled
current source and reduce the switching frequency.
oscillator, green mode operation of the power
The relation between Ri and switching frequency is:
supply can be achieved by using AT3263. The
controller will judge the load condition base on the
voltage of FB pin. In light load the FB voltage will
f PWM 
6500
khz 
RI
decrease, when VFB is lower than a set threshold
voltage, a FB depending time (TR2) will be generated
by the oscillator and decrease the operating
Built-in Slope Compensation
frequency of the power supply, the minimum
The sensed voltage across the sense resistor is used
frequency is set about 23kHZ. The function block and
for pwm control, and pulse by pulse current limit,
the working waveform can be depicted as below:
Built-in slope compensation circuit adds a voltage
ramp onto the current sense input voltage. This
greatly improves the close loop stability and prevents
the sub-harmonic oscillation of peak current mode
pwm control scheme.

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T E C H N O L O G Y AT3263

Leading Edge Blanking Protect Functions

Each time when the power MOSFET is switched on, To increase the reliability of power supply system
a turn-on spike will inevitably occur on the many protection functions is integrated in this
sense-resistor. To avoid premature termination of the controller, including Cycle-by-Cycle current limiting
switching pulse, a 270 nsec leading-edge blanking (OCP), Over Load Protection (OLP) and over voltage
time is built in. Conventional RC filtering can clamp, Under Voltage Lockout on VDD (UVLO). At
therefore be omitted. During this blanking period, the overload condition when FB input voltage exceeds
current-limit comparator is disabled and it cannot power limit threshold value for more than TD_PL
switch off the gate driver. (power limit debounce time), the controller reacts to
shut down the output power MOSFET. Device
Gate Driver restarts when VDD voltage drops below UVLO limit.
VDD is supplied by transformer auxiliary winding
The output stage of AT3263 is a fast totem pole gate output. It is clamped when VDD is higher than
driver. Cross conduction has been avoided to threshold value. The power MOSFET is shut down
minimize heat dissipation, increases efficiency and when VDD drops below UVLO limit and device enters
enhances reliability. The output driver is clamped by power on start-up sequence thereafter.
an internal 18V Zener diode in order to protect power
MOSFET transistors against undesirable gate over
voltage. A soft driving waveform is implemented to
minimize EMI.

Frequency Jitter

The frequency jitter function is integrated in the

controller, the jitter is modulated by a periodic signal,
the modulate signal frequency is much smaller than
the oscillator frequency, By this way，the EMI noise
has a wider spectrum with lower amplitudes.

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 T E C H N O L O G Y AT3263

Outline Information
P-DIP-8 Package

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 T E C H N O L O G Y AT3263

SOT-26 Package (Unit: mm)

-End of Specifications-

Amaxtronics Technology Corp.

U.S.A.: [email protected] China: [email protected]

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