Features Description: LTC3786 Low I Synchronous Boost Controller

LTC3786
Low IQ Synchronous
Boost Controller
FEATURES DESCRIPTION
n Synchronous Operation For Highest Efficiency and The LTC®3786 is a high performance synchronous boost
Reduced Heat Dissipation converter controller that drives all N-channel power
n Wide VIN Range: 4.5V to 38V (40V Abs Max) and MOSFETs. Synchronous rectification increases efficiency,
Operates Down to 2.5V After Start-Up reduces power losses and eases thermal requirements,
n Output Voltages Up to 60V allowing the LTC3786 to be used in high power boost
n ±1% 1.2V Reference Voltage applications.
n RSENSE or Inductor DCR Current Sensing
A 4.5V to 38V input supply range encompasses a wide
n 100% Duty Cycle Capability for Synchronous MOSFET
range of system architectures and battery chemistries.
n Low Quiescent Current: 55µA
When biased from the output of the boost converter or
n Phase-Lockable Frequency (75kHz to 850kHz)
another auxiliary supply, the LTC3786 can operate from
n Programmable Fixed Frequency (50kHz to 900kHz)
an input supply as low as 2.5V after start-up. The 55µA
n Adjustable Output Voltage Soft-Start
no-load quiescent current extends operating run time in
n Power Good Output Voltage Monitor
battery-powered systems.
n Low Shutdown Current IQ: <8µA
n Internal 5.4V LDO for Gate Drive Supply The operating frequency can be set for a 50kHz to 900kHz
n Thermally Enhanced 16-Pin 3mm × 3mm QFN and range or synchronized to an external clock using the
MSOP Packages internal PLL. The LTC3786 also features a precision 1.2V
reference and a power good output indicator. The SS pin
APPLICATIONS ramps the output voltage during start-up. The PLLIN/MODE
pin selects among Burst Mode® operation, pulse-skipping
n Industrial and Automotive Power Supplies
mode or continuous inductor current mode at light loads.
n Automotive Start-Stop Systems
n Medical Devices All registered trademarks and trademarks are the property of their respective owners.
n High Voltage Battery-Powered Systems
TYPICAL APPLICATION
12V to 24V/5A Synchronous Boost Converter
Efficiency and Power Loss
VIN 4.5V TO 24V vs Load Current
VBIAS 100 10000
SENSE+
90
LTC3786 4mΩ 220µF BURST
80 1000
PGOOD SENSE– EFFICIENCY BURST
70
POWER LOSS (mW)
PLLIN/MODE LOSS
EFFICIENCY (%)
3.3µH
RUN 60 100
FREQ TG
0.1µF 50
VOUT
SS SW 24V 40 10
15nF 0.1µF 220µF 5A
8.66k 30
ITH BOOST
220pF 20 VIN = 12V 1
BG VOUT = 24V
12.1k 10 Burst Mode OPERATION
VFB INTVCC FIGURE 8 CIRCUIT
4.7µF
0 0.1
GND
0.00001 0.0001 0.001 0.01 0.1 1 10
232k
OUTPUT CURRENT (A)
3786 TA01a 3786 TA01b
3786fc
For more information www.linear.com/LTC3786 1

LTC3786
ABSOLUTE MAXIMUM RATINGS (Notes 1, 3)
VBIAS ........................................................ –0.3V to 40V SENSE+, SENSE– ........................................ –0.3V to 40V

BOOST ........................................................–0.3V to 71V SENSE+ – SENSE– ..................................... –0.3V to 0.3V
SW ............................................................. –0.3V to 65V SS, ITH, FREQ, VFB............................... –0.3V to INTVCC
RUN ............................................................. –0.3V to 8V Operating Junction Temperature Range (Notes 2, 3)
Maximum Current Sourced into Pin LTC3786E, LTC3786I ..........................–40°C to 125°C
from Source >8V ..............................................100µA LTC3786H ...........................................–40°C to 150°C
PGOOD, PLLIN/MODE .................................. –0.3V to 6V Storage Temperature Range ....................–65°C to 150°C
INTVCC, (BOOST – SW) ............................... –0.3V to 6V Lead Temperature (Soldering, 10 sec)
MSE Package Only ............................................ 300°C
PIN CONFIGURATION
TOP VIEW
INTVCC
BOOST
VBIAS
TG
TOP VIEW
16 15 14 13
VFB 1 16 PGOOD
SENSE+ 2 15 SW SW 1 12 BG
SENSE– 3 14 TG PGOOD 2 11 GND
17
ITH 4 17 13 BOOST
SS 5 12 VBIAS VFB 3 GND 10 RUN
GND
PLLIN/MODE 6 11 INTVCC SENSE+ 4 9 FREQ
FREQ 7 10 BG
RUN 8 9 GND 5 6 7 8
MSE PACKAGE
SENSE–
ITH
SS
PLLIN/
MODE
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 40°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
TJMAX = 150°C, θJA = 68°C/W, θJC = 4.2°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION http://www.linear.com/product/LTC3786#orderinfo
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3786EMSE#PBF LTC3786EMSE#TRPBF 3786 16-Lead Plastic MSOP –40°C to 125°C
LTC3786IMSE#PBF LTC3786IMSE#TRPBF 3786 16-Lead Plastic MSOP –40°C to 125°C
LTC3786HMSE#PBF LTC3786HMSE#TRPBF 3786 16-Lead Plastic MSOP –40°C to 150°C
LTC3786EUD#PBF LTC3786EUD#TRPBF LFXW 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C
LTC3786IUD#PBF LTC3786IUD#TRPBF LFXW 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C
LTC3786HUD#PBF LTC3786HUD#TRPBF LFXW 16-Lead (3mm × 3mm) Plastic QFN –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
3786fc
2 For more information www.linear.com/LTC3786

LTC3786
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, unless otherwise noted (Note 2).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
VBIAS Chip Bias Voltage Operating Range 4.5 38 V
VFB Regulated Feedback Voltage ITH = 1.2V (Note 4) l 1.188 1.200 1.212 V
IFB Feedback Current (Note 4) ±5 ±50 nA
VREFLNREG Reference Line Voltage Regulation VBIAS = 6V to 38V 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 4)
Measured in Servo Loop; l 0.01 0.1 %
∆ITH Voltage = 1.2V to 0.7V
Measured in Servo Loop; l –0.01 –0.1 %
∆ITH Voltage = 1.2V to 2V
gm Error Amplifier Transconductance ITH = 1.2V 2 mmho
IQ Input DC Supply Current (Note 5)
Pulse-Skipping or Forced Continuous Mode RUN = 5V; VFB = 1.25V (No Load) 0.8 mA
Sleep Mode RUN = 5V; VFB = 1.25V (No Load) 55 80 µA
Shutdown RUN = 0V 8 20 µA
UVLO INTVCC Undervoltage Lockout Thresholds VINTVCC Ramping Up l 4.1 4.3 V
VINTVCC Ramping Down l 3.6 3.8 V
VRUN RUN Pin On Threshold VRUN Rising l 1.18 1.28 1.38 V
VRUNHYS RUN Pin Hysteresis 100 mV
IRUNHYS RUN Pin Hysteresis Current VRUN > 1.28V 4.5 µA
IRUN RUN Pin Current VRUN < 1.28V 0.5 µA
ISS Soft-Start Charge Current VSS = 0V 7 10 13 µA
VSENSE(MAX) Maximum Current Sense Threshold VFB = 1.1V l 68 75 82 mV
VSENSE(CM) SENSE Pins Common Mode Range (BOOST 2.5 38 V
Converter Input Supply Voltage VIN)
ISENSE+ SENSE+ Pin Current VFB = 1.1V 200 300 µA
ISENSE– SENSE– Pin Current VFB = 1.1V ±1 µA
tr(TG) Top Gate Rise Time CLOAD = 3300pF (Note 6) 20 ns
tf(TG) Top Gate Fall Time CLOAD = 3300pF (Note 6) 20 ns
tr(BG) Bottom Gate Rise Time CLOAD = 3300pF (Note 6) 20 ns
tf(BG) Bottom Gate Fall Time CLOAD = 3300pF (Note 6) 20 ns
RUP(TG) Top Gate Pull-Up Resistance 1.2 Ω
RDN(TG) Top Gate Pull-Down Resistance 1.2 Ω
RUP(BG) Bottom Gate Pull-Up Resistance 1.2 Ω
RDN(BG) Bottom Gate Pull-Down Resistance 1.2 Ω
tD(TG/BG) Top Gate Off to Bottom Gate On Switch-On CLOAD = 3300pF (Each Driver) 80 ns
Delay Time
tD(BG/TG) Bottom Gate Off to Top Gate On Switch-On CLOAD = 3300pF (Each Driver) 80 ns
Delay Time
DFMAXBG Maximum BG Duty Factor 96 %
tON(MIN) Minimum BG On-Time (Note 7) 110 ns
3786fc

LTC3786
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, unless otherwise noted (Note 2).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC Linear Regulator
VINTVCC(VIN) Internal VCC Voltage 6V < VBIAS < 38V 5.2 5.4 5.6 V
VLDO INT INTVCC Load Regulation ICC = 0mA to 50mA 0.5 2 %
Oscillator and Phase-Locked Loop
fPROG Programmable Frequency RFREQ = 25k 105 kHz
RFREQ = 60k 335 400 465 kHz
RFREQ = 100k 760 kHz
fLOW Lowest Fixed Frequency VFREQ = 0V 320 350 380 kHz
fHIGH Highest Fixed Frequency VFREQ = INTVCC 485 535 585 kHz
fSYNC Synchronizable Frequency PLLIN/MODE = External Clock l 75 850 kHz
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.2 0.4 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPG PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Negative –12 –10 –8 %
Hysteresis 2.5 %
VFB Ramping Positive 8 10 12 %
Hysteresis 2.5 %
tPGOOD(DELAY) PGOOD Delay PGOOD Going High to Low 25 µs
BOOST Charge Pump
IBOOST BOOST Charge Pump Available VSW = 12V; VBOOST – VSW = 4.5V; 85 µA
Output Current FREQ = 0V, Forced Continuous or
Pulse-Skipping Mode
Note 1: Stresses beyond those listed under Absolute Maximum Ratings where θJA = 68°C for the QFN package and θJA = 40°C for the MSOP
may cause permanent damage to the device. Exposure to any Absolute package.
Maximum Rating condition for extended periods may affect device Note 3: This IC includes overtemperature protection that is intended to
reliability and lifetime. protect the device during momentary overload conditions. The maximum
Note 2: The LTC3786 is tested under pulsed load conditions such that rated junction temperature will be exceeded when this protection is active.
TJ ≈ TA. The LTC3786E is guaranteed to meet specifications from Continuous operation above the specified absolute maximum operating
0°C to 85°C junction temperature. Specifications over the –40°C to junction temperature may impair device reliability or permanently damage
125°C operating junction temperature range are assured by design, the device.
characterization and correlation with statistical process controls. The Note 4: The LTC3786 is tested in a feedback loop that servos VFB to the
LTC3786I is guaranteed over the –40°C to 125°C operating junction output of the error amplifier while maintaining ITH at the midpoint of the
temperature range. The LTC3786H is guaranteed over the –40°C to 150°C current limit range.
operating temperature range. High temperatures degrade operating Note 5: Dynamic supply current is higher due to the gate charge being
lifetimes; operating lifetime is derated for junction temperatures greater delivered at the switching frequency.
than 125ºC. Note that the maximum ambient temperature consistent
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
with these specifications is determined by specific operating conditions
times are measured using 50% levels.
in conjunction with board layout, the rated package thermal impedance
and other environmental factors. The junction temperature (TJ in °C) is Note 7: see Minimum On-Time Considerations in the Applications
calculated from the ambient temperature (TA in °C) and power dissipation Information section.
(PD in Watts) according to the formula:
TJ = TA + (PD • θJA)
3786fc

LTC3786
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss Efficiency and Power Loss
vs Output Current vs Output Current
100 10000 100 10000
90 90
80 BURST 1000
80 1000
EFFICIENCY BURST
70 70
POWER LOSS (mW)

LOSS
POWER LOSS (mW)
EFFICIENCY (%)
EFFICIENCY (%)
60 100 60 100
VIN = 12V
50 VOUT = 24V 50
FIGURE 8 CIRCUIT 40 10
40 10
CCM EFFICIENCY
30 CCM LOSS 30
BURST EFFICIENCY 20 VIN = 12V 1
20 1
BURST LOSS VOUT = 24V
10 PULSE-SKIPPING EFFICIENCY 10 Burst Mode OPERATION
PULSE-SKIPPING LOSS FIGURE 8 CIRCUIT
0 0.1 0 0.1
0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10
OUTPUT CURRENT (A) OUTPUT CURRENT (A)
3786 G01 3786 G02
Load Step Load Step

Efficiency vs Input Voltage Forced Continuous Mode Burst Mode Operation
100
ILOAD = 2A
FIGURE 8 CIRCUIT LOAD STEP LOAD STEP
99 2A/DIV 2A/DIV
INDUCTOR INDUCTOR
98 CURRENT CURRENT
VOUT = 12V 5A/DIV
EFFICIENCY (%)
VOUT = 24V 5A/DIV

97
VOUT VOUT
96 500mV/DIV 500mV/DIV
95
3786 G04 3786 G05
VIN = 12V 200µs/DIV VIN = 12V 200µs/DIV
94 VOUT = 24V VOUT = 24V
LOAD STEP FROM 200mA TO 2.5A LOAD STEP FROM 200mA TO 2.5A
FIGURE 8 CIRCUIT FIGURE 8 CIRCUIT
93
0 5 10 15 20 25
INPUT VOLTAGE (V)
3786 G03
Load Step
Pulse-Skipping Mode Inductor Current at Light Load Soft Start-Up
LOAD STEP FORCED

2A/DIV CONTINUOUS
INDUCTOR MODE
CURRENT VOUT
5A/DIV Burst Mode 5V/DIV
OPERATION
5A/DIV
VOUT
PULSE-
500mV/DIV
SKIPPING MODE
0V
3786 G06 3786 G07
VIN = 12V 200µs/DIV VIN = 12V 5µs/DIV VIN = 12V 2ms/DIV
3786 G08
VOUT = 24V VOUT = 24V VOUT = 24V

LOAD STEP FROM 200mA TO 2.5A ILOAD = 200µA FIGURE 8 CIRCUIT
FIGURE 8 CIRCUIT FIGURE 8 CIRCUIT
3786fc

LTC3786
Regulated Feedback Voltage Soft-Start Pull-Up Current
vs Temperature vs Temperature Shutdown Current vs Temperature
1.212 11.0 12.0
11.5 VIN = 12V
1.209
REGULATED FEEDBACK VOLTAGE (V)
11.0
10.5
SHUTDOWN CURRENT (µA)

SOFT-START CURRENT (µA)
1.206 10.5
10.0
1.203 9.5
9.0
1.200 10.0 8.5
8.0
1.197 7.5
7.0
1.194 9.5
6.5
1.191 6.0
5.5
1.188 9.0 5.0
–45 –25 –5 15 35 55 75 95 115 135 155 –45 –25 –5 15 35 55 75 95 115 135 155 –45 –25 –5 15 35 55 75 95 115 135 155
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3786 G09 3786 G10 3786 G11
Shutdown Current Shutdown (RUN) Threshold

vs Input Voltage Quiescent Current vs Temperature vs Temperature
20 80 1.40
VIN = 12V
VFB = 1.25V
1.35
70
SHUTDOWN CURRENT (µA)
QUIESCENT CURRENT (µA)
15
RUN RISING
RUN PIN VOLTAGE (V)
1.30
60
10 1.25
50
1.20
RUN FALLING
5
40
1.15
0 30 1.10
0 5 10 15 20 25 30 35 40 –45 –25 –5 15 35 55 75 95 115 135 155 –45 –25 –5 15 35 55 75 95 115 135 155
INPUT VOLTAGE (V) 3786 G12
TEMPERATURE (°C) TEMPERATURE (°C)
3786 G13 3786 G14
Undervoltage Lockout Threshold

vs Temperature INTVCC Line Regulation INTVCC Line Regulation
4.4 5.5 5.5
NO LOAD NO LOAD
4.3 5.4 5.4
INTVCC RISING
4.2 5.3 5.3
4.1 5.2 5.2
INTVCC VOLTAGE (V)
INTVCC VOLTAGE (V)

INTVCC VOLTAGE (V)
4.0 5.1 5.1

3.9 5.0 5.0
INTVCC FALLING
3.8 4.9 4.9
3.7 4.8 4.8
3.6 4.7 4.7
3.5 4.6 4.6
3.4 4.5 4.5
–45 –25 –5 15 35 55 75 95 115 135 155 0 5 10 15 20 25 30 35 40 4.5 4.75 5.0 5.25 5.5 5.75 6.0
TEMPERATURE (°C) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
3786 G15
3786 G16 3786 G17
3786fc

LTC3786
Oscillator Frequency
INTVCC vs Load Current INTVCC vs Load Current vs Temperature
5.50 5.2 600
VIN = 12V VIN = 5V
FREQ = INTVCC
5.45 5.0 550
5.40
INTVCC VOLTAGE (V)

INTVCC VOLTAGE (V)
4.8 500
FREQUENCY (kHz)
5.35
4.6 450
5.30
4.4 400
5.25 FREQ = GND
4.2 350
5.20
5.15 4.0 300

0 20 40 60 80 100 120 140 160 180 0 10 20 30 40 50 60 –45 –25 –5 15 35 55 75 95 115 135 155
LOAD CURRENT (mA) LOAD CURRENT (mA) TEMPERATURE (°C)
3786 G20
3786 G18 3786 G19
Oscillator Frequency Maximum Current Sense SENSE Pin Input Current

vs Input Voltage Threshold vs ITH Voltage vs Temperature
360 120 260
FREQ = GND VSENSE = 12V
MAXIMUM CURRENT SENSE VOLTAGE (mV)
PULSE-SKIPPING MODE 240

358 100 FORCED CONTINUOUS MODE
Burst Mode OPERATION 220 SENSE+ PIN
OSCILLATOR FREQUENCY (kHz)
356 80 200
354
SENSE CURRENT (µA)

60 180
352 160
40 140
350
20 120
348 100
0
346 80
344 –20 60
40
342 –40
20 SENSE– PIN
340 –60 0
5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 –45 –25 –5 15 35 55 75 95 115 135 155
INPUT VOLTAGE (V) 3786 G21
ITH VOLTAGE (V) TEMPERATURE (°C)
3786 G22 3786 G23
SENSE Pin Input Current SENSE Pin Input Current Maximum Current Sense
vs ITH Voltage vs VSENSE Voltage Threshold vs Duty Cycle
260 260 120
VSENSE = 12V
MAXIMUM CURRENT SENSE VOLTAGE (mV)
240 240
220 220 100
SENSE+ PIN SENSE+ PIN
200 200
SENSE CURRENT (µA)
SENSE CURRENT (µA)
180 180 80
160 160
140 140
60
120 120
100 100
80 80 40
60 60
40 40 20
20 SENSE – PIN 20
SENSE – PIN
0 0 0
0 0.5 1 1.5 2 2.5 3 2.5 7.5 12.5 17.5 22.5 27.5 32.5 37.5 0 10 20 30 40 50 60 70 80 90 100
ITH VOLTAGE (V) VSENSE COMMON MODE VOLTAGE (V) DUTY CYCLE (%)
3786 G24 3786 G25
3786 G26
3786fc

LTC3786
Charge Pump Charging Current Charge Pump Charging Current
vs Operating Frequency vs Switch Voltage
110 120
VBOOST = 16.5V
CHARGE PUMP CHARGING CURRENT (µA)

CHARGE PUMP CHARGING CURRENT (µA)
100 FREQ = 0V
VSW = 12V –45°C
90 100
80 FREQ = INTVCC
25°C
80
70
60 130°C 60
50
40
40
30 155°C
20 20
10
0 0
50 150 250 350 450 550 650 750 850 5 10 15 20 25 30 35 40
OPERATING FREQUENCY (kHz) SWITCH VOLTAGE (V)
3786 G27
3786 G28
PIN FUNCTIONS (MSOP/QFN)
VFB (Pin 1/Pin 3): Error Amplifier Feedback Input. This SS (Pin 5/Pin 7): Output Soft-Start Input. A capacitor to
pin receives the remotely sensed feedback voltage from ground at this pin sets the ramp rate of the output voltage
an external resistive divider connected across the output. during start-up.
SENSE+ (Pin 2/Pin 4): Positive Current Sense Comparator PLLIN/MODE (Pin 6/Pin 8): External Synchronization Input
Input. The (+) input to the current comparator is normally to Phase Detector and Forced Continuous Mode Input.
connected to the positive terminal of a current sense resis- When an external clock is applied to this pin, it will force
tor. The current sense resistor is normally placed at the the controller into forced continuous mode of operation
input of the boost controller in series with the inductor. and the phase-locked loop will force the rising BG signal
This pin also supplies power to the current comparator. to be synchronized with the rising edge of the external
SENSE– (Pin 3/Pin 5): Negative Current Sense Comparator clock. When not synchronizing to an external clock, this
Input. The (–) input to the current comparator is normally input determines how the LTC3786 operates at light loads.
connected to the negative terminal of a current sense re- Pulling this pin to ground selects Burst Mode operation.
sistor connected in series with the inductor. The common An internal 100k resistor to ground also invokes Burst
mode voltage range on the SENSE+ and SENSE– pins is Mode operation when the pin is floated. Tying this pin
2.5V to 38V (40V abs max). to INTVCC forces continuous inductor current operation.
Tying this pin to a voltage greater than 1.2V and less than
ITH (Pin 4/Pin 6): Current Control Threshold and Error INTVCC – 1.3V selects pulse-skipping operation. This can
Amplifier Compensation Point. The voltage on this pin be done by adding a 100k resistor between the PLLIN/
sets the current trip threshold. MODE pin and INTVCC.
3786fc

LTC3786
PIN FUNCTIONS (MSOP/QFN)
FREQ (Pin 7/Pin 9): The Frequency Control Pin for the BG (Pin 10/Pin 12): Bottom Gate. Connect to the gate of
Internal VCO. Connecting the pin to GND forces the VCO the main N-channel MOSFET.
to a fixed low frequency of 350kHz. Connecting the pin
INTVCC (Pin 11/Pin 13): Output of Internal 5.4V LDO.
to INTVCC forces the VCO to a fixed high frequency of
Power supply for control circuits and gate drivers. De-
535kHz. The frequency can be programmed from 50kHz
couple this pin to GND with a minimum 4.7µF low ESR
to 900kHz by connecting a resistor from the FREQ pin to
ceramic capacitor.
GND. The resistor and an internal 20µA source current
create a voltage used by the internal oscillator to set the VBIAS (Pin 12/Pin 14): Main Supply Pin. It is normally
frequency. Alternatively, this pin can be driven with a DC tied to the input supply VIN or to the output of the boost
voltage to vary the frequency of the internal oscillator. converter. A bypass capacitor should be tied between this
pin and the GND pin. The operating voltage range on this
RUN (Pin 8/Pin 10): Run Control Input. Forcing this pin
pin is 4.5V to 38V (40V abs max).
below 1.28V shuts down the controller. Forcing this pin
below 0.7V shuts down the entire LTC3786, reducing BOOST (Pin 13/Pin 15): Floating Power Supply for the
quiescent current to approximately 8µA. An external Synchronous MOSFET. Bypass to SW with a capacitor
resistor divider connected to VIN can set the threshold and supply with a Schottky diode connected to INTVCC.
for converter operation. There is a 0.5µA pull-up current TG (Pin 14/Pin 16): Top Gate. Connect to the gate of the
for this pin. Once the RUN pin raises above 1.28V, an synchronous NMOS.
additional 4.5µA pull-up current is added to the pin for
programmable hysteresis. SW (Pin 15/Pin 1): Switch Node. Connect to the source
of the synchronous top MOSFET, the drain of the main
GND (Pin 9, Exposed Pad Pin 17/ Pin 11, Exposed Pad bottom MOSFET, and the inductor.
Pin 17): Ground. Connects to the source of the bottom
(main) N-channel MOSFET and the (–) terminal(s) of CIN PGOOD (Pin 16/Pin 2): Power Good Indicator. Open-drain
and COUT . All small-signal components and compensa- logic output that is pulled to ground when the output volt-
tion components should also connect to this ground. age is more than ±10 % away from the regulated output
The exposed pad must be soldered to the PCB for rated voltage. To avoid false trips the output voltage must be
thermal performance. outside of the range for 25µs before this output is activated.
3786fc

LTC3786
BLOCK DIAGRAM
INTVCC
DB
PGOOD BOOST
1.32V + S
Q
– R
TG CB
VFB
+ SHDN
SWITCHING
1.08V – VOUT
LOGIC SW
AND
20µA CHARGE
PUMP INTVCC COUT
FREQ
BG
CLK
VCO +
0.425V SLEEP
–
+
–
PFD
ICMP IREV L
–+ +– –
+
2mV SENSE –
2.8V
0.7V
PLLIN/ RSENSE
MODE SENSE+
SLOPE COMP
SYNC VIN
DET
100k
+ CIN
SENS LO VFB
– 2.5V
+
EA – 1.2V
– SS
VBIAS
+
OV
– 1.32V ITH CC
SHDN 0.5µA/
4.5µA
CC2 RC
5.4V +
–
LDO 11V 10µA
3786 BD
3.8V
SHDN SENS
LO
INTVCC GND RUN SS
CSS
3786fc

LTC3786
OPERATION (Refer to the Block Diagram)
Main Control Loop ance source, do not exceed the absolute maximum rating
The LTC3786 uses a constant-frequency, current mode of 8V. The RUN pin has an internal 11V voltage clamp
step-up control architecture. During normal operation, that allows the RUN pin to be connected through a resis-
the external bottom MOSFET is turned on when the clock tor to a higher voltage (for example, VIN), as long as the
maximum current into the RUN pin does not exceed 100µA.
sets the RS latch, and is turned off when the main current
An external resistor divider connected to VIN can set the
comparator, ICMP , resets the RS latch. The peak inductor
threshold for converter operation. Once running, a 4.5µA
current at which ICMP trips and resets the latch is con-
current is sourced from the RUN pin allowing the user to
trolled by the voltage on the ITH pin, which is the output
program hysteresis using the resistor values.
of the error amplifier, EA. The error amplifier compares
the output voltage feedback signal at the VFB pin, (which The start-up of the controller’s output voltage, VOUT , is
is generated with an external resistor divider connected controlled by the voltage on the SS pin. When the voltage
across the output voltage, VOUT , to ground) to the internal on the SS pin is less than the 1.2V internal reference, the
1.200V reference voltage. In a boost converter, the required LTC3786 regulates the VFB voltage to the SS pin voltage
inductor current is determined by the load current, VIN and instead of the 1.2V reference. This allows the SS pin to
VOUT . When the load current increases, it causes a slight be used to program a soft-start by connecting an external
decrease in VFB relative to the reference, which causes the capacitor from the SS pin to GND. An internal 10µA pull-
EA to increase the ITH voltage until the average inductor up current charges this capacitor creating a voltage ramp
current in each channel matches the new requirement on the SS pin. As the SS voltage rises linearly from 0V to
based on the new load current. 1.2V, the output voltage rises smoothly to its final value.
After the bottom MOSFET is turned off each cycle, the
Light Load Current Operation—Burst Mode Operation,
top MOSFET is turned on until either the inductor current
Pulse-Skipping or Continuous Conduction
starts to reverse, as indicated by the current comparator (PLLIN/MODE Pin)
IREV, or the beginning of the next clock cycle.
The LTC3786 can be enabled to enter high efficiency Burst
INTVCC Power Mode operation, constant-frequency pulse-skipping mode
Power for the top and bottom MOSFET drivers and most or forced continuous conduction mode at low load cur-
rents. To select Burst Mode operation, tie the PLLIN/MODE
other internal circuitry is derived from the INTVCC pin. The
VBIAS LDO (low dropout linear regulator) supplies 5.4V pin to ground. To select forced continuous operation, tie
from VBIAS to INTVCC. the PLLIN/MODE pin to INTVCC. To select pulse-skipping
mode, tie the PLLIN/MODE pin to a DC voltage greater
Shutdown and Start-Up (RUN and SS Pins) than 1.2V and less than INTVCC – 1.3V.
The LTC3786 can be shut down using the RUN pin. Pulling When the controller is enabled for Burst Mode opera-
this pin below 1.28V shuts down the main control loop. tion, the minimum peak current in the inductor is set to
Pulling this pin below 0.7V disables the controller and approximately 30% of the maximum sense voltage even
most internal circuits, including the INTVCC LDOs. In this though the voltage on the ITH pin indicates a lower value.
state, the LTC3786 draws only 8µA of quiescent current. If the average inductor current is higher than the required
Note: Do not apply load while the chip is in shutdown. The current, the error amplifier, EA, will decrease the voltage
output MOSFET will be turned off during shutdown and on the ITH pin. When the ITH voltage drops below 0.425V,
the output load may cause excessive power dissipation the internal sleep signal goes high (enabling sleep mode)
in the body diode. and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
The RUN pin may be externally pulled up or driven directly at 0.450V.
by logic. When driving the RUN pin with a low imped-
3786fc

LTC3786
In sleep mode, much of the internal circuitry is turned off reduced RF interference as compared to Burst Mode
and the LTC3786 draws only 55µA of quiescent current. operation. It provides higher low current efficiency than
In sleep mode, the load current is supplied by the output forced continuous mode, but not nearly as high as Burst
capacitor. As the output voltage decreases, the EA’s output Mode operation.
begins to rise. When the output voltage drops enough,
the ITH pin is reconnected to the output of the EA, the Frequency Selection and Phase-Locked Loop
sleep signal goes low, and the controller resumes normal (FREQ and PLLIN/MODE Pins)
operation by turning on the bottom external MOSFET on The selection of switching frequency is a trade-off between
the next cycle of the internal oscillator. efficiency and component size. Low frequency opera-
When the controller is enabled for Burst Mode operation, tion increases efficiency by reducing MOSFET switching
the inductor current is not allowed to reverse. The reverse- losses, but requires larger inductance and/or capacitance
current comparator (IREV) turns off the top external to maintain low output ripple voltage.
MOSFET just before the inductor current reaches zero, The switching frequency of the LTC3786’s controllers can
preventing it from reversing and going negative. Thus, be selected using the FREQ pin.
the controller operates in discontinuous current operation.
If the PLLIN/MODE pin is not being driven by an external
In forced continuous operation or when clocked by an clock source, the FREQ pin can be tied to GND, tied to
external clock source to use the phase-locked loop (see INTVCC, or programmed through an external resistor. Tying
the Frequency Selection and Phase-Locked Loop section), FREQ to GND selects 350kHz while tying FREQ to INTVCC
the inductor current is allowed to reverse at light loads or selects 535kHz. Placing a resistor between FREQ and GND
under large transient conditions. The peak inductor cur- allows the frequency to be programmed between 50kHz
rent is determined by the voltage on the ITH pin, just as and 900kHz, as shown in Figure 5.
in normal operation. In this mode, the efficiency at light
loads is lower than in Burst Mode operation. However, A phase-locked loop (PLL) is available on the LTC3786
continuous operation has the advantages of lower output to synchronize the internal oscillator to an external clock
voltage ripple and less interference to audio circuitry, as source that is connected to the PLLIN/MODE pin. The
it maintains constant-frequency operation independent LTC3786’s phase detector adjusts the voltage (through
of load current. an internal lowpass filter) of the VCO input to align the
turn-on of the external bottom MOSFET to the rising edge
When the PLLIN/MODE pin is connected for pulse-skipping of the synchronizing signal.
mode, the LTC3786 operates in PWM pulse-skipping mode
at light loads. In this mode, constant-frequency operation The VCO input voltage is prebiased to the operating fre-
is maintained down to approximately 1% of designed quency set by the FREQ pin before the external clock is
maximum output current. At very light loads, the current applied. If prebiased near the external clock frequency,
comparator ICMP may remain tripped for several cycles the PLL loop only needs to make slight changes to the
and force the external bottom MOSFET to stay off for VCO input in order to synchronize the rising edge of the
the same number of cycles (i.e., skipping pulses). The external clock’s to the rising edge of BG. The ability to
inductor current is not allowed to reverse (discontinuous prebias the loop filter allows the PLL to lock-in rapidly
operation). This mode, like forced continuous operation, without deviating far from the desired frequency.
exhibits low output ripple as well as low audio noise and
3786fc

LTC3786
The typical capture range of the LTC3786’s PLL is from Power Good
approximately 55kHz to 1MHz, and is guaranteed to lock
The PGOOD pin is connected to an open-drain of an
to an external clock source whose frequency is between
internal N-channel MOSFET. The MOSFET turns on and
75kHz and 850kHz.
pulls the PGOOD pin low when the VFB pin voltage is not
The typical input clock thresholds on the PLLIN/MODE within ±10% of the 1.2V reference voltage. The PGOOD
pin are 1.6V (rising) and 1.2V (falling). pin is also pulled low when the corresponding RUN pin
is low (shut down). When the VFB pin voltage is within
Operation When VIN > Regulated VOUT the ±10% requirement, the MOSFET is turned off and the
When VIN rises above the regulated VOUT voltage, the boost pin is allowed to be pulled up by an external resistor to a
controller can behave differently depending on the mode, source of up to 6V (abs max).
inductor current and VIN voltage. In forced continuous
mode, the loop keeps the top MOSFET on continuously once Operation at Low SENSE Pin Common Mode Voltage
VIN rises above VOUT . The internal charge pump delivers The current comparator in the LTC3786 is powered directly
current to the boost capacitor to maintain a sufficiently from the SENSE+ pin. This enables the common mode
high TG voltage. (The amount of current the charge pump voltage of SENSE+ and SENSE– pins to operate as low
can deliver is characterized by two curves in the Typical as 2.5V, which is below the INTVCC UVLO threshold. The
Performance Characteristics section.) figure on the first page shows a typical application when
the controller’s VBIAS is powered from VOUT while VIN
In pulse-skipping mode, if VIN is between 100% and 110%
supply can go as low as 2.5V. If the voltage on SENSE+
of the regulated VOUT voltage, TG turns on if the inductor
drops below 2.5V, the SS pin will be held low. When the
current rises above a certain threshold and turns off if the
inductor current falls below this threshold. This threshold SENSE+ voltage returns to the normal operating range, the
SS pin will be released, initiating a new soft-start cycle.
current is set to approximately 4% of the maximum ILIM
current. If the controller is programmed to Burst Mode BOOST Supply Refresh and Internal Charge Pump
operation under this same VIN window, then TG remains
off regardless of the inductor current. The top MOSFET driver is biased from the floating boot-
strap capacitor, CB, which normally recharges during each
If VIN rises above 110% of the regulated VOUT voltage in cycle through an external diode when the bottom MOSFET
any mode, the controller turns on TG regardless of the
turns on. There are two considerations to keep the BOOST
inductor current. In Burst Mode operation, however, the
supply at the required bias level. During start-up, if the
internal charge pump turns off if the chip is asleep. With
bottom MOSFET is not turned on within 100µs after UVLO
the charge pump off, there would be nothing to prevent
goes low, the bottom MOSFET will be forced to turn on
the boost capacitor from discharging, resulting in an
for ~400ns. This forced refresh generates enough BOOST-
insufficient TG voltage needed to keep the top MOSFET
SW voltage to allow the top MOSFET to be fully enhanced
completely on. To prevent excessive power dissipation
instead of waiting for the initial few cycles to charge the
across the body diode of the top MOSFET in this situa-
bootstrap capacitor, CB. There is also an internal charge
tion, the chip can be switched over to forced continuous
pump that keeps the required bias on BOOST. The charge
or pulse-skipping mode to enable the charge pump, or a
pump always operates in both forced continuous mode
Schottky diode can also be placed in parallel to the top
and pulse-skipping mode. In Burst Mode operation, the
MOSFET.
charge pump is turned off during sleep and enabled when
the chip wakes up. The internal charge pump can normally
supply a charging current of 85µA.
3786fc

LTC3786
APPLICATIONS INFORMATION
The Typical Application on the first page is a basic LTC3786 Filter components mutual to the sense lines should be
application circuit. LTC3786 can be configured to use either placed close to the LTC3786, and the sense lines should
inductor DCR (DC resistance) sensing or a discrete sense run close together to a Kelvin connection underneath the
resistor (RSENSE) for current sensing. The choice between current sense element (shown in Figure 1). Sensing cur-
the two current sensing schemes is largely a design trade- rent elsewhere can effectively add parasitic inductance
off between cost, power consumption and accuracy. DCR and capacitance to the current sense element, degrading
sensing is becoming popular because it does not require the information at the sense terminals and making the
current sensing resistors and is more power efficient, programmed current limit unpredictable. If DCR sensing
especially in high current applications. However, current is used (Figure 2b), sense resistor R1 should be placed
sensing resistors provide the most accurate current limits close to the switching node, to prevent noise from coupling
for the controller. Other external component selection is into sensitive small-signal nodes.
driven by the load requirement, and begins with the se-
lection of RSENSE (if RSENSE is used) and inductor value. Sense Resistor Current Sensing
Next, the power MOSFETs are selected. Finally, input and A typical sensing circuit using a discrete resistor is shown
output capacitors are selected. in Figure 2a. RSENSE is chosen based on the required
output current.
SENSE+ and SENSE– Pins
The current comparator has a maximum threshold
The SENSE+ and SENSE– pins are the inputs to the cur-
VSENSE(MAX) of 75mV. The current comparator threshold
rent comparators. The common mode input voltage range sets the peak of the inductor current, yielding a maximum
of the current comparators is 2.5V to 38V. The current average inductor current, IMAX, equal to the peak value
sense resistor is normally placed at the input of the boost
controller in series with the inductor. TO SENSE FILTER,
NEXT TO THE CONTROLLER
The SENSE+ pin also provides power to the current com-

parator. It draws ~200µA during normal operation. There
is a small base current of less than 1µA that flows into VIN
the SENSE– pin. The high impedance SENSE– input to the
INDUCTOR OR RSENSE
current comparators allows accurate DCR sensing.
3786 F01
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
VBIAS VIN VBIAS VIN

SENSE+ SENSE+
(OPTIONAL) C1 R2 DCR
SENSE– SENSE–
INTVCC INTVCC INDUCTOR
LTC3786 LTC3786 R1 L
BOOST BOOST
TG TG
SW VOUT SW VOUT
BG BG
SGND SGND
3786 F02a 3786 F02b
L R2
PLACE C1 NEAR SENSE PINS (R1||R2) • C1 = RSENSE(EQ) = DCR •
DCR R1 + R2
(2a) Using a Resistor to Sense Current (2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current

3786fc

LTC3786
less half the peak-to-peak ripple current, ∆IL. To calculate To ensure that the application will deliver full load current
the sense resistor value, use the equation: over the full operating temperature range, choose the
minimum value for the maximum current sense threshold
VSENSE(MAX)
R SENSE = (VSENSE(MAX)).
∆IL
I MAX + Next, determine the DCR of the inductor. Where provided,
2
use the manufacturer’s maximum value, usually given at
When using the controller in low VIN and very high voltage 20°C. Increase this value to account for the temperature
output applications, the maximum inductor current and coefficient of resistance, which is approximately 0.4%/°C. A
correspondingly the maximum output current level will conservative value for the maximum inductor temperature
be reduced due to the internal compensation required to (TL(MAX)) is 100°C.
meet stability criterion for boost regulators operating at To scale the maximum inductor DCR to the desired sense
greater than 50% duty factor. A curve is provided in the resistor value, use the divider ratio:
Typical Performance Characteristics section to estimate
this reduction in peak inductor current level depending R SENSE(EQUIV)
RD =
upon the operating duty factor. DCRMAX at TL(MAX)
Inductor DCR Sensing C1 is usually selected to be in the range of 0.1µF to 0.47µF.

For applications requiring the highest possible efficiency This forces R1|| R2 to around 2k, reducing error that might
at high load currents, the LTC3786 is capable of sensing have been caused by the SENSE– pin’s ±1µA current.
the voltage drop across the inductor DCR, as shown in The equivalent resistance R1|| R2 is scaled to the room
Figure 2b. The DCR of the inductor can be less than 1mΩ temperature inductance and maximum DCR:
for high current inductors. In a high current application
requiring such an inductor, conduction loss through a L
R1|| R2 =
sense resistor could reduce the efficiency by a few percent (DCR at 20°C ) • C1
compared to DCR sensing.
The sense resistor values are:
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop R1|| R2 R1 • RD
R1 = ; R2 =
across the external capacitor is equal to the drop across RD 1 – RD
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where The maximum power loss in R1 is related to duty cycle,
the DCR is greater than the target sense resistor value. and will occur in continuous mode at VIN = 1/2 VOUT :
To properly dimension the external filter components, the
( VOUT – VIN ) • VIN
DCR of the inductor must be known. It can be measured PLOSS _ R1 =
using a good RLC meter, but the DCR tolerance is not R1
always the same and varies with temperature. Consult Ensure that R1 has a power rating higher than this value.
the manufacturer’s data sheets for detailed information. If high efficiency is necessary at light loads, consider this
Using the inductor ripple current value from the inductor power loss when deciding whether to use DCR sensing or
value calculation section, the target sense resistor value is: sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
VSENSE(MAX) to the extra switching losses incurred through R1. However,
R SENSE(EQUIV) =
∆I L DCR sensing eliminates a sense resistor, reduces conduc-
I MAX +
2 tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
3786fc

LTC3786
Inductor Value Calculation The peak-to-peak gate drive levels are set by the INTVCC
voltage. This voltage is typically 5.4V. Consequently, logic-
The operating frequency and inductor selection are in-
level threshold MOSFETs must be used in most applica-
terrelated in that higher operating frequencies allow the
tions. Pay close attention to the BVDSS specification for
use of smaller inductor and capacitor values. Why would
the MOSFETs as well; many of the logic level MOSFETs
anyone ever choose to operate at lower frequencies with
are limited to 30V or less.
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because Selection criteria for the power MOSFETs include the on-
of MOSFET gate charge and switching losses. Also, at resistance, RDS(ON), Miller capacitance, CMILLER, input
higher frequency, the duty cycle of body diode conduction voltage and maximum output current. Miller capacitance,
is higher, which results in lower efficiency. In addition to CMILLER, can be approximated from the gate charge curve
this basic trade-off, the effect of inductor value on ripple usually provided on the MOSFET manufacturer’s data
current and low current operation must also be considered. sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
The inductor value has a direct effect on ripple current.
flat divided by the specified change in VDS. This result is
The inductor ripple current ∆IL decreases with higher
then multiplied by the ratio of the application applied VDS
inductance or frequency and increases with higher VIN:
to the gate charge curve specified VDS. When the IC is
VIN ⎛ V ⎞ operating in continuous mode, the duty cycles for the top
∆I L = ⎜ 1 – IN ⎟ and bottom MOSFETs are given by:
f •L⎝ VOUT ⎠
VOUT – VIN
Accepting larger values of ∆IL allows the use of low Main Switch Duty Cycle =
VOUT
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for VIN
Synchronous Switch Duty Cycle =
setting ripple current is ∆IL = 0.3(IMAX). The maximum VOUT
∆IL occurs at VIN = 1/2 VOUT .
If the maximum output current is IOUT(MAX) and each chan-
The inductor value also has secondary effects. The tran- nel takes one-half of the total output current, the MOSFET
sition to Burst Mode operation begins when the average power dissipations in each channel at maximum output
inductor current required results in a peak current below current are given by:
25% of the current limit determined by RSENSE. Lower
inductor values (higher ∆IL) will cause this to occur at PMAIN =
( VOUT – VIN ) VOUT • I OUT(MAX)2 • (1+ δ )
lower load currents, which can cause a dip in efficiency in VIN 2
the upper range of low current operation. In Burst Mode I OUT(MAX)
operation, lower inductance values will cause the burst •RDS(ON) + k • VOUT 3 • • CMILLER • f
frequency to decrease. Once the value of L is known, an VIN
inductor with low DCR and low core losses should be V
selected. PSYNC = OUT • I OUT(MAX)2 • (1+ δ ) • RDS(ON)
VIN
Power MOSFET Selection

Two external power MOSFETs must be selected for the where δ is the temperature dependency of RDS(ON)
LTC3786: one N-channel MOSFET for the bottom (main) (approximately 1Ω) is the effective driver resistance at the
switch, and one N-channel MOSFET for the top (synchro- MOSFET’s Miller threshold voltage. The constant k, which
nous) switch.
3786fc

LTC3786
accounts for the loss caused by reverse recovery current, The steady ripple voltage due to charging and discharging
is inversely proportional to the gate drive current and has the bulk capacitance in a single phase boost converter is
an empirical value of 1.7. given by:
Both MOSFETs have I2R losses while the bottom N-channel (
I OUT(MAX) • VOUT – VIN(MIN) )V
equation includes an additional term for transition losses, VRIPPLE =
COUT • VOUT • f
which are highest at low input voltages. For high VIN the
high current efficiency generally improves with larger
where COUT is the output filter capacitor.
MOSFETs, while for low VIN the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device The steady ripple due to the voltage drop across the ESR
with lower CMILLER actually provides higher efficiency. The is given by:
synchronous MOSFET losses are greatest at high input ∆VESR = IL(MAX) • ESR
voltage when the bottom switch duty factor is low or dur-
ing overvoltage when the synchronous switch is on close Multiple capacitors placed in parallel may be needed to
to 100% of the period. meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
The term (1 + δ) is generally given for a MOSFET in the ceramic capacitors are all available in surface mount
form of a normalized RDS(ON) vs Temperature curve, but packages. Ceramic capacitors have excellent low ESR
δ = 0.005/°C can be used as an approximation for low characteristics but can have a high voltage coefficient.
voltage MOSFETs. Capacitors are now available with low ESR and high ripple
current ratings (i.e., OS-CON and POSCAP).
CIN and COUT Selection
The input ripple current in a boost converter is relatively Setting Output Voltage
low (compared with the output ripple current), because The LTC3786 output voltage is set by an external feedback
this current is continuous. The input capacitor, CIN, volt- resistor divider carefully placed across the output, as shown
age rating should comfortably exceed the maximum input in Figure 3. The regulated output voltage is determined by:
voltage. Although ceramic capacitors can be relatively
tolerant of overvoltage conditions, aluminum electrolytic ⎛ R ⎞
capacitors are not. Be sure to characterize the input voltage VOUT = 1.2V ⎜ 1+ B ⎟
⎝ RA ⎠
for any possible overvoltage transients that could apply
excess stress to the input capacitors. Great care should be taken to route the VFB line away
The value of the CIN is a function of the source impedance, from noise sources, such as the inductor or the SW line.
and in general, the higher the source impedance, the higher Also, keep the VFB node as small as possible to avoid
the required input capacitance. The required amount of noise pickup.
input capacitance is also greatly affected by the duty cycle.
VOUT
High output current applications that also experience high
duty cycles can place great demands on the input supply,
RB
both in terms of DC current and ripple current. LTC3786
VFB
In a boost converter, the output has a discontinuous current, RA
so COUT must be capable of reducing the output voltage
ripple. The effects of ESR (equivalent series resistance) 3786 F03
and the bulk capacitance must be considered when choos- Figure 3. Setting Output Voltage
ing the right capacitor for a given output ripple voltage.
3786fc

LTC3786
Soft-Start (SS Pin) temperature, the LTC3786 INTVCC current is limited to
less than 20mA in the QFN package from a 40V supply:
The start-up of the VOUT is controlled by the voltage on
the SS pin. When the voltage on the SS pin is less than TJ = 70°C + (20mA)(40V)(68°C/W) = 125°C
the internal 1.2V reference, the LTC3786 regulates the VFB In an MSOP package, the INTVCC current is limited to less
pin voltage to the voltage on the SS pin instead of 1.2V. than 34mA from a 40V supply:
Soft-start is enabled by simply connecting a capacitor from TJ = 70°C + (34mA)(40V)(40°C/W) = 125°C
the SS pin to ground, as shown in Figure 4. An internal
10µA current source charges the capacitor, providing a To prevent the maximum junction temperature from being
linear ramping voltage at the SS pin. The LTC3786 will exceeded, the input supply current must be checked while
regulate the VFB pin (and hence, VOUT) according to the operating in continuous conduction mode (PLLIN/MODE
voltage on the SS pin, allowing VOUT to rise smoothly = INTVCC) at maximum VBIAS.
from VIN to its final regulated value. The total soft-start
time will be approximately: Topside MOSFET Driver Supply (CB, DB)
1.2V External bootstrap capacitors, CB, connected to the

tSS = CSS • BOOST pin supplies the gate drive voltage for the topside
10µA
MOSFET. Capacitor CB in the Block Diagram is charged
though external diode, DB, from INTVCC when the SW pin
LTC3786 is low. When the topside MOSFET is to be turned on, the
SS
CSS
driver places the CB voltage across the gate-source of the
SGND
desired MOSFET. This enhances the MOSFET and turns on
3786 F04 the topside switch. The switch node voltage, SW, rises to
VOUT and the BOOST pin follows. With the topside MOSFET
Figure 4. Using the SS Pin to Program Soft-Start on, the boost voltage is above the output voltage: VBOOST
= VOUT + VINTVCC. The value of the boost capacitor, CB,
INTVCC Regulator
needs to be 100 times that of the total input capacitance
The LTC3786 features an internal P-channel low dropout of the topside MOSFET(s). The reverse breakdown of the
linear regulator (LDO) that supplies power at the INTVCC external Schottky diode must be greater than VOUT(MAX).
pin from the VBIAS supply pin. INTVCC powers the gate
The external diode DB can be a Schottky diode or silicon
drivers and much of the LTC3786’s internal circuitry. The
diode, but in either case it should have low leakage and fast
VBIAS LDO regulates INTVCC to 5.4V. It can supply at least
recovery. Pay close attention to the reverse leakage at high
50mA and must be bypassed to ground with a minimum
temperatures where it generally increases substantially.
of 4.7µF ceramic capacitor. Good bypassing is needed to
supply the high transient currents required by the MOSFET The topside MOSFET driver includes an internal charge
gate drivers. pump that delivers current to the bootstrap capacitor from
the BOOST pin. This charge current maintains the bias
High input voltage applications in which large MOSFETs
voltage required to keep the top MOSFET on continuously
are being driven at high frequencies may cause the
during dropout/overvoltage conditions. The Schottky/
maximum junction temperature rating for the LTC3786
silicon diode selected for the topside driver should have a
to be exceeded. The power dissipation for the IC is equal
reverse leakage less than the available output current the
to VBIAS • IINTVCC. The gate charge current is dependent
charge pump can supply. Curves displaying the available
on operating frequency, as discussed in the Efficiency
charge pump current under different operating conditions
Considerations section. The junction temperature can be
can be found in the Typical Performance Characteristics
estimated by using the equations given in Note 2 of the
section.
Electrical Characteristics. For example, at 70°C ambient
3786fc

LTC3786
A leaky diode DB in the boost converter can not only ously from the phase detector output, pulling up the VCO
prevent the top MOSFET from fully turning on but it can input. When the external clock frequency is less than fOSC,
also completely discharge the bootstrap capacitor CB and current is sunk continuously, pulling down the VCO input.
create a current path from the input voltage to the BOOST If the external and internal frequencies are the same but
pin to INTVCC. This can cause INTVCC to rise if the diode exhibit a phase difference, the current sources turn on for
leakage exceeds the current consumption on INTVCC. an amount of time corresponding to the phase difference.
This is particularly a concern in Burst Mode operation The voltage at the VCO input is adjusted until the phase
where the load on INTVCC can be very small. The external and frequency of the internal and external oscillators are
Schottky or silicon diode should be carefully chosen such identical. At the stable operating point, the phase detector
that INTVCC never gets charged up much higher than its output is high impedance and the internal filter capacitor,
normal regulation voltage. CLP , holds the voltage at the VCO input.
Typically, the external clock (on PLLIN/MODE pin) input
Fault Conditions: Overtemperature Protection
high threshold is 1.6V, while the input low threshold is 1.2V.
At higher temperatures, or in cases where the internal
Note that the LTC3786 can only be synchronized to an
power dissipation causes excessive self heating on-chip
external clock whose frequency is within range of the
(such as an INTVCC short to ground), the overtemperature
shutdown circuitry will shut down the LTC3786. When the LTC3786’s internal VCO, which is nominally 55kHz to
junction temperature exceeds approximately 170°C, the 1MHz. This is guaranteed to be between 75kHz and 850kHz.
overtemperature circuitry disables the INTVCC LDO, causing Rapid phase locking can be achieved by using the FREQ pin
the INTVCC supply to collapse and effectively shut down to set a free-running frequency near the desired synchro-
the entire LTC3786 chip. Once the junction temperature nization frequency. The VCO’s input voltage is prebiased
drops back to approximately 155°C, the INTVCC LDO turns at a frequency corresponding to the frequency set by the
back on. Long-term overstress (TJ > 125°C) should be FREQ pin. Once prebiased, the PLL only needs to adjust
avoided as it can degrade the performance or shorten the frequency slightly to achieve phase lock and synchro-
the life of the part. nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
Since the shutdown may occur at full load, beware that
prevent the operating frequency from passing through a
the load current won’t result in high power dissipation in
large range of frequencies as the PLL locks.
the body diodes of the top MOSFET. In this case, PGOOD
output may be used to turn the system load off. 1000
900
Phase-Locked Loop and Frequency Synchronization 800
The LTC3786 has an internal phase-locked loop (PLL) 700

FREQUENCY (kHz)
600
comprised of a phase frequency detector, a lowpass filter
500
and a voltage-controlled oscillator (VCO). This allows the
400
turn-on of the bottom MOSFET to be locked to the rising
300
edge of an external clock signal applied to the PLLIN/MODE 200
pin. The phase detector is an edge-sensitive digital type 100
that provides zero degrees phase shift between the external 0
and internal oscillators. This type of phase detector does 15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
not exhibit false lock to harmonics of the external clock. 3786 F05
If the external clock frequency is greater than the internal Figure 5. Relationship Between Oscillator Frequency
oscillator’s frequency, fOSC, then current is sourced continu- and Resistor Value at the FREQ Pin
3786fc

LTC3786
Table 1 summarizes the different states in which the FREQ losses in LTC3786 circuits: 1) IC VBIAS current, 2) INTVCC
pin can be used. regulator current, 3) I2R losses, 4) Bottom MOSFET transi-
tion losses and 5) Body diode conduction losses.
Table 1
FREQ PIN PLLIN/MODE PIN FREQUENCY 1. The VBIAS current is the DC supply current given in the
0V DC Voltage 350kHz Electrical Characteristics table, which excludes MOSFET
INTVCC DC Voltage 535kHz driver and control currents. VBIAS current typically
Resistor DC Voltage 50kHz to 900kHz results in a small (<0.1%) loss.
Any of the Above External Clock Phase Locked to External Clock 2. INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
Minimum On-Time Considerations
from switching the gate capacitance of the power MOS-
Minimum on-time, tON(MIN), is the smallest time duration FETs. Each time a MOSFET gate is switched from low to
that the LTC3786 is capable of turning on the bottom high to low again, a packet of charge, dQ, moves from
MOSFET. It is determined by internal timing delays and INTVCC to ground. The resulting dQ/dt is a current out
the gate charge required to turn on the top MOSFET. Low of INTVCC that is typically much larger than the control
duty cycle applications may approach this minimum circuit current. In continuous mode, IGATECHG = f(QT +
on-time limit. QB), where QT and QB are the gate charges of the topside
In forced continuous mode, if the duty cycle falls below and bottom side MOSFETs.
what can be accommodated by the minimum on-time, 3. DC I2R losses. These arise from the resistances of the
the controller will begin to skip cycles but the output will MOSFETs, sensing resistor, inductor and PC board
continue to be regulated. More cycles will be skipped when traces and cause the efficiency to drop at high output
VIN increases. Once VIN rises above VOUT , the loop keeps currents.
the top MOSFET continuously on. The minimum on-time
4. Transition losses apply only to the bottom MOSFET(s),
for the LTC3786 is approximately 110ns.
and become significant only when operating at low input
Efficiency Considerations voltages. Transition losses can be estimated from:
The percent efficiency of a switching regulator is equal to V 3

Transition Loss = (1.7 ) OUT I MAX • CRSS • f
the output power divided by the input power times 100%. VIN
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would 5. Body diode conduction losses are more significant at high-
produce the greatest improvement. Percent efficiency er switching frequency. During the dead time, the loss in
can be expressed as: the top MOSFETs is IOUT • VDS, where VDS is around 0.7V.
At higher switching frequency, the dead time becomes
%Efficiency = 100% – (L1 + L2 + L3 + ...) a good percentage of switching cycle and causes the
where L1, L2, etc., are the individual losses as a percent- efficiency to drop.
age of input power. Other hidden losses, such as copper trace and internal
Although all dissipative elements in the circuit produce battery resistances, can account for an additional efficiency
losses, five main sources usually account for most of the degradation in portable systems. It is very important to
include these system-level losses during the design phase.
3786fc

LTC3786
Checking Transient Response This is why it is better to look at the ITH pin signal which
The regulator loop response can be checked by looking at is in the feedback loop and is the filtered and compensated
the load current transient response. Switching regulators control loop response.
take several cycles to respond to a step in load current. The gain of the loop will be increased by increasing
When a load step occurs, VOUT shifts by an amount equal RC and the bandwidth of the loop will be increased by
to ∆ILOAD • ESR, where ESR is the effective series resis- decreasing CC. If RC is increased by the same factor that
tance of COUT . ∆ILOAD also begins to charge or discharge CC is decreased, the zero frequency will be kept the same,
COUT generating the feedback error signal that forces the thereby keeping the phase shift the same in the most
regulator to adapt to the current change and return VOUT to critical frequency range of the feedback loop. The output
its steady-state value. During this recovery time VOUT can voltage settling behavior is related to the stability of the
be monitored for excessive overshoot or ringing, which closed-loop system and will demonstrate the actual overall
would indicate a stability problem. OPTI-LOOP® compen- supply performance.
sation allows the transient response to be optimized over
A second, more severe transient is caused by switching
a wide range of output capacitance and ESR values. The
in loads with large (>1µF) supply bypass capacitors. The
availability of the ITH pin not only allows optimization of
discharged bypass capacitors are effectively put in parallel
control loop behavior, but it also provides a DC-coupled
with COUT , causing a rapid drop in VOUT . No regulator can
and AC-filtered closed-loop response test point. The DC alter its delivery of current quickly enough to prevent this
step, rise time and settling at this test point truly reflects the sudden step change in output voltage if the load switch
closed-loop response. Assuming a predominantly second resistance is low and it is driven quickly. If the ratio of
order system, phase margin and/or damping factor can be CLOAD to COUT is greater than 1:50, the switch rise time
estimated using the percentage of overshoot seen at this should be controlled so that the load rise time is limited to
pin. The bandwidth can also be estimated by examining the approximately 25 • CLOAD. Thus, a 10µF capacitor would
rise time at the pin. The ITH external components shown require a 250µs rise time, limiting the charging current
in the Figure 8 circuit will provide an adequate starting to about 200mA.
point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero Design Example
loop compensation. The values can be modified slightly As a design example, assume VIN = 12V(nominal),
to optimize transient response once the final PCB layout VIN = 22V (max), VOUT = 24V, IOUT(MAX) = 4A, VSENSE(MAX)
is complete and the particular output capacitor type and = 75mV and f = 350kHz.
value have been determined. The output capacitors must
be selected because the various types and values determine The inductance value is chosen first based on a 30% ripple
the loop gain and phase. An output current pulse of 20% current assumption. Tie the MODE/PLLIN pin to GND,
to 80% of full-load current having a rise time of 1µs to generating 350kHz operation. The minimum inductance
10µs will produce output voltage and ITH pin waveforms for 30% ripple current is:
that will give a sense of the overall loop stability without VIN ⎛ V ⎞
breaking the feedback loop. ∆I L = ⎜ 1 – IN ⎟
f •L⎝ VOUT ⎠
Placing a power MOSFET and load resistor directly
across the output capacitor and driving the gate with an The largest ripple happens when VIN = 1/2VOUT = 12V,
appropriate pulse generator is a practical way to produce where the average maximum inductor is IMAX = IOUT(MAX)
a realistic load step condition. The initial output voltage • (VOUT/VIN) = 8A. A 6.8µH inductor will produce a 31%
step resulting from the step change in output current ripple current. The peak inductor current will be the maxi-
may not be within the bandwidth of the feedback loop, mum DC value plus one-half the ripple current, or 9.25A.
so this signal cannot be used to determine phase margin.
3786fc

LTC3786
The RSENSE resistor value can be calculated by using the 1. Put the bottom N-channel MOSFET MBOT and the top
maximum current sense voltage specification with some N-channel MOSFET MTOP in one compact area with
accommodation for tolerances: COUT .
75mV 2. Are the signal and power grounds kept separate? The
R SENSE ≤ = 0.008Ω
9.25A combined IC signal ground pin and the ground return
of CINTVCC must return to the combined COUT (–)
Choosing 1% resistors: RA = 5k and RB = 95.3k yields an terminals. The path formed by the bottom N-channel
output voltage of 24.072V. MOSFET and the capacitor should have short leads and
The power dissipation on the topside MOSFET in each chan- PC trace lengths. The output capacitor (–) terminals
nel can be easily estimated. Choosing a Vishay Si7848BDP should be connected as close as possible to the (–)
MOSFET results in: RDS(ON) = 0.012Ω, CMILLER = 150pF. At source terminal of the bottom MOSFET.
maximum input voltage with T(estimated) = 50°C: 3. Does the LTC3786 VFB pin’s resistive divider connect
to the (+) terminal of COUT? The resistive divider must
( 24V – 12V ) 24V 2
be connected between the (+) terminal of COUT and
PMAIN = • ( 4A )
2
(12V ) signal ground and placed close to the VFB pin. The
• ⎡⎣1+ ( 0.005 ) ( 50°C – 25°C )⎤⎦ • 0.008Ω
feedback resistor connections should not be along the
high current input feeds from the input capacitor(s).
3 4A
+ (1.7 ) ( 24V ) (150pF ) ( 350kHz ) = 0.7W 4. Are the SENSE– and SENSE+ leads routed together with
12V minimum PC trace spacing? The filter capacitor between
COUT is chosen to filter the square current in the output. SENSE+ and SENSE– should be as close as possible
The maximum output current peak is: to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
⎛ RIPPLE% ⎞
I OUT(PEAK) = I OUT(MAX) • ⎜ 1+ ⎟ 5. Is the INTVCC decoupling capacitor connected close
⎝ 2 ⎠
to the IC, between the INTVCC and the power ground
⎛ 31% ⎞ pin? This capacitor carries the MOSFET drivers’ cur-
= 4 • ⎜ 1+ ⎟ = 4.62A
⎝ 2 ⎠ rent peaks. An additional 1µF ceramic capacitor placed
immediately next to the INTVCC and GND pins can help
A low ESR (5mΩ) capacitor is suggested. This capacitor improve noise performance substantially.
will limit output voltage ripple to 23.1mV (assuming ESR
dominate ripple). 6. Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
PC Board Layout Checklist nodes. All of these nodes have very large and fast
moving signals and, therefore, should be kept on the
When laying out the printed circuit board, the following output side of the LTC3786 and occupy a minimal PC
checklist should be used to ensure proper operation of trace area.
the IC. These items are also illustrated graphically in the
layout diagram of Figure 6. Figure 7 illustrates the current 7. Use a modified “star ground” technique: a low imped-
waveforms present in the various branches the synchro- ance, large copper area central grounding point on
nous regulator operating in the continuous mode. Check the same side of the PC board as the input and output
the following in your layout: capacitors with tie-ins for the bottom of the INTVCC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the GND pin of the IC.
3786fc

LTC3786
PC Board Layout Debugging Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
It is helpful to use a DC-50MHz current probe to monitor
coincide with high input voltages and low output currents,
the current in the inductor while testing the circuit. Moni-
tor the output switching node (SW pin) to synchronize look for capacitive coupling between the BOOST, SW, TG,
the oscilloscope to the internal oscillator and probe the and possibly BG connections and the sensitive voltage
actual output voltage. Check for proper performance over and current pins. The capacitor placed across the current
the operating voltage and current range expected in the sensing pins needs to be placed immediately adjacent to
application. The frequency of operation should be main- the pins of the IC. This capacitor helps to minimize the
tained over the input voltage range down to dropout and effects of differential noise injection due to high frequency
until the output load drops below the low current opera- capacitive coupling.
tion threshold— typically 10% of the maximum designed An embarrassing problem, which can be missed in an
current level in Burst Mode operation. otherwise properly working switching regulator results
The duty cycle percentage should be maintained from cycle when the current sensing leads are hooked up backwards.
to cycle in a well designed, low noise PCB implementation. The output voltage under this improper hook-up will still
Variation in the duty cycle at a subharmonic rate can sug- be maintained, but the advantages of current mode control
gest noise pick-up at the current or voltage sensing inputs will not be realized. Compensation of the voltage loop will
or inadequate loop compensation. Overcompensation of be much more sensitive to component selection. This
the loop can be used to tame a poor PC layout if regulator behavior can be investigated by temporarily shorting out
bandwidth optimization is not required. the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
Reduce VIN from its nominal level to verify operation with
high duty cycle. Check the operation of the undervoltage
lockout circuit by further lowering VIN while monitoring
the outputs to verify operation.
3786fc

LTC3786
SENSE+ PGOOD VPULLUP

SENSE– SW L1 RSENSE
LTC3786 TG
CB
FREQ BOOST
M1 +
fIN PLLIN/MODE BG M2
RUN
VFB VBIAS
GND
+ VIN
ITH
GND
INTVCC VOUT
SS
3786 F06
Figure 6. Recommended Printed Circuit Layout Diagram
RSENSE L1 SW VOUT
VIN
RIN
CIN COUT RL
3786 F07
BOLD LINES INDICATE HIGH SWITCHING CURRENT.

KEEP LINES TO A MINIMUM LENGTH
Figure 7. Branch Current Waveforms
3786fc

LTC3786
VBIAS
SENSE+ VIN
RSENSE CIN 5V TO 24V
LTC3786
4mΩ 22µF
SENSE–
L
PLLIN/MODE 3.3µH
RUN TG
FREQ VOUT
CSS 0.1µF SW 24V
SS
CB 0.1µF MTOP COUTA + COUTB 5A*
22µF
BOOST 220µF
CITH 15nF ×4
RITH 8.66k BG MBOT
ITH D
CITHA 220pF INTVCC
CINT
4.7µF
RA 12.1k GND
VFB 100k
PGOOD
RS
232k
3786 F08
CIN, COUTA: TDK C4532X5R1E226M
COUTB: SANYO 50CE220LX
D: BAS140W
L: PULSE PA1494.362NL
MBOT, MTOP: RENESAS HAT2169H
*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
Figure 8. High Efficiency 24V Boost Converter
VBIAS
SENSE+ VIN
LTC3786
4mΩ 6.8µF
SENSE– ×4
L
PLLIN/MODE 3.3µH
RUN TG
FREQ VOUT
CSS 0.1µF SW 28V
SS
6.8µF
BOOST 220µF
CITH 15nF ×4
RITH 8.66k BG MBOT
ITH D
CITHA 220pF INTVCC
CINT
4.7µF
RA 12.1k GND
VFB 100k
PGOOD
RS
261k
3786 F09
CIN, COUTA: TDK C4532X7R1H685K
COUTB: SANYO 63CE220KX
D: BAS140W
MBOT, MTOP: RENESAS HAT2169H

3786fc

LTC3786
VBIAS
SENSE+ VIN
LTC3786
5mΩ 6.8µF
SENSE– ×4
L
PLLIN/MODE 10.2µH
RUN TG
FREQ VOUT
CSS 0.1µF SW 36V
SS
6.8µF
BOOST 220µF
CITH 15nF ×4
RITH 8.66k BG MBOT
ITH D
CITHA 220pF
INTVCC
CINT
4.7µF
RA 12.1k GND
VFB 100k
PGOOD
RS
357k
3786 F10
D: BAS170W
MBOT, MTOP: RENESAS RJIC0652DPB
VBIAS
SENSE+ VIN
RSENSE CIN 5.8V TO 34V
LTC3786
9mΩ 22µF
SENSE–
L
10µH
• •
C
10µF
PLLIN/MODE TG
RUN
FREQ D VOUT
CSS 0.1µF SW 10.5V
BOOST COUT 1.2A
SS
270µF
CITH 100nF BG MBOT
RITH 13k
ITH
CITHA 10pF INTVCC
CINT
4.7µF
GND
RA 115k 100k
VFB PGOOD
RS
887k
3786 F11
CIN: SANYO 50CE220LX

COUT: SANYO SVPC270M
D: DIODES, INC. B360A-13-F
L: COOPER BUSSMANN DRQ125-100
MBOT: BSZ097NO4L
Figure 11. 10.5V Nonsynchronous SEPIC Converter

3786fc

LTC3786
VBIAS
VIN
4.5V TO 24V START-UP
SENSE+ CIN VOLTAGE OPERATES THROUGH
22µF TRANSIENTS DOWN TO 2.5V
RSENSE
LTC3786 5mΩ
SENSE–
L
60.4k 3.2µH
fSW = 400kHz RUN
FREQ TG
VOUT*
CSS
SW 10V
0.1µF CB MTOP COUTA + COUTB 5A
SS 0.1µF 22µF
150µF
CITH ×3
RITH BOOST
10nF
4.64k BG MBOT
ITH
CITHA D
100pF
INTVCC
CINT
RA 4.7µF
12.1k GND
VFB 100k
PLLIN/MODE
RB 100k
88.7k PGOOD
3786 F12a
COUTB: SANYO 35HVH150M
L: SUMIDA CDEP106-3R2-88
MBOT, MTOP: RENESAS HAT2170
D: INFINEON BAS140W
*WHEN VIN > 10V, VOUT FOLLOWS VIN.
100
VIN = 12V
98
VIN = 9V
96
EFFICIENCY (%)
VIN = 6V
94
92
90
88
86
1 2 3 4 5 6
OUTPUT CURRENT (A)
3786 F12b
3786fc

LTC3786
VIN
CIN 2.7V TO 4.2V
SENSE+
47µF
RSENSE ×2
LTC3786 6mΩ
SENSE–
L
PLLIN/MODE 0.67µH
RUN TG
VOUT
FREQ SW 5V
CSS CB COUT 4A
MTOP
0.1µF 0.1µF 47µF
×4
SS BOOST
CITH BG MBOT
6.8nF RITH
5.11k D2
D1
ITH Q
CITHA VBIAS
100pF INTVCC
CINT
4.7µF 100k
RA GND
1M VOUT VIN
150k C2 C1
VFB PGOOD 10µF LTC1754-5 10µF
RB C+ SHDN
CFLY
475k
1µF C– GND
3786 F13a
CIN, COUT: TDK C3225X5R1A476M
L: TOKO FDV0840-R67M
MBOT, MTOP: INFINEON BSC046N02KS
Q: VISHAY SILICONIX Si1499DH
D1: INFINEON BAS140W
D2: NXP PMEG2005EJ
CFLY: MURATA GRM39X5R105K6.3AJ
C1, C2: MURATA GRM40X5R106K6.3AJ
98
VIN = 4.2V
96
VIN = 3.3V
94
EFFICIENCY (%)
VIN = 2.7V
92
90
88
86
0 1 2 3 4
OUTPUT CURRENT (A)
3786 F13b
Figure 13. Low IQ Lithium-Ion to 5V/4A Boost Converter
3786fc

LTC3786
VBIAS VIN
SENSE+ 5V TO 24V
CIN
LTC3786 RS2 22µF
C1 L
26.1k RS1
0.1µF 10.2µH
1% 53.6k
RUN 1%
SENSE–
FREQ
CSS TG
0.1µF VOUT
SW 24V
SS CB MTOP COUTA
+ 4A
0.1µF COUTB
CITH 22µF
RITH 220µF
15nF BOOST ×4
8.87k
ITH BG MBOT
CITHA D
220pF INTVCC CINT
4.7µF
RA GND
12.1k PLLIN/MODE
VFB 100k
PGOOD
RB
232k
3786 F14a
C1: TDK C1005X7R1C104K
COUTB: SANYO, 50CE220AX
MBOT, MTOP: RENESAS RJK0305
D: INFINEON BAS140W
100
VIN = 12V
98
96
EFFICIENCY (%)
94
92
90
88
86
0 1 2 3 4
OUTPUT CURRENT (A)
3786 F14b
Figure 14. High Efficiency 24V Boost Converter with Inductor DCR Current Sensing
3786fc

LTC3786
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
VBIAS
SENSE+ VIN
LTC3786 10nF
15mΩ 22µF
SENSE– T D
×2
1:10 VOUT
PLLIN/MODE
350V
25k • COUT 10mA
fSW = 105kHz RUN
68nF
FREQ TG 22Ω • ×2
CSS
0.1µF
SS 220pF
CITH SW
RITH
22nF
8.66k BOOST
ITH BG MBOT
CITHA
100pF
INTVCC
CINT
16.2k 4.7µF
1% GND
VFB 100k
PGOOD
1M 1M 1.5M
1% 1% 1%
3786 F15
CIN: TDK C3225X7R1C226M
COUT: TDK C3225X7R2J683K
D: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES
MBOT: VISHAY SILICONIX Si7850DP
T: TDK DCT15EFD-U44S003
Figure 15. Low IQ High Voltage Flyback Power Supply
VBIAS
SENSE+ VIN
LTC3786
6mΩ 10µF
SENSE– ×2
L
PLLIN/MODE 10µH
RUN TG
FREQ D VOUT
CSS 0.1µF SW 24V
SS COUTA
+ COUTB 2A
47µF
BOOST 10µF
CITH 22nF ×4
RITH 8.66k BG MBOT
ITH
CITHA 100pF
INTVCC
CINT
12.1k 4.7µF
1% GND
VFB 100k
PGOOD
232k
1%
3786 F15
CIN, COUTA: MURATA GRM31CR61E106KA12
COUTB: KEMET T495X476K035AS
D: ON SEMI MBRS340T3G
L: VISAY SILICONIX IHLP-5050FD-01 10µH
MBOT: VISHAY SILICONIX Si4840BDP
Figure 16. Low IQ Nonsynchronous 24V/2A Boost Converter

3786fc

LTC3786
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3786#packaging for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev F)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 0.102 2.845 0.102
(.112 .004) 0.889 0.127 (.112 .004)
(.035 .005)
1 8 0.35
REF
5.10 1.651 0.102

1.651 0.102 3.20 – 3.45
(.201) 0.12 REF
(.065 .004) (.126 – .136) (.065 .004)
MIN
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
16 9 FOR REFERENCE ONLY
0.305 0.038 0.50 NO MEASUREMENT PURPOSE
(.0120 .0015) (.0197) 4.039 0.102
TYP BSC (.159 .004)
(NOTE 3) 0.280 0.076
RECOMMENDED SOLDER PAD LAYOUT
16151413121110 9 (.011 .003)
REF
DETAIL “A”
0.254
(.010) 3.00 0.102
0 – 6 TYP 4.90 0.152
(.118 .004)
(.193 .006)
GAUGE PLANE (NOTE 4)
0.53 0.152
(.021 .006)
1234567 8
DETAIL “A” 1.10 0.86
0.18 (.043) (.034)
(.007) MAX REF
SEATING
PLANE 0.17 – 0.27 0.1016 0.0508
(.007 – .011) (.004 .002)
TYP 0.50
NOTE: (.0197)
MSOP (MSE16) 0213 REV F
1. DIMENSIONS IN MILLIMETER/(INCH) BSC

2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
3786fc

LTC3786
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC3786#packaging for the most recent package drawings.
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 0.05
3.50 0.05 1.45 0.05

2.10 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.115 PIN 1 NOTCH R = 0.20 TYP
3.00 0.10 0.75 0.05 OR 0.25 × 45 CHAMFER
TYP
(4 SIDES) 15 16
PIN 1 0.40 0.10
TOP MARK
(NOTE 6) 1
1.45 0.10 2
(4-SIDES)
(UD16) QFN 0904
0.200 REF 0.25 0.05

0.00 – 0.05 0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3786fc

LTC3786
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 9/11 Updated the Topside MOSFET Driver Supply (CB, DB) section. 18
Updated Figure 12. 27
B 9/16 Added H-Grade 2, 4
C 11/17 Clarified graphs G01 and G08 5
Changed INTVCC to GND on G20 7
Changed Pin 9 to Pin 8 for PLLIN/Mode pin function 8
Changed from (VOUT • VIN) to (VOUT – VIN) 15
3786fc
33
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTC3786
as described herein will not infringe on existing patent rights.
LTC3786
TYPICAL APPLICATION
High Efficiency 48V Boost Converter
VBIAS
SENSE+ VIN
LTC3786
8mΩ 6.8µF
SENSE– ×4
L
PLLIN/MODE 16µH
RUN TG
FREQ VOUT
CSS 0.1µF SW 48V
SS
6.8µF
BOOST 220µF
CITH 15nF ×4
RITH 8.66k BG MBOT
ITH D
CITHA 220pF INTVCC
CINT
4.7µF
RA 12.1k GND
VFB 100k
PGOOD
RS
475k
3786 TA02
D: BAS170W
MBOT, MTOP: RENESAS RJK0652DPB
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC3788/LTC3788-1 Dual Output, Low IQ Multiphase Synchronous Boost 4.5V (Down to 2.5V after Start-up) ≤ VIN ≤ 38V, VOUT up to 60V, 50kHz
Controller to 900kHz Fixed Operating Frequency, 5mm × 5mm QFN-32, SSOP-28
LTC3787 Single Output, Low IQ Multiphase Synchronous Boost 4.5V (Down to 2.5V after Start-up) ≤ VIN ≤ 38V, VOUT up to 60V, 50kHz
Controller to 900kHz Fixed Operating Frequency, 4mm × 5mm QFN-28, SSOP-28
LTC3769 60V Low IQ Synchronous Boost Controller 4.5V (Down to 2.3V after Start-up) ≤ VIN ≤ 60V, VOUT up to 60V,
50kHz to 900kHz Fixed Operating Frequency, 4mm × 4mm QFN-24,
TSSOP-20
LTC3784 60V Single Output, Low IQ Multiphase Synchronous 4.5V (Down to 2.3V after Start-up) ≤ VIN ≤ 60V, VOUT up to 60V, 50kHz
Boost Controller to 900kHz Fixed Operating Frequency, 4mm × 5mm QFN-28, SSOP-28
LTC3862/LTC3862-1 Single Output, Multiphase Current Mode Step-Up DC/DC 4V ≤ VIN ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz Fixed
Controller Operating Frequency, SSOP-24, TSSOP-24, 5mm × 5mm QFN-24
LT3757/LT3758 Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ VIN ≤ 40V/100V, 100kHz to 1MHz Fixed Operating Frequency,
3mm × 3mm DFN-10 and MSOP-10E
LTC1871, LTC1871-1, Wide Input Range, No RSENSE Low IQ Boost, Flyback and 2.5V ≤ VIN ≤ 36V, 50kHz to 1MHz Fixed Operating Frequency,
LTC1871-7 SEPIC Controller MSOP-10
LTC3859AL Low IQ, Triple Output Buck/Buck/Boost Synchronous All Outputs Remain in Regulation Through Cold Crank, 4.5V(Down to
DC/DC Controller 2.5V after Start-up) ≤ VIN ≤ 38V, VOUT(BUCKS) Up to 24V, VOUT(BOOST)
Up to 60V, IQ = 28µA
LTC3789 High Efficiency Synchronous 4-Switch Buck-Boost 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, SSOP-28, 4mm × 5mm QFN-28,
DC/DC Controller SSOP-28
LT8710 Synchronous SEPIC/Inverting/Boost Controller with 4V ≤ VIN ≤ 80V, SSOP-28, TSSOP-20
Output Current Control
3786fc
34
LT 1117 REV C • PRINTED IN USA
www.linear.com/LTC3786
For more information www.linear.com/LTC3786  LINEAR TECHNOLOGY CORPORATION 2010

Features Description: LTC3786 Low I Synchronous Boost Controller

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LTC3786

n High Voltage Battery-Powered Systems

For more information www.linear.com/LTC3786 1

VBIAS ........................................................ –0.3V to 40V SENSE+, SENSE– ........................................ –0.3V to 40V

ORDER INFORMATION http://www.linear.com/product/LTC3786#orderinfo

2 For more information www.linear.com/LTC3786

For more information www.linear.com/LTC3786 3

4 For more information www.linear.com/LTC3786

POWER LOSS (mW)

POWER LOSS (mW)

Load Step Load Step

VOUT = 24V 5A/DIV

LOAD STEP FORCED

VOUT = 24V VOUT = 24V VOUT = 24V

For more information www.linear.com/LTC3786 5

SHUTDOWN CURRENT (µA)

Shutdown Current Shutdown (RUN) Threshold

QUIESCENT CURRENT (µA)

Undervoltage Lockout Threshold

INTVCC VOLTAGE (V)

4.0 5.1 5.1

6 For more information www.linear.com/LTC3786

INTVCC VOLTAGE (V)

5.15 4.0 300

Oscillator Frequency Maximum Current Sense SENSE Pin Input Current

PULSE-SKIPPING MODE 240

SENSE CURRENT (µA)

SENSE CURRENT (µA)

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CHARGE PUMP CHARGING CURRENT (µA)

PIN FUNCTIONS (MSOP/QFN)

8 For more information www.linear.com/LTC3786

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INTVCC GND RUN SS

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The SENSE+ pin also provides power to the current com-

Figure 1. Sense Lines Placement with Inductor or Sense Resistor

VBIAS VIN VBIAS VIN

Figure 2. Two Different Methods of Sensing Current

14 For more information www.linear.com/LTC3786

Inductor DCR Sensing C1 is usually selected to be in the range of 0.1µF to 0.47µF.

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Power MOSFET Selection

16 For more information www.linear.com/LTC3786

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1.2V External bootstrap capacitors, CB, connected to the

18 For more information www.linear.com/LTC3786

The LTC3786 has an internal phase-locked loop (PLL) 700

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The percent efficiency of a switching regulator is equal to V 3

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SENSE+ PGOOD VPULLUP

Figure 6. Recommended Printed Circuit Layout Diagram

BOLD LINES INDICATE HIGH SWITCHING CURRENT.

Figure 7. Branch Current Waveforms

24 For more information www.linear.com/LTC3786

*WHEN VIN < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.