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  • Coa 03 Function Interconnection

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    muhammad farooq
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    This document provides an overview of computer functions and interconnection. It discusses implementing functions via hardwired or software-based approaches. It describes the basic components of a computer including the control unit, arithmetic logic unit, memory, and input/output. It then explains the instruction cycle involving fetch and execute steps. The document discusses interrupts and how they allow other modules to interrupt normal processing. It also covers how components are interconnected using buses for data, addresses, and control and how this allows different units to communicate.

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    This document provides an overview of computer functions and interconnection. It discusses implementing functions via hardwired or software-based approaches. It describes the basic components of a computer including the control unit, arithmetic logic unit, memory, and input/output. It then explains the instruction cycle involving fetch and execute steps. The document discusses interrupts and how they allow other modules to interrupt normal processing. It also covers how components are interconnected using buses for data, addresses, and control and how this allows different units to communicate.

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    29 views61 pages

    Coa 03 Function Interconnection

    Uploaded by

    muhammad farooq
    This document provides an overview of computer functions and interconnection. It discusses implementing functions via hardwired or software-based approaches. It describes the basic components of a computer including the control unit, arithmetic logic unit, memory, and input/output. It then explains the instruction cycle involving fetch and execute steps. The document discusses interrupts and how they allow other modules to interrupt normal processing. It also covers how components are interconnected using buses for data, addresses, and control and how this allows different units to communicate.

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    © All Rights Reserved
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    of 61

    Computer Organization & Architecture

    Chapter 3

    Computer Functions and Interconnection

    1440
    March 2019
    Implementing Function
     Hardwired vs. Software based

     Hardwired systems are inflexible


    —Application Specific IC (ASIC)
    —Field Programmable Gate Array (FPGA)

     Software based systems are flexible


    —General purpose hardware can do different
    tasks, given correct control signals
    —Instead of re-wiring, supply a new set of
    control signals (software)
    Hardwired Program
    Software Program Execution
    What is a program?
     A sequence of steps (instructions)
     For each step, an arithmetic or logical
    operation is done
     For each operation, a different set of
    control signals is needed
    Function of Control Unit
     For each operation a unique code is
    provided
    —e.g. ADD, MOVE
     A hardware segment accepts the code and
    issues the control signals

     We have a programmable machine


    called computer!
    Computer Components
     Control Unit (CU) & Arithmetic and Logic
    Unit (ALU) constitute the Central
    Processing Unit (CPU)
     Data and instructions need to get into the
    system and results out
    —Input/output
     Temporary storage of code and results is
    needed
    —Main memory
    Computer Components: Top Level View
    Instruction Cycle
     Processing required for a single
    instruction is called Instruction Cycle
     Two steps:
    —Fetch
    —Execute

    Basic Instruction Cycle


    Functions in Fetch Cycle
     Program Counter (PC) holds address of
    next instruction to be fetched
    —Processor fetches instruction from memory
    location pointed to by PC
    —Increment PC
    —Unless told otherwise
     Instruction is loaded into Instruction
    Register (IR)
    —Processor interprets (decode) instruction and
    performs required actions
    Functions in Execute Cycle
     Processor-memory movement
    —data transfer between CPU and main memory
     Processor-I/O movement
    —Data transfer between CPU and I/O module
     Data processing
    —Some arithmetic or logical operation on data
     Control
    —Alteration of sequence of operations
    —e.g. jump
     Combination of above
    Characteristics of Hypothetical Machine
    Program Execution (Fetch & Execute)
    PC=Program Counter
    AC=Accumulator
    IR=Instruction Register

    0x1=Load AC from Memory


    0x2=Store AC to Memory
    0x5=Add to AC from Memory

    Memory containing:
    Instructions and Data

    Instruction format:
    Opcode + Address

    [email protected] 13
    Instruction Cycle State Diagram
    Interrupts
    Interrupts
     Mechanism by which other modules may
    interrupt normal sequence of processing in
    CPU. (provide the way to improve
    processing efficiency)
     Interrupts from Program
    — Overflow, division by zero, illegal instruction
     Interrupts from Timer
    — Generated by internal processor timer
    — Used in pre-emptive multi-tasking
     Interrupts from I/O
    — From I/O controller for some I/O event
     Interrupts from Hardware failure
    — Power failure, memory parity error
    Types of Interrupts
    Program Flow Control
    Transfer of Control via Interrupts
    Interrupt Cycle
     Added to instruction cycle
     Processor checks for interrupt
    —Indicated by an interrupt signal
     If no interrupt, fetch next instruction
     If interrupt pending:
    —Suspend execution of current program
    —Save context
    —Set PC to start address of interrupt handler
    —Process the interrupt
    —Restore context and resume interrupted
    program
    Instruction Cycle with Interrupts
    Instruction Cycle (with Interrupts)
    Handling Multiple Interrupts
     Sequential
    —Processor will ignore further interrupts while
    processing one interrupt
    —Interrupts remain pending and are checked
    after first interrupt has been processed
    —Interrupts handled in sequence as they occur
     Priority Based
    —Low priority interrupts can be interrupted by
    higher priority interrupts
    —When higher priority interrupt has been
    processed, processor returns to previous
    interrupt
    Multiple Interrupts – Sequential
    Multiple Interrupts – Nested
    Time Sequence of Multiple Interrupts

    ISR=Interrupt Service Routine


    Interconnecting Components
    Connecting the System
     Network of components in a computer
    —Memory
    —Input/Output
    —CPU
     All the units must be connected
     Different type of connection for different
    type of units
    Memory Connection
     Receives/sends data
     Receives addresses of memory locations
     Receives control signals
    —Read operation
    —Write operation
    —Timing Information
    Input/Output Interaction (data)
     Similar to memory from computer’s
    viewpoint
     Output
    —Send data to peripheral
    —Peripherals receive data from computer
     Input
    —Receive data from peripheral
    —Peripherals send data to computer
    Input/Output Interaction (signalling)
     Computer send control signals to
    peripherals
     Receive control signals from computer
     Receive addresses from computer
    —physical port numbers are used to identify
    peripheral
     Send interrupt signals (control)
    CPU Connection
     Reads instruction and data
     Writes out data (after processing)
     Sends control signals to other units
     Receives (& acts on) interrupts
    What is a Bus?
     A communication pathway connecting two
    or more devices
     Usually broadcast
     Often grouped
    —Data, Control, Address, Power, etc.
    —Many channels in one bus
    —e.g. 32 bit data bus consists of 32 separate
    single bit channels
    Data Bus
     Carries data
    —Remember that there is no difference between
    “data” and “instruction” at this level
     Width is a key performance element
    —8, 16, 32, 64 bit
    Address bus
     Identify the source or destination of data
    —e.g. CPU needs to read an instruction (data)
    from a given location in memory
     Width of the Address Bus determines
    maximum memory capacity of system
    —e.g. 8080 has 16 bit address bus giving 64k
    address space
    Control Bus
     Control and timing information
    —Memory read/write signal
    —Interrupt request
    —Clock signals
    Bus Interconnection
     Many possible interconnection systems
     Single and multiple BUS structures are
    used
    —e.g. Control/Address/Data bus (PC)
    —e.g. Unibus (DEC-PDP)
     System Bus
    —Bus connecting major computer components
    i.e. processor, memory, I/O
    —Typically consists of many parallel lines
    Bus Interconnection Scheme
    Finding Bus in my System
     What do buses look like?
    —Parallel lines on circuit boards
    —Ribbon cables
    —Strip connectors on mother boards
     e.g. PCI
    —Sets of wires
    Single Bus Problem
     Lots of devices on one bus leads to:
    —Propagation delays
     Long data paths mean that co-ordination of bus
    usage can adversely affect performance
     Most systems use multiple buses to
    overcome this problem
    Bus Types
     Dedicated
    —Separate data & address lines
     Multiplexed
    —Shared lines
    —Address valid or data valid control line
    —Advantage - fewer lines
    —Disadvantages - More complex control
    ISA: Industry Standard Architecture
    ISA Card and ISA Slots on Motherboard
    Bus Arbitration
     More than one modules may be accessing
    the bus
    —e.g. CPU and DMA controller
     Only one module should control bus at
    one time
     A bus controller or arbiter is required
    —Arbitration may be centralised or distributed
     Centralized Bus Controller vs.
     Control logic on each module on bus
    Timing
     Co-ordination of events on bus
     Synchronous
    —Events determined by clock signals
    —Control Bus includes clock line
    —A single 1-0 is a bus cycle
    —All devices can read clock line
    —Usually sync on leading edge
    —Usually a single cycle for an event
     Asynchronous
    —Occurrence of one event follows the
    occurrence of previous event
    PCI Bus
     Peripheral Component Interconnection
    —Processor independent
    —High bandwidth
    —For high speed I/O
    —Graphics Display Adapter, Network Interface
    Controller, Disk Controller, etc.
     Up to 64 data lines at 66 MHz
    —64*66M = 4224 Mbps
     Intel began work on PCI in 1990 for
    Pentium systems
    —Later made it public for industry
    standardization
    PCI Bus Interconnection
    PCI Bus
     May be configured as 32 or 64-bit bus
     PCI Bridge
    —Acts as data buffer
    —Allows to have PCI speed different from
    processor’s I/O speed
    —Keeps PCI independent of processor speed
    PCI Bus Interconnection
    PCI Bus Arbiter
     Centralized, synchronized arbitration
     Request & Grant signals
    PCI Bus Lines
     Systems lines
    —Including clock and reset
     Address & Data
    —32 time multiplexed lines for address/data
    —Interrupt & validate lines
     Interface Control
     Arbitration
    —Not shared
    —Direct connection to PCI bus arbiter
     Error lines
    PCI Commands
     Transaction between initiator (master) and
    target
     Master claims bus
     Determine type of transaction
    —e.g. I/O read/write
     Every data transfer is a single transaction
    —Address phase
    —One or more data phases
    PCI Express
     Created by Intel, Dell, HP, IBM in 2004
     Width in bits = 1 to 32
     PCI Express 1.0 (x32)
    —2001, 64Gbps
     PCI Express 2.0 (x32)
    —128Gbps
     PCI Express 3.0 (x16)
    —2011, 128Gbps
     PCI Express 3.0 (x32)
    —2011, 256Gbps
    PCI Express
    PCI Express
    PCI Express
    Legacy PCI Architecture
    PCIe Architecture
    PCI Express Switched Fabric
    PCI Express Switched Fabric
    Questions ???

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