CD 1814146
CD 1814146
CD 1814146
Information classified Confidential - Do not copy (See last page for obligations)
■ Audio decoding (MPEG1, 2, MP3, Dolby® Description
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Digital 5.1)
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The STi5189 uses state-of-the-art process
■ Linux and OS21 compatible ST40 applications
technology to provide an ultra low-cost, fully
CPU (350 MHz)
featured, SD set-top box SoC. It is a highly
■ 16-bit SDR/DDR1 compatible local memory integrated solution combining QPSK (quadrature
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interface phase shift keying) demodulation, audio/video
■ Multi-stream, DVR capable transport stream decoding and applications processing into a
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Ethernet MAC MII/RMII, DVB-CI) The STi5189 provides a solution for operators to
■ Flash and peripheral memory interface specify a range of low-cost SD STBs including
supporting NOR, NAND and Serial Flash low-cost Zappers, interactive STBs and DVR-
capable STBs, with content delivery using
■ Advanced security features, compatible with broadcast or broadband networks, or both (Hybrid
on
STBus
Contents
1 Related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 STi5189 programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 CPU documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 STi5189 features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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3.1 IQ to MPEG2 TS block conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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3.4 Audio/video decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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5 Architecture features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Satellite receiver subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.1 Embedded QPSK demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.1 STBus interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.2 Processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.3 Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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6.1 Video decode flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1 15 mm x 15 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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7.2 23 mm x 23 mm package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.3 Environmentally friendly packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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8.3 23 x 23 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.4 Ball list sorted by ball number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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9.12 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.13 Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.14 Video mapping with DENC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.15 CEC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.16 Serial Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.17 Infrared interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.18 USB 2.0 ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.19 Ethernet and TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.20 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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9.21 Asynchronous serial controller (ASC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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9.22 Synchronous serial controller (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.23 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.24 Programmable I/O ports (GPIO and PIO) . . . . . . . . . . . . . . . . . . . . . . . . 76
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9.25 Alternative functions (mapped to PIO pins) . . . . . . . . . . . . . . . . . . . . . . . 78
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10 Mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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12 QPSK demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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12.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.3 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.3.1 I2C chip addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.3.2 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.3.3 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.3.4 I2C interface in standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.3.5 Identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.3.6 I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.4 Clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.4.1 Clock inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.4.2 Internal clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.4.3 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.5 Signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.5.1 Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.5.2 Timing recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.5.3 Carrier recovery and derotator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.5.4 Equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
12.5.5 Noise indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.5.6 Forward error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12.6 DiSEqC 2.x interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.6.1 Transmit DiSEqC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
12.6.2 DiSEqC receive interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
12.7 Fast channel acquisition and blind search . . . . . . . . . . . . . . . . . . . . . . . 105
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12.7.1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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13 QPSK interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
13.1 DiSEqC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
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13.2 DVB-S and DIRECTV registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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15.10 Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
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15.10.1 Combining resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
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15.10.2 Power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.10.3 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
15.10.4 Long time-out reset timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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15.10.5 Smartcard reset detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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18.2 Interrupt level controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
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19 Memory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
19.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
19.2 ST40-300 CPU memory management . . . . . . . . . . . . . . . . . . . . . . . . . . 257
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19.2.1 External memories and on-chip peripherals address map . . . . . . . . . 257
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21.7.2 PCM decoder output interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
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21.7.3 External audio DAC interface timing requirements . . . . . . . . . . . . . . . 275
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21.8 General PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
21.9 Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
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21.9.1 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
21.9.2 External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
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22 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
1 Related documents
This datasheet is a part of the STi5189 documentation suite, which forms a complete
system description and programming guide. This datasheet is intended for hardware
engineers, and describes the pins, package, electrical characteristics and timing information
for the STi5189 device.
To obtain an up-to-date specification of this product, this datasheet should be read in
conjunction with the latest product errata sheet (bug list) obtainable from
STMicroelectronics.
The documents related to this datasheet are described in the following sections.
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1.1 STi5189 programming manual
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The programming manual describes programming of the interfaces and peripherals of the
STi5197 device. It is intended for software and system engineers.
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1.2 CPU documentation
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The ST40 core and its instruction set are documented in the ST40 32-bit CPU Core
Architecture Manual.
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2 Introduction
The STi5189 is optimized for secure Pay-TV applications with integrated DVB, DES, Multi2
and ICAM descramblers and smartcard interfaces. It also has advanced security features
normally found in mid-to-high end devices to further safeguard operator and content
investment.
The STi5189 offers enhancements in performance, features and integration to current users
of ST’s MPEG2 SD family of audio/video decoders and QPSK demodulators, whilst
reducing cost and time-to-market for the next generation of deployments. Few external
components are required to realize a complete STB solution, resulting in very low BOM
cost.
The STi5189 proposes a very small package version allowing unrivaled small applications
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and cost reduction.
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2.1
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STi5189 features summary
The STi5189 integrates in a single IC, QPSK demodulation, FEC, Multi-stream transport
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demultiplexer, applications CPU, audio/video decode, video processing, graphics and
display, advanced security, STB peripherals, audio/video DACs, digital audio/video outputs,
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– DVB-S decoding
– Up to 60 MSPS operation
– Automatic spectral inversion ambiguity resolution
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● Interface to and boot from Serial Flash through high-speed SPI interface:
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– Dual output read support
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● Graphics/Display processing:
– High-performance 2-D graphics blitter accelerator and display compositor, Link-list
control
– Multi-plane video/graphics composition with alpha blending, typical four-plane use
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case (background color + still plane + video plane + OSD plane) and integrated
Tile RAM bandwidth saver for enhanced performance
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– High-quality horizontal and vertical reformatting and resizing, with sample rate
conversion/filtering for video and graphics
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– 8 bpp CLUT and 16 bpp/32 bpp true color graphics formats supported
– Advanced anti-flicker filtering
– De-interlacing SD to 480p/576p for HDMI output
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● Display output:
– PAL/NTSC/SECAM encoder
– Encoding of CGMS, Teletext, WSS, VPS, closed caption
– RoviTM 7.1D and DCS copy protection
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● Connectivity:
– 10/100 Ethernet MAC with MII/RMII interface to external PHY
– USB 2.0 host controller with ULPI interface to external PHY
● On-chip STB peripherals:
– Two smartcard interfaces with integrated clock generation
– Four UARTs with Tx and Rx FIFOs
– Three SSCs for I²C/SPI master/slave interfaces, one of which can be dedicated for
tuner control with minimum tuner disturbance
– Five 8-bit GPIO banks with alternate functions
– Infrared transmitter/receiver
– PWM
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– CEC line controller
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● System services:
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– All clocks generated from a single external crystal
– Integrated DCO for clock recovery
– Low power/RTC/watchdog controller
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– JTAG/TAP interface
● Advanced security:
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– 23 mm x 23 mm
– 15 mm x 15 mm full specification
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3 Functional overview
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It also provides a DiSEqC™ bi-directional interface for flexible control of the outdoor unit.
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The device accepts baseband differential signals as I and Q inputs. Analog to digital
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conversion is performed by two 8-bit ADCs. The signal is then demodulated by the QPSK
demodulator to recover a byte stream. The FEC block then performs convolutional
de-interleaving, Reed–Solomon decoding and de-randomizing to provide an MPEG2
transport stream.
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The QPSK demodulator and FEC unit is compliant with the DVB-S specification. The high
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3.2 Transport
The STi5189 is able to receive and process transport streams from different sources
including the internal QPSK demodulator, an external parallel/serial transport stream input
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and from a network or HDD source through two internal transport streams from memory
paths. A transport stream output is also available to route TS streams to an external DVB-CI
module which is then returned through the external TS input, eliminating the need for
external buffers. The external TS input can also be used to attach a second
tuner/demodulator front end to support dual tuner DVR applications.
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Transport streams are processed by the integrated Programmable Transport Stream engine
(PTI). This performs PID filtering, packet demultiplexing, descrambling and section filtering
on multiple transport streams received from the broadcast, IP and HDD sources.
DES, DVB and Multi2 ciphers are supported for descrambling. The STi5189 integrates the
latest version of NDS’s ICAM CA (v2.2), and is compatible with the advanced security
requirements of all the mainstream CA vendors including Conax, Irdeto, Nagra, NDS and
Viaccess.
3.3 Connectivity
The STi5189 has a range of options for connecting to external peripherals or IP network
devices, such as wired Ethernet, xDSL, Wi-Fi, and so on. These interfaces enable the
delivery of IP streams received over broadband networks and support streaming over home
networks. These interfaces include a USB 2.0 host controller with a digital ULPI interface
(PHY attached externally) and a 10/100 Ethernet MAC with MII/RMII interface (PHY
attached externally).
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The STi5189 integrates a graphics and display subsystem that can deliver a high-quality
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visual experience for applications. The heart of this subsystem is a high-performance
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multi-operator 2D graphics blitter/compositor. This is a link-list-based module that also
supports a high-priority composition thread to perform the main display composition of video
and graphics planes. The CPU can also intervene to generate graphics and subtitle.
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Paced interleaving of application tasks within the composition thread ensures the most
efficient use of the blitter/compositor for enhanced graphics performance. Both 8 bpp CLUT
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(32-bit entries) and 16 bpp/32 bpp true color graphics formats are supported. True color
formats include ARGB1555, ARGB4444, ARGB8888, RGB565 and YCbCr422.
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The STi5189 graphics sub-system benefits further from a tile RAM to reduce latency and
bandwidth of blitter/compositor operations, resulting in significant increases in display
rendering and overall system performance. Further enhancements include an advanced
anti-flicker filter engine, capable of frame-to-field or frame-to-frame operations, filter strength
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Audio is output over an S/PDIF interface, stereo analog DACs (DAC is high drive and does
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not require buffers) and a digital PCM output interface. It is possible to output both
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compressed and decoded audio streams, at the same time, over different interfaces (for
example, Dolby Digital 5.1 over S/PDIF with decoded MPEG1 audio through the analog
output).
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3.7 Processor and memory
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The STi5189 embeds the latest ST40 applications processor, the ST40-300, with two-way
set associative caches, a 32 K instruction cache, 32 K data cache, FPU and MMU. At an
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operating frequency of 350 MHz it can deliver > 580 DMIPs performance.
The STi5189 supports both SDR and DDR1 memory technology on its 16-bit Local Memory
Interface (LMI), providing a high bandwidth, unified memory for code, data, audio and video
buffers, graphics, and so on. Up to 64 Mbytes capacity can be supported with a single
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512 Mbit device and 128 Mbytes capacity can be supported by two 512 Mbit devices.
A 16-bit Flexible Memory Interface (FMI) is used for connecting to Flash and
RAM/peripherals supporting a standard 8- or 16-bit asynchronous read/write protocol.
Synchronous or burst mode Flash can also be supported. Both NOR and NAND Flash can
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be used, with the ability to boot from either. The STi5189 integrates a NAND controller for
accessing NAND Flash and to perform ECC generation.
Interfacing and booting from Serial Flash devices attached through high-speed SPI is also
supported.
3.8 DVR
The STi5189 supports the attachment of an HDD through USB 2.0 or EIDE (PIO mode),
allowing DVR STBs to be developed. The STi5189 can support recording of up to two SD
streams, with local playback of a third SD stream with trick modes. Streams can be
encrypted to/from the HDD using the T-DES cipher. Basic DVR time-shift capability, without
HDD attachment, can also be supported, either over USB 2.0 with attached Flash drive or
with NAND Flash attached directly on the FMI.
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3.11 Low power modes
Two low power modes are supported by the STi5189, passive and active standby modes.
Passive standby mode reduces the power consumption to a minimum. Almost all the device
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is powered down (clocks reduced/stopped and interfaces disabled) and the ST40 CPU can
remain running at the minimum frequency possible. The LMI puts the SDRAM into
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self-refresh mode before powering down. The device context is fully maintained. The device
can be quickly powered up without re-booting by an IR remote control event, an internal
timer event or an external interrupt.
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Active standby mode is a user-defined configuration where selected features and interfaces
can be powered down (clocks reduced/stopped and interfaces disabled) while required
features can remain clocked at full speed. In a typical configuration, the STB may not be
on
decoding or displaying a program (that is, decoders and DACs are powered down), but is
required to respond to data or messages arriving through the broadcast or broadband
connection (transport or Ethernet subsystems remain active).
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FMI. Any Flash type (Serial NOR, parallel NOR, NAND) can be used with this package. The
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following features are available with this package option:
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● All the features as in the BGA15 mm x 15 mm package
● DVB-CI support
● NAND Flash storage
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● FMI interfaces available, secure boot from any Flash (Serial, NAND or NOR)
● HDD attachment through EIDE
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With this package, DVB-CI and Ethernet are mutually exclusive options.
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Smartcard 0
RF IN
AGC
2
Satellite I C ST8024
tuner
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IQ+/-
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SC0
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DDR LMI
SSC/I2C
SDRAM E2 PROM
STi5189
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HS_SPI 15 mm x 15 mm Analog audio,
Flash L/R
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CVBS
CVBS
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Display driver
UART
or FP micro
4 digit, 7 segment 30 MHz
PIOs
display
Left
IR Rx
Front panel display Right
and controls S/PDIF
on
S/PDIF
JTAG
Reset DCU
Power supply
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IDC (20)
Ethernet USB
PHY PHY
LNA, splitters
ST3232 ST8024
RMII ULPI
AGC
Satellite Satellite I2C
tuner tuner IQ+/- UART
IF
AGC
Information classified Confidential - Do not copy (See last page for obligations)
UART/SC
Serial TSin
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STV289 I2C
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SSC/I2C
E2 PROM
STi5189
DDR LMI
15 mm x 15 mm
SDRAM TV
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CVBS
SCART
HS_SPI
Flash RGB STv
AUX/
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641x
loop-through
30 MHz SCART
Display driver UART
fid
JTAG
Reset DCU
Power supply
C
IDC (20)
Smartcard 1 Smartcard 0
RF IN
AGC
Satellite I2C ST8024
ST8024
tuner IQ+/-
TS OUT
SC1
DVB-CI TS IN
UART/SC
SSC/I2C
FMI E2 PROM
I STi5189
Information classified Confidential - Do not copy (See last page for obligations)
Buffers
23 mm x 23 mm Analog audio,
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L/R
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DDR LMI
SDRAM
CVBS
HS_SPI CVBS
Flash
30 MHz
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Display driver UART
4 digit, 7 segment Left
or FP micro
display
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PIOs Right
S/PDIF
Front panel display IR Rx S/PDIF
and controls
fid
JTAG
Reset DCU
Power supply
on
IDC (20)
C
Video decoder
Information classified Confidential - Do not copy (See last page for obligations)
MPEG-2 profiles/levels Main profile at main level (MP@ML), main profile at low level (MP@LL)
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supported Simple profile at main level (SP@ML)
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Width: 720 x 576 pixels = 45 x 36
Maximum picture size
Number of macroblocks: 45 x 36 = 1620
MPEG-1: -1024 to 1023 (full pel), -512 to 511.5 (half pel) horizontal and vertical
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Motion vector range
MPEG-2: -1024 to 1023.5 horizontal and -128 to 127.5 vertical
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(200 MHz DDR). Supports 64 Mbit, 128 Mbit, 256 Mbit or 512 Mbit SDRAM (DDR or
SDRAM LMI interface
SDR). Fully cacheable address space for data and instructions, with data cacheability
controlled in 512 Kbyte blocks for up to 8 Mbytes.
Automatic detection of start codes (of picture layer and above) to enable the
on
decoding
Automatic concealment of errors detected by VLD and decoding pipeline by macroblock
Error concealment
copy
Display
Information classified Confidential - Do not copy (See last page for obligations)
Horizontal: maximum vector size: 2047 pels, resolution: 1/8 pel
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Pan and scan vectors
Vertical: maximum vector size: 1022 lines, resolution: 1 line
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Blitter-based composition
The OSD plane is managed as a set of horizontal bands with a specification comprising
configuration, bitmap and, for CLUT formats, palette information for each region. The
OSD operates in one of two modes, palette mode or true color mode.
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Palette mode: Each region can be independently specified with a resolution of 8 bpp.
Regions are frame based. Each region palette can support up to 256 colors with up to
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resolution in one of the following direct color formats: RGB565, ARGB1555, ARGB4444
or ARGB8888.
A vertical interfield, anti-flicker filter is provided to reduce flicker on interlace displays. It
is available for both palette and true color modes.
on
Audio decoder
Bit streams accepted MPEG-1 layers I, II and III (MP3), Dolby digital 5.1
ISO/IEC 11172-3 layers I and II
All MPEG input bit rates supported with sampling rates of 32 kHz, 44.1 kHz and
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Performance
48 kHz, free format at 32 kHz and 48 kHz sampling rates.
Decodes in single channel, dual channel, stereo or joint stereo modes
Error concealment Automatic error concealment on CRC or synchronization error detection
General
Support for A/V sync PTS/DTS extraction from MPEG packet layers with automatic association
5 Architecture features
The major components of the STi5189 are described in the following sections.
Information classified Confidential - Do not copy (See last page for obligations)
On the side of the transport stream received from the QPSK demodulator, the STi5189 can
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also support an external transport stream input.
5.1.1
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Embedded QPSK demodulator
The embedded QPSK demodulator has the following features:
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● Fast channel acquisition:
– Rapid scanning in seconds for satellite transponders
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5.2 Decoder
Information classified Confidential - Do not copy (See last page for obligations)
includes two-way, set-associative caches and an interrupt controller with 15 user interrupt
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sources and an interrupt expansion port.
The LMI is used for all code/data requirements in unified memory applications, including
graphics, video and audio buffers. It is a 16-bit wide SDR/DDR SDRAM interface with a peak
bandwidth of 800 Mbytes (DDR running @ 200 MHz). It supports 64-Mbit, 128-Mbit,
256-Mbit or 512-Mbit devices. The LMI provides a fully cacheable address space for data
and instructions, with data cacheability controllable at block level.
on
The STi5189 is capable of booting directly from Serial Flash. Code can then be copied into
LMI memory and executed from there. Secure boot from Serial NOR Flash is supported.
Information classified Confidential - Do not copy (See last page for obligations)
● DMA transfers the PES data to audio and video decoders through circular buffers
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● DMA transfers the section data to separate buffers for further processing by the CPU
● DVB transport streams with data rates up to 100 Mbit/s
● PID filtering to select the audio, video and data packets to be processed
● can support 48 PID slots
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● Descramble streams using the following ciphers:
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– DVB-CSA
– DES-ECB
– NDS specific streams that are supported by the integrated ICAM functionality
fid
● has a section filter core that filters DVB standard sections using 48 x 8 byte filters
The MPEG graphics and display architecture shown in the following figure provides the
graphics, video-stream processing and display capabilities of the STi5189:
DDR
16
Blitter
LMI
Omega2 interconnect
Information classified Confidential - Do not copy (See last page for obligations)
as illustrated in the following figure:
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Figure 5. Example of composition
Background
color
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fid
Decompressed
video
on
Replay
On-screen
Score Stats
display
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OSD plane
The OSD plane is managed as a set of horizontal bands with a specification comprising
configuration, bitmap and, for CLUT formats, palette information for each region. The OSD
operates in one of two modes, palette mode or true color mode.
Palette mode: Each region can be independently specified with a resolution of 8 bpp.
Regions are frame based. Each region palette can support up to 256 colors with up to 24-bit
resolution per color entry.
True color mode: Each region can be independently specified with a 16 bpp/32 bpp
resolution in one of the following direct color formats: RGB565, ARGB1555, ARGB4444 or
ARGB8888.
A vertical inter-field, anti-flicker filter is provided to reduce flicker on interlace displays. It is
available for both palette and true color modes.
Display mixing
Display planes are mixed by the blitter using alpha blending between the planes. Mixing of
the OSD plane with the lower layers is achieved using one of the following on a per region
basis:
● a 4-bit alpha blending component per region (true color mode and palette mode without
anti-aliasing enabled)
● an individual 6-bit alpha component per color (palette mode with anti-aliasing enabled)
● alpha with pixel (ARGB1555, ARGB4444 or ARGB8888, true color mode only)
Information classified Confidential - Do not copy (See last page for obligations)
standards. 480i/576i is output with a 27 MHz pixel clock and de-interlaced 480p/576p can
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also be output with a 54 MHz pixel clock. Both formats can be used to interface to an
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external HDMI transmitter if the application requires an HDMI interface.
CEC controller
The STi5189 integrates a hardware CEC controller to support HDMI applications with a
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low-cost external HDMI transmitter. The CEC controller offloads the CPU from the low-level
bit timing, bit shaping and arbitration needs of the CEC protocol.
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Genlocking
fid
Genlocking locks the STi5189 OSD to an incoming analog signal. The RGB signals contain
OSD that can be overlaid on top of analog CVBS, allowing single OSD for both digital and
analog reception. The OSD active signal can be used as a fast blanking signal to switch
between CVBS and RGB, as illustrated in the following figure.
on
The STi5189 does not require any external PLL to lock its own pixel clock. It uses its own
internal PLL, which reduces the overall BOM.
CVBS
from analog
tuner Sync HSync
Extractor VSync RGB
27 MHz STi5189
OSD
Xtal active
Genlocked to incoming CVBS
One integrated quad-DAC provides four analog TV outputs, on which it is possible to output
either (CVBS + RGB) or (CVBS + YUV) or (S - VHS (Y/C) + CVBS1 + CVBS2).
Information classified Confidential - Do not copy (See last page for obligations)
Figure 7. Audio subsystem
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DMA request
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DMA request
Memory
FS
Stereo
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analog
Audio outputs
decoder
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System interconnect
on
S/PDIF output
S/PDIF
player
CPU Interrupts
C
Information classified Confidential - Do not copy (See last page for obligations)
● two smartcard controllers
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● four ASCs (UARTs) which are generally used by the smartcard controllers or for
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modem application
● three SSCs for I²C master/slave interfaces, with SPI support
● five GPIO ports
● infrared blaster/decoder interface module
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● DVB common interface support
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● a low-power/RTC/watchdog controller
● DCU toolset support
● a JTAG/TAP interface
on
The STi5189 has a clock master. The Flash clock output may be phase aligned to optimize
the external bus performance of the FMI.
VCXO functionality has been integrated using a special purpose frequency synthesizer, thus
removing the need for an external varactor diode or VCXO module.
6 Dataflow
This chapter describes the system dataflow for audio/video reproduction from the front-end
compressed stream through the audio/video decoders and various buffers to the final
audio / video presentation.
In the following dataflow, the programmable transport interface (PTI) performs the transport
stream demultiplexing. The channel 0 DMA generates audio and video circular buffers in the
main memory.
Information classified Confidential - Do not copy (See last page for obligations)
Figure 8. Video decode flow
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Transport In (from demodulator section)
LMI
Memory buffer Association
table of
TSIS PTI Ch0 PTI Vid address
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FDMA PES/SCD and SC
PES buff
by FDMA
FDMA
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Vid
ES VidDMA
fid
Vid VidDMA
Video
TMP
VidDMA
on
Vid420
out
BlitDMA
OSD
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BlitDMA BLIT
Video + Display
background buffers
(444)
The PTI channel 0 circular video buffer is accessed by the FDMA, which is a linear linked-list
machine. The synchronization is described in the following paragraph:
The host CPU is interrupted by a programmed timer event from system services, for
example, every 10 ms. The interrupt routine reads the Ch0 write pointer from the PTI; using
this and the previous write pointer, a single pass linear access is activated using a dedicated
process (PPSCD) running on the FDMA (with hardware assist) to perform PES parsing and
start code detect.
The FDMA PPSCD process generates an elementary stream (ES) buffer in the main
memory and an association table, which can be placed in the external memory or local
SRAM.
Each entry of the PPSCD table contains the following information:
● start code value
● PTS if present
● start code offset in the PES buffer
● start code address in the ES buffer
This table is accessed by the video driver running on the host CPU. The ES video buffer is
accessed directly using the linear DMA engine inside the video decoder. This block
generates several intermediate buffers during the prediction and reconstruction phases of
decode, before generating a final video buffer in YCbCr 4:2:0 format.
Information classified Confidential - Do not copy (See last page for obligations)
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The video buffer is read directly by the blitter, which performs multiple passes to format
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convert and blend the video buffer with a background and OSD overlay, before rendering a
final display buffer in YCbCr 4:2:2 format.
The picture composed by the blitter is always frame based. The final presentation buffer is
read by the GDMA, which drives the digital encoder to produce composite video output. The
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GDMA should be programmed to access the presentation buffer field based.
Standard audio decode flow: The elementary stream, corresponding to the bypass (Dolby
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stream), is moved to the S/PDIF player by the FDMA. The FDMA performs appropriate
formatting for the S/PDIF player. The S/PDIF player outputs the data on the S/PDIF output.
fid
The audio elementary stream is read from buffers in memory by the ST40 CPU executing
the decoding firmware. The decoded audio is then written back to decoded audio buffers in
memory. The CPU can also perform some post-processing.
The FDMA can also move the decoded audio, which is buffered external to the audio
on
decoder, to the S/PDIF player after appropriate formatting. The formatting consists of the
addition of channel status, user data and validity flag.
The CPU generates a PCM buffer that can be used to generate the beep tones or sync
noise. The contents of the buffer are moved to the PCM player by the FDMA. The quad
C
7.1 15 mm x 15 mm package
The following table gives the values of the dimensions marked in Figure 9:
Information classified Confidential - Do not copy (See last page for obligations)
A1 0.21 0.00827399
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A2 1.085 0.0428
A3 0.30 0.0118
A4 0.80 0.0315
(2)
b 0.35 0.40 0.45 0.0137899 0.0158 0.0177
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D 14.85 15.00 15.15 0.58509 0.591 0.5969
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D1 13.60 0.5358
E 14.85 15.00 15.15 0.58509 0.591 0.5969
fid
E1 13.60 0.5358
e 0.80 0.0315
F 0.70 0.0276
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1. LFBGA stands for Low profile Fine Pitch Ball Grid Array.
- Low profile: 1.20 mm < A = 1.70 mm/Fine pitch: e < 1.00 mm pitch.
-The total profile height (Dim A) is measured from the seating plane to the top of the component
-The maximum total package height is calculated by the following methodology:
A Max = A2 Typ+A1 Typ + V (A1²+A3²+A4² tolerance values)
2. The typical ball diameter before mounting is 0.40 mm.
3. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball,
there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A
and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
4. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball,
there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis
perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained
entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones.
5. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other
feature of package body or integral heatslug.
A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of
each corner is optional.
Information classified Confidential - Do not copy (See last page for obligations)
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fid
on
C
7.2 23 mm x 23 mm package
The following table gives the values of the dimensions marked in Figure 10:
Information classified Confidential - Do not copy (See last page for obligations)
A3 0.52 0.02047
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A4 0.785 0.030905
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b 0.40 0.50 0.60 0.01576 0.0197 0.0237
D 22.80 23.00 23.20 0.89764 0.905509 0.913383
D1 20.80 0.818895
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D2 19.30 19.50 19.70 0.7598401 0.7677141 0.775588
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Information classified Confidential - Do not copy (See last page for obligations)
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nt
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e
fid
on
C
Information classified Confidential - Do not copy (See last page for obligations)
Function Type Key
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Transport and Demodulator SIG
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PIO/peripheral SIG
Video SIG
Audio SIG
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System (JTAG, interrupts) SIG
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Ground VSS/GND
Do not connect(1) DNC
No ball -
on
1. DNC: There is no internal connection to these balls. Routing is NOT allowed over these balls.
C
8.2 15 x 15 package
NOT_LMICLK
B PIO3[1] PIO1[6] LMIADDR[6] LMIADDR[7]
OUT
LMIDATA[14]
Information classified Confidential - Do not copy (See last page for obligations)
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VCCA2V5_DA VCCA2V5_DA
E
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VDD33 VDD33 LMICLKEN GND GND GND
CS CS
MASS_QUIET[
F REXT[35]
35]
IDUMPX
en
G VOUT XOUT UOUT GND GND GND
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MASS_QUIET[
H REXT[10] WOUT
10]
IDUMPUVW GND GND GND
fid
GNDA2V5_DA
J ADAC_AOL ADAC_VBG ADAC_AOR ADAC_VSSAH
CS
GND GND GND
GNDA2V5_DA
K ADAC_VCCAH PIO2[3]
CS
GND GND GND
on
TS0OUTERR
L OR
TS0INDATA[3] PIO2[4] PIO3[5] PIO3[6] GND GND GND
TS0OUTDATA[ TS0OUTDATA[
M 7] 6]
TS0INDATA[2] GND GND GND GND
C
TS0OUTBITO
TS0OUTDATA[ TS0OUTDATA[
N 4] 5]
RBYTECLKVA
LID
TS0OUTDATA[
P TS0INDATA[1] TS0INDATA[4]
2]
USB_DATA[3] VDD1V0 VDD1V0
TS0OUTDATA[
R 3]
TS0INDATA[5] TS0INDATA[0] USB_DIR USB_DATA[1] USB_DATA[4] USB_DATA[7] SPI_NOTCS
TS0OUTBITO TS0INBITORB
T TS0INDATA[6]
RBYTECLK
TS0INDATA[7]
YTECLK
USB_DATA[0] USB_DATA[2] USB_CLK USB_DATA[5] SPI_CLK
1 2 3 4 5 6 7 8 9
LMIRDNOTW
LMIDATA[9] LMIDQM[1] LMIDQS[0] LMIDATA[6] LMIDATA[4]
R
LMIADDR[0] LMIADDR[2] LMIADDR[1] C
Information classified Confidential - Do not copy (See last page for obligations)
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CEC PIO4[1] PIO4[2] F
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GND GND GND PIO3[2] PIO3[3] PIO4[0] PIO3[7] G
en
GND GND GND PIO3[4] SPDIF PIO0[4] PIO0[6] PIO0[5] H
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10 11 12 13 14 15 16 17 18
8.3 23 x 23 package
39/294
B
VCCA2V5_
DACS
VCCA2V5_
DACS
REXT[10]
IDUMPUV
W
C VDD33_25
LMIADDR[5 LMIADDR[9 LMIADDR[1
] ] 2]
C VOUT XOUT
VCCA2V5_
DACS
IDUMPX REXT[35]
on VDD33 VDD33_25
LMIADDR[4 LMIADDR[1
] 1]
LMICLKEN
NOT_LMIC
LKOUT
ADAC_VSS LMIDATA[1
en
E ADAC_AOR ADAC_AOL PIO3[1] PIO1[7] VDD33 VDD33 VDD33_25 GND
AH 3]
ADAC_VCC
F PIO2[4] PIO2[3] GND VDD33 VDD33 VDD33_25 GND
AH
J
TS0INDATA TS0OUTER
[3]
TS0OUTDA TS0OUTDA
ROR
TS0INDATA
GND
GNDA2V5_
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GNDA2V5_
DACS
GNDA2V5_
VDD33
GND GND
GND
GND
GND
GND GND
TA[6] TA[7] [2] DACS DACS
TS0OUTBI
TS0OUTDA TS0OUTDA GNDA2V5_
K TORBYTEC GND GND GND GND GND GND GND
TA[4] TA[5] DACS
LKVALID
TS0OUTBI
TS0OUTDA TS0INDATA
M TORBYTEC GND GND GND GND GND GND GND
TA[2] [6]
LK
TS0INDATA TS0OUTPA
STi5189
N GND GND GND GND GND GND GND GND
[7] CKETCLK
Information classified Confidential - Do not copy (See last page for obligations)
Confidential
STi5189
Table 8. Ballout - Top-right
15 16 17 18 19 20 21 22 23 24 25 26 27
LMIADDR[1
LMIDATA[8] REXT_LMI LMIDQS[0] LMIDATA[6] LMIBA[0] LMIADDR[3] GND GND B
0]
GND GND
fid
GND LMIDATA[1]
NOT_LMIRA
S
PIO4[1] PIO3[7] PIO4[0] E
Doc ID 8141465 Rev 5
en
GND GND GND GND GND CEC PIO3[2] F
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
l GND
GND
GND
PIO0[4] PIO0[7]
PIO0[1]
PIO0[3]
PIO0[2] PIO0[0]
J
AUXCLKOU NOT_RESE
GND GND GND GND GND PIO1[5] M
T T
NOTASEBR
GND GND GND GND GND GND GND PIO2[0] N
K
40/294
Information classified Confidential - Do not copy (See last page for obligations)
Confidential
41/294
TS0INERR TS0INDATA
R GND GND GND GND GND GND GND GND
OR [0]
TS0INBITO
TS0INBITO TS0INPAC
C
T RBYTECLK GND GND GND GND GND GND GND
RBYTECLK KETCLK
VALID
V
CSn[3]
RBn[2]
CSn[2]
RBn[3]
CSn[1]
NOT_FMIC
RBn[1]
GND
on GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
fid
SB
SC SD 23]
Y
FMIADDR[
21]
FMIADDR[
22]
FMIADDR[
5] en GND GND GND GND
AA
FMIADDR[
3]
FMIADDR[
FMIADDR[
7]
FMIADDR[
GND
l
AB GND GND GND GND GND
20] 17]
FMIADDR[ FMIADDR[
AG VDD33 VDD33 FMIDATA[5] FMIDATA[2]
9] 11]
STi5189
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Information classified Confidential - Do not copy (See last page for obligations)
Confidential
STi5189
Table 10. Ballout - Bottom-right
GNDA2V5_
GND GND GND GND GND PIO2[6] PIO2[7] PIO3[0] T
C
PLL_FS_BE
GNDA2V5_ GNDA2V5_
on
GND GND GND GND GND TMS TCK NOT_TRST TDI U
PLL_FS_BE PLL_FS_BE
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GNDA1V0_F GNDA1V0_F VDDA1V0_F
GND GND VBASE AA
E E E
l
E E E E
USB_DATA[ USB_DATA[
IP GND GND AG
3] 4]
15 16 17 18 19 20 21 22 23 24 25 26 27
42/294
Information classified Confidential - Do not copy (See last page for obligations)
STi5189 BGA footprint and ball list
A1 PIO1[7] VCCA2V5_DACS
A2 LMIADDR[4] VCCA2V5_DACS
A3 LMIADDR[5] MASS_QUIET[10]
A8 LMIDATA[13] -
A10 LMIDATA[8] LMIADDR[6]
A11 - LMIADDR[8]
Information classified Confidential - Do not copy (See last page for obligations)
A15 LMIDATA[0] -
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A16 NOT_LMICAS -
A17 NOT_LMICS LMIVREF
A18 LMIBA[1] LMIDQM[0]
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A24 - LMIADDR[0]
A25 - LMIADDR[2]
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A26 - GND
A27 - GND
fid
B1 PIO3[1] VCCA2V5_DACS
B2 PIO1[6] VCCA2V5_DACS
B3 LMIADDR[6] REXT[10]
on
B4 LMIADDR[7] IDUMPUVW
B7 NOT_LMICLKOUT -
B8 LMIDATA[14] -
C
B9 - VDD33_25
B10 LMIDQS[1] LMIADDR[5]
B11 LMIVREF LMIADDR[9]
B12 - LMIADDR[12]
B14 LMIDATA[3] -
B15 LMIDATA[1] -
B16 NOT_LMIRAS LMIDATA[8]
B17 LMIBA[0] REXT_LMI
B18 LMIADDR[10] LMIDQS[0]
B19 - LMIDATA[6]
B23 - LMIBA[0]
B24 - LMIADDR[10]
B25 - LMIADDR[3]
B26 - GND
B27 - GND
C1 VDD33_25 VOUT
C2 VDD33_25 XOUT
C3 VDD33_25 VCCA2V5_DACS
C4 VDD33_25 IDUMPX
C5 LMIADDR[9] REXT[35]
C6 LMIADDR[12] -
Information classified Confidential - Do not copy (See last page for obligations)
C7 LMICLKOUT -
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C8 LMIDATA[15] VDD33
C9 LMIDATA[11] VDD33_25
C10 LMIDATA[9] LMIADDR[4]
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C11 LMIDQM[1] LMIADDR[11]
C12 LMIDQS[0] LMICLKEN
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C14 LMIDATA[4] -
C15 LMIRDNOTWR LMIDATA[11]
C16 LMIADDR[0] LMIDATA[9]
C17 LMIADDR[2] LMIDQS[1]
on
C22 - NOT_LMICAS
C23 - NOT_LMICS
C24 - LMIADDR[1]
C25 - PIO4[7]
C26 - PIO4[5]
C27 - PIO4[6]
D1 VDD33 WOUT
D2 VDD33 ADAC_VBG
D3 VDD33 UOUT
D4 VDD33 VCCA2V5_DACS
D5 LMIADDR[8] MASS_QUIET[35]
D6 LMIADDR[11] PIO1[6]
D7 GND VDD33
D8 GND VDD33
D9 LMIDATA[12] VDD33_25
D10 LMIDATA[10] -
D11 REXT_LMI LMIADDR[7]
D12 LMIDQM[0] LMICLKOUT
D13 LMIDATA[7] LMIDATA[15]
D14 LMIDATA[2] LMIDATA[14]
D15 LMIADDR[3] LMIDATA[12]
Information classified Confidential - Do not copy (See last page for obligations)
D16 PIO4[6] LMIDATA[10]
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D17 PIO4[7] LMIDQM[1]
D19 - LMIDATA[4]
D20 - LMIDATA[2]
en
D21 - LMIDATA[0]
D22 - LMIRDNOTWR
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D23 - LMIBA[1]
fid
D24 - PIO4[4]
D25 - PIO4[2]
D26 - PIO4[3]
E2 VCCA2V5_DACS ADAC_VSSAH
on
E3 VCCA2V5_DACS ADAC_AOR
E4 VDD33 ADAC_AOL
E5 VDD33 PIO3[1]
C
E6 LMICLKEN PIO1[7]
E7 GND VDD33
E8 GND VDD33
E9 GND -
E10 GND VDD33_25
E11 GND -
E12 GND GND
E13 LMIDATA[5] -
E14 PIO4[3] LMIDATA[13]
E15 PIO4[5] -
E16 PIO4[4] GND
E18 - GND
E20 - GND
E21 - LMIDATA[1]
E22 - NOT_LMIRAS
E23 - PIO4[1]
E24 - PIO3[7]
E25 - PIO4[0]
F3 REXT[35] PIO2[4]
F4 MASS_QUIET[35] PIO2[3]
F5 IDUMPX ADAC_VCCAH
Information classified Confidential - Do not copy (See last page for obligations)
F6 - GND
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F7 - VDD33
F9 - VDD33
F11 - VDD33_25
en
F13 - GND
F14 CEC -
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F16 PIO4[2] -
F17 - GND
F19 - GND
F21 - GND
on
F22 - GND
F23 - CEC
F24 - PIO3[2]
C
G3 VOUT -
G4 XOUT PIO3[5]
G5 UOUT PIO3[6]
G6 - GND
G7 GND -
G8 GND VDD33
G9 GND -
G10 GND VDD33
G11 GND -
G12 GND VDD33_25
G14 PIO3[2] GND
G15 PIO3[3] -
G16 PIO4[0] GND
G17 PIO3[7] -
G18 - GND
G20 - GND
G22 - GND
G23 - PIO3[3]
G24 - PIO3[4]
H2 REXT[10] -
H3 WOUT TS0INDATA[3]
Information classified Confidential - Do not copy (See last page for obligations)
H4 MASS_QUIET[10] TS0OUTERROR
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H5 IDUMPUVW GND
H7 GND GNDA2V5_DACS
H8 GND -
en
H9 GND VDD33
H10 GND -
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H12 GND -
H13 - GND
H14 PIO3[4] -
H15 SPDIF GND
on
H16 PIO0[4] -
H17 PIO0[6] GND
H18 PIO0[5] -
C
H19 - GND
H21 - GND
H23 - SPDIF
H24 - PIO0[6]
H25 - PIO0[5]
J1 ADAC_AOL -
J2 ADAC_VBG TS0OUTDATA[6]
J3 ADAC_AOR TS0OUTDATA[7]
J4 ADAC_VSSAH TS0INDATA[2]
J5 GNDA2V5_DACS -
J6 - GNDA2V5_DACS
J7 GND -
J8 GND GNDA2V5_DACS
J9 GND GND
J10 GND GND
J11 GND GND
J12 GND -
J13 - GND
J14 DNC GND
J15 PIO0[3] GND
J16 PIO0[7] -
Information classified Confidential - Do not copy (See last page for obligations)
J17 - GND
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J18 - GND
J19 - GND
J20 - GND
en
J22 - GND
J24 - PIO0[4]
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J25 - PIO0[7]
fid
J26 - PIO0[3]
K1 - TS0OUTBITORBYTECLKVALID
K2 - TS0OUTDATA[4]
K3 ADAC_VCCAH TS0OUTDATA[5]
on
K4 PIO2[3] -
K5 GNDA2V5_DACS GND
K7 GND GNDA2V5_DACS
C
K8 GND -
K9 GND GND
K10 GND GND
K11 GND GND
K12 GND GND
K13 - GND
K14 PIO1[1] GND
K15 PIO1[2] GND
K16 PIO0[1] GND
K17 PIO0[0] GND
K18 PIO0[2] GND
K19 - GND
K21 - GND
K23 - GND
K25 - PIO0[1]
K26 - PIO0[2]
K27 - PIO0[0]
L1 TS0OUTERROR TS0INDATA[4]
L2 TS0INDATA[3] TS0INDATA[5]
L3 PIO2[4] TS0OUTDATA[3]
L4 PIO3[5] TS0INDATA[1]
Information classified Confidential - Do not copy (See last page for obligations)
L5 PIO3[6] -
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L6 - GND
L7 GND -
L8 GND GND
en
L9 GND GND
L10 GND GND
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L19 - GND
L20 - GND
L22 - GND
L24 - PIO1[1]
L25 - PIO1[4]
L26 - PIO1[3]
L27 - PIO1[2]
M2 TS0OUTDATA[7] TS0OUTDATA[2]
M3 TS0OUTDATA[6] TS0OUTBITORBYTECLK
M4 TS0INDATA[2] TS0INDATA[6]
M5 GND GND
M7 GND GND
M8 GND -
M9 GND -
M10 GND GND
M11 GND GND
M12 GNDA1V0_FE GND
M13 - GND
M14 NOTASEBRK GND
M15 NOT_RESET GND
M16 AUXCLKOUT GND
Information classified Confidential - Do not copy (See last page for obligations)
M17 - GND
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M18 - GND
M19 - -
M21 - GND
en
M23 - DNC
M24 - AUXCLKOUT
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M25 - NOT_RESET
fid
M26 - PIO1[5]
N3 TS0OUTDATA[4] TS0INDATA[7]
N4 TS0OUTDATA[5] TS0OUTPACKETCLK
N5 TS0OUTBITORBYTECLKVALID -
on
N6 - GND
N8 - GND
N9 - GND
C
N10 - GND
N11 - GND
N12 - GND
N13 - GND
N14 GNDA2V5_FE GND
N15 PIO2[1] GND
N16 PIO2[0] GND
N17 - GND
N18 - GND
N19 - GND
N20 - GND
N22 - GND
N24 - PIO2[0]
N25 - NOTASEBRK
P3 TS0INDATA[1] -
P4 TS0INDATA[4] TS0OUTDATA[0]
P5 TS0OUTDATA[2] TS0OUTDATA[1]
P6 DNC -
P7 USB_DATA[3] GND
P8 VDD1V0 -
P9 VDD1V0 GND
Information classified Confidential - Do not copy (See last page for obligations)
P10 VDD1V0 GND
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P11 VDD1V0 GND
P12 DNC GND
P13 VDDA2V5_BE GND
en
P14 QPSK_AGC GND
P15 PIO1[0] GND
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P23 - PIO2[5]
P24 - PIO2[1]
R2 TS0OUTDATA[3] -
C
R3 TS0INDATA[5] TS0INERROR
R4 TS0INDATA[0] TS0INDATA[0]
R5 USB_DIR -
R6 USB_DATA[1] GND
R7 USB_DATA[4] -
R8 USB_DATA[7] GND
R9 SPI_NOTCS GND
R10 VDD1V0 GND
R11 VDD1V0 GND
R12 VBASE GND
R13 DISEQCOUT GND
R14 VCCA2V5_FE GND
R15 QPSK_DAC GND
Information classified Confidential - Do not copy (See last page for obligations)
T1 TS0INDATA[6] -
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T2 TS0OUTBITORBYTECLK TS0INBITORBYTECLK
T3 TS0INDATA[7] TS0INPACKETCLK
T4 TS0INBITORBYTECLK TS0INBITORBYTECLKVALID
en
T5 USB_DATA[0] GND
T6 USB_DATA[2] -
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T7 USB_CLK GND
fid
T8 USB_DATA[5] -
T9 SPI_CLK -
T10 VDD1V0 GND
T11 VDD1V0 GND
on
T15 QP GND
T16 TMS GND
T17 NOT_TRST GND
T18 TCK GND
T19 - -
T21 - GNDA2V5_PLL_FS_BE
T23 - GND
T24 - PIO2[6]
T25 - PIO2[7]
T26 - PIO3[0]
U1 TS0OUTPACKETCLK CSn[3]
U2 TS0OUTDATA[1] CSn[2]
U3 TS0INBITORBYTECLKVALID CSn[1]
U4 USB_STP RBn[1]
U5 USB_NXT -
U6 - GND
U8 USB_DATA[6] GND
U9 SPI_DATAIN GND
U10 - GND
U11 VDD10REG GND
U12 QPSK_SDAT GND
Information classified Confidential - Do not copy (See last page for obligations)
U13 - GND
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U14 - GND
U15 QM GND
U16 IM GND
en
U17 XTALI GND
U18 TDI GND
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U19 - GND
fid
U20 - GNDA2V5_PLL_FS_BE
U22 - GNDA2V5_PLL_FS_BE
U24 - TMS
U25 - TCK
on
U26 - NOT_TRST
U27 - TDI
V1 TS0OUTDATA[0] RBn[2]
C
V2 TS0INERROR RBn[3]
V3 TS0INPACKETCLK NOT_FMICSB
V4 RESETEXTOUT -
V5 - GND
V7 - GND
V9 SPI_DATAOUT GND
V10 - GND
V11 VDDA1V0_FE GND
V12 - GND
V13 - GND
V14 - GND
V15 - GND
V16 IP GND
Information classified Confidential - Do not copy (See last page for obligations)
W2 - NOT_FMICSC
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W3 NOT_FMICSD
W4 - FMIADDR[23]
W6 - GND
en
W8 - GND
W9 - GND
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W10 - GND
fid
W11 - GND
W12 - -
W13 - GND
W14 - GND
on
W15 - GND
W16 - -
W17 - GND
C
W18 - GND
W19 - GND
W20 - VDD1V0
W22 - VDD1V0
W24 - VDD1V0
W25 - VDD1V0
W26 - VDD1V0
Y3 - FMIADDR[21]
Y4 - FMIADDR[22]
Y5 - FMIADDR[5]
Y7 - GND
Y9 - GND
Y11 - GND
Y13 - GND
Y15 - GND
Y17 - GND
Y19 - VDD10REG
Y21 - VDD1V0
Y23 - VDD1V0
Y24 - VDD1V0
Y25 - VDD1V0
Information classified Confidential - Do not copy (See last page for obligations)
AA4 - FMIADDR[3]
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AA5 - FMIADDR[7]
AA6 - GND
AA8 - GND
en
AA10 - GND
AA12 - GND
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AA14 - GND
fid
AA16 - GND
AA18 - GND
AA20 - VBASE
AA22 - GNDA1V0_FE
on
AA23 - GNDA1V0_FE
AA24 - VDDA1V0_FE
AB4 - FMIADDR[20]
C
AB5 - FMIADDR[17]
AB6 - GND
AB7 - GND
AB9 - GND
AB11 - GND
AB13 - GND
AB15 - GND
AB17 - GND
AB19 - GND
AB21 - GND
AB22 - GNDA1V0_FE
AB23 - GNDA1V0_FE
AB24 - VCCA2V5_FE
AB25 - VCCA2V5_FE
AC3 - FMIADDR[8]
AC4 - FMIADDR[6]
AC5 - NOT_FMICSA
AC6 - NOT_FMIBE[1]
AC7 - NOT_FMIOE
AC8 - GND
AC10 - GND
Information classified Confidential - Do not copy (See last page for obligations)
AC12 - GND
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AC14 - NAND_WAIT
AC16 - GND
AC18 - GND
en
AC20 - DNC
AC21 - QPSK_SDAT
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AC22 - GND
fid
AC23 - QPSK_AGC
AC24 - VCCA2V5_FE
AC25 - GNDA2V5_FE
AC26 - GNDA2V5_FE
on
AD2 - FMIADDR[4]
AD3 - FMIADDR[18]
AD4 - FMIADDR[19]
C
AD5 - FMIADDR[2]
AD6 - FMIADDR[1]
AD7 - NOT_FMIBE[0]
AD8 - FMIDATA[14]
AD9 - FMIFLASHCLK
AD11 - FMIDATA[3]
AD12 - FMIDATA[9]
AD13 - FMIDATA[8]
AD14 - NOT_FMIBAA
AD15 - RESETEXTOUT
AD16 - USB_DIR
AD17 - USB_CLK
AD19 - SPI_DATAOUT
AD20 - SPI_NOTCS
AD21 - DISEQCOUT
AD22 - QPSK_SCLT
AD23 - QPSK_DAC
AD24 - DNC
AD25 - GNDA2V5_FE
AD26 - GNDA2V5_FE
AD27 - XTALO
Information classified Confidential - Do not copy (See last page for obligations)
AE1 - NOT_FMILBA
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AE2 - FMIWAIT
AE3 - FMIRDNOTWR
AE4 - FMIADDR[14]
en
AE5 - FMIADDR[12]
AE6 - FMIADDR[16]
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AE8 - FMIDATA[7]
fid
AE9 - FMIDATA[15]
AE10 - FMIDATA[12]
AE11 - FMIDATA[11]
AE12 - FMIDATA[10]
on
AE13 - FMIDATA[0]
AE15 - USB_STP
AE16 - USB_NXT
C
AE17 - USB_DATA[1]
AE18 - USB_DATA[6]
AE19 - SPI_DATAIN
AE20 - SPI_CLK
AE23 - DNC
AE24 - QM
AE25 - DISEQCIN
AE26 - GND
AE27 - XTALI
AF1 - VDD33
AF2 - VDD33
AF3 - FMIADDR[10]
AF4 - FMIADDR[13]
AF5 - FMIADDR[15]
AF9 - FMIDATA[6]
AF10 - FMIDATA[13]
AF11 - FMIDATA[4]
AF12 - FMIDATA[1]
AF16 - USB_DATA[0]
AF17 - USB_DATA[2]
AF18 - USB_DATA[5]
Information classified Confidential - Do not copy (See last page for obligations)
AF19 - USB_DATA[7]
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AF24 - QP
AF25 - IM
AF26 - GND
en
AF27 - GND
AG1 - VDD33
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AG2 - VDD33
fid
AG3 - FMIADDR[9]
AG4 - FMIADDR[11]
AG10 - FMIDATA[5]
AG11 - FMIDATA[2]
on
AG17 - USB_DATA[3]
AG18 - USB_DATA[4]
AG25 - IP
C
AG26 - GND
AG27 - GND
9 Connections
VDD33_25 LMI supply, 2V5/3V3 C1, C2, C3, C4 B9, C9, D9, E10, F11, G12
AF1, AF2, AG1, AG2, C8, D7,
VDD33 3V3 I/O supply D1, D2, D3, D4, E4, E5 D8, E7, E8, F7, F9, G8, G10,
H9
Information classified Confidential - Do not copy (See last page for obligations)
A26, A27, B26, B27, E12, E16,
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E18, E20, F6, F13, F15, F17,
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F19, F21, F22, G6, G14, G16,
G18, G20, G22, H5, H11, H13,
H15, H17, H19, H21, J9, J10,
J11, J13, J14, J15, J17, J18,
en
J19, J20, J22, K5, K9, K10,
K11, K12, K13, K14, K15, K16,
K17, K18, K19, K21, K23, L6,
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Information classified Confidential - Do not copy (See last page for obligations)
and analog T10, T11 Y21, Y23, Y24, Y25
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Common supply for
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VDDA1V0_FE AD12, FEOSC, V11 AA24
FEPLL
On-chip voltage
VDD10REG U11 Y19
regulator
en
Ground for the 2.5 V
GNDA2V5_FE supply of the N14 AC25, AC26, AD25, AD26
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front-end
Common supply for
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9.2 System
Some system functions use GPIO pins, which are shared with other functions. For further
C
9.3 Interrupts
Some interrupt functions use GPIO pins, which are shared with other functions. For further
details, see Table 41.
EXTINT[0] Interrupt from/to external device I/O PIO3[0] (Alt 1) R16 T26
EXTINT[1] Interrupt from/to external device I/O PIO3[4] (Alt 1) H14 G24
EXTINT[2] Interrupt from external device I PIO3[1] B1 E5
Information classified Confidential - Do not copy (See last page for obligations)
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9.4 Demodulator IF interface
Table 15. Demodulator functions
Signal Ball (15 mm x 15 mm Ball (23 mm x 23 mm
en
Description I/O Type
name package) package)
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9.8 Transport
Some transport functions use GPIO pins, which are shared with other functions. For further
Information classified Confidential - Do not copy (See last page for obligations)
details, see Table 41.
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Table 19. Transport functions
Ball Ball
(15 mm x 15 (23 mm x 23
Signal name Description Dir Type
en
mm mm
package) package)
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Information classified Confidential - Do not copy (See last page for obligations)
data bit for TS0
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Parallel interface output
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TS0OUTDATA[4] O Digital Schmitt N3 K2
data bit for TS0
Parallel interface output
TS0OUTDATA[5] O Digital Schmitt N4 K3
data bit for TS0
en
Parallel interface output
TS0OUTDATA[6] O Digital Schmitt M3 J2
data bit for TS0
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Information classified Confidential - Do not copy (See last page for obligations)
FMIADDR[4] O 4 mA Digital AD2
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FMIADDR[5] O 4 mA Digital Y5
FMIADDR[6] O 4 mA Digital AC4
FMIADDR[7] O 4 mA Digital AA5
en
FMIADDR[8] O 4 mA Digital AC3
FMIADDR[9] O 4 mA Digital AG3
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Information classified Confidential - Do not copy (See last page for obligations)
FMIDATA[6] IO 4 mA Digital AF9
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FMIDATA[7] IO 4 mA Digital AE8
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Data
FMIDATA[8] IO 4 mA Digital AD13
FMIDATA[9] IO 4 mA Digital AD12
FMIDATA[10] IO 4 mA Digital AE12
en
FMIDATA[11] IO 4 mA Digital AE11
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Information classified Confidential - Do not copy (See last page for obligations)
RBn[3] Ready not busy for fourth I 4 mA Digital V2
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device in the flex mode
9.11 tia
Local memory interface (LMI)
en
The LMI supports four memory configurations, 64 Mbits, 128 Mbits, 256 Mbits or 512 Mbits,
organized as 2 Mbytes x 4 banks x 16 bits. The 128 Mbit configuration uses all signals on
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the interface, with the LMI’s LMIADDR[11:0] pins being directly connected to DDR SDRAM’s
A[11:0]. For 256 Mbits and 512 Mbits configurations, LMIADDR12 is also connected to the
DDR SDRAM’s A12 bit. Only one device can be connected to a board, operating in SSTL
fid
weak mode.
Ball Ball
(15 mm x 15 (23 mm x 23
Signal name Description I/O Drive Type
mm mm
package) package)
Information classified Confidential - Do not copy (See last page for obligations)
LMIDQS[1] Data strobe O Programmable Digital B10 C17
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ReadNotWrite
LMIRDNOTWR O Programmable Digital C15 D22
enable
Input reference
LMIVREF I - Analog B11 A17
voltage
en
NOT_LMICAS Col address strobe O Programmable Digital A16 C22
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9.12 Audio
Table 23. Audio functions
Ball Ball
Signal name Description I/O Type (15 mm x 15 mm (23 mm x 23 mm
package) package)
Information classified Confidential - Do not copy (See last page for obligations)
SPDIF IEC60958/61937 digital audio output O Digital H15 H23
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9.13
Table 24.
Video
Video functions
tia
en
Ball Ball
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Information classified Confidential - Do not copy (See last page for obligations)
Signal name Description I/O Type (15 mm x 15 mm (23 mm x 23 mm
l
package) package)
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SPI_CLK SPI clock output to Serial Flash O Digital T9 AE20
SPI_DATAIN SPI data input from Serial Flash I Digital U9 AE19
SPI_DATAOUT SPI data output to Serial Flash O Digital V9 AD19
en
SPI_NOTCS SPI chip select output to Serial Flash O Digital R9 AD20
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All infrared interface functions use GPIO pins, which are shared with other functions. For
further details, see Table 41.
on
Information classified Confidential - Do not copy (See last page for obligations)
USB_DATA[3] - - I/O P7 AG17
Data bus
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USB_DATA[4] - - I/O R7 AG18
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USB_DATA[5] - - I/O T8 AF18
USB_DATA[6] - - I/O U8 AE18
USB_DATA[7] - - I/O R8 AF19
en
USB_NXT 1 1 Next data I/O U5 AE16
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Information classified Confidential - Do not copy (See last page for obligations)
l
The details of the pins and the proposed sharing are given in the following table:
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Table 31. Ethernet functions
Ball
Ethernet Ball
Ethernet function (23 mm x 23
en
function TS function Range RMII Pins I/O (15 mm x 15
description mm
(MII) mm package)
package)
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TS0OUTBITORBYTE AC presenting
TX_EN 1 Y 1 O N5 K1
CLKVALID nibbles on MII for Tx
Data signals driven M2, M3, N4, J3, J2, K3,
TXD[3:0] TS0OUTDATA [7:4] [1:0] 4 O
by the mac N3 K2
on
Information classified Confidential - Do not copy (See last page for obligations)
COL TS0INDATA [2] - 1 detection of a I M4 J4
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collision
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Timing reference for
TXCLK TS0INDATA [1] - 1 I P3 L4
TX_EN and TXD
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9.20 Smartcard
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All smartcard functions use GPIO pins, which are shared with other functions. For further
details, see Table 41.
fid
mm package) package)
PIO4[0]
SC1_DATAINOUT/ASC1_TXD ASC1 receive/transmit data I/O G16 E25
(Alt 2)
PIO4[1](
SC1_DATAIN/ ASC1_RXD ASC1 receive data I F15 E23
Alt 2)
PIO4[7]
SC1_DETECT Smartcard1 detect I D17 C25
(Alt 2)
PIO4[6](
SC1_DIR Smartcard1 direction O D16 C27
Alt 2)
Information classified Confidential - Do not copy (See last page for obligations)
PIO4[4]
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SC1_RESET Smartcard1 reset O E16 D24
(Alt 2)
9.21 tia
Asynchronous serial controller (ASC)
en
There are four ASCs available. The ASC0 and ASC1 are smartcard capable.
All ASC functions use GPIO pins, which are shared with other functions. For further details,
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Information classified Confidential - Do not copy (See last page for obligations)
● SSC1 interface is proposed for the connection to the tuner. The configuration bit
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CFG_CTRL_K[27] has to be set to 1, allowing the SSC1 interface to be routed to
QPSK_SCLT and QPSK_SDAT pads. While it could be possible to connect any other
I2C controlled device to the same line, this is not recommendable due to the possible
tuner sensibility to noises.
● SSC2 interface is available at PIO3[3:2] pads.
en
The SSC0 and SSC2 functions use GPIO pins, which are shared with other functions. For
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m package) package)
9.23 Debug
Table 35. Debug functions
Ball Ball
Signal name Description I/O Type (15 mm x 15 mm (23 mm x 23 mm
package) package)
Information classified Confidential - Do not copy (See last page for obligations)
TAP boundary scan - test data
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TDO O Digital V18 V27
output - decoder
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TAP boundary scan - test mode
TMS I Digital T16 U24
select - decoder
NOTASEBRK ST40 debug I/O Digital M14 N25
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Figure 11. Recommended connections
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VCC 3.3 V
10kΩ
fid
NOT_TRST
TRIGOUT0 TRIGGERIN
TRIGIN TRIGGEROUT
NOT_RST NOTRESETIN
C
Board 10kΩ
power-on reset
Target board
Note: If there is a lot of noise on the clock line, a capacitor in the range from 10 pF to 100 pF can
be fitted between TCK and ground near the target STi5189.
Information classified Confidential - Do not copy (See last page for obligations)
PIO0[2] IO 4 mA Digital K18 K26
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PIO0[3] Programmable I/O IO 4 mA Digital J15 J26
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bank 0 decoder
PIO0[4] section IO 4 mA Digital H16 J24
PIO0[5] IO 4 mA Digital H18 H25
PIO0[6] IO 4 mA Digital H17 H24
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PIO0[7] IO 4 mA Digital J16 J25
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Digital -
PIO3[0] IO 4 mA R16 T26
I2C
Digital -
PIO3[1] IO 4 mA B1 E5
I2C
Digital -
PIO3[2] IO 4 mA G14 F24
Programmable I/O I2C
bank 3 decoder Digital -
PIO3[3] section IO 4 mA G15 G23
I2C
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PIO3[4] IO 4 mA Digital H14 G24
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PIO3[5] IO 4 mA Digital L4 G4
PIO3[6] IO 4 mA Digital L5 G5
PIO3[7] IO 4 mA Digital G17 E24
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Digital -
PIO4[0] IO 4 mA G16 E25
I2C
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Digital -
PIO4[1] IO 4 mA F15 E23
I2C
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Digital -
PIO4[2] IO 4 mA F16 D25
Programmable I/O I2C
bank 4 decoder Digital -
PIO4[3] section IO 4 mA E14 D26
I2C
on
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Pin
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Push-pull
tri-state
weak pull-up
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Alternative function Alternative function input
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1 0
Alternative function output
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Table 37 to Table 41 show the mapping of the alternative functions. Unless otherwise stated,
the default after reset for alternative functions is the PIO port or pin function.
The alternative configurations are set using the PIOn_ALTFOP_MUX_SEL_BUS [7:0] bits in
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the CFG_CTRL_F (PIO0 and PIO1), CFG_CTRL_G (PIO2 and PIO3) and CFG_CTRL_O
(PIO4) top-level configuration registers.
Configured by
pio0_altfop_mux_sel_bus1<7:0>
pio0_altfop_mux_sel_bus0<7:0>
00 = Alt0, 01 = Alt1, 10 = Alt2, 11= Alt3
K17 K27 0 SC0_DATAOUT/ASC0_TXD O - - - -
K16 K25 1 SC0_DATAIN/ASC0_RXD I General- - - - -
I/O
K18 K26 2 SC0_CG_EXTCLK I purpose I/O - - - -
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J15 J26 3 SC0_CG_CLK O CLK_SC O - -
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H16 J24 4 SYSRV_SC_RESET_0 O - - ASC0_RTS O - -
H18 H25 5 SYSRV_SC_POWER_0 O - - ASC0_CTS I - -
H17 H24 6 SC0_DIR/ASC0_NOTOE - - - - - - -
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J16 J25 7 SYSRV_SC_DETECT_0 I - - - - - -
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Configured by
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pio1_altfop_mux_sel_bus1<7:0>
pio1_altfop_mux_sel_bus0<7:0>
00 = Alt0, 01 = Alt1, 10 = Alt2, 11= Alt3
General-
P15 R25 0 - - I/O FDMA_REQ_0 I - -
purpose I/O(1)
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General-
K14 L24 1 - B I/O FDMA_REQ_1 I - -
purpose I/O(1)
General-
K15 L27 2 I/O ASC2_TXD O TVO_DENC_CFC I - -
purpose I/O
General-
L17 L26 3 I/O ASC2_RXD I PIXCLK_FROM_PAD I - -
purpose I/O
General-
L15 L25 4 I/O ASC2_RTS O HSYNC_FROM_PAD I - -
purpose I/O
General- VSYNC_FROM_PAD/
L16 M26 5 I/O ASC2_CTS I I/O - -
purpose I/O CLK_27_FROM_PAD
General- SSC0_SERIAL_CLOC
B2 D6 6 - I I/O B - -
purpose I/O(1) KINOUT(1)
General- SSC0_SERIAL_DATAI
A1 E6 7 - B I/O B - -
purpose I/O(1) NOUT_MTSR
1. If CFG_CTRL_M[14] = 1, SSC0 will be used for SPI transactions.
Configured by
pio2_altfop_mux_sel_bus1<7:0>
pio2_altfop_mux_sel_bus0<7:0>
00 = Alt0, 01 = Alt1, 10 = Alt2, 11= Alt3
General- PCM_DATAOU
N16 N24 0 I/O ASC3_TXD O - - -
purpose I/O T
General- PCM_LRCLKO
N15 P24 1 I/O ASC3_RXD I - - -
Information classified Confidential - Do not copy (See last page for obligations)
purpose I/O UT
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General- PCM_SCLKOU
P17 R24 2 I/O ASC3_CTS I - - -
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purpose I/O T
General-
purpose I/O/
K4 F4 3 PWM_CAPTURE[0] I PCM_MCLK - - -
I/O/DVBCI_RE O
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SET
General-
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purpose
L3 F3 4 I/O/I PWM_OUT[0] O PCM_SCLK - - -
I/O/DVBCI_CD
1
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General-
P16 P23 5 I/O ASC3_RTS O IRB_PPM_IN I - -
purpose I/O
General-
R17 T24 6 I/O IRB_UHF_IN I PCM_DATAIN - - -
on
purpose I/O
General- IRB_PPM_OUT/FP
R18 T25 7 I/O O/I PCM_LRCLKIN - - -
purpose I/O RESET (long time)
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Configured by
pio3_altfop_mux_sel_bus1<7:0>
pio3_altfop_mux_sel_bus0<7:0>
00 = Alt0, 01 = Alt1, 10 = Alt2, 11= Alt3
General-
R16 T26 0 I/O EXTINT0 I/O PAD_VSYNC O - -
purpose I/O
General- FDMA_REQ_TOP
B1 E5 1 I/O EXTINT2 I O - -
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purpose I/O AD[0]
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General- SSC2_MTSR_ FDMA_REQ_TOP
G14 F24 2 I/O B O - -
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purpose I/O DINOUT AD[1]
General- SSC2_SCLKI
G15 G23 3 I/O B PAD_VSYNC_EN O - -
purpose I/O NOUT
General-
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H14 G24 4 I/O EXTINT1 I/O PAD_HSYNC O - -
purpose I/O
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General-
purpose
L4 G4 5 I/O - - PAD_HSYNC_EN O - -
I/O/DVBCI_BU
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S_REQ
General-
purpose
L5 G5 6 I/O - - - - - -
I/O/DVBCI_BU
on
S_GNT
General-
G17 E24 7 I/O DVO CLK O - O - -
purpose I/O
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Configured by
pio4_altfop_mux_sel_bus1<7:0>
pio4_altfop_mux_sel_bus0<7:0>
00 = alt0, 01 = alt1, 10 = alt2, 11= alt3
SC1_DATAINOUT/
G16 E25 0 DVO_DATA[0] O - - B - -
ASC1_TXD
General-
F15 E23 1 DVO_DATA[1] O I/O ASC1_RXD I - -
purpose I/O
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SC1_CG_EXTCL
F16 D25 2 DVO_DATA[2] O - - I/O - -
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K/ASC1_RTS
E14 D26 3 DVO_DATA[3] O ASC1_CTS I/O SC1_CG_CLK O - B
E16 D24 4 DVO_DATA[4] O - - SC1_RESET O - -
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General- SC1_COMD_VCC
E15 C26 5 DVO_DATA[5] O I/O O - -
purpose I/O (SC1_POWER)
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General- SC1_DIR/ASC1N
D16 C27 6 DVO_DATA[6] O I/O O - -
purpose I/O OTOE
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General-
D17 C25 7 DVO_DATA[7] O I/O SC1_DETECT I - -
purpose I/O
on
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10 Mode pins
The mode pins are a group of signals configured in the input mode, and are dedicated to
capture values during the power-on-reset sequence that are used to configure certain
defined functionalities.
The mode pins are captured at the rising-edge of the RST_N signal during the reset phase,
and are made available to the system to define operating modes, mainly boot mode
configuration. The mapping of the mode pins is given in Table 42.
The mode pins are applicable for the 23 mm x 23 mm package (since they use FMI balls)
and mainly affect how and from where the device boots. The mode pins must be pulled high
or low externally to define the correct functionality even if there is only one valid setting. For
Information classified Confidential - Do not copy (See last page for obligations)
the 15 mm x 15 mm package there are no mode pins and the reset behavior of the STi5189
is fixed to boot from Serial Flash without stretch mode reset. Other settings are not relevant
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for the 15 mm x 15 mm package.
Table 42.
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Mode pins - value latched at reset
Ball (23 mm x 23 mm 15 mm x 15 mm package
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Description
package) internal fixed setting
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Reset period
FMIADDR23 0: 200 ms stretch mode reset 1: Normal reset period
1: Normal reset period
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Boot mode
00: Parallel NOR Flash
01: NAND Flash
10: Serial Flash
FMIADDR[22:21] 10: Serial Flash
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11: Reserved
The boot mode can be forced to NAND Flash or Serial
Flash regardless of the mode pins settings by software
anti-fuse configuration.
NAND Flash address type
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Boot bank port size for parallel NOR Flash and NAND Boot from Serial Flash only;
FMIADDR2
Flash; must be pulled high (='1') not applicable
Boot bank port size for parallel NOR FLASH and NAND
Flash
0: 16 bits
1: 8 bits Boot from Serial Flash only;
FMIADDR1
not applicable.
Note that for NAND Flash, if 2 x 8 bit mode is used, the
boot mode should be configured for 8 bits. If 16-bit mode is
used, the boot mode should be configured for 16 bits
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Note: The 15 mm x 15 mm variant only supports the Serial Flash, which is activated by default.
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There is no need to control the mode pins in this version.
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on
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Asynchronous serial controller: UART2 0xFD13 2000
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Asynchronous serial controller: UART3 0xFD13 3000
Consumer electronics control (CEC) 0xFDE4 0000
Digital encoder 0xFD70 0000
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DVO 0xFD70 0600
Ethernet 0xFDE0 0000
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Information classified Confidential - Do not copy (See last page for obligations)
Synchronous serial controller: SSC2 0xFD14 2000
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System services 0xFDC0 0000
Transport stream merger and router registers 0xFDE2 0000
2-D blitter display engine 0xFD80 0000
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TVOut Teletext 0xFD70 0700
USB 0xFDD0 0000
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12 QPSK demodulator
12.1 Overview
The QPSK demodulator is a channel receiver for satellite television reception. It also
contains a forward error correction (FEC) unit with both an inner (Viterbi) and a outer (Reed-
Solomon) decoder and DiSEqC interface for flexible control of the outdoor unit.
The QPSK demodulator accepts 8-bit I and Q input signals. The FEC unit is compliant with
the DIRECTV® and DVB-S specifications. All processing is digital. The Reed–Solomon
decoder corrects up to eight erroneous bytes per packet.
A derotator, located before the Nyquist root filter, allows a wide range of offset tracking. The
high sampling rate facilitates the implementation of low-cost, direct conversion tuners.
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The QPSK demodulator is controlled through an internal I2C interface, allowing easy control
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of its functionalities. The I2C is also available outside the chip, through an internal repeater,
to control the tuner. This IP operates with a recommended 100 MHz and can process
variable modulation rates up to 50 Mbauds. The MPEG transport streams is internally
routed to the packet demultiplexer and MPEG decoder or it can be output to implement
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applications like the common interface.
The multi-standard capability associated with a broad range of input frequency operations
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makes it easy to use. Its low power consumption and low external component count makes
it perfect for all satellite applications.
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12.2 Architecture
Figure 13. QPSK subsystem main functions with needed analog IPs
diseqc_out
DiSEqC
diseqc_in 2.0 QPSK subsystem
DiSEqC manager
(agc)
QPSK
AGC1
demodulator
Cancellation
Dual
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[Qm, Qp] ADC Derotator interpolation AGC2
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Offset
filter
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Analog
Timing
recovery
loop
PLL Timing
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DCO
loop
Clock
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manager
SSC1 from comms
Slave
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I 2C LOCK
sdat manager
To tuner indicator and monitoring
sclt
on
ERROR
Transport stream
monitoring
manager
FEC
Energy Reed- Inner VITERBI
Solomon soft
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Transport stream SS
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5. The STi5189 acknowledges every byte transfer. The I2C controller puts the SDA line
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into high impedance after each byte transmitted and the STi5189 drives the line low to
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acknowledge reception.
1. The first byte gives the device master address plus the direction bit (R/W = 0).
2. The second byte contains the internal address of the first register to be accessed.
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4. The first byte gives the device master address plus the direction bit (R/W = 1).
5. The second byte is the first byte of data read out (The I2C controller is in high
impedance state and the STi5189 drives the SDA line).
6. Subsequent bytes are then read out until a STOP is reached.
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The I2C read and write modes are shown in the following figure:
Write registers 0 to 3 with AA, BB, CC, DD and I2C chip address D0
Start Device address, read D1 ACK Data read CC ACK Data read DD ACK Stop
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12.3.6 I2C bus repeater
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In some applications, signal interference generated by the SDA/SCL lines of the I2C bus
may significantly degrade the tuner performance. To avoid this problem, the STi5189 offers
an I2C bus repeater so the SDAT and SCLT lines are activated only when necessary and
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muted otherwise.
Both SDAT and SCLT pins are set to high impedance at reset. When the microprocessor
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writes 1 into register bit I2CRPT.I2CT_ON, the next I2C message on SDA and SCL is
repeated on the SDAT and SCLT pins, respectively. There are two options for controlling I2C
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To write to the tuner, the external microprocessor must perform the following sequence for
each tuner message:
1. Program 1 in I2CRPT.I2CT_ON to enable messages to be transferred from the main
I2C bus to the repeater.
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The stability is obtained by introducing a programmable delay in the SDA line. The delay
may also be introduced in the SCL line if necessary (though not for reasons of stability).
The delay function is controlled through register I2CRPT fields ENARPTLEVEL and
SCLTDELAY. ENARPTLEVEL sets the division ratio which controls the delay inserted on the
SDAT line. SCLTDELAY activates the same delay on the SCLT line; this makes the delay
equal on SDAT and SCLT but implements the delay with respect to the main I2C bus.
The condition for SDA line stability is:
Delay >= R x C x FMCLK/1613
C may be measured by a capacitance meter on the SDA I2C line (pF).
R is the total value of the pull up resistance (kOhms).
FMCLK is the master clock rate (100 MHz).
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Delay is defined in the ENARPTLEVEL field of the I2CRPT register (periods of FMCLK).
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Example R = 3 kOhms, C = 47 pF, FMCLK = 100 MHz.
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Delay >= 3 x 47 x 100/1613 = 8.74
Choose a delay close to 8.74 in this case 8, corresponding to ENARPT_LEVEL = 0b100
The maximum rate on the I2C bus is also fixed by ENARPTLEVEL, R, C and FMCLK.
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I2C max speed <= 1613/(4 x R x C) = 1613/(4 x 3 x 47) = 2.8 MHz, and
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I2C max speed <= FMCLK/(4 x Division_ratio value) = 100/(4 x 8) = 3.1 MHz
Thus the maximum speed allowed on the repeater bus is 2.8 MHz (the minimum of the two
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above equations).
In addition to the above, the START, ACK and STOP conditions must be respected.
START condition: SDA must fall 1/2 clock period prior to SCL falling.
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Data: 8-bit data are presented on SCL falling edge and read in (to the tuner) on SCL rising
edge.
ACK condition: A ninth SCL pulse with SDA set high Z is sent. The master then senses that
the line has been pulled low by the tuner to complete the acknowledge.
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STOP condition: SCL must rise 1/2 clock period prior to SDA rising.
If for any reason the master detects the SDA rising, whilst SCL is high, the transaction will
be aborted.
If not used for the I2C repeater, both SDAT and SCLT can be used as general-purpose
input / output ports.
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Two lower frequencies, F22FR and F22RX, from 22 kHz to 100 kHz, are needed for LNB
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control or DiSEqC control transmission and reception.
burst modulator
(DiSEqC[1:0]) 1/0
1/0
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In general the STi5189 is programmed using scripts and low level application (LLA) drivers
supplied by STMicroelectronics. The following description provides an aid to understanding
the register settings but does not replace the need to reference the application notes, LLA
drivers and scripts.
12.5.1 Demodulation
The demodulator block performs QPSK demodulation according to DIRECTV and DVB-S
specifications. This implementation is based on the STv0289B demodulator core and has
the following functions:
● automatic gain correction (AGC1)
● IQ DC offset corrections
● carrier frequency and phase acquisition and tracking
● symbol timing acquisition and tracking
AGC1
The input signal (from analog-to-digital converter) is initially conditioned by the RF AGC
stage.
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The modulus of the I and Q input is compared to a programmable threshold,
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m1 = 4.AGC1REF and the difference is integrated, the integrated value may be read in
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register AGC1IN.
This signal is converted into a pulse density modulation signal by a first order ΣΔ DAC which
drives the AGCRF output pin, it must be externally low pass filtered.
This controls the gain command of any amplifier preceding the signal path analog-to-digital
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converter. The AGC output stage is filtered by a simple analog filter.
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m1 value
-
Sqroot(I^2+Q^2) + ΣΔ DAC
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The output is a 3.3 V tolerant open drain or push pull stage, configurable through the bit
AGC_OPDRAIN.
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The coefficient βagc is programmable through the AGC1C register (AGCIQ_BETA field). The
reset value of AGCIQ_BETA allows an initial settling time of less than 100 k master clock
periods. TMCLK represents the period of the master clock (FMCLK).
Offset cancellation
This device suppresses the residual DC component on I and Q (bit ENA_ADJ in AGC1C
register). The compensation may be frozen to its last value by resetting the DC offset
compensation bit in AGC control register AGC1C at address 0x0E (bit AVERAGE_ON).
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of the AGC).
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Table 44. AGC2 coefficients
AGC2 coefficient BETA_AGC2
000 0
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001 1
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010 4
011 16
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100 64
101 256
110 NA
on
111 NA
If the AGC2 coefficient = 0, the gain remains unchanged from its last value.
The time constant is independent of the symbol frequency; however it does depend on the
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modulus, m1, of the input signal programmed in the AGC1REF register with the following
approximate relationship:
TAGC2 = {60 x 103 x TMCLK} / {AGC1REF x BETA_AGC2}
to have a symmetrical capture range. Reading RTFM and RTFL allows optimal trimming of
the timing range.
The actual symbol frequency is:
F M_CLK
F S_REG ⎛ 1 + T MG_REG --------⎞
1
F S = ------------------
20 ⎝ 19⎠
2 2
where FS_REG is the content of the symbol frequency register and TMG_REG the content of
the timing frequency registers (RTFM and RTFL).
Loop equation
The timing loop may be considered as a second order loop. The natural frequency and the
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damping factor may be calculated using the following formula:
FN = 1.849 x 10-6 x FS √(AGC2REF x β)
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where, FS is the symbol frequency, AGC2REF is the AGC2 reference level and β is
programmed by the timing control register: (RTC)
β = 2BETA_TMG
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The damping factor is:
ξ = {47.6 x10-3 x √AGC2REF x 2ALPHA_TMG} / √2BETA_TMG
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Table 45 shows the natural frequency in DVB-S, with nominal reference level
AGC2REF = 72, for different values of BETA_TMG and ALPHA_TMG without noise.
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Table 45. Natural frequency for different values of BETA_TMG and ALPHA_TMG
ALPHA_TMG 1 2 3 4 5
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The timing lock indicator is a function of the lock condition, but also of the current signal to
noise ratio. The timing lock parameters must be programmed as a function of the AGC2
reference level (rounded to the closest value):
● TH1 = 8.6 x AGC2REF
● TH2 = 29.8 x AGC2REF
● IND1MAX = 1.6 x AGC2REF
When the timing is locked, the indicator is positive; otherwise it is negative. The value needs
10 to 20 Ksymbols to stabilize.
In order to avoid wrong information, some hysteresis is provided by register THH:
● lock flag is set if timing lock indicator goes above THH
● lock flag is reset if timing lock indicator goes under -THH
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Recommended value is THH = 8.
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12.5.3 Carrier recovery and derotator loop
The tracking range of the derotator is ± FMCLK / 2 (± FSAMPLING/2). The initial frequency
search may therefore be performed on several MHz ranges without reprogramming the
tuner.
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Three phase detectors are selectable using software as follows:
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● Phase detector algorithm 1: this algorithm is used with QPSK reception, for initial
capture or for tracking with CNR > 6 dB.
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● Phase detector algorithm 2: for QPSK reception, it is used after locking, to minimize the
bit error rate in low channel noise conditions. Algorithm 2 is recommended in tracking
for most applications.
The loop is controlled through α and β parameters.
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The carrier loop control registers are at addresses 0x16 (ACLC alpha carrier), 0x17 (BCLC
beta carrier), 0x2B and 0x2C (CFRM and CFRL respectively, MSB and LSB carrier
frequency).
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Loop parameters
As for the timing loop, the carrier loop is a 2nd-order system where two parameters, α and
β, may be programmed with ALPHA and BETA, respectively. In QPSK, with high CNR the
natural frequency (FN) is:
FN = 2.485 x 10-6 x FMCLK √{(AGC2REF x β) x (FS / FMCLK)}
The damping factor is:
ξ = 7.807 x 10-6 x α √{(AGC2REF / β) x (FS / FMCLK)}
where α = (2 + a) x 211+alpha with 1 ≥ a ≥0 and β = (4 + c + d) x 2beta-1 with 1 ≥ d ≥ 0 and
1 ≥ c ≥ 0.
Derotator frequency
The derotator frequency can be either measured (read operation) or forced (write
operation).
(freq)kHz = Derot_freq / 216) x (FMCLK) kHz
The derotator frequency is a 16-bit signed value in registers CFRM (MSB at 0x2B) and
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CFRL (LSB at 0x2C).
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Carrier frequency offset detector
The carrier recovery loop features a carrier frequency offset detector. When the carrier
frequency offset detector is enabled, the central loop frequency is modified proportionally to
the carrier offset. The gain and time constants of the detector are set by register CFD bits
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BETA_FC and FDCT respectively. When the carrier loop is about to phase lock with the
carrier, the frequency detector stops automatically and the phase lock is ensured by the
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selected phase detector. This switchover point is determined by the threshold (CFD).
For stability reasons, the gain BETA_FC should not exceed the coefficient e of BCLC[5:2].
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I, Q symbol monitoring
The IQ symbol values presented to the FEC can be read out through registers ISYMB and
on
QSYMB. This allows a symbol diagram of the IQ symbols entering the FEC to be displayed
during debug.
The observation points are the following (see register SYMBCTRL):
● after offset cancellation
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12.5.4 Equalization
The DVB-S and DIRECTV modes benefit from an equalizer that compensates for reflections
in the co-axial cable between the LNB and the tuner. The equalizer employed may correct
for reflections over a maximum of five symbols and up to a return loss of 10 dB on the
antenna connectors. No adjustment or control is required by the user.
The equalizer can be enabled or disabled from register EQUA. The equalizer may reset from
that register. The equalizer tap values can be read from registers EQUAI1[5] and
EQUAQ1[5].
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The Viterbi decoder is controlled through the FECM register. Using this register, the Viterbi
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decoder can be switched between DVB-S and DIRECTV modes (bit FECMODE in register
FECM), a sync byte search can be de-activated and IQ swap can be enforced.
The FEC mode register FECM is at address 0x30.
In DVB-S and DIRECTV system modes, data is fed to the Viterbi decoder. Other parts of the
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decoding may be bypassed.
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At the input of the Viterbi decoder, a Kdiv gain, programmable in register VITPROG, may be
applied on I and Q for the calculation of the metrics.
The puncture rate and phase are estimated on the error rate basis. Several rates are
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allowed and may be enabled or disabled through register programming: the rates are 1/2,
2/3, 3/4, 5/6, 6/7, 7/8 in DIRECTV system or DVB-S.
For each enabled rate, the current error rate is compared to a programmable threshold. If it
is greater than this threshold, another phase (or another rate) is tried until the right rate is
obtained.
A programmable hysteresis is added to avoid losing the phase during short term
perturbations.
The rate may also be imposed by external software and the phase is incremented only upon
request by the microprocessor. The error rate may be read at any time.
The decoder is controlled through several Viterbi threshold registers: VTH12 (0x31), VTH23
(0x32), VTH34 (0x33), VTH56 (0x34), VTH67 (0x35) and VTH78 (0x36). For each Viterbi
threshold register, bits[6:0] represent an error rate threshold, the average number of errors
occurring during 256-bit periods.
The maximum programmable value is 127/256 (higher error rates are of no practical use).
The puncture rate register PR is at address 0x37. Synchronization is controlled through the
FECM (0x30) register. The automatic rate research is only performed through the enabled
rates (see the corresponding bit set in PR).
Note: In order to minimize the Viterbi search time, the puncture rates 3/4, 5/6, 7/8 may be disabled
in DIRECTV system. In DVB-S, the puncture rate 6/7 may be disabled.
Register VSEARCH is at address 0x38. Bits AM and F program the automatic/manual
(or computer aided) search mode as follows:
● If AM = 0 and F = 0, automatic mode is set. Successive enabled punctured rates are
tried with all possible phases until the system is locked and the block sync is found.
This is the default (reset) mode.
● If AM = 0 and F = 1, the current puncture rate is frozen. If no sync is found, the phase is
incremented, but not the rate number. This mode shortens recovery time under noisy
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conditions. The puncture rate is not supposed to change in a given channel. In a typical
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computer-aided implementation, the search begins in automatic mode. The
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microprocessor reads the error rate (VERROR) or flag PRF (VSTATUS) to detect the
capture of a signal, then it switches F to 1 until a new channel is requested by the
remote control.
● If AM = 1, manual mode is set. In this case, only one puncture rate should be validated.
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The system is forced to this rate on the current phase, ignoring bit TO (time-out in
VSEARCH) and the error rate. In this mode, each 0 to 1 transition of bit F leads to a
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The IQ symmetry may also be swapped either manually (in register FECM) or automatically
(SWAP_EN in register VITPROG). In that case the bit SYM of register FECM is a status of
the symmetry found.
on
Register VERROR (read only) is at address 0x2F. The last value of the error rate may be
read at any time in the register. Unlike the Viterbi threshold, the possible range is from 0 to
255/256.
Register VSTATUS (read only) is at address 0x24.
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Error monitoring
A 16-bit counter, ERRCNT, counts errors at different levels. ERRCNT is fed by one of the
following:
● the input QPSK bit errors (that are corrected by the Viterbi decoder)
● the bit
● the byte errors (that are corrected by the Reed–Solomon decoder)
● the packet error (not correctable, leading to a pulse at the ERROR output)
The content of ERRCNT may be transferred to the read only error-count registers ECNTM
(MSB at 0x26) and ECNTL (LSB at 0x27).
Two functional modes are proposed, depending on control register ERRCTRL (0x3B) bit[7]:
● ERRMODE = 0: error rate measurement. This provides the number of errors occurring
within a specified number of output bytes, NB. NB has four possible values defined by
bits NOE. Every NB bytes, the state of the error counter is transferred to the 16-bit
error-count registers and then the error counter is reset. The error-count registers may
be read by the microprocessor through the I2C bus. Two ways of reading may be used:
16-bit reading, starting with the MSB or 8-bit reading (LSB only or MSB only).
● ERRMODE = 1: the error counter just counts the errors and directly transfers the
content of the error counter. When the MSB byte is read, the error counter is reset.
In both modes, the 16-bit counter is saturated to its maximum value.
A second error monitor is added, with an identical control register ERRCTRL2 at address
0x3D, and the contents of ERRCNT2 may be transferred to ECNTM2 (0x3E) and ECNTL2
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(0x3F). With this second error monitor, two error rates may be simultaneously monitored, for
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example, QPSK bit error and packet error rate.
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Convolutive de-interleaver
In DVB-S, the convolutive de-interleaver is 17 x 12. The periodicity of 204 bytes per sync
byte is retained. In DIRECTV system, the convolutive de-interleaver is 146 x 13 and there is
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also a periodicity of 147 bytes per sync byte. The de-interleaver may be bypassed (RS 0x39
bit DEINT).
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The input blocks are 204 bytes long with 16 parity bytes in DVB-S. The sync byte is the first
byte of the block. Up to 8 byte errors may be fixed.
The code generator polynomial is:
g(x) = (x - ω0)(x - ω1)...(x - ω15)
on
x15 + x14 + 1
The polynomial is initialized every eight blocks with the sequence 100 1010 1000 0000.
The sync words are unscrambled and the scrambler is reset every eight packets.
Synchronization
In DVB-S, the packet length after inner decoding is 204. The sync word is the first byte of
each packet. Its value is 0x47, but this value is complemented every eight packets. In
DIRECTV system, the packet length is 147 and the sync word is 0x1D.
An up/down sync counter counts whenever a sync word is recognized with the correct timing
and counts down during each missing sync word. This counter is bounded by a
programmable maximum (bit H in VSEARCH register). When this value is reached, bit LK
(locked) is set in register VSTATUS. When the event counter counts down to 0, this flag is
reset.
The time-out period for this sync word search is selectable through register VSEARCH (bit
TO).
Information classified Confidential - Do not copy (See last page for obligations)
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Typical byte transfer loop
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1. DIS_PRECHARGE is set to 1 (DISEQC register) to put the transmitter into a waiting
state.
2. One to 16 bytes can be transferred by writing to the FIFO.
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3. DIS_PRECHARGE is set to 0 and the transmitter begins sending data.
4. To transfer more than 16 bytes, the FIFO must not be full: FIFOFULL = 0. Use the
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equation
number of bytes = 16 - TXFIFO_BYTES
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Transmit format
There are two modes for DiSEqC output; modulated and envelope. The mode is selectable
from register bit DISEQC.CMD_ENV. In the modulated mode the output is a gated 22 kHz
square wave signal. In the envelope mode, the tone is replaced by logic high, a logic low
replaces ‘no tone’.
When the modulation is active, the DiSEqC output is forced alternately to VDD and VSS
levels.
Byte format
● Idle state, no modulation is present at the output
● Byte transmission, the byte is sent (MSB first) and is followed by an odd parity bit.
A byte transmission is therefore a 9-bit serial transmission with an odd number of ones.
Each bit lasts 33 F22 periods and the transmission is PWM-modulated.
Transmission of ones
During transmission of ones, modulation is active for 11 pulses, then inactive for 22 pulses
(1/3 PWM).
Transmission of zeros
There are two submodes controlled by bits DISEQC.DISEQC_MODE.
● DISEQC_MODE = 10: modulation is active for 22 pulses, then inactive for 11 pulses
(2/3 PWM). This is the normal mode
● DISEQC_MODE = 11: modulation is active for 33 pulses (3/3 PWM). This is used for
SA, SB modes
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Idle 11 periods 11 periods 11 periods Next bit
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Transmission of ones
Transmission of zeros:
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a) DISEQC_MODE = 10
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b) DISEQC_MODE = 11
fid
Some extra commands have been designed to be detected by a cheaper analog circuit in
the case of a simple two-state switch. In this type of application where the slave IC would not
be used to provide any additional functionality (such as 13/17 V detection or continuous
22 kHz detection), tone burst commands are alternatives to the DiSEqC commands for the
C
Information classified Confidential - Do not copy (See last page for obligations)
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Envelope mode
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An envelope mode is available for all the previously described transmissions. For that, the
bit CMD_ENV must be activated in the DISEQC register. In the envelope mode, a 22 kHz
envelope output is generated instead of a modulated signal output. It may control the on/off
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switch of an external 22 kHz oscillator.
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This information is delivered by a flag in a status register. This flag is set at the beginning of
the transmission and is reset after a time that includes both the transmission and a period
defined by the I2C bus.
on
Possible
Tone burst new tone burst
C
Information classified Confidential - Do not copy (See last page for obligations)
To digital core + DISEQC_IN
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Vdd/2
- Down current 200 mV to 1 V
source control
5A
R 0: Hi-Z
1: Active
en
GND_DISRX
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fid
R
Hi-Z mode
Up current source control = 1
Down current source control = 0
GND_DISRX
The DiSEqC input may be selected through the PINSELECT (DISEQC2) bits to be the
DISEQC_IN pin or the GPIO0 pin (default). The input may be inverted (should the envelope
mode require it).
A test mode allows the DiSEqC Tx to be looped back into the Rx (accessible though bit
DISEQC2.ONECHIPTRX).
The received bytes are stacked in the receiver FIFO and can be read by access to the
DISEQCFIFO register. The status registers (DISRX_ST0, DISRX_ST1) provide information
concerning the state of the receiver:
● reception ended
● receiver active
● continuous tone detected
● 4 bytes ready for reading
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● FIFO empty
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● reception failed
● parity error detected
● wrong number of bits to make a byte detected
● FIFO overflow
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● number of bytes in FIFO
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In addition to the above, status registers are interrupt flags (in register DISEQC2):
● generate interrupt at end of receive block
fid
● generate interrupt if there are 8 or more bytes in the FIFO ready for reading
Automatic symbol rate search, signal acquisition and signal tracking are built into the
STi5189 using a simple state machine, controlled by I2C commands. This state machine
significantly reduces the required software and also decreases the duration of the
transponder acquisition. The result is simplified scanning software routines, full satellite
C
12.7.1 Control
The fast channel acquisition is performed in two steps. The first step, coarse autosearch,
enables the rough estimation of the QPSK carrier within a given RF bandwidth. The second
step, fine scan enables automatic lock to the previously estimated QPSK carrier. The timing
lock indicator indicates success, see Figure 23.
Hard
Coarse autoscan
Soft
Nothing found
Wait timeout (max. 15 ms)
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Adjust timing loop parameters
Adjust carrier loop parameters
Adjust fine parameters
Launch fine scan
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Fine scan
Center
fid
In this mode, the symbol frequency registers (SFRH, SFRM and SFRL) and carrier
frequency registers (CFRM and CFRL) are updated by a loop in order to reach the
approximate input baud rate and carrier position.
The coarse carrier frequency loop is controlled by the KC field in the COARP2 register as
follows:
● KC = 0: the carrier frequency is frozen
● KC = 1 to 4: the loop is active; the value KC = 4 gives the minimum time constant to
recover any carrier frequency up to +/- to Fadc / 2
Decreasing KC by one unit doubles the time constant and halves the variance on the carrier
frequency.
The coarse baud rate loop is controlled by the KS field in register COARP2 as follows:
● KS = 0: the symbol frequency is frozen
● KS = 1 to 4: the loop is active; the value KS = 4 gives the minimum time constant to
recover any symbol frequency up to Fadc / 2
Decreasing KS by one unit doubles the time constant and decreases the variance on the
symbol frequency rate.
The baud rate loop converges to a value close to the symbol frequency, depending on the
signal to noise ratio and on the roll off of the transmitter. It may be altered by changing the
value of the field KT in register COARP1.
KI in the ASCTRL register must be set to 2.
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the 15 MSB’s of the boundaries of the scanning. A mode bit (STOP_ON_FMIN,
STOP_ON_FMAX) selects the system behavior when a boundary is reached as follows:
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● If the bit is set, the scanning stops.
● If reset, the scanning is automatically reversed with the same step.
The scanning is automatically and definitively stopped when the timing lock flag,
TMG_LOCK in the TLIRM register is set.
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Channel centering
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After decoding a lock condition, which stops the symbol frequency scanning, the current
symbol frequency is obtained by a combination of the symbol frequency register and the
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timing register.
When the CENTER bit is set in the ASCTRL register and the timing lock indicator is set (see
Section : Timing lock indicator), an automatic process allows pulling the timing register close
to 0 by adjusting the symbol frequency register accordingly.
on
The adjusting speed is controlled by the scan step and the action stops when the residual
timing offset is under 61 ppm.
C
Register addresses are accessed through the I2C bus, controlled by the SSC, provided as
QPSKBaseAddress + offset
The QPSKBaseAddress is:
0xFD14 0000
It is in fact SSCBaseAddress.
.
Information classified Confidential - Do not copy (See last page for obligations)
0x00 ID Identification register page 111
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0x01 I2CRPT Serial bus repeater control register page 141
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0x02 ACR Auxiliary clock register page 142
0x03 F22FR F22 transmit frequency register page 115
0x04 F22RX F22 receive frequency register page 116
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0x05 DISEQC DiSEqC control register 1 page 111
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Information classified Confidential - Do not copy (See last page for obligations)
0x25 LDI Carrier lock detect register page 123
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0x26 ECNTM Error 1 count register (MSB) page 138
0x27 ECNTL Error 1 count register (LSB) page 139
0x28 SFRH symbol frequency register (HSB) page 119
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0x29 SFRM symbol frequency register (MSB) page 119
0x2A SFRL symbol frequency register (LSB) page 119
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Information classified Confidential - Do not copy (See last page for obligations)
0x50 ASCTRL Autoscan control register page 151
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0x51 COARP1 Coarse1 control register page 151
0x52 COARP2 Coarse2 control register page 152
0x53 FMINM FMIN register (MSB) page 152
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0x54 FMINL FMIN register (LSB) page 152
0x55 FMAXM FMAX register (MSB) page 153
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ID Identification register
7 6 5 4 3 2 1 0
CHIP_IDENT RELEASE
Information classified Confidential - Do not copy (See last page for obligations)
Address: QPSKBaseAddress + 0x00
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Type: R
Reset: 0x10
Description: Identification register. This register is accessible in standby mode. See also
Section 12.3.5: Identification register.
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DISEQCMODE
DIS_RESET
CMD_ENV
TIM_OFF
LOW_Z
PORT0
Information classified Confidential - Do not copy (See last page for obligations)
DISEQC2 DiSEqC control register 2
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7 6 5 4 3 2 1 0
IRQ_HALF_FIFO
RECEIVER_ON
ONESHIP_TRX
IRQ_RXEND
EXT_ENVEL
PINSELECT
RESERVED
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Reset: 0x00
Description: DiSEqC control register 2. See also Section 12.6: DiSEqC 2.x interface.
on
DISEQCFIFO
[7:0] DISEQCFIFO: DiSEqC transmitter FIFO or DiSEqC receiver FIFO 16 bytes deep.
Information classified Confidential - Do not copy (See last page for obligations)
DISEQCSTA1 DiSEqC transmitter status register 1
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7 6 5 4 3 2 1 0
Reset: 0x00
Description: DiSEqC transmitter status register 1. See also Section 12.6: DiSEqC 2.x interface.
fid
GAPBURST_FLAG
RESERVED
TIM_CMD
Address: QPSKBaseAddress + 0x08
Type: R/W
Reset: 0x04
Description: DiSEqC transmitter status register 2. See also Section 12.6: DiSEqC 2.x interface.
Information classified Confidential - Do not copy (See last page for obligations)
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[7:4] RESERVED: Must be programmed to zero.
[3:1] TIM_CMD[2:0]: Gap length, number of 22 kHz periods between successive bursts.
000: 330
001: 440
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010: 550
011: 660
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100: 1320
101: 1760
110: 2200
fid
111: 2640
[0] GAPBURST_FLAG: Status. When active, Tx gap (as programmed in <TIM_CMD>) has not yet
expired.
on
ABORT_DIS
RX_ACTIVE
8BFIFORDY
RESERVED
RX_END
Information classified Confidential - Do not copy (See last page for obligations)
RX_FAIL PARITY_FAIL FIFO_OVER FIFO_BYTENBR
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Address: QPSKBaseAddress + 0x0B
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Type: R
Reset: 0x00
Description: DiSEqC receiver status register 2. See also Section 12.6: DiSEqC 2.x interface.
en
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7 6 5 4 3 2 1 0
FFTX_REG
FFRX_REG
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[7:0] FFRX_REG: Tone modulation frequency control.
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FDiSEqC_Rx = FMCLK / (32 x F22RXdec).
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For 22 kHz operation and FMCLK=100 MHz, F22RX = 142dec, 0x8Ehex.
control
7 6 5 4 3 2 1 0
fid
AGC_OPDRAIN
AVERAGE_ON
AGCIQ_BETA
ENA_DCADJ
IAGC
on
Description: AGC1 control register and DC offset compensation control. See also Section : AGC1.
[7] ENA_DCADJ:
1: DC offset compensation is ON.
[6] AVERAGE_ON:
0: DC offset compensation is frozen to its last value.
[5] AGC_OPDRAIN: Set AGCRF pad in open drain configuration.
0: Pushpull pad
1: OP drain pad
[4] IAGC: Inverted shape of AGCRF pin.
0: No inversion
1: Polarity is inverted
[3:0] AGCIQ_BETA[3:0]: Gain coefficient of AGC1.
AGC1REF
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AGC1IN AGC1 accumulator status register
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7 6 5 4 3 2 1 0
AGC1_VALUE
[7:0] AGC1_VALUE[7:0]: Integrated value of the difference between the modulus of I, Q input and
the programmable threshold m1 = 4.AGCREF. (unsigned value).
7 6 5 4 3 2 1 0
SERIAL_O_D0
RESERVED
OUTRS_HZ
C
ALPHA_TMG[3:0] BETA_TMG[3:0]
[7:4] ALPHA_TMG: Timing loop control, refer to timing recovery loop section for details.
Information classified Confidential - Do not copy (See last page for obligations)
[3:0] BETA_TMG: Timing loop control, refer to timing recovery loop section for details.
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RTFM Timing recovery control register
7 6 5 4 3 2 1 0
TIMING_LOOP_FREQ_MSB
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Address: QPSKBaseAddress + 0x22
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Type: R/W
Description: Timing recovery control register. See also Section : Timing control.
fid
7 6 5 4 3 2 1 0
TIMING_LOOP_FREQ_LSB
Type: R/W
Description: Timing recovery control register. See also Section : Timing control.
SYMB_FREQ_HSB
[7:0] SYMB_FREQ_HSB: Symbol frequency register (MSBs). The reset value corresponds to
FMCLK / 2.
Information classified Confidential - Do not copy (See last page for obligations)
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SFRM Timing recovery control register
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7 6 5 4 3 2 1 0
SYMB_FREQ_MSB
Reset: 0x00
Description: Timing recovery control register. See also Section : Timing control.
fid
SYMB_FREQ_LSB RESERVED
C
STEP1_MINUS STEP1_PLUS
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[3:0] STEP1_PLUS: Timing lock setting register. Must be programmed to 4.
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TLIRM Timing lock control register
7 6 5 4 3 2 1 0
Type: R
Description: Timing lock control register. See also Section : Timing lock indicator.
fid
7 6 5 4 3 2 1 0
TMG_FINAL_IND_LSB
RESERVED AGC2_COEFF
[7:3] RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
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[2:0] AGC2_COEFF[2:0]: Gain coefficient of AGC2.
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AGC2REF Post-Nyquist AGC reference control register
7 6 5 4 3 2 1 0
en
RESERVED AGC2_REF
Type: R/W
fid
Reset: 0x48
Description: Post-Nyquist AGC reference control register. See also Section : Nyquist root and
interpolation filters.
on
[7] RESERVED
[6:0] AGC2_REF[6:0]: Reference value of AGC2.
C
AGC2_INTEGRATOR_MSB
AGC2_INTEGRATOR_LSB
Information classified Confidential - Do not copy (See last page for obligations)
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CFD Carrier lock control register
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7 6 5 4 3 2 1 0
Reset: 0xF7
fid
Description: Carrier lock control register. See also Section : Carrier frequency offset detector.
[1:0] LDL[1:0]: Lock detector threshold to disable the carrier frequency offset detector.
00: -16
01: -32
10: -48
11: -64
LOCK_DET_INTEGR
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7 6 5 4 3 2 1 0
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LOCK_THRESHOLD
Description: Carrier lock control register. See also Section : Carrier lock detector.
fid
7 6 5 4 3 2 1 0
LOCK_THRESHOLD2
Reset: 0x00
Description: Carrier lock control register. See also Section : Carrier lock detector.
ALPHA
NOISE
ACLC
Information classified Confidential - Do not copy (See last page for obligations)
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[7] DEROT_ON_OFF: Derotator ON/OFF.
0: OFF
1: ON
[6] ACLC: ‘a’ coefficient for alpha = (2 + a) x 2b x 214
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[5:4] NOISE[1:0]: Noise estimator time constant.
00: 4 k symbols
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01: 16 k symbols
10: 64 k symbols
11: 256 k symbols
fid
7 6 5 4 3 2 1 0
ALGO BETA
Type: R/W
Reset: 0x58
Description: Carrier recovery control register. See also Section 12.5.3: Carrier recovery and
derotator loop.
CARRIER_FREQUENCY_MSB
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CFRL Carrier recovery frequency (LSBs) register
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7 6 5 4 3 2 1 0
CARRIER_FREQUENCY_LSB
7 6 5 4 3 2 1 0
NOISE_IND_MSB
Type: R
Description: Noise indicator (MSBs) register. See also Section 12.5.5: Noise indicator.
NOISE_IND_LSB
Information classified Confidential - Do not copy (See last page for obligations)
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7 6 5 4 3 2 1 0
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RESET_EQUA
MODE_COEF
RESERVED
RESERVED
EQUA_ON
en
Address: QPSKBaseAddress + 0x18
Type: R/W
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Reset: 0x13
fid
Description: Equalizer control and roll off control register. See also Section : Nyquist root and
interpolation filters.
1: Equalizer is ON.
[3] MODE_COEF: Nyquist filter roll-off factor.
0: Raised cosine at 35% (DVB-S)
1: Raised cosine at 20% (DIRECTV system)
[2:0] RESERVED: Must be set to 001.
EQUAI1
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EQUAQ1 Equalizer TAP 1 Q value
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7 6 5 4 3 2 1 0
EQUAQI
Reset: 0x00
Description: Equalizer TAP 1 Q value.
fid
7 6 5 4 3 2 1 0
EQUAI2
Type: R
Reset: 0x00
Description: Equalizer TAP 2 I value.
EQUAQ2
Information classified Confidential - Do not copy (See last page for obligations)
EQUAI3 Equalizer TAP 3 I value
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7 6 5 4 3 2 1 0
EQUAI3
Reset: 0x00
Description: Equalizer TAP 3 I value.
fid
7 6 5 4 3 2 1 0
EQUAQ3
Type: R
Reset: 0x00
Description: Equalizer TAP 3 Q value.
EQUAI4
Information classified Confidential - Do not copy (See last page for obligations)
EQUAQ4 Equalizer TAP 4 Q value
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7 6 5 4 3 2 1 0
EQUAQ4
Reset: 0x00
Description: Equalizer TAP 4 Q value.
fid
7 6 5 4 3 2 1 0
EQUAI5
Type: R
Reset: 0x00
Description: Equalizer TAP 5 I value.
EQUAQ5
Information classified Confidential - Do not copy (See last page for obligations)
VSTATUS Viterbi status register
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7 6 5 4 3 2 1 0
CF RESERVED PRF LK PR
Reset: 0x00
Description: Viterbi status register. This register is accessible in the standby mode. See also
fid
[7] CF: Carrier found flag. When CF (see Section : Carrier frequency offset detector) is set, a
QPSK signal is present at the input of the Viterbi decoder.
on
[3] LK: Locked/Searching sync word. LK indicates the state of the sync word search:
0 for searching and 1 when found.
[2:0] PR[2:0]: Current puncture rate. The current puncture rate (CPR) bits hold the current puncture
rate indices, as follows:
000: Punctured 1/2
001: Punctured 2/3
010: Punctured 3/4
011: Punctured 5/6
100: Punctured 6/7
101: Punctured 7/8
110: Reserved
111: Reserved
ERROR_VAL
[7:0] ERROR_VAL: (Not signed). Number of bits corrected by the Viterbi decoder per packet of
256 bits.
Information classified Confidential - Do not copy (See last page for obligations)
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FECM FEC mode register
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7 6 5 4 3 2 1 0
Reset: 0x00
fid
MDIV_MANT[4:2]
MDIV_MANT[1:0]
SWAP_ENABLE
MDIVIDER
Address: QPSKBaseAddress + 0x3C
Type: R/W
Reset: 0x80
Description: Viterbi metric control register. See also Section : Viterbi decoder and synchronization.
Information classified Confidential - Do not copy (See last page for obligations)
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[7:5] MDIV_MANT[4:2]: Viterbi coefficient mantissa MSBs.
[4] SWAP_ENABLE: Allow automatic research of IQ symmetry
[3:2] MDIV_MANT[1:0]: Viterbi coefficient mantissa LSBs.
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[1:0] MDIVIDER: Viterbi coefficient exponent. Selects division ratio at Viterbi decoder input:
Kdiv = MDIV_MANT[4:0] x 2 (MDIVIDER - 8)
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7 6 5 4 3 2 1 0
RESERVED VTH12
Type: R/W
Reset: 0x1E
Description: Viterbi 1/2 threshold register. See also Section : Viterbi decoder and synchronization.
C
RESERVED VTH23
Information classified Confidential - Do not copy (See last page for obligations)
[6:0] VTH23: Rate = 2/3 puncture rate threshold.
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VTH34 Viterbi 3/4 threshold register
7 6 5 4 3 2 1 0
RESERVED VTH34
en
Address: QPSKBaseAddress + 0x33
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Type: R/W
Reset: 0x0F
fid
Description: Viterbi 3/4 threshold register. See also Section : Viterbi decoder and synchronization.
7 6 5 4 3 2 1 0
RESERVED VTH56
RESERVED VTH67
Information classified Confidential - Do not copy (See last page for obligations)
[6:0] VTH67: Rate = 6/7 puncture rate threshold.
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VTH78 Viterbi 7/8 threshold register
7 6 5 4 3 2 1 0
RESERVED VTH78
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Address: QPSKBaseAddress + 0x36
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Type: R/W
Reset: 0x05
fid
Description: Viterbi 7/8 threshold register. See also Section : Viterbi decoder and synchronization.
Information classified Confidential - Do not copy (See last page for obligations)
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[7] AM:
0: Automatic search mode
1: Manual search mode
[6] F: Freeze
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[5:4] SN[1:0]: This is the averaging period. The field gives the number of bits required to calculate
the rate error.
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[1:0] H[1:0]: This is the hysteresis value. This field is used to program the maximum value of the
sync counter. The unit is the block duration (204 bytes in DVB-S, 147 in DIRECTV system).
00: 16 blocks
01: 32 blocks (reset value)
10: 64 blocks
11: 128 blocks
Information classified Confidential - Do not copy (See last page for obligations)
1: The input flow is de-interleaved.
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[6] OUTRS_PS: Output type.
0: Parallel output mode.
1: Serial output mode.
[5] RS: Reed-Solomon enable.
0: No correction happens, all the data is fed to the descrambler. The error signal remains
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inactive.
1: The input code is corrected.
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EN_STBACKEND
INV_DERROR
ENA8_LEVEL
INV_DSTART
INV_DVALID
Information classified Confidential - Do not copy (See last page for obligations)
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[7] INV_DVALID:
0: Normal mode.
1: DVALID is inverted.
[6] INV_DSTART:
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0: Normal mode.
1: DSTART is inverted.
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[5] INV_DERROR:
0: Normal mode.
1: DERROR is inverted.
fid
[3:0] ENA8_LEVEL: Reed–Solomon output FIFO clock division ratio, on CLK_OUT/byte clock
0000: Output FIFO disable.
Parallel mode: output clock period = ENA8_LEVEL x 4 x TM_CLK.
0001: 4 x TM_CLK
0010: 8 x TM_CLK
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0011: 12 x TM_CLK
0100: 16 x TM_CLK
...
1110: 56 x TM_CLK
1111: 60 x TM_CLK
Information classified Confidential - Do not copy (See last page for obligations)
1: Error count.
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[6] RESERVED: Must be programmed to zero.
[5:4] ERR_SOURCE: Error source. The error sources are as follows:
00: QPSK bit errors.
01: Viterbi bit errors.
10: Viterbi byte errors.
en
11: Packet errors.
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1: Counter reset.
[1:0] NOE: The NOE bits represent the count period in bytes (NB).
00: 212 bytes.
01: 214 bytes.
on
7 6 5 4 3 2 1 0
ERROR_COUNT_MSB
ERROR_COUNT_LSB
Information classified Confidential - Do not copy (See last page for obligations)
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7 6 5 4 3 2 1 0
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ERR_SOURCE2
RESET_CNT2
ERRMODE2
RESERVED
RESERVED
NOE2
en
Address: QPSKBaseAddress + 0x3D
Confidential
Type: R/W
Reset: 0x01
fid
0: Error rate.
1: Error count.
[6] RESERVED: Must be programmed to zero.
[5:4] ERR_SOURCE2[1:0]: Error source. The error sources are as follows:
C
ERROR_COUNT2_MSB
Information classified Confidential - Do not copy (See last page for obligations)
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7 6 5 4 3 2 1 0
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ERROR_COUNT2_LSB
ENARPT_LEVEL[2:0]
STOP_ENABLE
SDAT_VALUE
SCLT_VALUE
SCLT_DELAY
I2CT_ON
Information classified Confidential - Do not copy (See last page for obligations)
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Reset: 0x57
tia
Description: Serial bus repeater control register. This register is accessible in the standby mode.
See also Section 12.3.6: I2C bus repeater.
en
[7] I2CT_ON:
1: Switches on the I2C repeater block.
Confidential
[6:4] ENARPT_LEVEL[2:0]: Delay applied to applied to SDAT line. Advised value is 0x5. The units
are in cycles of FMCLK (100 MHz default).
fid
000: 128
001: 64
010: 32
011: 16
100: 8
on
101: 4
110: 64
111: 32
[3] SCLT_DELAY:
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1: The same delay as for the SDAT line is applied to the SCLT line.
[2] SCLT_VALUE: Force SCLT value I2CT_ON must be off.
[1] STOP_ENABLE:
1: The I2C repeater is automatically turned off at the end of the transaction (on first
encountered stop condition).
[0] SDAT_VALUE: Force sdat_value, I2CT_ON must be off.
PRESCALER DIVIDER
Information classified Confidential - Do not copy (See last page for obligations)
values in these fields configure the auxiliary clock function, the prescaler value, the clock signal
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frequency.
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The frequency range is given for FMCLK = 150 MHz.
010X XXXX LF generator 64 fM_CLK / 2048 / (32 + ACR[4:0]) 2.3 to 1.16 kHz
011X XXXX LF generator 128 fM_CLK / 4096 / (32 + ACR[4:0]) 580 to 1150 Hz
100X XXXX LF generator 256 fM_CLK / 8192 / (32 + ACR[4:0]) 290 to 572 Hz
on
101X XXXX LF generator 512 fM_CLK / 16384 / (32 + ACR[4:0]) 145 to 286 Hz
110X XXXX LF generator 1024 fM_CLK / 32768 / (32 + ACR[4:0]) 72 to 143 Hz
111X XXXX LF generator 2048 fM_CLK / 65536 / (32 + ACR[4:0]) 36 to 71 Hz
C
Information classified Confidential - Do not copy (See last page for obligations)
001: Functions as output port. DAC permanently outputs 1.
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010: High impedance mode.
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100: Functions as DAC. Duty cycle modulated at FMCLK / 16.
101: Functions as DAC. Duty cycle modulated at FMCLK / 4.
110: Functions as DAC. Duty cycle modulated at FMCLK.
Others: Reserved functions.
en
[4] RESERVED: This bit must be programmed to zero.
[3:0] DACMSB: 4 MSBs.
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7 6 5 4 3 2 1 0
DACLSB
Type: R/W
Reset: 0x00
Description: DAC register (LSB). This register is accessible in the standby mode.
C
PLL_MDIV
PLL_SELRATIO
BYP_PLL_ADC
BYP_PLL_FSK
BYPASS_PLL
RESERVED
PLL_STOP
SEL_OSCI
STANDBY
Information classified Confidential - Do not copy (See last page for obligations)
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Note: FSK is not supported in STi5189.
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[7] STANDBY: Stop all clocks except I2C clock.
0: Device is in standby.
1: Device is active.
en
[6] RESERVED: Must be set to 0.
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DISEQC_POFF
FSK_INV_CLK
ADC_INMODE
OSCI_POFF
RESERVED
RESERVED
FSK_POFF
ADC_PON
Address: QPSKBaseAddress + 0x42
Type: R/W
Reset: 0x0C
Description: Analog IPs control register. This register is accessible in the standby mode.
Information classified Confidential - Do not copy (See last page for obligations)
Note: FSK is not supported in the STi5189.
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[7] FSK_INV_CLK: Invert clock for FSK analog IP.
[6] RESERVED: Must be set to 0.
en
[5] ADC_PON: ADCs power ON.
0: ADC is active.
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1: 2 Vpp
[3] DISEQC_POFF: DiSEqC analog IP power OFF.
0: DiSEqC analog is active
1: DiSEqC analog is in standby.
on
RESERVED SYMB_CHOICE
Information classified Confidential - Do not copy (See last page for obligations)
[1:0] SYMB_CHOICE: I and Q choice for reading.
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00: After demodulation.
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01: After polyphase filter.
10: After derotation.
11: After dc_adjust.
I_SYMB
Type: R
Description: I symbol register. See also Section : I, Q symbol monitoring.
on
7 6 5 4 3 2 1 0
Q_SYMB
Information classified Confidential - Do not copy (See last page for obligations)
[7] SDAT_OD: Open drain configuration of GPIO pin.
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0: Push-pull.
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1: Open-drain.
[6:1] SDAT_CFG[5:0]: See Table 47.
[0] SDAT_XOR:
en
1: XOR the result of SDAT_CFG configuration.
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0 0 Force output to 0
1 1 Force output to 1
2 to 7 - Reserved
on
Information classified Confidential - Do not copy (See last page for obligations)
7 6 5 4 3 2 1 0
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AGC_OD AGC_CFG AGC_XOR
Description: AUXCK I/O control register. This register is accessible in standby mode. Same as
SDATCFG except for address and reset values.
7 6 5 4 3 2 1 0
NVIT_LOCK RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
0: No interrupt request has been detected since last erase of this bit.
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1: An interrupt request has been detected since last erase of this bit.
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The bits of these registers are erased after a read. At offset address 0x045, register is
having MSB bits and at offset address 0x046, register is having LSB bits.
en
[15] TMG_LOCK: Demodulator symbol rate locked.
[14] TMG_LOSS: Demodulator symbol rate lost.
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[11] DIS_TX: This interrupt flag is raised when any of the following events arise:
Gap burst terminated (gap burst flag going low).
DiSEqC transmitter FIFO now empty.
DiSEqC transmitter FIFO now has only 4 bytes.
on
[10] DIS_RX: DiSEqC receiver FIFO now has 8 more bytes waiting to be read or end of message
has been detected.
[9] RS_OV: Reed–Solomon FIFO overflow detected.
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7 6 5 4 3 2 1 0
NVIT_LOCK RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
standby mode. At offset address 0x043, register is having MSB bits and at offset
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address 0x044, register is having LSB bits.
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[15] TMG_LOCK: Enable TMG_LOCK interrupt request.
[14] TMG_LOSS: Enable TMG_LOSS interrupt request.
en
[13] CF_LOCK: Enable CF_LOCK interrupt request.
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FROZE_LOCK
RESERVED
COARSE
CENTER
FINE
KI
Address: QPSKBaseAddress + 0x50
Type: R/W
Reset: 0x10
Information classified Confidential - Do not copy (See last page for obligations)
Description: Autoscan control register. See also Section : First step: coarse autosearch.
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[7:6] RESERVED: Must be set programmed to 0.
[5] FROZE_LOCK: Control.
1: Froze accu1 and accu2 (see registers ACCU1VAL and ACCU2VAL).
en
[5:3] KI[1:0]: Control, integration ratio of power spectrum measurements in the coarse mode.
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11: 1/16
[2] CENTER: Control.
1: Reduce residual offset of Fs.
on
[1] FINE:
1: Enabled fine mode.
[0] COARSE: Control.
1: Enable coarse mode.
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RESERVED KT
RESERVED KC KS
Information classified Confidential - Do not copy (See last page for obligations)
[5:3] KC[2:0]: Control, frequency carrier correction ratio.
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[2:0] KS[2:0]: Control, frequency timing correction ratio.
FMINM
7 6 5 tia 4 3 2
FMIN register (MSB)
1 0
en
STOPON_FMIN
FMIN
Confidential
fid
Description: FMIN register (MSB). See also Section : Second step: fine scan.
FMIN
FMAX
Address: QPSKBaseAddress + 0x55
Type: R/W
Reset: 0x00
Description: FMAX register (MSB). See also Section : Second step: fine scan.
Information classified Confidential - Do not copy (See last page for obligations)
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[7] STOPON_FMAX: Control.
1: Stops fine mode if current timing frequency is above FMAX value.
[6:0] FMAX[14:8]: Control, maximum frequency bound.
en
FMAXL FMAX register (LSB)
Confidential
7 6 5 4 3 2 1 0
FMAX
fid
Description: FMAX register (LSB). See also Section : Second step: fine scan.
FINE_INCR
STEP2_MINUS STEP2_PLUS
Information classified Confidential - Do not copy (See last page for obligations)
indicator.
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[3:0] STEP2_PLUS[3:0]: Control, increase by STEP2PLUS the accumulator of the second indicator.
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TH2 Threshold2 (MSB) register
7 6 5 4 3 2 1 0
en
TH2
Type: R/W
fid
Reset: 0x86
Description: Threshold2 (MSB) register. See Section : Timing lock indicator.
on
7 6 5 4 3 2 1 0
TH1
Information classified Confidential - Do not copy (See last page for obligations)
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THH Threshold H register
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7 6 5 4 3 2 1 0
RESERVED THH
Reset: 0x08
Description: Threshold H register. See Section : Timing lock indicator.
fid
IND1_THRESHOLD
ACCU1_VAL
[7:0] ACCU1_VAL[7:0]: MSB of accumulator1. The accumulator1 MSB can be preset by writing in
this register.
Information classified Confidential - Do not copy (See last page for obligations)
ACCU2VAL Accumulator 2 status register
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7 6 5 4 3 2 1 0
ACCU2_VAL
fid
[7:0] ACCU2_VAL[7:0]: MSB of accumulator2. The accumulator2 MSB can be preset by writing in
this register.
on
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14 Configuration registers
The following functions are enabled and disabled using the configuration registers:
● alternative assignments on pins
● video DAC control
● audio DAC control
● interrupt direction
● FMI pull-ups
● smartcard clock selection
● DMAREQ direction and polarity
Information classified Confidential - Do not copy (See last page for obligations)
Note: Control and monitor registers A and B are high-speed (HS) registers and other registers are
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high-density (HD) registers.
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Addresses are provided as the ICHSBaseAddress and ICHDBaseAddress + offset.
The ICHSBaseAddress is 0xFD00 2000.
The ICHDBaseAddress is 0xFD90 1000.
en
.
Information classified Confidential - Do not copy (See last page for obligations)
0x0040 CFG_CTRL_K Interconnect configuration control register K page 177
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0x0044 CFG_CTRL_L Interconnect configuration control register L page 178
0x0048 CFG_CTRL_M Interconnect configuration control register M page 178
0x004C CFG_CTRL_N Interconnect configuration control register N page 179
en
0x0050 CFG_CTRL_O Interconnect configuration control register O page 180
0x0054 CFG_CTRL_P Interconnect configuration control register P page 180
Confidential
Information classified Confidential - Do not copy (See last page for obligations)
CFG_MONITOR_A Configuration monitoring register A
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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COMPENSATION_CODE_IN_NON_DDR_PAD
DLL_LOCK_TOCORE
DLL_CMD_TOCORE
en
RESERVED
RESERVED
Confidential
fid
on
[31:0] RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
14.1.2 High-density configuration monitor registers
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This group of registers lies in the high-density (HD) domain which consists of a set of
sixteen 32-bit configuration monitor registers housed inside transport subsystem and caters
for monitoring the status of the rest of the chip.
en
CFG_MONITOR_C Configuration monitoring register C
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
fid
[31:0] RESERVED
C
[31:0] RESERVED
COMPENSATION_CODE_IN_NON_DDR_PAD
COMPENSATION_CODE_IN_DDR_PAD
USB_POWERDOWN_ACK
SPDIF_EOLATENCY
TST_VBGUP_EXT
ADAC_VMCUP
TST_UP_EXT
ADAC_BUSY
ADAC_VMC
RESERVED
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
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Address: ICHDBaseAddress + 0x0028
Type: R
Reset: 0x0000
en
Description: Interconnect configuration monitoring register E.
Confidential
[31] RESERVED:
fid
[30] USB_POWERDOWN_ACK:
[29] TST_UP_EXT:
[28:22] COMPENSATION_CODE_IN_NON_DDR_PAD:
on
[21:15] COMPENSATION_CODE_IN_DDR_PAD:
[14:5] RESERVED
[4] ADAC_BUSY:
C
[3] SPDIF_EOLATENCY:
[2] ADAC_VMC: ADAC output
[1] ADAC_VMCUP: ADAC output
[0] TST_VBGUP_EXT: ADAC output
[31:0] RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
CFG_MONITOR_G Configuration monitoring register G
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
Reset: 0x0000
Description: Interconnect configuration monitoring register G.
fid
[31:0] RESERVED
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CPU_DEVICE_ID
Type: R/W
Reset: 0x0000
Description: Configuration monitoring register H.
[31:0] CPU_DEVICE_ID
[31:0] RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
CFG_MONITOR_J Configuration monitoring register J
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPENSATION_3V3_2_NON_DDR_OK
COMPENSATION_3V3_1_NON_DDR_OK
COMPENSATION_3V3_0_NON_DDR_OK
COMPENSATION_3V3_NON_DDR_OK
COMPENSATION_2V5_DDR_OK
QPSKBIST_OUT_COUNT_VAL
LMI_FMI_PMU_PDSTAT_CFG
TST_QPSK_PLL_BEND_BUS
TST_QPSK_PLL_BBAD_BUS
EXT_ST40_CORE_PDACK
FMI4_PWRDWN_ACK
en
QPSK_PLL_LOCK
RESERVED
RESERVED
Confidential
fid
on
[31] COMPENSATION_2V5_DDR_OK
[30] COMPENSATION_3V3_NON_DDR_OK
[29: 28] RESERVED
[27] COMPENSATION_3V3_2_NON_DDR_OK:
[26] QPSK_PLL_LOCK: QPSK PLL lock monitor.
[25] RESERVED:
[24] LMI_FMI_PMU_PDSTAT_CFG
[23] COMPENSATION_3V3_1_NON_DDR_OK
[22] COMPENSATION_3V3_0_NON_DDR_OK
[21] EXT_ST40_CORE_PDACK
[20] FMI4_PWRDWN_ACK
Information classified Confidential - Do not copy (See last page for obligations)
l
Description: Configuration monitoring register K.
[31:16] RESERVED
[15:0] RESERVED tia
en
CFG_MONITOR_L Configuration monitoring register L
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
fid
Reset: 0x0000
Description: Configuration monitoring register L.
C
[31:0] RESERVED
[31:0] RESERVED
[31:0] RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
CFG_MONITOR_O Configuration monitoring register O
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHIP_PUBLIC_ID
Reset: 0x0000
Description: Configuration monitoring register O.
fid
[31:0] CHIP_PUBLIC_ID:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
Type: R/W
Reset: 0x0000
Description: Configuration monitoring register P.
[31:0] RESERVED
[31:0] RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
CFG_MONITOR_R Configuration monitoring register R
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
Reset: 0x0000
Description: Configuration monitoring register R.
fid
[31:0] RESERVED
on
C
Information classified Confidential - Do not copy (See last page for obligations)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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RESERVED
fid
[31:0] RESERVED
on
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SH4_REQ_FILTER
STICKY_BIT
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
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Address: ICHSBaseAddress + 0x0004
Type: R/W
en
Reset: 0x0000
Description: Interconnect configuration control register B.
Confidential
fid
[31] STICKY_BIT: The post-reset value of this bit is 0. If set to 1, it can only be cleared by reset
operation.
[30] RESET_THE_DESIGN_ON_SECURITY_BREACH:
[29] SH4_REQ_FILTER:
on
[28:0] RESERVED
C
CFG_PIO_IN_MUX_ASC0_RXD
TSIS_SERIAL_NOT_PARALLEL
SELECT_ADDRESS_I2C_289
FMI_PULLUP_DISABLE[1:0]
GRANT_RETRACT_EN_INT
PTI_TS_BITBYTECLK_SEL
DMAREQ_POLARITY[1:0]
QPSK_DEBUG_CONFIG
DEBUG_OR_TS_OUT
SEL_1394_PHI_CLK
AUX_PIX_CLK_SEL
MASK_EXT_REQ
VOL_REQ_POFF
IRB_DISABLE
SEL_FE_TS
RESERVED
RESERVED
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
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Address: ICHDBaseAddress + 0x0000
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en
Type: R/W
Reset: 0x0000
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[25:24] FMI_PULLUP_DISABLE[1:0]
00: No disable
01: Reserved
11: Disable for FMI pull ups
10: Reserved
[23] AUX_PIX_CLK_SEL: Select recovered pix clock or aux clock at AUXCLKOUT pad.
0: Recovered clock (PIX_CLK)
1: Auxiliary clock (AUX_CLK)
[22] IRB_DISABLE: Enable/disable IRB
0: Enable (default)
1: Disable
[21:12] RESERVED
[11] VOL_REQ_POFF: Power off for voltage regulator. Default is normal mode.
0: Normal mode
1: Power down
[10] RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
[4] DEBUG_OR_TS_OUT:
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0: FE TS out. TS0OUT pads direction is output.
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1: TSmerger 1394 output to pad.
[3] TSIS_SERIAL_NOT_PARALLEL: First TS configuration.
0: Parallel
1: Serial
en
[2] SEL_FE_TS: TS stream. Must be programmed to 0.
0: TS stream from QPSK
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[1] QPSK_DEBUG_CONFIG: Default 0. IP289 I2C inputs from PIO1[0] and PIO1[1].
1: IP289 inputs from BE COMMS SSC1 interface
fid
FUNC_CFG_SOFTPUPOVERIDE
ADAC_SOFT_MUTE_DISABLE
FUNC_CFG_NPDVRAMP_EXT
FUNC_CFG_CMDDOWN_EXT
ADAC_ANA_BG_PWR_DOWN
FUNC_CFG_VMCUP_DIGEXT
FUNC_CFG_VMCUP_ANEXT
FUNC_CFG_CMDUPN_EXT
ADAC_ANA_PWR_DOWN
PCM_LRCLOCK_INVERT
ADAC_DIG_PWR_DOWN
VID_DAC_POFF_YCC_N
TSTSTRUCTURAL_CFG
ADAC_GAIN_CTRL_INT
VID_DAC_CMDR_YCC
VID_DAC_CMDS_YCC
PCM_CHANNEL_SEL
ADAC_SOFT_RST_N
PCM_SOURCE_SEL
FDMA_CLK_SEL
VDAC_HZ_YCC
RESERVED
RESERVED
RESERVED
Address: ICHDBaseAddress + 0x0004
Information classified Confidential - Do not copy (See last page for obligations)
Type: R/W
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Reset: 0x0000
Description: Interconnect configuration control D.
en
[31:26] RESERVED
Confidential
1: Invert LR lock
[21:20] RESERVED
[19] FDMA_CLK_SEL: FDMA clock source
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0: From PLL
1: From frequency synthesizer
[18] ADAC_SOFT_MUTE_DISABLE:
0: SOFT_MUTE is ON
1: SOFT_MUTE is OFF
On reset mute is ON.
[17] ADAC_DIG_PWR_DOWN:
0: Digital power down. Overridden by TST_DCPATHOFF.
[16] ADAC_ANA_PWR_DOWN:
0: Analog power down. Overridden by TST_DCPATHOFF.
[15] ADAC_ANA_BG_PWR_DOWN:
0: Analog bandgap power down mode
[14] RESERVED
[13] ADAC_SOFT_RST_N: Soft reset of ADAC. The soft reset bit is inverted. Active low. Write 1 to
soft reset ADAC.
0: Soft reset applied
1: Soft reset inactive
[12] VID_DAC_POFF_YCC_N
0: Disable power of all three DACs. This bit is inverted so on power up it is low.
This bit is reset to 1 inside the Group3 wrapper.
[11] VID_DAC_CMDR_YCC: Level control for UOUT, WOUT, VOUT.
[10] VID_DAC_CMDS_YCC: Level control for UOUT, WOUT, VOUT.
[9] VDAC_HZ_YCC:
1: YCC outputs are high impedance
Information classified Confidential - Do not copy (See last page for obligations)
[8] FUNC_CFG_CMDDOWN_EXT: To control CMDDOWN, VRAMP input
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[7] FUNC_CFG_CMDUPN_EXT: To control CMDUPN, VRAMP input
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[6] FUNC_CFG_SOFTPUPOVERIDE: Soft power up/down override
[5] FUNC_CFG_NPDVRAMP_EXT: To control NPDVRAMp, VRAMP input
[4] FUNC_CFG_VMCUP_DIGEXT: To control VMCUP, digital part input
en
[3] FUNC_CFG_VMCUP_ANEXT: To control VMCUP, VRAMP input
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ETHERNET_INTERFACE_ON
DISABLE_MSG_FOR_WRITE
DISABLE_MSG_FOR_READ
SMARTCARD_CLK1_SEL
SMARTCARD_CLK0_SEL
MII_PHYCLK_OUT_EN
VCI_ACK_SOURCE
MAC_SPEED_SEL
ETHERNET_SEL
RESERVED
RESERVED
RESERVED
MII_MODE
Address: ICHDBaseAddress + 0x0008
Information classified Confidential - Do not copy (See last page for obligations)
Type: R/W
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Reset: 0x0000
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Description: Interconnect configuration control E.
[31:18] RESERVED:
en
[17] SMARTCARD_CLK1_SEL: Clock select for smartcard 2
Confidential
[16:11] RESERVED
[10] SMARTCARD_CLK0_SEL:
fid
0: Smartcard clock is provided from external source through PIO0 [2] (default)
1: Smartcard clock is provided from system services.
[9] RESERVED
[8:7] ETHERNET_SEL: These pins are used together for MII/RMII Mode.
on
If CFG_CTRL_E[8:7] = 00, pads are used for transport in/out and Ethernet is not available.
If CFG_CTRL_E[8:7] = 10, pads are used for RMII Ethernet mode. During this time due to less
number of pins used by Ethernet, serial transport IN is available.
If CFG_CTRL_E[8:7] = 11, pads are used for MII mode Ethernet and no transport in/out is
C
available.
[6] MII_PHYCLK_OUT_EN: Ethernet PHY clock out direction control. Default is OUT.
1: PHYCLK_IN comes from TS0OUTERROR pad
[5] DISABLE_MSG_FOR_WRITE:
0: Message mode
1: IP requests write transactions in packet mode
[4] DISABLE_MSG_FOR_READ:
0: Message mode
1: IP requests read transactions in packet mode
[3] VCI_ACK_SOURCE:
1: Posted write
[2] MII_MODE: This is input to Ethernet IP. This bit decides MII/RMII mode in IP.
0: RMII mode
1: MII mode
[1] MAC_SPEED_SEL: Select MAC clock speed. 25/2.5 MHz
[0] ETHERNET_INTERFACE_ON: This is input to Ethernet IP. This states if TXCLK, RXCLK to
MAC are to be used from TXCLK, RXCLK pins of Ethernet IP or from internal clock divider
using clock from ClockGen.
0: TXCLK and RXCLK for MAC come from internal clock divider using clock from ClockGen.
1: TXCLK and RXCLK become MII/RMII (CFG_CTRL_E[2]) mode dependent.
RXCLK and TXCLK in MII mode should be given By PHY device.
RXCLK and TXCLK are not used in RMII mode, only PHY_CLK (Ref_Clk) is used.
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Address: ICHDBaseAddress + 0x000C
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Type: R/W
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Reset: 0x0000
Description: Interconnect configuration control F.
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[31:24] PIO1_ALTFOP_MUX_SEL_BUS1: Selection of alternative functions on PIO port 1.
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIO3_ALTFOP_MUX_SEL_BUS1 PIO3_ALTFOP_MUX_SEL_BUS0 PIO2_ALTFOP_MUX_SEL_BUS1 PIO2_ALTFOP_MUX_SEL_BUS0
Type: R/W
Reset: 0x0000
Description: Interconnect configuration control G.
LMIPADPULLUP_CTRL_FROM_CORE
LMI_ZOUTPROGA_FROM_CORE
CFG_FMI4_MASTER_BOOTED
MODEZI_CTRL_FROM_CORE
VID_DAC_POFF_YCC_INT2
USB_POWERDOWN_REQ
PMU_FMI_PD_CFG
RESERVED
RESERVED
RESERVED
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
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Address: ICHDBaseAddress + 0x0014
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Type: R/W
Reset: 0000
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Description: Interconnect configuration control H.
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This bit along with bit[29] used for LMI pads pull up/pull down control. Both should not be high
at the same time.
[29] LMIPADPULLUP_CTRL_FROM_CORE: Pull up control for LMI pads.
0: Pull down
C
1: Pull up
[28] LMI_ZOUTPROGA_FROM_CORE: LMI ZOUTPROGA control for LMI pads
0: DDR strong output
1: DDR weak output
[27] RESERVED
[26] PMU_FMI_PD_CFG: LMI power down request for self refresh mode
[25:22] RESERVED
[21] CFG_FMI4_MASTER_BOOTED: Configuration to gate FMI4 request until master has booted.
0: Gate the FMI4 request
1: FMI4 request from slave
[20:10] RESERVED
[9] VID_DAC_POFF_YCC_INT2: Video DAC2 power OFF
[8] USB_POWERDOWN_REQ: USB power down request
[7:0] RESERVED
PIO_FUNCTIONALITY_ON_PIO1_7
PIO_FUNCTIONALITY_ON_PIO1_1
BLITTERS3_PRI_CTRL
BLITTERS2_PRI_CTRL
BLITTERS1_PRI_CTRL
ADAC_MODE_SELECT
FMI4_PWRDWN_REQ
BLITTERD_PRI_CTRL
ULPI_PHY_RST_O_N
BLITTERS3_ALT_PRI
BLITTERS2_ALT_PRI
BLITTERS1_ALT_PRI
BLITTERD_ALT_PRI
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
Address: ICHDBaseAddress + 0x0018
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Type: R/W
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Reset: 0x0000
Description: Interconnect configuration control I.
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[31] FMI4_PWRDWN_REQ: Power down request for FMI4.
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DLL_EXT_CMD_CTRL
DLL_INT_CMD_CTRL
DLL_DE0_OFF_CMD
DLL_USER_CMD
DLL_OFF_CMD
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
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Description: Interconnect configuration control J.
[31:29] RESERVED
[28:20] DLL_DE0_OFF_CMD tia
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[19:11] DLL_USER_CMD
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[10:2] DLL_OFF_CMD
[1] DLL_INT_CMD_CTRL
fid
[0] DLL_EXT_CMD_CTRL
QPSK_TUNER_SELECT
DLL_DE1_RST_CMD
DLL_DE1_OFF_CMD
DLL_DE0_RST_CMD
RESERVED
[26:18] DLL_DE1_RST_CMD:
[17:9] DLL_DE1_OFF_CMD:
[8:0] DLL_DE0_RST_CMD:
Information classified Confidential - Do not copy (See last page for obligations)
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Description: Interconnect configuration control L.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMPENSATION_3V3_SLEEPINHBT
COMPENSATION_3V3_CHIPSLEEP
COMPENSATION_2V5_ACCURATE
COMPENSATION_3V3_ACCURATE
fid
COMPENSATION_2V5_3V3_CFG
COMPENSATION_2V5_FREEZE
COMPENSATION_3V3_FREEZE
GLOBAL_POWER_DOWN_REG
QPSKBIST_PLL_SOURCE_VAL
QPSKBIST_CMP_MASK_VAL
LMI_MEM_BASE_ADDR_SIG
SPI_CS_WHEN_SSC_USED
QPSKBIST_KEEP_FAILS
SPI_BOOTNOTCOMMS
LMIVERF_CFG_CTRL
ULPI_DDR_EN_I
RESERVED
RESERVED
on
C
[31] GLOBAL_POWER_DOWN_REG: This bit is used as power down request to mask interrupt to
reach sh4.
[30] LMIVERF_CFG_CTRL: Enable LMIVREF
[29:28] RESERVED
[27] COMPENSATION_3V3_SLEEPINHBT: Compensation control
[26] COMPENSATION_3V3_CHIPSLEEP: Compensation control
[25] COMPENSATION_2V5_FREEZE: Compensation control
Information classified Confidential - Do not copy (See last page for obligations)
[12] ULPI_DDR_EN_I: DDR enable for ULPI operation. Default is 0.
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0: Normal 8-bit SDR ULPI operation
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1: 4-bit DDR ULPI operation
[11:4] LMI_MEM_BASE_ADDR_SIG: LMI memory base address. Default reset value is 0x0C for 29
bit. When program, reset value is 0x40 in 32-bit mode for LMI memory base address.
[3] QPSKBIST_KEEP_FAILS: QPSK bist
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[2] QPSKBIST_PLL_SOURCE_VAL: QPSK bist
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
on
[31:0] RESERVED
PIO4_ALTFOP_MUX_SEL_BUS1
PIO4_ALTFOP_MUX_SEL_BUS0
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
Address: ICHDBaseAddress + 0x0050
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Type: R/W
Reset: 0x0000
Description: Interconnect configuration control O.
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[31:16] RESERVED
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RESERVED
Reset: 0x0000
Description: Interconnect configuration control P.
[31:0] RESERVED
AD12PP_INMODE1_INT
AD12PP_INMODE0_INT
AD12PP_BIASCLK_INT
AD12PP_TREFM_INT
AD12PP_TREFP_INT
AD12PP_FS50M_INT
AD12PP_FS20M_INT
AD12PP_TVCM_INT
AD12PP_POFF_INT
AD12PP_ULP2_INT
AD12PP_ULP1_INT
AD8S_TREFQ_INT
AD12PP_TBG_INT
AD8S_TREFI_INT
AD8S_TBG_INT
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
Reset: 0x0000
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Description: Interconnect configuration control Q.
[31:15] RESERVED
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[14] AD8S_TREFQ_INT: Dual ADCS control
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[13] AD8S_TREFI_INT: Dual ADCS control
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RESERVED
Address: ICHDBaseAddress + 0x005C
Type: R/W
Reset: 0x0000
Description: Interconnect configuration control R.
Information classified Confidential - Do not copy (See last page for obligations)
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[31:0] RESERVED
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fid
on
C
15 System services
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● CPU programmable interrupt
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Figure 24. STi5189 system services architecture
STBus
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System services
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DIV Subsystem
30 MHz domain DIV clocks
DIV
fid
PLL
DIV
VCXO DIV
Xtal Synths
30 MHz
Watchdog
on
Reset
CTRL Subsystem
CTRL reset
LP timer
C
NOT_RESET
Reset out
Wake up from comms
Reset
x1
Event sw
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Prog Rp
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Standby
sw
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There is one mode of operation, which is clock master. Within this mode there are three
states of operation:
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● x1
● programmable (reduced power mode exists within the programmable mode of
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operation)
● standby
fid
Following reset the system services block transitions into the x1 state causing all clocks to
be sourced from 30 MHz. All other transitions into the x1 state after reset are through
software by programming the MODE_CONTROL register or event-based from the standby
mode.
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To program the divider channels, the software must cause a transition to the x1 state. The
subsystem clocks are shut down (zeroed) in a clean way and then re-started synchronously
using the external 30 MHz clock. The divider channels can then be programmed. When
programming is complete a further software transition is made into the programmable state,
C
this transition causes a second clean switch to the newly programmed clock divider outputs.
It is possible to transition from programmable mode to standby mode with software. The
return path transition to x1 mode only occurs if the low power alarm is activated. Also if there
is an external interrupt (wake up) from the comms subsystem.
The reason standby transitions to x1 mode is because the PLL could be disabled within
standby. Therefore, no PLL clocks are running.
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15.3.1 Subsystem clocks
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The subsystem clocks are generated using the frequency synthesizer PLLs as shown in the
following table. The resulting ranges are used to divide the blocks among a number of clock
domains. The CLK_DDR clock is not present in Table 49, which is 4 x CLK_LMI.
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Table 49. Subsystem clock frequencies
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CLK_ST40_ICK PLL A
ST40 ICK 350 - 350
(700 MHz)
ST40 PCK CLK_ST40_PCK 133 - 133
on
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The STi5189 uses two PLLs in a frequency synthesizer configuration, primarily driven from
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an external 30 MHz crystal.
The PLLs provide system clocks up to 800 MHz. These two clocks are individually
selectable by the programmable dividers that source the clocks shown in Table 49, resulting
in greater system flexibility.
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PLL frequency calculation
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The PLLs have three dividers, which are referred to as M (pre-divider), N (feedback-divider)
and P (post-divider). These dividers are located in the PLLx_CONFIGn registers. The output
fid
clock of the frequency of the PLL is controlled by binary values applied to the programmable
registers as defined by the following formula:
2× N
F ( clockout ) = ------------------- × F ( refclock )
on
P
M× 2
1 ≤M ≤256, 1 ≤N ≤256, 0 ≤P ≤5
F ( refclock )
1MHz ≤------------------------------- ≤200MHz
M
2× N
200MHz ≤⎛ --------------⎞ × F ( refclock ) ≤800MHz
⎝ M ⎠
⎛ 2× N ⎞
6.25MHz ≤⎜ -------------------⎟ × F ( refclock ) ≤800MHz
⎝ M × 2 P⎠
Two PLL frequencies that fulfill the STi5189 system requirements are:
● CLOCKOUT = 700 MHz, NDIV = 70 PDIV = 0 MDIV = 6,
● CLOCKOUT = 800 MHz, NDIV = 80 PDIV = 0 MDIV = 6.
Note: To achieve the correct frequencies, PLLA and PLLB must be programmed with the values
0x2404 and 0x4406, respectively, following a reset, see PLLx_CONFIG0.
Using these frequencies, Table 50 gives subsystem frequencies for functional, reset and
reduced power modes.
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ratio ratio
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PLL
Frequency synthesizers
CLK_SPARE_FS 27 30 0 27 FS-A(0)
CLK_PCM 13.8 30 0 13.8 FS-A(1)
CLK_SPDIF 13.8 N/A 30 N/A 0 13.8 FS-A(2)
CLK_DSS 27 30 0 27 FS-A(3)
CLK_PIX 54 30 0 54 FS-B(0)
CLK_FDMA_FS 27 - 30 - 0 27 FS-B(1)
CLK_AUX 27 - 30 - 0 27 FS-B(2)
CLK_USB 48 - 30 - 0 48 FS-B(3)
1. Func1 frequencies are the recommended frequencies for STi5189.
2. These frequencies are fallback setting in case of X1 to programmable mode not functioning.
3. Stand by behavior of PLL divider clocks is influenced by the configuration of lp_mode_dis0 (0x118 register).
4. During reduced power mode, the programmable dividers are sourced with 30 MHz and the functional divide ratio applied.
For this table, the Func1 divide ratios will be applied.
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5 0x04 0x0739C 0x0 0x0
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5.5 0x00 0x0071C 0x1 0x0
6 0x01 0x00E38 0x1 0x1
6.5 0x02 0x01C78 0x1 0x0
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7 0x03 0x03C78 0x0 0x0
7.5 0x04 0x07878 0x1 0x0
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Semi-synchronous operation
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(1 to 215)
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● SDIV[2:0] in the [clock]_SETUP0 register: output divider (2 to 256) - SDIV:
– SDIV = 000 divides by 2,
– SDIV = 001 divides by 4,
– SDIV = 010 divides by 8,
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– SDIV = 011 divides by 16,
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32 clocks
30 MHz CLKREF FMX CLKOUT
00 NDIV[1:0]
PLL Phase Digital
1 SELF27 core selector algorithm
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MD [4:0]
PE [15:0]
SDIV [2:0]
where FPLL = 216 MHz (27 MHz osc) / 240 MHz (30 MHz osc).
To avoid glitches at the frequency synthesizer output, only the MD, PE and EN_PRG
parameters can be changed.
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1
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48 12.288 0x11 = 17 0x3600 = 13824 4
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64 16.384 0x1A = 26 0x5100 = 20736 3
96 24.576 0x11 = 17 0x3600 = 13824 3
88.2 22.5792 0x13 = 19 0x6F05 = 28421 3
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128 32.768 0x1A = 26 0x5100 = 20736 2
176.4 45.1584 0x13 = 19 0x6F05 = 28421 2
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Multiplexing after the frequency synthesizer outputs allows clock switching when in the
standby mode (LP_MODE_SYNTH_DIS[n]). A glitch free multiplexer (GFM) switches
cleanly between frequency synthesizer output when transitioning between the x1 and
programmable states. For further details, see Section 15.5.
For improved performance, FS_CLK[6] can be used as an additional source clock for
CLK_AUX. The switch between the divider clock output and FS_CLK[6] is glitch free and
controlled by the ALT_TRANSPORT_SELECT register. The advantage of using a frequency
synthesizer clock is the maximum frequency of 216 MHz with fine adjust capabilities.
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Like CLK_SYS which is being shared widely within the system, a clock gating approach
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using notech cbuf cells is being implemented for the full STi5189 chip. Here, a register
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based configuration bits can switch on and off various IP’s running on CLK_SYS. The
register used for this purpose is DYNAMIC_POWER_CONFIG (0x128: inside the system
services).
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Note the timings to switch OFF a subsystem and then switch it ON again lies with the
software control. Here, the host will take responsibility to make sure when to switch off a
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subsystem by receiving the acknowledgment signals from the IPs and also whether to give a
reset to the system on powering up.
fid
CLK_SYS CP
Cbuf G GDMA
E E
on
TE
G CLK_SYS
CP
CP Blitter
Cbuf G
E
C
CLK_SYS
CP
Cbuf cells
Cbuf G FMI
E
CLK_SYS CLK_SYS CP
Cbuf G TS merger
E
System services Dynamic power control
CLK_SYS
CP
Cbuf G PTI
E
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Fmax subsystem clock to logic 0. Software can also override the standby mode so that
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instead of transitioning to logic 0 the resultant subsystem clock is 30 MHz.
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Note: All divider clocks behavior in the standby mode can be defined (30 MHz/0 MHz) using the
LP_MODE_DIS0 and LP_MODE_DIS1 register.
asserted (the maximum count is 12 days before the low power alarm is asserted).This
causes the control FSM to transition to x1 mode. The other event is the active high external
wake up. This is synchronized into the 30 MHz domain as shown in the following figure:
25-bit counter
30 MHz
LP_COUNT_ENABLE_REG 1s tick
C
30 MHz
20-bit decrement counter Low
power
alarm Standby
LP_COUNT_REGx*x event
EN =0
D
30 MHz
logic0
External wake up
30 MHz
15.7.1 RTC_LP
RTC_LP is a 64-bit counter. It is shadowed by two 32-bit registers (RTCS_LSB_LP and
RTCS_MSB_LP) in the 30 MHz domain. RTC_LP is never reset and is only programmed
through the shadow registers.
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Note: Data is always available for reading and the returned value always agrees with what was last
written, even if not yet accepted by the RTC_LP.
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When a previous write has not yet been accepted, a second write cannot take place.
15.7.2 RTC_27
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RTC_27 runs continuously from a divided CLK27IN tick. The control of the counter is
identical to the control of RTC_LP. The counter tick is a divide of 30 MHz to make it as close
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to 32 kHz (32.768 kHz) as possible. The tick generated is 30 MHz / 824. Therefore, the
generated LPCLKIN is 36.407 kHz.
fid
frequency synthesizer, which uses a fixed and stable 30 MHz clock produced by a crystal as
a reference.
These three clocks are:
● PIX_CLK (27 MHz) used for standard definition display
C
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(FS0) PIX_CLK
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PCM audio
frequency
synthesizer LD Capture Comparison FS1 set-up
Free-running counter by the CPU values update
(FS1) DIN register
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(CPT_PCM) with previous value
(DCO_PCM_CNT)
PCM_CLK Readable
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register
Note: The FS0 set-up values are updated using the PCR value included in the stream.
fid
The recovery is done as usual for PIX_CLK by comparing the 42-bit PCR value located in
the adaptation field of the stream, with the local STC value when a packet arrived. This
generates a potential correction that is applied to the PIX_CLK frequency synthesizer. The
frequency synthesizer is programmed with new set-up values to slow or accelerate the
clock.
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For the audio PCM clock recovery, two counters are used.
● A PCM free-running counter clocked by the PCM audio frequency synthesizer FS1.
● A reference counter clocked by the standard definition video frequency synthesizer
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FS0. The maximum value of this counter is programmable defining the time interval
between two consecutive resets. This counter is used as a time-base.
When this reference counter resets, the values of the free-running counter clocked at
PCM_CLK is captured into a readable register. This event generates an interrupt to the
CPU. The CPU reads the value and compares it with the previously captured value. The
difference between two adjacent values gives an indication of the correction to apply to the
PCM audio frequency synthesizer FS1.
The decision to correct the frequency synthesizer set-up is under the control of the software.
The same principle applies for the recovery of the SPDIF_CLK. A free-running counter is
clocked with the S/PDIF frequency synthesizer FS2. The same reference counter is used.
When this counter resets, the output of the free-running counter clocked at SPDIF_CLK is
captured into a readable register.
The counters are 32-bit counters.
Information classified Confidential - Do not copy (See last page for obligations)
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Smartcard power control detects when the smartcard has been removed from the system. It
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is hardware detect as power to the smartcard needs to be removed before software can
respond. Smartcard power can be disabled or inverted using SC_CONTROL_CONFIG[0]
as shown in the following figure:
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Figure 30. Smartcard power control architecture
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SC_CONTROL_CONFIG
fid
SC_CONTROL_CONFIG
C
NOT_RESET Timer
De-glitch 10 us
RESETEXTOUT
WATCHDOG_RST_REQ RST
CTRL SC RESET OUT
Watchdog
timer
LT_RST_REQ
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Front panel Deglitch and
reset through
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PIO input 4s timer
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en
Tap link Other system ST40-300 1 ms
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RESET_GLOBAL
combined into one pulse of a minimum 200 ms (stretched reset). The stretched reset is
triggered internally by watchdog, long time-out, NOT_RESET and smartcard insertion
signals as well as by an external reset. Internal resets are maskable. Therefore, the
smartcard insertion reset can be disabled using maskable bits.
15.10.3 Watchdog
The watchdog timer is enabled by the WD_COUNT_ENABLE in the
WATCHDOG_COUNTER_CFG1 register. On assertion of WD_COUNT_ENABLE, the
WD_COUNT figure is decremented from the preloaded value on a 1 s timer tick. When the
decremented count reaches 1, the watchdog reset is asserted. This causes a subsystem
and global asynchronous reset. A masking bit in the RESET_STATUS register masks the
watchdog reset.
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Synchronizer
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RST_LONGTIME
MICRO_TICK (1 μs)
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30 MHz longtime counter 22-bit
EN
30 MHz
RESET_LONGTIME_IN_SENSE =4s Long time-out reset
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Control
30 MHz
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30 MHz
RESET_MASK_BIT[1]
fid
30 MHz
RST_N_HW
on
deglitcher removes any bounce in the signal from the smartcard. Smartcard reset is enabled
by the SC_INS_RST_EN bit in the SC_INSERTION_RST_CFG register. The sense of the
detect signal can also be inverted using the SC_DETECT_SENSE bit in the same register.
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DDR_CLK
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LMI_CLK
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NOT_RST_DDR
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The CPU programmable interrupt is asserted when a count ranging from 1 ms to 100 ms
reaches zero. The counter (CPU_INT_COUNT_CONFIG[6:0] in CPU_INT_CFG) is
decremented on a microsecond tick. The reset condition is 10 ms but it can be programmed
on
over a range from 1 ms to 100 ms. The generated interrupt is synchronized into the CPU
clock domain. Its status is captured by a status bit in the CPU_INT_CFG register, which is
cleared when written to.
Note: Registers (except addresses 0x160 to 0x16F) are read only until they have been unlocked
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(write access). This is carried out with the REGISTER_LOCK_CFG register (address
0x300). For further details, see Section 15.2.1: Programming the registers.
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0x008 PLLB_CONFIG0 PLLB configuration 0 page 206
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0x00C PLLB_CONFIG1 PLLB configuration 1 page 206
FS216_A setup configuration register
0x010 FS216X4_SETUP_A page 212
(required F10)
0x014 FS216X4_CLK1_SETUP0 FS216 x 4 set up configuration register page 214
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0x018 FS216X4_CLK1_SETUP1 CLK_SPARE (channel 1) page 218
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0x0048 - 0x004F
FS216_B setup configuration register
0x0050 FS216X4_SETUP_B page 213
(required F10)
0x0054 FS216X4_CLK5_SETUP0 FS216 x 4 set up configuration register page 216
CLK_PIX (channel 5). Required frequency is
0x0058 FS216X4_CLK5_SETUP1 54 MHz. page 219
0x005C - 0x005F
0x006C - 0x006F
RESERVED - -
0x0078 - 0x007F
0x0088 - 0x008F
0x090 CLKDIV0_CONFIG0 page 207
0x094 CLKDIV0_CONFIG1 Clock divider configuration page 208
0x098 CLKDIV0_CONFIG2 page 209
0x0A0 CLKDIVn_CONFIG0 page 207
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0x0A4 CLKDIVn_CONFIG1 Clock divider configuration page 208
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0x0A8 CLKDIVn_CONFIG2 page 210
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0x0B0 CLKDIVn_CONFIG0 page 207
0x0B4 CLKDIVn_CONFIG1 Clock divider configuration page 209
0x0B8 CLKDIVn_CONFIG2 page 211
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0x010C - 0x010F RESERVED - -
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0x0124 LP_MODE_COUNTER_CFG1 Low power count value and low power enable page 223
Dynamic power control capability for the full
0x0128 DYNAMIC_POWER_CONFIG page 234
chip
C
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0x0200 RTCS_LSB_LP Low power timer LSB page 223
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0x0204 RTCS_MSB_LP Low power timer MSB page 224
0x0208 RTCS_CONTROL_LP Low power timer control page 224
0x020C - 0x020F RESERVED - -
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0x210 RTCS_LSB_27 Low power timer LSB page 225
0x214 RTCS_MSB_27 Low power timer MSB page 225
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RESERVED
MODE
[31:2] RESERVED
[1:0] MODE: Mode control:
00: Stay in current state 01: Transition into X1 state
10: Transition into programmable mode 11: Transition into standby mode
RESERVED
KEY_LOCK
KEY
Address: SysServBaseAddress + 0x0300
Type: R/W
Reset: 0x0100
Description: Lock and unlock register control. All registers (except the DCO registers at addresses
at SysServBaseAddress + 0x160 to 0x16F and at DCOBaseAddress) are read only
Information classified Confidential - Do not copy (See last page for obligations)
until they have been unlocked (given write access). This is carried out with this
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register.
[31:9] RESERVED
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[8] KEY_LOCK: Signifies lock state of registers.
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0: Registers unlocked for access.
1: All registers locked. Read access only.
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CLOCK_OUT_SEL
CLOCK_OBS
RESERVED
C
[31:6] RESERVED
[5] CLOCK_OBS: Observe alternate clocks on O_FREQ_SYNTH[6].
0: Frequency synthesizer AUX_CLK (default) on O_FREQ_SYNTH[6]
1: Alternate clocks selected by CLOCK_OUT_SEL[4:0]
Note: The clock observation multiplexer divides clocks greater than 100 MHz to avoid high
Information classified Confidential - Do not copy (See last page for obligations)
frequency clocks on the PCB. Hence, except div6, div7 and div8 all other divider
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clocks, which are selected on the observation multiplexer clocks, are divided by 2
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from their actual values. This is followed to avoid unpredictable behavior on the PCB.
The clock observation multiplexer is used for system testing. It will not be free of
glitches. It is needed purely for observation purposes.
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FORCE_CFG Force to programmed output in X1 mode
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FS_FORCE[7:0]
PLL_FORCE
RESERVED
fid
Type: R/W
Reset: 0x0000
Description: Force to programmed output in X1 mode. Force of control FSM.
C
[31:19] RESERVED
[18:11] FS_FORCE[7:0]: Force frequency synthesizer clocks to programmed output when in X1 mode.
0: X1 mode output clock.
1: FS output clock.
[10:0] PLL_FORCE: Force divider clocks to programmed output when in X1 mode.
0: X1 mode output clock.
1: Divided PLL output clock.
PLL_FORCE[0] to select PLL for PLL_CLOCK[0].
PLL_FORCE[5] to select PLL for PLL_CLOCK[5].
ALT_TRANSPORT_SELECT
PLL_27_SELECT
PLL_SELECT
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
Address: SysServBaseAddress + 0x0180
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Type: R/W
Reset: 0x0BDE
Description: PLL and divider selection. Multiplexer selects for PLL/dividers.
en
[31:13] RESERVED
Confidential
0: Select PLLA.
1: Select PLLB.
1 Bit/divider for system flexibility.
Only glitch clean if programmed within X1 mode.
C
RESERVED N M
[31:16] RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
[15:8] N: Pre-divider ratio setup from 1 to 256.
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[7:0] M: Pre-divider ratio setup from 1 to 126.
RESERVED
SETUP
LOCK
POFF
Confidential
P
fid
[31:16] RESERVED
C
RESERVED N M
[31:16] RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
[15:8] N: Pre-divider ratio setup from 1 to 256.
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[7:0] M: Pre-divider ratio setup from 1 to 126.
RESERVED
SETUP
LOCK
POFF
Confidential
P
fid
[31:16] RESERVED
C
RESERVED CLKDIV_SEQ
[31:16] RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
[15:0] CLKDIV_SEQ: Clock divider divides sequence bit pattern.
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CLKDIVn_CONFIG0 Clock divider sequence bit pattern
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CLKDIV_SEQ
en
Address: SysServBaseAddress + 0x0A0 + (n - 1) * 0x0C (where n = 1 to 4)
Confidential
Type: R/W
fid
[31:16] RESERVED
[15:0] CLKDIV_SEQ: Clock divider divides sequence bit pattern.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CLKDIV_SEQ
[31:16] RESERVED
[15:0] CLKDIV_SEQ: Clock divider divides sequence bit pattern.
CLKDIV_SEQ[19:16]
RESERVED
Address: SysServBaseAddress + 0x094
Type: R/W
Reset: 0x0000
Information classified Confidential - Do not copy (See last page for obligations)
Description: Clock divider sequence bit pattern.
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[31:5] RESERVED
[4:0] CLKDIV_SEQ[19:16]: Clock divider divides sequence bit pattern.
en
CLKDIVn_CONFIG1 Clock divider sequence bit pattern
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKDIV_SEQ[19:16]
fid RESERVED
on
[31:5] RESERVED
[4:0] CLKDIV_SEQ[19:16]: Clock divider divides sequence bit pattern.
CLKDIV_SEQ[19:16]
RESERVED
Address: SysServBaseAddress + 0x0D4 + (n - 6) * 0x0C (where n = 6 to 10)
Type: R/W
Reset: 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
Information classified Confidential - Do not copy (See last page for obligations)
Description: Clock divider sequence bit pattern.
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[31:5] RESERVED
[4:0] CLKDIV_SEQ[19:16]: Clock divider divides sequence bit pattern.
en
CLKDIV0_CONFIG2 Clock divider sequence bit pattern
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKDIV_DEPTH
CLKDIV_EVEN
CLKDIV_HNO
CLKDIV_EN
RESERVED
fid
on
[31:7] RESERVED
[6] CLKDIV_HNO:
EVEN 0 HNO 0: Divide by odd whole number, for example, 5
EVEN 0 HNO 1: Divide by half ratio, for example, 4.5
EVEN 1 HNO 1: Divide by even whole number, for example, 6
EVEN 1 HNO 0: RESERVED
[5] CLKDIV_EVEN:
EVEN 0 HNO 0: Divide by odd whole number, for example, 5
EVEN 0 HNO 1: Divide by half ratio, for example, 4.5
EVEN 1 HNO 1: Divide by even whole number, for example, 6
EVEN 1 HNO 0: RESERVED
[4] CLKDIV_EN: RESERVED. This bit is always set to 1.
CLKDIV_DEPTH
CLKDIV_EVEN
CLKDIV_HNO
CLKDIV_EN
RESERVED
Address: SysServBaseAddress + 0x0A8 + (n - 1) * 0x0C (where n = 1 to 4)
Information classified Confidential - Do not copy (See last page for obligations)
Type: R/W
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Reset: 0x0075, 0x0075, 0x0071, 0x0071
tia
Description: Clock divider sequence bit pattern.
[31:7] RESERVED
en
[6] CLKDIV_HNO:
Confidential
CLKDIV_DEPTH
CLKDIV_EVEN
CLKDIV_HNO
CLKDIV_EN
RESERVED
Address: SysServBaseAddress + 0x0D8 + (n - 6) * 0x0C (where n = 6 to 10)
Type: R/W
Reset: 0x0075, 0x0075, 0x0075, 0x0071, 0x0071
Description: Clock divider sequence bit pattern.
Information classified Confidential - Do not copy (See last page for obligations)
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[31:7] RESERVED
[6] CLKDIV_HNO:
EVEN 0 HNO 0: Divide by odd whole number, for example, 5
EVEN 0 HNO 1: Divide by half ratio, for example, 4.5
en
EVEN 1 HNO 1: Divide by even whole number, for example, 6
EVEN 1 HNO 0: Reserved
Confidential
[5] CLKDIV_EVEN:
EVEN 0 HNO 0: Divide by odd whole number, for example, 5
fid
SELBW_X4[1:0]
NSB_X4[3:0]
RESERVED
RESERVED
SELSDIV3
POFF_X4
NRST
NDIV
Address: SysServBaseAddress + 0x0010
Type: R/W
Information classified Confidential - Do not copy (See last page for obligations)
Reset: 0xF10
l
Description: FS216_A set up configuration register (required F10).
[31:12] RESERVED
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[11:8] NSB_X4[3:0]: Active low standby for digital parts of frequency synthesizer.
en
NSB[0] = FS / CLK1
Confidential
[0] NDIV: QUAD FS216x4 control. Coding of the input divider, if NDIX is set to:
0: Input frequency is 27 MHz (24 MHz and 30 MHz).
1: Input frequency is 54 MHz.
1. SELSDIV3 functionality is not supported by the Quad FS analog IP. Hence, whether SELSDIV3 is 0 or 1 does not in any
way affect the FS operation.
SELBW_X4[1:0]
NSB_X4[3:0]
RESERVED
RESERVED
SELSDIV3
POFF_X4
NRST
NDIV
Address: SysServBaseAddress + 0x0050
Type: R/W
Reset: 0xF10
Description: FS216_B set up configuration register (required F10).
Information classified Confidential - Do not copy (See last page for obligations)
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[31:12] RESERVED
[11:8] NSB_X4[3:0]: Active low standby for digital parts of frequency synthesizer.
NSB[0] = FS / CLK1
[7] SELSDIV3(1): Common div3 control.
en
0: Disable
1: Enable
Confidential
[4] NRST: Active low reset of digital part of frequency synthesizer (gated with reset).
[3] POFF_X4: QUAD FS216 x 4 control
0: Analog part switched ON.
1: Analog part switched OFF.
on
[2:1] RESERVED
[0] NDIV: QUAD FS216 x 4 control. Coding of the input divider, if NDIX is set to:
0: Input frequency is 27 MHz (24 MHz and 30 MHz).
1: Input frequency is 54 MHz.
C
1. SELSDIV3 functionality is not supported by the Quad FS analog IP. Hence, whether SELSDIV3 is 0 or 1 does not in any
way affect the FS operation.
RESERVED
RESERVED
SEL_OUT
EN_PRG
OP_EN
SDIV3
SDIV
MD
Address: SysServBaseAddress + 0x014
Type: R/W
Reset: 0x0AF1
Description: FS216 x 4 set up configuration register for channel 1. The required frequency of
channel 1 (clk_spare) is 27 MHz.
Information classified Confidential - Do not copy (See last page for obligations)
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[31:13] RESERVED
[12] SDIV3: Div3 control option.
0: Disable
1: Enable
en
This is inverted to the quad frequency synthesizer macro for backwards compatibility.
[11] OP_EN: Output enable for CLK.
Confidential
0: Output disable
1: Output enable
fid
EN_PRG has no effect for PIX_CLK, PCM_CLK and SPDIF_CLK clocks. The EN_PRG pin for
these channels is controlled by the DCO_MODE_CFG register.
[4:0] MD: Coarse selector bus for digital algorithm of the phase taps choice.
RESERVED
RESERVED
SEL_OUT
EN_PRG
OP_EN
SDIV3
SDIV
MD
Address: SysServBaseAddress + 0x020 + (n-2) * 0x010 (where n = 2 to 4)
Type: R/W
Reset: 0xB31, 0xB31, 0x0AF1
Description: FS216 x 4 set up configuration registers for channel 2, 3 and 4. The required
frequency of:
Information classified Confidential - Do not copy (See last page for obligations)
channel 2 (CLK_PCM) is 13.8 MHz,
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channel 3 (CLK_SPDIF) is 13.8 MHz,
channel 4 (CLK_DSS) is 27 MHz.
en
[31:13] RESERVED
[12] SDIV3: Div3 control option.
Confidential
0: Disable
1: Enable
fid
This is inverted to the quad frequency synthesizer macro for backwards compatibility.
[11] OP_EN: Output enable for CLK.
0: Output disable
1: Output enable
on
RESERVED
RESERVED
SEL_OUT
EN_PRG
OP_EN
SDIV3
SDIV
MD
Address: SysServBaseAddress + 0x054
Type: R/W
Reset: 0xAB1
Description: FS216 x 4 set up configuration register for channel 5. The required frequency for
channel 5 (CLK_PIX) is 54 MHz. Recommended frequency is 27 MHz. Hence,
Information classified Confidential - Do not copy (See last page for obligations)
program the value 0x0EBF.
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[31:13] RESERVED
[12] SDIV3: Div3 control option.
0: Disable
en
1: Enable
This is inverted to the quad frequency synthesizer macro for backwards compatibility.
Confidential
1: Output enable
This bit should always be set at 1.
[10] RESERVED
[9] SEL_OUT
on
[5] EN_PRG: New incoming data (ME and PE) are taken into account when set to 1.
EN_PRG has no effect for PIX_CLK, PCM_CLK and SPDIF_CLK clocks. The EN_PRG pin for
these channels is controlled by the DCO_MODE_CFG register.
[4:0] MD: Coarse selector bus for digital algorithm of the phase taps choice.
RESERVED
RESERVED
SEL_OUT
EN_PRG
OP_EN
SDIV3
SDIV
MD
Address: SysServBaseAddress + 0x060 + (n - 6) * 0x010 (where n = 6 to 8)
Type: R/W
Reset: 0xAF1, 0xAF1, 0x0AB3
Description: FS216 x 4 set up configuration registers for channel 6, 7 and 8. The required
frequency for:
Information classified Confidential - Do not copy (See last page for obligations)
channel 6 (CLK_FDMA_FS) is 27 MHz,
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channel 7 (auxiliary clock) is 27 MHz,
channel 8 (CLK_USB) is 48 MHz.
en
[31:13] RESERVED
[12] SDIV3: Div3 control option.
Confidential
0: Disable
1: Enable
fid
This is inverted to the quad frequency synthesizer macro for backwards compatibility.
[11] OP_EN: Output enable for CLK.
0: Output disable
1: Output enable
on
RESERVED PE
Information classified Confidential - Do not copy (See last page for obligations)
[31:16] RESERVED
l
[15:0] PE: Fine selector bus for digital algorithm of the phase taps choice.
FS216X4_CLKn_SETUP1
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6
Clock set up 1
5 4 3 2 1 0
en
RESERVED PE
Confidential
[31:16] RESERVED
[15:0] PE: Fine selector bus for digital algorithm of the phase taps choice.
RESERVED PE
Information classified Confidential - Do not copy (See last page for obligations)
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[31:16] RESERVED
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[15:0] PE: Fine selector bus for digital algorithm of the phase taps choice.
RESERVED PE
Confidential
Type: R/W
Reset: 0x1C72, 0x1C72, 0x0000
Description: FS216 x 4 set up configuration registers for channel 6, 7 and 8. The required
on
frequency for:
channel 6 (CLK_FDMA_FS) is 27 MHz,
channel 7 (auxiliary clock) is 27 MHz,
C
[31:16] RESERVED
[15:0] PE: Fine selector bus for digital algorithm of the phase taps choice.
RP_SEL_ETHERNET
RP_SEL_ST40_PCK
RP_SEL_ST40_ICK
RP_SEL_SPARE
RP_SEL_FDMA
RP_SEL_DDR
RP_SEL_SYS
RP_SEL_LMI
RP_SEL_BIT
RP_SEL_AV
RESERVED
RESERVED
PLL_SEL
Address: SysServBaseAddress + 0x0114
Information classified Confidential - Do not copy (See last page for obligations)
Type: R/W
l
Reset: 0x0000
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Description: Select reduced power mode. Bit[11] of this register configures all dividers to reduced
power mode. Bits[10:0] configures all dividers to reduced power mode on an
individual basis and selects reduced power mode for a particular programmable
divider.
en
Confidential
[31:12] RESERVED
[11] PLL_SEL: Select reduced power for all programmable dividers.
fid
General information:
Bit[1] or bit[5]) = DDR reduced power
Bit[1] is for LMI clock and bit[5] is for DDR clock.)
[4] RP_SEL_FDMA: Select reduced power for CLK_FDMA.
[3] RP_SEL_SYS: Select reduced power for CLK_SYS, which is being shared and going to
multiple locations.
[2] RP_SEL_BIT: Select reduced power for CLK_BIT.
[1] RP_SEL_LMI: Select reduced power for CLK_LMI.
[0] RESERVED
LP_MODE_PLL_DIS
LP_MODE_DIV_DIS
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
Type: R/W
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Reset: 0x07F5
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Description: Clock divider low power control register.
[31:13] RESERVED
en
[12:11] LP_MODE_PLL_DIS: Disables PLL clocks when in the standby mode.
Confidential
LP_MODE_FS216X4_DIS
LP_MODE_SYNTH_DIS
Address: RESERVED
SysServBaseAddress + 0x011C
Type: R/W
Information classified Confidential - Do not copy (See last page for obligations)
Reset: 0x00FF
l
Description: Frequency synthesizer low power control register.
[31:10] RESERVED
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[9:8] LP_MODE_FS216X4_DIS: Disable frequency synthesizer clocks when in the standby mode.
en
This is to give lower power requirements in the standby mode: 10 mW max (analog), 8 mW max
(digital).
Confidential
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LP_COUNT
[31:16] RESERVED
[15:0] LP_COUNT: Low power count. Binary coded.
LP_COUNT[19:0]. Maximum count of 1048576 seconds.
LP_COUNT_ENABLE
LP_COUNT[19:16]
RESERVED
Address: SysServBaseAddress + 0x0124
Type: R/W
Reset: 0x000F
Information classified Confidential - Do not copy (See last page for obligations)
Description: Low power count value and low power enable.
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[31:5] RESERVED
[4] LP_COUNT_ENABLE: Low power counter enable.
en
[3:0] LP_COUNT[19:16]: Low power count value programmed by comms subsystem through
interconnect. Binary coded.
Confidential
16.6.1 CLK_LP
on
RTCS_LSB
C
[31:0] RTCS_LSB(1): LSW and MSW of RTC_LP register except during the low power mode and
when writing a new value to the RTC.
1. This is overwritten by the counter on the first CLK_LP after reset removal.
RTCS_MSB
[31:0] RTCS_MSB(1): LSW and MSW of RTC_LP register except during the low power mode and
Information classified Confidential - Do not copy (See last page for obligations)
when writing a new value to the RTC.
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1. This is overwritten by the counter on the first CLK_LP after reset removal.
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RTCS_CONTROL_LP Low power timer control
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC_START_REG
en RESERVED
Confidential
fid
Reset: 0x0000
Description: Low power timer control.
[31:1] RESERVED
C
[0] RTC_START_REG
0: Does not stop counting
1: Starts RTC_LP counting
16.6.2 CLK_27
RTCS_LSB
Information classified Confidential - Do not copy (See last page for obligations)
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[31:0] RTCS_LSB(1): LSW and MSW of RTC_27 register except during the low power mode and
tia
when writing a new value to the RTC.
1. This is overwritten by the counter on the first rtc27 tick after reset removal.
RTCS_MSB
fid
[31:0] RTCS_MSB(1): LSW and MSW of RTC_27 register except during the low power mode and
when writing a new value to the RTC.
C
1. This is overwritten by the counter on the first rtc27 tick after reset removal.
RTC_START_REG
RESERVED
Address: SysServBaseAddress + 0x0218
Type: R/W
Reset: 0x0000
Information classified Confidential - Do not copy (See last page for obligations)
Description: Low power timer control.
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[31:1] RESERVED
[0] RTC_START_REG
0: Does not stop counting
en
1: Starts RTC_27 counting
Confidential
SYNTHESIZER_MODE
on
RESERVED
C
[31:1] RESERVED
[0] SYNTHESIZER_MODE: DCO FSM control bit.
0: Program complete/switch to glitch free clock.
1: Program EN/PE/MD bits.
[31:0] DCO_SD_CNT: DCO SD reference count load value is read when DCP_CMD/LD is 1 or
SD_COUNT is 0.
Information classified Confidential - Do not copy (See last page for obligations)
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DCO_CMD DCO command
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
INT
LD
en
Confidential
Reset: 0x0001
Description: DCO command register.
on
[31:2] RESERVED
[1] INT: Interrupt
When read:
C
0: No interrupt
1: Interrupt
When 1 is written to this bit, the interrupt is cleared and the bit must return to 0 to allow correct
operation.
[0] LD: Reference counter load.
0: Allows counting.
1: Loads reference counter (SD) with DCO_SD_COUNT and PCM/HD count loaded with zero.
DCO_PCM_CNT
Information classified Confidential - Do not copy (See last page for obligations)
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DCO_HD_COUNT DCO HD count value
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DCO_HD_CNT
en
Address: SysServBaseAddress + 0x016C
Type: R
Confidential
Reset: 0x00000000
fid
SC_CTRL_SMARTCARD1_DISAB
SC_CTRL_SMARTCARD0_DISAB
SC_CTRL_SMARTCARD1_EN
SC_CTRL_SMARTCARD0_EN
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
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Address: SysServBaseAddress + 0x0144
Type: R/W
Reset: 0x0000
en
Description: Smartcard power control.
Confidential
[31:4] RESERVED
fid
smartcard1.
0: Enable non-inverted sense
1: Enable inverted sense
[1] SC_CTRL_SMARTCARD0_DISABLE: Disable smartcard power control for smartcard0.
C
0: Disable
1: Enable
[0] SC_CTRL_SMARTCARD0_EN: Enable non-inverted/inverted sense power control for
smartcard0.
0: Enable non-inverted sense
1: Enable inverted sense
TST_SCANMODE_RESET_STATUS
LONG_TIMEOUT_RESET_STATUS
RESET_LONGTIME_IN_SENSE
SC_DETECT_RESET_STATUS
RESET_SC_OUT_SENSE
RESET_MASK_BITS[2:0]
RESET_SELECT_ALT
RST_N_PAD_STATUS
WD_RESET_STATUS
RESERVED
RESERVED
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
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Address: SysServBaseAddress + 0x0140
Type: R/W
Reset: 0x05C0
en
Description: Reset status.
Confidential
[31:14] RESERVED
fid
[13] RESET_LONGTIME_IN_SENSE
0: Active high 1: Active low
[12] RESET_SC_OUT_SENSE
0: Active high 1: Active low
on
(1):
[11] RESET_SELECT_ALT Select 200 ms reset for all reset sources. Alternate reset
capabilities.
0: Select 200 ms reset pulse 1: Select other resets
[10:9] RESERVED
C
[8:6] RESET_MASK_BITS[2:0]:
0: No mask on reset 1: Mask on reset
bit[6] mask for watchdog reset. bit[7] mask for long time reset.
bit[8] mask for smartcard detect reset.
[5] TST_SCANMODE_RESET_STATUS(2):
0: No scanmode reset asserted 1: Scanmode reset asserted
(2)
[4] RST_N_PAD_STATUS
0: No pad reset asserted 1: Reset state
(2)
[3] SC_DETECT_RESET_STATUS
0: No smartcard detect reset asserted 1: Smartcard detect reset asserted
[2] RESERVED
[1] LONG_TIMEOUT_RESET_STATUS(2)
0: No long time out reset asserted 1: Long time out reset asserted
(2)
[0] WD_RESET_STATUS
0: No watchdog reset asserted 1: Watchdog reset asserted
1. Do not select this within 200 ms of a normal non 200 ms reset as it will go into another reset.
2. To clear status bits[5:0], write 0 operation followed by write 1 operation for that bit is required to clear it.
RESERVED WD_COUNT
Information classified Confidential - Do not copy (See last page for obligations)
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[31:16] RESERVED
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[15:0] WD_COUNT: Watchdog program value. Binary coded.
Maximum count of 1048576 seconds. This does not record the current watchdog count.
SC1_RDP_CONTROL_ENABLE
SC0_RDP_CONTROL_ENABLE
SC_DETECT_SENSE
fid
SC_INS_RST_EN
RESERVED
on
Type: R/W
Reset: 0x0000
Description: Smartcard insertion reset control.
[31:6] RESERVED
[5] SC1_RDP_CONTROL_ENABLE
SC1_RDP_CONTROL_ENABLE active high onto O_SYS_SER_SPARE[1]. When high,
override all other functional controls on SC0 set of pads.
[4] SC0_RDP_CONTROL_ENABLE
SC0_RDP_CONTROL_ENABLE active high onto O_SYS_SER_SPARE[0]. When high,
override all other functional controls on SC0 set of pads.
Note: Software should always set bit[1] and bit[3] to 0 value. Software should never assert
the reset generation for smartcard 1.
Information classified Confidential - Do not copy (See last page for obligations)
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WATCHDOG_COUNTER_CFG1 Watchdog counter 1
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD_COUNT_ENABLE
WD_COUNT[19:16]
RESERVED
en
Confidential
fid
[31:5] RESERVED
C
CPU_INT_COUNT_CONFIG
CPU_INT_STATUS
RESERVED
Information classified Confidential - Do not copy (See last page for obligations)
Address: SysServBaseAddress + 0x0150
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Type: R/W
Reset: 0x000A
Description: CPU interrupt control configuration.
en
[31:8] RESERVED
Confidential
1: Interrupt reached
Writing 0 clears interrupt and status.
Writing from 0 to 1, loads a new count value and the count is started. Leave at 1 to continue
counting.
on
DP_CONTROL_TSMERGER_SYS
DP_CONTROL_AUD_DECODER_
DP_CONTROL_ETHERNET_SYS
DP_CONTROL_TILERAM_SYS
DP_CONTROL_LCMPEG_SYS
DP_CONTROL_GDMA_SYS
DP_CONTROL_FDMA_SYS
DP_CONTROL_PDES_SYS
DP_CONTROL_CLKBDISP
DP_CONTROL_CLKFDMA
DP_CONTROL_BLIT_SYS
DP_CONTROL_USB_SYS
DP_CONTROL_FMI_SYS
DP_CONTROL_PTI_SYS
DP_CONTROL_CLKUSB
DP_CONTROL_SPARE
DP_CONTROL[0]
Information classified Confidential - Do not copy (See last page for obligations)
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Address: SysServBaseAddress + 0x0128
Type: R/W
Reset: 0x0000
en
Description: Dynamic power control capability for the full chip.
Confidential
[31:16] DP_CONTROL_SPARE: Spare bits to further support clock gating and power within the chip.
fid
Information classified Confidential - Do not copy (See last page for obligations)
[3] DP_CONTROL_AUD_DECODER_SYS: Audio decoder clock gating control for CLK_SYS.
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0: No clock gating, normal clock.
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1: Power down, clock is stopped to the IP/system concerned.
[2] DP_CONTROL_USB_SYS: USB clock gating control for CLK_SYS.
0: No clock gating, normal clock.
1: Power down, clock is stopped to the IP/system concerned.
en
[1] DP_CONTROL_GDMA_SYS: GDMA clock gating control for CLK_SYS.
Confidential
Note: For the top-level SoC integrator, use inverter and cbuf cells as shown in Figure 27.
on
C
17 Interrupt system
17.1 Overview
The interrupt system allows an on-chip module or external interrupt pin to interrupt an active
process so that an interrupt handling process can be run. Interrupts are signaled by one of
the following:
● a signal on an external interrupt pin
● a signal from an internal peripheral or subsystem
● software asserting an interrupt in the pending register
Interrupts are implemented by an on-chip interrupt controller (For further details, see
Information classified Confidential - Do not copy (See last page for obligations)
Section 17.2: Interrupt controller) and an on-chip interrupt level controller (ILC) (For further
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details, see Section 17.3: Interrupt handlers). The ILC multiplexes the 46 incoming interrupt
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sources onto the 20 programmable ILC interrupt level inputs (16 to the CPU and 4 available
externally). Multiplexing is controlled by software. An overview of the interrupt system is
shown in the following figure:
Interrupt
To PIO3[0:3] controller
interrupt steering output Four external, off chip interrupts
NMI
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IRL[3:0]
System services Wake up interrupt Priority encoder
Comms
ILC
on
Internal LPC
External
(16 interrupt levels)
wake up
Comms Infrared
module
transmitter
/receiver
C
Comms
irq
TVOut Transport
FDMA Blitter
Pins INTERRUPT[3:0] can be connected to both the interrupt steering outputs or the four
external interrupt inputs.
Note: The four remote OFF chip interrupts are routed from the ILC to PIO3 pads, two of which are
routed are as DMAREQ, PIO3[0,1] and two are routed as external interrupts
EXT_INT_OUT, PIO3[0] and PIO3[4].
External interrupts
● NMI: external interrupt source.
● IRLINT: four eternal interrupt sources IRL0 to IRL3, which can be configured as four
independent interrupts or encoded to provide 15 external interrupt levels.
These interrupts are managed by the INTC interrupt controller integrated into the ST40-300
CPU core.
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The four external asynchronous interrupts are routed to the ILC3 interrupt controller before
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reaching the ST40 in order to synchronize and change the polarity, if needed.
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Internal peripheral interrupts
● On-chip peripherals interrupt sources.
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The INTC controls all the on-chip peripherals interrupts.
All interrupts (except NMI) are assigned a priority level between 0 and 15: level 15 is the
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highest and level 1 the lowest, level 0 means that the interrupt is masked. The NMI is
defined to have a fixed priority level of 16.
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When the priorities for multiple interrupt sources are set to the same level and such
interrupts are generated at the same time, they are handled according to the default order
listed in Table 55.
Updating of interrupt priority level setting registers A, B, C and D should only be performed
whilst the BL bit in SR is set to 1. To prevent erroneous interrupt acknowledgment, first read
any of the interrupt priority level setting registers, then clear the BL bit to 0. This secures the
necessary timing internally.
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NMI - 0x1C0 16 - - High
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IRL3 to IRL0 = F 0x200 15 - -
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IRL3 to IRL0 = E 0x220 14 - -
IRL3 to IRL0 = D 0x240 13 - -
IRL3 to IRL0 = C 0x260 12 - -
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IRL3 to IRL0 = B 0x280 11 - -
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Table 55. ST40 core interrupt exception vectors and rankings (continued)
Interrupt Priority
INTEVT IPR (bit Default
Interrupt source priority (initial within IPR
code numbers) priority
value) setting unit
0x460
0x480
0x4A0
0x4C0
Reserved(2) -
0x700
0x740
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0x760
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0x780
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WDT ITI 0x560 15 to 0 (0) IPRB[15:12] - -
- Reserved 0x3E0 -
Other interrupts are device specific.
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1. Default priority position of external interrupts using the expander. The details of interrupts in this group are an integration
option.
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2. These INTEVT codes are used by CSP modules present in other ST40 series. These codes should be avoided when
allocating new codes for cascaded interrupt controllers to avoid potential software conflicts.
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ST40-C230 IRQ
(CPU core)
C
INTC
ILC (comms)
On-chip
peripherals
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interrupt request signal to the CPU.
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4. The CPU receives an interrupt at a break in instructions.
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5. The interrupt source code is set in INTEVT.
6. SR and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD) and register bank bit (RB) in SR are set to 1.
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8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in
the vector base register (VBR) and 0x0000 0600). The interrupt handler may branch
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with the INTEVT register value as it is offset to identify the interrupt source. This
enables it to branch to the handling routine for the individual interrupt source.
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Note: 1 The interrupt mask bits[I3:I0) in SR are not changed by acceptance of an interrupt in the
CPU.
2 The interrupt source flag should be cleared in the interrupt handler. To ensure that an
interrupt request that should have been cleared is not inadvertently accepted again, read
on
the interrupt source flag after it has been cleared, before clearing the BL bit or executing an
RTE instruction.
To handle nested interrupts, an interrupt handler should include the following procedure:
1. Branch to a specific interrupt handler corresponding to a code set in INTEVT. The code
in INTEVT can be used as a branch-offset for branching to the specific handler.
2. Clear the cause of the interrupt in each specific handler.
3. Save SSR and SPC to memory.
4. Clear the BL bit in SR and set the accepted interrupt level in the interrupt mask bits in
SR.
5. Handle the interrupt.
6. Set the BL bit in SR to 1.
7. Return the SSR and SPC from memory.
8. Execute the RTE instruction.
When this procedure is followed in order, an interrupt of higher priority than the 1 being
handled can be accepted after clearing BL in step 4.
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of the 16 levels in the interrupt controller. This disables the interrupt source from generating
an interrupt, without disabling all other interrupt sources mapped on to that interrupt level.
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This would be the case if the INC_MASK register in the interrupt controller was used.
All internal interrupts are assumed to be level sensitive and active high.
Each external interrupt source can be used to trigger an interrupt and can be programmed
to trigger on rising or falling (or either) edges or on the high or low logic level of the incoming
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interrupt source signal. This is controlled by writing to the ILC_MODEn registers.
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The default state of the interrupt level controller trigger mode registers is no trigger,
therefore, these registers need to be programmed if external interrupts are to be enabled.
The default state of the enable registers is low, therefore these registers need to be
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interrupt level controller may conflict. The ILC_INPUT_INTERRUPTn register has the same
function as in the STi5500, STi5505, STi5508, STi5518 and can be used to indicate the
current logic state of all the interrupt sources. This register is just a buffered version of the
interrupt source signals before the trigger mode detection stage. ILC_INPUT_INTERRUPTn
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does not latch the signal, as the ILC_STATUSn register does, for interrupt sources defined
with an edge sensitive trigger mode. The ILC_STATUSn register is more useful because of
this feature, as it can be read by the interrupt handler software routine to determine which
interrupt sources have triggered.
For example, if the interrupt source is external and provides a pulse, the interrupt level
controller would have the interrupt source trigger mode set to be rising edge. On a rising
edge, the corresponding bit in the ILC_STATUSn register would be set high and would
remain set until explicitly cleared by the interrupt handler routine writing to the
corresponding bit in the ILC_CLEAR_STATUSn register. However if the pulse was short, by
the time the interrupt handler was executed and had read the ILC_INPUT_INTERRUPTn
register, the pulse may have returned to a logic low and the bit would be read as zero. Thus,
the cause of interrupt could not be determined if more than one interrupt source had been
multiplexed on to the interrupt level.
So now, using the ILC_STATUSn register, it is possible to multiplex interrupt sources of
different types, including edge sensitive, on to the same interrupt level in the interrupt
controller.
The STi5189 interrupt level controller also has two registers mapped into its register
address space, which have no connection with normal interrupt operation. These registers
control the wake up of the CPU by an external interrupt pin, when it has been put into low
power mode, by the low power controller module. The register INC_SELNOTINV controls
whether the four external interrupt pins are active high or low, to wake up the CPU from low
power mode. The setting of this register has no effect on the triggering of the external
interrupt pins in the interrupt level controller. The register INC_EN_INT is a mask register to
enable or disable the external interrupt pins from waking up the CPU from low power mode.
Again, this has no effect on the masking of these interrupts in the interrupt level controller.
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assigned as shown in the following table:
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Table 56. STi5189 interrupt assignments
INT n Peripheral Description of the function
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31 Reserved Reserved
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32 VTG 1 TVOut
33 VTG 2 TVOut
34 FDMA FDMA interrupts
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35 BLIT CQ1 Blitter
36 BLIT CQ2 Blitter
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External inputs
64
ExtIntIn0
(EXT0)
From external devices
65(EXT1) ExtIntIn1
66(EXT2) ExtIntIn2
67(EXT3) Reserved -
68
IR wake up From pins through pulse stretcher
(EXT4)
69 to 70 Reserved -
External outputs
0(EXT0) ExtIntOUT0
To external devices dmareq_to_pads
1 (EXT1) ExtIntOUT1
2 to 5 Reserved -
6 (EXT6) FDMA REQ0 External DMA request to pad
7 (EXT7) FDMA REQ1 External DMA request to pad
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Wake up Wake up Wake up system services
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0 to 15 C1 interrupts
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0x0000 INTC_ICR Interrupt control page 246
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0x0004 INTC_IPRA Interrupt priority level A page 247
0x0008 INTC_IPRB Interrupt priority level B page 247
0x000C INTC_IPRC Interrupt priority level C page 247
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0x0010 INTC_IPRD Interrupt priority level D page 248
(2)
Interrupt level controller registers
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RESERVED
RESERVED
NMIB
NMIE
NMIL
IRLM
MAI
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detection mode for external interrupt input pin NMI and indicates the input signal level
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at the NMI pin. This register is initialized by a power-on reset or manual reset. Initial
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value is 0x8000 when the NMI pin is high, 0x0000 when the NMI pin is low.
[15] NMIL: NMI interrupt level. Reports the level of the signal input at the NMI pin. This bit can be
read to determine the NMI pin level. It cannot be modified.
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0: NMI input level is low
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[9] NMIB: NMI block mode. Selects whether NMI requests are held pending or immediately
detected when the SR.BL bit is 1. If an interrupt request is accepted while SR.BL = 1, the
previous exception information is lost, so should be saved beforehand. This bit is cleared
automatically when an NMI interrupt is accepted.
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[15:12] TMU0:
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[11:8] TMU1:
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[7:4] TMU2:
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[3:0] RESERVED:
WDT RESERVED
Type: R/W
Description: Interrupt priority level B register. This register is initialized by a power-on reset or
manual reset. Initial value is 0x0000.
on
[15:12] WDT:
[11:0] RESERVED:
C
RESERVED UDI
[15:4] RESERVED:
[3:0] UDI:
[15:12] IRL0:
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[11:8] IRL1:
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[7:4] IRL2:
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[3:0] IRL3:
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18.2 Interrupt level controller registers
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ILC_INPUT_INTER
RESERVED EXT[7:0]
RUPT0
ILC_INPUT_INTER
on
RESERVED
RUPT1
ILC_INPUT_INTER
RESERVED INT[43:32]
RUPT2
ILC_INPUT_INTER
INT[31:0]
RUPT3
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ILC_STATUS1 RESERVED
ILC_STATUS3 INT[31:0]
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Description: ILC status registers
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The status of the interrupt numbers is inferred by reading this register. The bit in the
status register is at logic 1 on the following conditions:
– If the corresponding interrupt number is internal (synchronous), then the
interrupt number should be at logic 1.
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– If the corresponding interrupt number is external (asynchronous), then the
interrupt number should match the programmed trigger condition.
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There are two status registers from 0x200 to 0x27C. The contents of this register are
at logic 0 on reset.
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ILC_CLEAR_STA
RESERVED EXT[7:0]
TUS0
ILC_CLEAR_STA
RESERVED
TUS1
ILC_CLEAR_STA
RESERVED INT[43:32]
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TUS2
ILC_CLEAR_STA
INT[31:0]
TUS3
ILC_ENABLE1 RESERVED
ILC_ENABLE3 INT[31:0]
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Description: Enable registers. Interrupt generation from an interrupt number is enabled only if the
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corresponding bit in the enable register is set to logic 1. The contents of this register
are at logic 0 on reset.
There are two enable registers at 0x400 and 0x404.
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ILC_CLEAR_ENABLEn Clear enable locations
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ILC_CLEAR_E
RESERVED EXT[7:0]
NABLE0
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ILC_CLEAR_E
RESERVED
NABLE1
ILC_CLEAR_E
RESERVED INT[43:32]
NABLE2
ILC_CLEAR_E
on
INT[31:0]
NABLE3
Reset: Undefined
Description: Clear enable locations. Any bit in the enable register can be cleared by performing a
clear bit operation on the appropriate location.
There are two locations at 0x480 and 0x484 corresponding to respective enable
registers.
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Reset: Undefined
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Description: Set enable locations. Any bit in the enable register can be set by performing a set bit
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operation on the appropriate location (set bit operation is performing a write operation
with logic 1 on the data bus corresponding to the location which has to be set).
There are two locations at 0x500 and 0x504 corresponding to respective enable
registers.
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ILC_WAKEUP_ENABLE Wake up enable
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Reset: 0
Description: This register is used to enable the external interrupt (asynchronous) for wake up by
interrupt generation. Only the locations corresponding to external interrupts are valid.
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The external interrupt enables the wake up by interrupt generation only if the
corresponding bit in this register is set to logic 1. The contents of this register are set
to logic 0 on reset.
The location at 0x604 corresponds to respective interrupt numbers.
Note: Interrupts EXT4 to EXT7 are not valid outputs, see Table 56: STi5189 interrupt
assignments for a list of interrupt numbers.
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interrupt pin is at logic 0. The contents of this register are set to logic 1 on reset.
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The location at 0x688 corresponds to respective interrupt numbers.
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Note: Interrupts EXT4 to EXT7 are not valid outputs, see Table 56: STi5189 interrupt
assignments for a list of interrupt numbers.
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ILC_PRIORITYn ILC priority
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED PRIORITY_LEVELS_0_TO_15
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Reset: 0
Description: The priority register assigns the interrupt number to one of the available interrupt
levels. The assignment is done by writing appropriate word into the priority register.
Bits[14:4] must be set to 0 all the time.
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To map an interrupt number on the interrupt level of a local processor (ST40 core), a
value between 0x0000 to 0x7FFF needs to be written. For example, the ST40 core
has 16 interrupt levels, values between 0x0000 to 0x000F are valid. Other values
from 0x0010 to 0x7FFF are invalid.
To map an interrupt number on the interrupt level of an external processor, a value
between 0x8000 to 0xFFFF has to be written. ILC can only map on to four interrupt
levels of an external processor, therefore, the values between 0x8000 to 0x8003 are
valid. Other values from 0x8004 to 0xFFFF are invalid.
For example,
If bit[15] is set to 1, bits 0 and 1 are used to determine which of the four external
interrupts is to be set.
If bit[15] is set to 0, bits 0 to 3 are used to determine which of the 16 interrupt levels
are to be set.
The register is set to 0x0000 on reset. The address of the priority register
corresponding to interrupt number n is at 0x800 + (n x 0x008).
RESERVED MODE[2:0]
RESERVED MODE[2:0]
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mode register is present for internal interrupts. All the internal interrupt numbers are
assumed active high.
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– The trigger modes can be programmed to appropriate trigger levels by writing
the values as shown in the following table. Use the syntax 0xnnnn nnnn for the
address.
– Include the values outside the address range.
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ILC_MODE0: [31:3]
RESERVED
ILC_MODE1: [31:3]
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RESERVED MODE[2:0]
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– The trigger modes can be programmed to appropriate trigger levels by writing
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the values as shown in the following table. Use the syntax 0xnnnn nnnn for the
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address.
– Include the values outside the address range.
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[31:3] RESERVED
[2:0] MODE[2:0]
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100: Falling edge trigger mode 101: Any edge trigger mode
110: No trigger mode 111: No trigger mode
19 Memory system
The STi5189 has a fully unified memory system based on 16-bit SDRAM main memory.
Information classified Confidential - Do not copy (See last page for obligations)
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Table 58. Internal peripheral base addresses
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Target name Start offset End offset Size
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2. To be decoded on FMI port.
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3. To be decoded on LMI ports.
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Note: Address ranges which are not assigned to any IP are reserved and any access to these
addresses get R_OPC[0] = 1.
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on
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The STi5189 on-chip peripherals are mapped in area 6 of the ST40 in 29-bit mode. The
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STi5189 memory and peripheral mapping is shown in the following figure:
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Figure 36. STi5189 memory and peripheral mapping
0x0000 0000
FMI 128 MB
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0x0800 0000
Tile SRAM Bank 0
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0x0880 0000
RESERVED
Bank 2
on
RESERVED
RESERVED
0x4000 0000
Bank 3
LMI 1024 MB
(32 bit)
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0x8000 0000
RESERVED
0xFC00 0000 DDR 128 MB
ST40 core debug 16 MB (max)
0xFD00 0000
On chip ST40 32-bit addressing mode
peripherals 32 MB
0xFF00 0000
ST40 core 16 MB
peripherals
0xFFFF FFFF
Note: The path to the LMI in the STBus nodes has to consider the two LMI address ranges (29-
and 32-bit)
20 Electrical specifications
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VDDE3V3
For 8 volts -0.5 8.8 V
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LMI supply voltage for 2.5 V DDR -0.5 4.44 V
VDD33_25
LMI supply voltage for 3.3 V SDR -0.5 5.45 V
VDD1V0 1.0 V supply for core and analog -0.5 1.78 V
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VDD1V0_FE Common supply for AD12, FEOSC and FEPLL -0.5 1.78 V
VDDA2V5_BE Common supply for FS and PLL -0.5 4.44 V
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VCCA2V5_DACS Common supply for audio and video DACs -0.5 4.44 V
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(2)
VESD_RCDM Electrostatic discharge voltage - JESD22-C101 - Class I -
1. AC transient overshoot of 0.7 V above VDD33 + 0.5 V is allowed for a maximum period of 2 ns.
2. For a definition of the ESD classes, see the relevant JEDEC standards or contact STMicroelectronics customer support.
Note: 1 These AMR values are applicable to all pins powered to the given voltage.
2 These are the maximum limits. Exceeding them may result in permanent damage to the
device. Operation at these limits is not intended.
3 Stresses greater than those listed in Table 59 may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other
conditions outside those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
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VCCA2V5_DACS Common supply for audio and video DACs 2.3 2.5 2.7 V -
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VCCA2V5_FE 2V5 analog supply of the front end. 2.3 2.5 2.7 V -
ADAC_VCCAH Audio DAC Output buffer power supply 7.2 8.0 8.8 V -
I3V3 3.3V I/O supply current - 0.040 0.050 A 1, 2, 3
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I33_25 LMI supply current at 2.6V - 0.035 0.040 A 1, 2, 3
Combined 1V0 supply current:
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Note: 1 The power consumption depends on chip activity and silicon temperature. Silicon
temperature depends on the PCB layout. The values in this table are measured in the ST
application environment and may vary from one application to another.
2 Typical values correspond to the power consumption for standard devices at typical voltage
conditions at an ambient temperature of 70 ° C.
3 Maximum current values correspond to the maximum power consumption for corner devices
with maximum power supplies at an ambient temperature of 70 ° C.
4 All IP’s powered down with the exception of the ST40, timers and interrupt handler running
at a reduced clock speed, the DDR in self-refresh mode and with the LMI pad supply
VDD33_25 powered down.
5 Typical value corresponds to the power consumption of standard devices at typical voltage
conditions at an ambient temperature of 25 ° C.
6 Maximum value corresponds to the power consumption for corner devices at maximum
voltage conditions at an ambient temperature of 25 ° C.
7 DDR is running at 200 MHz.
Information classified Confidential - Do not copy (See last page for obligations)
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.
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Symbol Parameter Min Typical Max Units
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● QPSK
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Table 62. Standard digital 3.3 V pad DC specifications
Symbol Parameter Min Typical Max Units Note
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VIH Logic 1 (high-level) input voltage 2.0 - VDD33 + 0.5 V -
VIL Logic 0 (low-level) input voltage -0.5 - 0.8 V -
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pins)
COUT Output capacitance - - 15 pF -
VHYS Schmitt trigger hysteresis voltage 0.495 - 0.62 V 3
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VIH(DC) DC input logic high (VIN) VREF + 0.15 - VDD33_25 + 0.3 V -
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VIL(DC) DC input logic low (VIN) -0.3 - VREF - 0.15 V -
VIH(AC) AC input logic high (VIN) VREF + 0.31 - VDD33_25 + 0.3 V -
VIL(AC) AC input logic low (VIN) Vss - 0.3 - VREF - 0.31 V -
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VOH Output logic 1 voltage VREF + 0.76 - V -
VOL Output logic 0voltage - - VREF - 0.76 V -
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(1)
Output rise slew rate 1.0 - 4 V/ns
SRR
0.5 - 4 - -
1.0 - 4 V/ns (2)
SRF Output fall slew rate
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0.5 - 4 - -
Freq Operational frequency - - 200 MHz -
1. Vout from VREF - 0.76 V to Vref + 0.76 V
2. Vout from VREF + 0.76 V to Vref - 0.76 V
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0.3
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VDD33_25 = 3.135V
2 - -
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Iout = -12mA
VDD33_25 = 3.135V
VOH Output logic 1 voltage 2.4 - - V
Iout = -12mA
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VDD33_25 = 3.135V
2.8 - -
Iout = -100uA
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VDD33_25 = 3.135V
- - 0.45
Iout = -12mA
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VDD33_25 = 3.135V
VOL Output logic 0 voltage - - 0.4 V
Iout = -12mA
VDD33_25 = 3.135V
- - 0.2
Iout = -100uA
on
Information classified Confidential - Do not copy (See last page for obligations)
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Parameter Typical Unit
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SNR 90 at Fs = 44.1 kHz, 48 kHz, 96 kHz @ 2 Vrms dB
Dynamic range(1) -90 at Fs = 44.1 kHz, 48 kHz, 96 kHz @ 2 Vrms dB
66 at Fs = 44.1 kHz, 48 kHz, 96 kHz @ 2 Vrms
THD + Noise(2) dB
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72 at Fs = 44.1 kHz, 48 kHz, 96 kHz @ 1.4 Vrms
Noise floor -80 to 100 (20 Hz to 50 Hz) @ 2 Vrms dB
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Output 3 dB bandwidth @
BDW DC to 30 - - MHz
Fclk = 160 MHz
F_clk Clock speed - - 160 MHz
VCCA2V5_DACS Analog supply 2.3 2.5 2.7 V
VDD1V0 Digital supply 1.0 1.05 1.15 V
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Rref = 2.05 kOhms (code min) (code max)
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Full scale gain error Full scale gain error (5) - - +/- 7 %
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Rout DAC output resistance @ DC 100 - - kOhms
PSRR scale)
(dVout/dVvcca) Power supply rejection ratio @ 1 MHz
-26 -29 - dB
(full scale)
Table 70. Static electrical performance Rref = 7.73 kohm, Rload = 140 ohm
Symbol Parameter Min. Typ. Max. Unit
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Iout
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DAC output current 0 (code min) - 10.0 (code max) mA
Rref = 7.73 kOhms
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Full scale gain error Full scale gain error (2) - - +/- 7 %
Rout DAC output resistance @ dc 100 - - kOhms
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Note: 1 Under ideal supply conditions.
2 This value includes the 1% variation of reference resistor (Rref) and 1% of load.
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Information classified Confidential - Do not copy (See last page for obligations)
GM I/Q gain mismatch - - 4.5% -
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Table 73. Front-end ADCs AC specifications
Symbol Parameter Min Typ Max Unit
21 Timing specification
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Digital I/O
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– DMA requests on page 276
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– asynchronous serial controller on page 276
– synchronous serial controller on page 277
– infrared receiver/transmitter on page 278
● Video outputs on page 278
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● Audio outputs on page 274
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Load capacitance on the tester differs according to the way measurements are taken. In
standard mode, it is evaluated to approximately 50 pF whereas for high speed
measurements with 50 Ω termination the figure is around 15 pF.
The default drive strength setting used for all characterization and simulation work is 25 pF.
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21.1 System
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Power supplies
NOT_RESET
MODE inputs
tMODSRST
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tMODHRST
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21.1.2 Reset timing
The tRSTHRSTL value in the following figure and table is for power-on reset when the device
is cold:
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Figure 38. Reset timings
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NOT_RESET
tRSTLRSTH
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NOT_WD_RESET
tWDRSTLRSTH
Crystal requirements
The external 30 MHz crystal has the following requirements:
● 30.000 MHz fundamental frequency
● parallel resonance
● 40 ppm accuracy
Information classified Confidential - Do not copy (See last page for obligations)
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21.2 LMI interface specification
The LMI is compliant with the DDR1 JEDEC specification for operation up to 200 MHz.
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21.3 Flexible memory interface (FMI)
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All the outputs come from a multiplexer controlled by the clock. It is assumed that the FMI
will be programmed so that all the outputs will be changed on the falling edge of the clock.
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All synchronous transactions originate and terminate at flip flops within the padlogics.
Outputs are generated with respect to the falling edge of the bus clock and inputs are
sampled with respect to the rising edge of the bus clock.
FMI-clock: FMIFLASHCLK
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tFMI-clock
FMI-clock
tECHEOV
FMI-outputs
tEIVECH
tECHEIX
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FMI-inputs
tECHEOZ
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FMI tri-state
outputs
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tECHEON
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These values are static offsets within a bus cycle, they should be read in conjunction with
the waveforms in flexible memory interface (FMI), which are cycle accurate only.
Parallel 27 Mbit/s 37 ns
Serial 100 Mbit/s 10 ns
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Figure 41. Parallel transport stream input timings (27 Mbyte/s input rate)
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tLCLLCL
TS0INBITORBYTECLK
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tLCLLCL tLCHLCH
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TS0INBITORBYTECLKVALID
TS0INDATA[7:0]
TS0INPACKETCLK
on
tLDVLCH
tLCHLDX
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Figure 42. Serial transport stream input timings (100 Mbit/s input data rate)
tLCLLCL
TS0INBITORBYTECLK
tLCLLCL tLCHLCH
TS0INBITORBYTECLKVALID
TS0INDATA[0]
TS0INERROR
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TS0INPACKETCLK
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tLDVLCH tLCHLDX
tVOREF
TS0OUTBITORBYTECLK
tVOCHAOV1
TS0OUTDATA[7:0]
TSOUTERROR
TS0OUTBITORBYTECLKVALID
TS0OUTPACKETCLK
TCK
tTCHTIX
TDI
TMS
tTIVTCH
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TDO
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tTCHTOV
21.7 Audio
21.7.1 S/PDIF
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The S/PDIF output is Manchester encoded and hence self-clocking. There are no
requirements on this signal relative to other chip signals.
PCM_MCLK
PCM_DATAOUT
PCM_LRCLKOUT
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Table 83. PCM data output
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Symbol Parameter Min Max Units
MCLK
on
PCMDATA
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LRCLK
PIOREF
tPCHPOV
PIOOUT V
tPCHWDZ
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PIOREF is any PIO pin
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PIOOUT
PIOOUT is any other PIO pin
Table 85.
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General PIO timing parameters
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Symbol Parameter Min Max Units
1. These apply to all GPIO outputs with the exception of the two SSC ports. See Table 86 for PIO timings when in alternate
function.
21.9.3 ASC
There are four UARTs. These are, by definition, asynchronous and have no skew or timing
constraints.
21.9.4 SSC
There are three SSC interfaces and alternate functions of the PIO’s. See Section 9.24:
Programmable I/O ports (GPIO and PIO). The maximum bit rate for SPI is 10 Mbit/s. The
SSC supporting SPI can be configured to sample on either the rising or falling edge. Data is
sampled using a majority scheme based on communications clock sampling, therefore,
timing constraints are defined in periods of the communications clock.
TCHCH
SSCn_SCLKINOUT
TiCHDV
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SSCn_M[TS/RS]R_DIN
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TiCHDH ToCLDV
SSCn_M[TS|RS]R_DOUT
SSCn_MRST_DINOUT
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(n = 0, 1, 2)
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data stable
Required time elapsed from rising (capture) clock edge for input
tiCHDH 6T + 10 - - ns
data to hold
Required time elapsed from falling (launch) clock to output data
toCLDV 2T - 3T + 10 ns
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stable
1. T is 1 period communications clock, 16.7 ns for standard 60 MHz communications frequency.
TCHCH
SSCn_SCLKINOUT
TiCHDS TiCHDH
SSCn_M[TS/RS]R_DIN
SSCn_M[TS/RS]R_DOUT
SSCn_MRST_DINOUT
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1. The data is launched during the low period of the clock but captured during the high period of the clock. There is no clock
inversion.
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2. A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of
the SCLK signal.
3. Both SDA and SCLK are considered data signals and are synchronized with respect to the communications clock. All
parameters are fully programmable in H9 IP block.
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4. Capacitive load for clock and data bus is 400 pF maximum for I2C. (10 pF per I2C device) Other devices, such as a serial
EEPROM, have a typical value of 8 pF.
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21.9.5 IRB
There are two inputs and one output and are alternate functions of the PIO - see
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Section 9.24: Programmable I/O ports (GPIO and PIO). No constraints on timing or skew.
PAD_DENC_TZ[8]
tVOCHAOV1
PAD_DENC_TZ[7:0]
TVOCHAOV2
PAD_HSYNC
PAD_VSYNC
21.11 DVO
Figure 51. DVO timing diagram
tVOREF
DVOCLK
tVOCHAOV1
DVO_DATA[7:0]
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Table 90. DVO timing values tia
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Symbol Parameter Min Nom Max Units
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TSC THC
Control in
USB_NXT,
USB_DIR TSD THD
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Data in
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USB_DATA[7:0]
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TSDD THDD
Data in
USB_DATA[3:0]
TDC
TSDD THDD
Control out TDC
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USB_STP
TDD
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Data out
USB_DATA[7:0]
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TDDD TDDD
Data out
USB_DATA[3:0]
on
USB_CLOCK_FROM_PAD - - - 60 MHz
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Figure 53. Receive signal timing relationship at the MII PHY interface
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RXCLK
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tsetup thold
RX_DV
RX_ER
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RX_D*
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Figure 54. Transmit signal timing relationship at the MII PHY interface
on
TXCLK
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tsetup thold
TX_EN
TX_D*
TXCLK - 25 - MHz
TXD[3:0], TX_EN, RXD[3:0], RX_DV, RX_ER
30 - - ns
(data setup to REF_CLK rising edge)
TXD[3:0], TX_EN, RXD[3:0], RX_DV, RX_ER
0 - - ns
(data hold from REF_CLK rising edge)
RXCLK - 25 - MHz
RX_DV, RX_ER
30 - - ns
(data setup to REF_CLK rising edge)
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RXD[3:0], RX_DV, RX_ER
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0 - - ns
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(data hold from REF_CLK rising edge)
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400ns
MDC
10ns
on
MDIO
(Output)
C
400ns
MDC
10ns 0ns
MDIO
(input)
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from REF_CLK rising edge)
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21.14 SPI timing
SPI_CLOCK
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t
t
TIS
TIH
DATAIN
TOV
QPSK_CLK
tVOCHAOV1
TS0OUTDATA[7:0]
TS0OUTPACKETCLK
TS0OUTERROR
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TS0OUTBITORBYTECLKVALID
tVOREF QPSK_CLK 8 - - ns
Output delay with respect
tVOCHAOV1 - - 1.60 ns
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to QPSK_CLK
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22 Licenses
Supply of this product does not convey a license under the relevant intellectual property of
the companies mentioned in this chapter nor imply any right to use this intellectual property
in any finished end-user or ready to use final product. An independent license for such use
is required and can be obtained by contacting the company or companies concerned.
Once the license is obtained, a copy must be sent to STMicroelectronics.
The details of all the features requiring licenses are not provided within the datasheet and
register manual. They are provided only after a copy of the license has been received by
STMicroelectronics.
The features requiring licenses include:
Information classified Confidential - Do not copy (See last page for obligations)
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CSS
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CSS DVD Copy Protection is intellectual property of Matsushita Electronics Industrial Co.
The CSS DVD Copy Protection license allows the use of the CSS decryption cell embedded
in the STi5189.
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For all details, contact Matsushita at:
Matsushita Electronics Industrial Co. LTD, CSS Interim License
Confidential
Dolby Digital, Pro Logic and MLP Lossless are intellectual properties of Dolby Labs. The
Dolby Digital, Pro Logic or MLP Lossless license allows the use of the corresponding
decoder embedded in the STi5189.
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Two types of license exist: S license must be obtained for samples (up to 25 units). P license
must be obtained for production.
For all details, contact Dolby Labs at:
Dolby Labs, 100 Potrero Avenue, San Francisco, CA 94103, USA
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Rovi™
Compliant Devices can only be sold or distributed to Authorized Buyers.
In the event that the Rovi variant of this Device is supplied, attention is drawn to the following
notice:
This device is protected by U.S. patent numbers 6,516,132; 5,583,936; 6,836,549; and
7,050,698 and other intellectual property rights. The use of Rovi Corporation's copy
protection technology in the device must be authorized by Rovi Corporation and is intended
for home and other limited pay-per-view uses only, unless otherwise authorized in writing by
Rovi Corporation. Reverse engineering or disassembly is prohibited.
Dwight Cavendish
The STi5189 is enabled with the Dwight Cavendish Copy Protection Process. Activation of
the Dwight Cavendish Copy Protection is subject to Dwight Cavendish Intellectual Property
Rights and is not permitted otherwise than with an express written license from Dwight
Cavendish.
Information classified Confidential - Do not copy (See last page for obligations)
For all details, contact SRS Labs at:
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SRS Labs Inc., 2909 Daimler Street, Santa Ana, CA 92705 USA
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DTS® (ES, 96/24, Neo)
DTS ES, DTS 96/24 and DTS Neo are intellectual properties of Digital Theater Systems Inc.
The DTS licenses allow the use of the corresponding decoder executed in the STi5189.
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For all details, contact Digital Theater Systems Inc at:
DTS, 5171 Clareton Drive, Agoura Hills, CA 91301, USA
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DVB-MHP
Manufacturers of set-top boxes and other receiving devices are required to obtain the MHP
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Test Suite, which is used to ensure that the specification has been correctly implemented.
The completion of this certification process enables a manufacturer to apply to use the MHP
logo on their products as a mark of compliance. A license fee is also payable to the holders
of essential IPR in the MHP specifications. The patent holders have formed a patent pool
which is administered by Via Licensing. The schedule of fees due can be seen on the Via
Licensing website http://www.vialicensing.com/licensing/MHP_index.cfm.
For more information on licensing costs for device manufacturers, and to see a list of
companies with the right to display the MHP logo on their equipment see Implementing
MHP http://www.mhp.org/manufacturers.htm.
AACS
AACS is an intellectual property of AACS LA, LLC. The AACS license allows the use of
AACS in the STi5189.
For all details, contact AACS LA, LLC at:
Information classified Confidential - Do not copy (See last page for obligations)
c/o AACS Administration, 5440 SW Westgate Drive, Suite 217, Portland, Oregon 97221
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AAC
AAC is an intellectual property of Fraunhofer Institut Integrierte Schaltungen.
For all details, contact Fraunhofer Institute IIS, Am Wolfsmantel 33, 91058 Erlangen,
Germany.
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List of registers
Information classified Confidential - Do not copy (See last page for obligations)
AGC1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 PR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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AGC1REF . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 VSEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
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AGC1IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 RS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
TSREG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 RSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 ERRCTRL. . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
RTFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 ECNTM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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RTFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 ECNTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SFRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 ERRCTRL2. . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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LDT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
ACLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 SDATCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
BCLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 SCLTCFG. . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
CFRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 AGCCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
CFRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 AUXCKCFG . . . . . . . . . . . . . . . . . . . . . . . . . . 148
NIRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 DISEQCCFG . . . . . . . . . . . . . . . . . . . . . . . . . 148
NIRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 IRQSTATx . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
EQUA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 IRQMSKx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
EQUAI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 ASCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
EQUAQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 COARP1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
EQUAI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 COARP2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
EQUAQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 FMINM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
EQUAI3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 FMINL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
EQUAQ3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 FMAXM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
EQUAI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 FMAXL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
EQUAQ4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 FINEINC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
EQUAI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 STEP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
EQUAQ5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 TH2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Information classified Confidential - Do not copy (See last page for obligations)
CFG_MONITOR_I. . . . . . . . . . . . . . . . . . . . . .163 FS216X4_CLK1_SETUP1 . . . . . . . . . . . . . . . 218
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CFG_MONITOR_J . . . . . . . . . . . . . . . . . . . . .163 FS216X4_CLKn_SETUP1 . . . . . . . . . . . . . . . 218
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CFG_MONITOR_K . . . . . . . . . . . . . . . . . . . . .164 FS216X4_CLK5_SETUP1 . . . . . . . . . . . . . . . 219
CFG_MONITOR_L . . . . . . . . . . . . . . . . . . . . .164 FS216X4_CLKn_SETUP1 . . . . . . . . . . . . . . . 219
CFG_MONITOR_M. . . . . . . . . . . . . . . . . . . . .164 REDUCED_POWER_CONTROL. . . . . . . . . . 220
CFG_MONITOR_N . . . . . . . . . . . . . . . . . . . . .165 LP_MODE_DIS0 . . . . . . . . . . . . . . . . . . . . . . 221
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CFG_MONITOR_O . . . . . . . . . . . . . . . . . . . . .165 LP_MODE_DIS1 . . . . . . . . . . . . . . . . . . . . . . 222
CFG_MONITOR_P . . . . . . . . . . . . . . . . . . . . .165 LP_MODE_COUNTER_CFG0 . . . . . . . . . . . . 222
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ILC_WAKEUP_ENABLE . . . . . . . . . . . . . . . . .251
ILC_WAKEUP_ACTIVE_LEVEL . . . . . . . . . . .252
ILC_PRIORITYn . . . . . . . . . . . . . . . . . . . . . . .252
ILC_MODEn . . . . . . . . . . . . . . . . . . . . . . . . . .253
ILC_MODE2 . . . . . . . . . . . . . . . . . . . . . . . . . .254
Information classified Confidential - Do not copy (See last page for obligations)
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23 Revision history
Information classified Confidential - Do not copy (See last page for obligations)
- Replaced EMI with FMI.
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- Added pin E13 and K8 in Table 11.
- Added Alt2 function in Table 39.
10-Nov-2009 B
- Updated Alt1 and Alt3 function of PIO4[3] and Alt2 function of PIO4[0] in
Table 41.
- Added Chapter 1: Related documents.
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- Reversed the bank numbers in Figure 36.
Confidential
Information classified Confidential - Do not copy (See last page for obligations)
- Renamed the V4 ball in 15 x 15 mm package and AD15 ball in
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23 x 23 mm package throughout the datasheet.
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- Added the RESETEXTOUT signal in Table 13.
- Updated Table 29.
- Updated PIO3[7] in Table 40.
- Updated table headings in Table 49.
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- Updated the “Parameter” column in Table 74.
- Renamed the signal name in Figure 37.
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- Updated the maximum value of VDD1V0 in Table 60, Table 63, Table 65
and Table 67.
- Updated Table 59.
- Added ARGB8888 throughout the datasheet where ARGB4444 is
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mentioned.
- Updated description of bit [11:1] in the PLL_SELECT_CFG register.
- Renamed the headings of Table 5, Table 6, Table 7, Table 8, Table 9 and
Table 10.
- Added note 1 in Section 20.1: Absolute maximum ratings.
- Added a footnote below Table 4.
- Updated row ‘b’ of the Table 3.
- Added Section 20.3: System: oscillator.
- Updated Section 3.7: Processor and memory.
- Updated feature “Target speed at 350 MHz delivering > 630 DMIPs” in
Section 2.1: STi5189 features summary.
Information classified Confidential - Do not copy (See last page for obligations)
03-Apr-2012 5 Updated Table 91: USB timing values on page 280.
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CONFIDENTIALITY OBLIGATIONS:
This document contains sensitive information.
Its distribution is subject to the signature of a Non-Disclosure Agreement (NDA).
It is classified “CONFIDENTIAL”.
At all times you should comply with the following security rules
(Refer to NDA for detailed obligations):
Do not copy or reproduce all or part of this document
Keep this document locked away
Further copies can be provided on a “need to know basis”, please contact your local ST sales office.
Information classified Confidential - Do not copy (See last page for obligations)
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Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
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Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
Confidential
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
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third party products or services or any intellectual property contained therein.
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