17eel38 El Lab Manual

S.J.P.
N Trust's
Hirasugar Institute of Technology, Nidasoshi

Inculcating Values, Promoting Prosperity
Approved by AICTE New Delhi, Recognized by Govt. of Karnataka and Affiliated to VTU Belagavi
Tq: Hukkeri Dist: Belagavi
DEPARTMENT OF ELECTRICAL & ELECTRONICS

ENGINEERING
LABORATORY MANUAL
Name of the Lab: Electronics Laboratory
Semester: III
Subject Code: 17EEL38
Prepared by: Prof. Sagar Sudhakar Birade

Electronics Laboratory 2018-19
Overview
Year / Semester 2nd Year /3rd Semester Academic Year 2018 - 19
Laboratory Title Electronics Lab Laboratory Code 17EEL38
Total Contact Hours 42 Hours Duration of SEE 3 Hours
IA Marks 40 Marks SEE Marks 60 Marks
Lab Manual Author Prof. Sagar S Birade Sign - Date
Checked By Sign - Date
Objectives
 To design and test half wave and full wave rectifier circuits.
 To design and test different amplifier and oscillator circuits using BJT.
 To study the simplification of Boolean expressions using logic gates.
 To realize different Adders and Subtractors circuits.
 To design and test counters and sequence generators.
Description
1.0 Learning Objectives
Student aims to understand, design and analyze the basic applications of the diodes, mainly the rectifier
circuits. In this laboratory student designs many circuits‟ namely rectifiers, transistor amplifiers, RC
phase shift oscillator, realize adder/subtractor circuit, code conversion and counter circuits etc.
2.0 Learning Outcomes
The student, after successful completion of the course, will be able to
1. To design and test half wave and full wave rectifier circuits.
2. To design and test different amplifier and oscillator circuits using BJT.
3. To study the simplification of Boolean expressions using logic gates.
4. To realize different Adders and Subtractors circuits.
5. To design and test counters and sequence generators.
Prerequisites
 Basic knowledge of bread board connection methods.
 Details of various elements like pin configuration of different logic gates, color code of
resistors etc.
 Analog Electronic Circuits design and analysis
Base Course
1. Analog Electronic Circuits.
2. Basic Electrical/Electronics Engineering.
Introduction
In Electronics Lab we are conducting experiments using Diode, Transistors, Logic Gates and
different IC‟s such as rectifiers, transistor amplifiers, RC phase shift oscillator, realize adder/subtractor
circuit, code conversion and counter circuits etc. At the end of the course student will be able to
understand and design transistor circuits, digital circuits and get the performance practically.
Resources Required
1. Signal Generator
2. Regulated Power Supply
3. Digital Storage Oscilloscope
4. Bread Boards
Dept. Electrical and Electronics Engineering.

Hirasugar Institute of Technology Nidasoshi
Page 1
General Instructions
1. After circuit connection, before switching ON the supply, verify it by instructor or lab in
charge.
2. Make sure voltage level of power supply is at minimum value at the start.
3. Before leaving the lab keep all the equipments properly.
Contents
Expt Date Date

Title of the Experiment
No. Planned Conducted
Design and Testing of Full wave – centre tapped transformer

1 type and Bridge type rectifier circuits with and without
Capacitor filter. Determination of ripple factor, regulation and
efficiency.
Static Transistor characteristics for CE, CB and CC modes and
2
determination of h parameters.
Frequency response of single stage BJT and FET RC coupled
3 amplifier and determination of half power points, bandwidth,
input and output impedances.
4 Design and testing of BJT - RC phase shift oscillator for given
frequency of oscillation.
5 Determination of gain, input and output impedance of BJT
Darlington emitter follower with and without bootstrapping.
6 Simplification, realization of Boolean expressions using logic
gates/Universal gates.
7 Realization of half/Full adder and Half/Full Subtractors using
logic gates.
8 Realization of parallel adder/Subtractors using 7483 chip- BCD
to Excess-3 code conversion & Vice -Versa.
9 Realization of Binary to Gray code conversion and vice versa.
10 Design and testing Ring counter/Johnson counter.
11 Design and testing of Sequence generator.
12 Realization of 3 bit counters as a sequential circuit and MOD –
N counter design using 7476, 7490, 74192, 74193.
Evaluation Scheme
1. Lab activity – Continuous Assessment, Attendance, Journal – 30 Marks.
2. Internal exam at the end of semester – 10 Marks.
3. Semester End Exam – 60 Marks.
Reference
1. „Electronic Devices and Circuit Theory‟, Robert L Boylestad Louis Nashelsky Published by
Pearson 11th Edition 2015.
2. Fundamentals of Analog Circuits Thomas L Floyd Pearson 2nd Edition, 2012.
3. “Digital Integrated Electronics” by H. Taub and D. Schilling
4. https://www.aec.at/futurelab/en/

Page 2
EXPERIMENT NO -1
Full Wave Rectifiers
Aim: Design and Testing of Full wave – centre tapped transformer type and Bridge type
rectifier circuits with and without Capacitor filter. Determination of ripple factor, regulation
and efficiency.
Full Wave rectifier without Filter

Apparatus Required:
Sl.No Name of the Component Quantity

1 Bread Board 1
2 Diode 4
3 Centre tapped transformer 1
4 Ammeter 2
5 Voltmeter 1
6 Capacitor 1
7 Connecting Wire few
Circuit Diagram:
Design:
Let output DC voltage required = 10V, and IL(max) = 150mA
2Vm

For Full Wave rectifier Vdc =
xVdc
Therefore Vm = = 16V
2
Vm 16
Transformer Secondary voltage = = = 11.3V
2 2
V 10
Choose 230V/12V transformer RL = dc = = 67 Ω
I L ( Max)
150m
Power dissipated in RL is
PL =Vdc x IL(max) = 10 x 150x 10-3 = 1.5 watts
Choose RL = 100Ω with the help of DRB

Page 3
Calculations:
I ac
Ripple factor γ = I dc
I 2 dc
% Efficiency η = I2 2
x 100
dc +I ac
V dc (NL ) −V dc
% Regulation = x 100
V dc
Tabular Column:
RL in  Vdc in Idc in mA Iac in mA Ripple Efficiency %Regulation

volts factor (γ)
Max (NL)

Page 4
Full Wave rectifier with C- Filter
Circuit Diagram
Design:
To design a Full wave rectifier with C-filter for the following specifications
Let output DC voltage required = 17V, and IL(max) = 150mA and ripple factor =0.04
For Full Wave rectifier with C-filter Vdc =Vm
Therefore transformer secondary voltage

Vm 17
Vrms = = = 12 V
2 2
Choose 230V/12V transformer
V 17
RL = dc = = 113.33Ω
IL ( Max)
150m
Choose RL = 150Ω by use of DRB
For Full wave rectifier with C-filter

1
Ripple factor =4 3 fR L C
1
Therefore C= 4 = 481 µF
3 X50 X150 X0.04
Choose C= 470 µF /25V a standard value
Calculations:
I ac

Page 5
Tabular column:
RL in  Idc in mA Iac in mA Ripple factor (γ)
Procedure:
For Full Wave Rectifier
1. Connect the circuit as shown in figure.
2. Set the DRB to maximum and note down value of Vdc (No Load) (here maximum
resistance is designated as No load).
3. Vary the DRB (in steps of 100, 200, 300)and note down the values of Idc, Iac, and
Vdc and record the readings in the tabular column.
4. Observe the output waveforms on the Oscilloscope and draw these waveforms to scale.
5. For each value of Idc determine the values of ripple factor, efficiency and regulation.
6. Connect the circuit with Capacitor -filter as shown in the fig 4.

7. Calculate the value of Capacitor for the given value of ripple factor (Assume RL to
some value) by using the formula and then repeats the steps 2-5
Result:
Ripple Factor Efficiency % Regulation
Full wave Bridge
rectifier without Filter
Full wave Bridge
rectifier with C-Filter
Conclusion:

Page 6
Full Wave Bridge Rectifier without Filter
Circuit Diagram:
DESIGN:
Let output DC voltage required = 10V, and IL(max) = 150mA
2Vm

For Full Wave rectifier Vdc =
xVdc
Therefore Vm = = 16V
2
Vm 16
Transformer Secondary voltage = = = 11.3V
2 2
V 10
RL = dc = = 67 Ω
IL ( Max)
150m

Page 7
Calculations:
I ac
I 2 dc
%Efficiency η = I2 2
x 100
dc +I ac
V dc (NL ) −V dc
% Regulation = x 100
V dc
Tabular column:
RL in  Vdc in Idc in mA Iac in mA Ripple Efficiency %Regulation

volts Factor (γ)
Max
(NL)

Page 8
Full Wave Bridge Rectifier with C- Filter
Circuit Diagram:
Design:
To design a Full wave bridge rectifier with C-filter for the following specifications
Let output DC voltage required = 17V, and IL(max) = 150mA and ripple factor =0.04
For Full Wave rectifier with C-filter Vdc =Vm
Therefore transformer secondary voltage
Vm 17
Vrms = = = 12 V
2 2
V 17
RL = dc = = 113.33Ω
I L ( Max)
150m

1
For Full wave rectifier with C-filter Ripple factor =4 3 fR L C
1
Therefore C= 4 = 481 µF [Choose C= 470 µF /25V a standard value]
3 X50 X150 X0.04
Calculations:
I ac

Page 9
Tabular column:
RL in  Idc in mA Iac in mA Ripple

factor (γ)
Procedure:
For Full Wave Bridge Rectifier
1. Connect the circuit as shown in circuit diagram.5
2. Set the DRB to maximum and note down value of Vdc (No Load) (here maximum
resistance is designated as No load).
3. Vary the DRB (in steps of 100, 150, 300)and note down the values of Idc, Iac, and
Vdc and record the readings in the tabular column.
4. Observe the output waveforms on the Oscilloscope and draw these waveforms to scale.
5. For each value of Idc determine the values of ripple factor, efficiency and regulation.
6. Connect the circuit with Capacitor -filter as shown in the fig 6.

7. Calculate the value of Capacitor for the given value of ripple factor (Assume RL to
some value) by using the formula and then repeats the steps 2-5
Result:
Ripple Factor Efficiency % Regulation

Full wave Bridge
rectifier without Filter
Full wave Bridge
rectifier with C-Filter
CONCLUSION:

Page 10
Experiment No. 2
CE, CB & CC CONFIGURATIONS
Aim: To study the input and output characteristics of a transistor in Common Emitter
configuration.
Apparatus Required:
S.No. Name Quantity

1 Transistor BC 107 1(One) No.
2 Resistors (1K , 100K ) 1(One) No. Each
3 Bread board 1(One) No.
4 Dual DC Regulated Power supply (0 - 30 V) 1(One) No.
5 Digital Ammeters (0 - 200 mA, 0-200 A) 1(One) No. Each
6 Digital Voltmeter (0 - 20V) 2(Two) No.
7 Connecting wires (Single Strand) Few.
Circuit Diagram:
h – Parameter model of CE transistor:

Page 11
Observations:
Input Characteristics
VBB (Volts) VCE = 0V VCE = 5V
VBE (Volts) IB (µA) VBE (Volts) IB (µA)
Output Characteristics
VCC (Volts) IB = 0 µA IB = 20 µA IB = 40 µA
VCE (Volts) IC (mA) VCE (Volts) IC (mA) VCE (Volts) IC (mA)
Graph:
Procedure:
Input Characteristics:
1. Connect the circuit as shown in the circuit diagram.

2. Keep output voltage VCE = 0V by varying VCC.
3. Varying VBB gradually, note down base current IB and base-emitter voltage VBE.
4. Step size is not fixed because of non linear curve. Initially vary VBB in steps of 0.1V.
Once the current starts increasing vary VBB in steps of 1V up to 12V.
5. Repeat above procedure (step 3) for VCE = 5V.

Page 12
Output Characteristics:

2. Keep emitter current IB = 20 A by varying VBB.
3. Varying VCC gradually in steps of 1V up to 12V and note down collector current IC and
Collector-Emitter Voltage(VCE).
4. Repeat above procedure (step 3) for IB = 60µA, 0µA.
To Plot Graph:
1. Plot the input characteristics by taking VBE on X-axis and IB on Y-axis at a constant
VCE as a constant parameter.
2. Plot the output characteristics by taking VCE on X-axis and taking IC on Y-axis taking
IB as a constant parameter.
Calculations from Graph:

1. Input Characteristics: To obtain input resistance find VBE and IB for a constant VCE
on one of the input characteristics.
Input impedance = hie = Ri = VBE / IB (VCE is constant)
Reverse voltage gain = hre = VEB / VCE (IB = constant)
2. Output Characteristics: To obtain output resistance find IC and VCB at a constant IB.
Output admittance 1/hoe = Ro = IC / VCE (IB is constant)
Forward current gain = hfe = IC / IB (VCE = constant)
Result:
The h-parameters for a transistor in CE configuration are:
a. The Input Resistance (hie) _______________Ohms.

b. The Reverse Voltage Gain (hre) _______________.
c. The Output Conductance (hoe) _______________ Mhos.
d. The Forward Current Gain (hfe) _______________.
Conclusion:

Page 13
Aim: To study the input and output characteristics of a transistor in Common Base
Configuration.
Apparatus Required:
S.No. Name Quantity

2 Resistors (1K ) 2(Two) No.
4 Dual DC Regulated Power supply (0 – 30 V) 1(One) No.
5 Digital Ammeters ( 0 – 200 mA) 2(Two) No.
6 Digital Voltmeter (0-20V) 2(Two) No.
7 Connecting wires (Single Strand) few
Circuit Diagram:
h – Parameter model of CB transistor:

Page 14
Observations:
VEE (Volts) VCB = 0V VCB = 4V
VEB (Volts) IE (mA) VEB (Volts) IE (mA)
VCC (Volts) IE = 0mA IE = 5V IE = 10mA
VCB (Volts) IC (mA) VCB (Volts) IC (mA) VCB (Volts) IC (mA)
Graph:
1. Plot the input characteristics for different values of VCB by taking VEE on X-axis and IE
on Y-axis taking VCB as constant parameter.
2. Plot the output characteristics by taking VCB on X-axis and taking IC on Y-axis taking
IE as a constant parameter.

Page 15
Procedure:
1) Connect the circuit as shown in the circuit diagram.
2) Keep output voltage VCB = 0V by varying VCC.
3) Varying VEE gradually, note down emitter current IE and emitter-base voltage(VEE).
4) Step size is not fixed because of nonlinear curve. Initially vary VEE in steps of 0.1 V.
Once the current starts increasing vary VEE in steps of 1V up to 12V.
5) Repeat above procedure (step 3) for VCB = 4V.
2. Keep emitter current IE = 5mA by varying VEE.
3. Varying VCC gradually in steps of 1V up to 12V and note down collector current IC and
collector-base voltage (VCB).
4. Repeat above procedure (step 3) for IE = 10mA.
5.
Repeat above procedure (step 3) for IE = 10mA.
Calculations from Graph:
The h-parameters are to be calculated from the following formulae:

1. Input Characteristics: To obtain input resistance, find VEE and IE for a constant
VCB on one of the input characteristics.
Input impedance = hib = Ri = VEE / IE (VCB = constant)
Reverse voltage gain = hrb = VEB / VCB (IE = constant)
2. Output Characteristics: To obtain output resistance, find IC and VCB at a
constant IE.
Output admitance = hob = 1/Ro = IC / VCB (IE = constant)
Forward current gain = hfb = IC / IE (VCB = constant)
Result:
The h-parameters for a transistor in CB configuration are:
a. The Input resistance (hib) __________________ Ohms.

b. The Reverse Voltage Transfer Ratio (hrb) __________________.
c. The Output Admittance (hob) __________________ Mhos.
d. The Forward Current gain (hfb) __________________.
Conclusion:

Page 16
Aim: To study the input and output characteristics of a transistor in Common Collector
Configuration.
Apparatus Required:
S.No. Name Quantity
2 Resistors (39KΩ, 1KΩ) 2(Two) No.
4 Dual DC Regulated Power supply (0 – 30 V) 1(One) No.
5 Digital Ammeters ( 0 – 300µA, 0-10mA) 2(Two) No.
6 Digital Voltmeter (0-10V, 0-1V) 2(Two) No.
7 Connecting wires (Single Strand) few
Circuit Diagram:
h – Parameter model of CB transistor:

Page 17
Observations:
Sl. Applied VCE = 2V VCE = 5V VCE = 10V
No Voltage
VBE (V) IB (µA) VBE (V) IB (µA) VBE (V) IB (µA)
VBB (V)
1
2
3
4
5
Sl. Applied IB = 10µA IB = 20µA IB = 30µA
No Voltage
VCE (V) IC (mA) VCE (V) IC (mA) VCE (V) IC (mA)
VCC (V)
1
2
3
4
5
Graph:
1. Plot the input characteristics for different values of VCE by taking VBE on X-axis
and IB on Y-axis taking VCC as constant parameter.
2. Plot the output characteristics by taking VCE on X-axis and taking IC on Y-axis
taking IB as a constant parameter.

Page 18
Procedure:
2. Keep output voltage VCE as constant 2V by varying VCC.
3. Varying VBB gradually, note down base current IB and emitter-base voltage (VBE).
4. Step size is not fixed because of nonlinear curve. Initially vary VEE in steps of 0.1 V.
Once the current starts increasing vary VBB in steps of 1V up to 12V.
5. Repeat above procedure (step 3) for VCE = 5V & 10V.
1. Fix base current, IB at constant value say 10µA.
2. Vary the output voltage VCC in steps.
3. Measure the voltage VCE and current IC for different values.
4. Repeat above steps for IB = 20µA, 30µA
5. Draw output static characteristics for tabulated values.
Result:
The h-parameters for a transistor in CB configuration are:
a. The Input resistance (hib) __________________ Ohms.
b. The Reverse Voltage Transfer Ratio (hrb) __________________.
c. The Output Admittance (hob) __________________ Mhos.
d. The Forward Current gain (hfb) __________________.
Conclusion:

Page 19
EXPERIMENT NO -3
RC – COUPLED SINGLE STAGE BJT AMPLIFIER
Aim: To find the Frequency response of single stage BJT and FET RC coupled amplifier
and determination of half power points, bandwidth, input and output impedances.
Apparatus Required:
S.N Particulars Type Range Quantity

1. Transistor SL100 --- 01
2. Capacitors 0.47F 02
---
47 F 01
3. Resistors 22 K 01
1 K 01
--- 4.7 K 01
270 01
10K 01
4. Regulated Power Supply --- 0-32 V 01
5. Signal Generator --- --- 01
6. Oscilloscope and Probes --- --- 01
7. Bread Board --- --- 01
8. Connecting wires --- --- few
Circuit Diagram:

Page 20
Frequency Response
Design:
Let VCC = 12V, IC = 4.5mA, β= 100( for SL100)
Calculation of RE
𝑉𝑐𝑐 12
VRE = = = 1.2V
10 10
That is IERE = 1.2V
1.2 1.2 1.2
Therefore RE = = = = 0.267KΩ
𝐼𝐸 𝐼𝑐 4.5𝑚𝐴
Use RE = 270Ω

Page 21
Calculation of R1 and R2
From the biasing circuit
VB = VBE +VRE = 0.7 +1.2 = 1.9Vs
𝐼𝐶 4.5𝑚𝐴
IB = = = 0.045mA
𝛽 100
Assume 10IB flows through R1 and 9IB flows through R2
𝑉 𝐶𝐶 −𝑉 𝐵 12−1.9
R1 = = = 22.4KΩ
10𝐼𝐵 10 𝑋 0.045
Use R1 = 22KΩ
Also we have
VB = VR2 = 9IB x R2
𝑉𝐵 1.9
Therefore R2 = = = 4.69KΩ
9𝐼𝐵 9𝑥 0.045𝑚
Use R2 =4.7KΩ
Procedure:
1. Connect the biasing circuit as shown in the figure -2, set the RPS voltage Vcc = 12V.
Measure the DC voltages (Using Oscilloscope) VB at the base, VC at the collector and VE
at the emitter with respect to ground. Then determine
VCE = VC – VE = ________ V
𝑉𝑐𝑐 −𝑉𝑐
IC = = _______ mA (then Q point is given by VCE, IC)
𝑅𝑐
2. Connect the RC coupled amplifier circuit shown in figure-1.
3. Apply the input sine wave at frequency say 10KHz from the signal generator and adjust
peak –to-peak amplitude (Vi) of 20 to 50 milli volts (till maximum undistorted sine
wave output is obtained).
4. Vary the input sine wave frequency from 10Hz to 1MHz in suitable steps and measure
the output voltage V0 of the amplifier at each step using Oscilloscope(Keeping input
amplitude remains constant throughout the frequency range) and record the readings in
the tabular column.
5. Calculate the Gain in dB
6 Plot the graph of gain in dB v/s the frequency in semi log graph sheet and determine
lower cutoff frequency (f1) , upper cutoff frequency (f2), mid band voltage gain Amid ,
and gain bandwidth product (GBW).

Page 22
Procedure: For measuring the input impedance „Zi‟
1. Connect the circuit as shown in fig.3
2. Set the following.
i) DRB to its minimum value „0‟
ii) Input sine wave amplitude is kept at 50mV.
iii) Frequency around 10 kHz.
iv) Measure p-p Vo
3. Let Vo = Va, Increase DRB till Vo = Va/2. So that the corresponding DRB value
gives the input impedance „Zi‟ of the RC Coupled amplifier.
Calculation of RC
𝑉𝑐𝑐 12
Choose VCE = = = 6V
2 2
VCC- ICRC-VCE-VRE = 0
12- 4.5RC-6-1.2 =0
Therefore RC = 1.07KΩ
Use RC = 1 KΩ
Calculation of Bypass capacitor (CE) and coupling capacitors (CC1 and CC2)
1
Let XCE = RE at frequency f =100Hz
10
1 𝑅𝐸
That is =
2𝜋𝑓𝑋 𝐶𝐸 10
10 10
Therefore CE = = =59µF
2𝜋𝑓𝑋 𝑅𝐸 2𝜋 𝑋 100 𝑋 270
Use standard value CE = 47µF (Electrolytic)
Also use CC1 and CC2 = 0.1µF (ceramic)

Page 23
ii) Determination of Input Impedance (Zi) and Output Impedance (Z0)
Procedure: For measuring the output impedance „ZO‟

1. Connect the circuit as shown in fig.4
2. Set the following.
i. DRB to its Maximum value.
ii. Input sine wave amplitude is kept at 50mV
iii. Frequency around 10 kHz.
iv. Measure p-p Vo
Let Vo = Vb, Decrease DRB till Vo = Vb/2
3. So that the corresponding DRB value gives the Output impedance „Zo‟ of the RC
Coupled amplifier
Results:
 Mid band voltage gain = _________

 Mid band voltage gain in dB = _________dB
 Lower cutoff frequency = _________HZ
 Upper cutoff frequency = _________Hz
 Band width = _________Hz
 Gain Bandwidth Product = _________Hz
 Input Impedance = _________Ω
 Output Impedance =__________Ω
Conclusion:

Page 24
EXPERIMENT NO 4
BJT RC PHASE SHIFT OSCILLATOR
Aim: To design and verify the performance of RC Phase shift Oscillator.
Apparatus required:

2. Capacitors Ceramic 0.1F 01
--- ” --- 0.01F 03
Electrolytic 47F 01
6.8 K 01
Carbon 1 K 01
2.2 K 02
470  01
4. Regulated Power Supply 0-32 01
5. Potentiometer 10 K 01
6. Oscilloscope and Probes --- 01
7 Bread Board -- 01
8 Connecting wires --- few
Circuit diagram:

Page 25
Design:
Amplifier design:
Let VCC = 12V, IC = 4mA, hfe= 100 (for SL100)

Let VE = 2V, VCE = 6V
𝑉 𝑉 2
Therefore RE = 𝐼 𝐸 = 𝐼 𝐸 = 4𝑚𝐴 = 0.5KΩ = 500Ω
𝐸 𝐶
Use RE = 470Ω
RC: From the biasing circuit (apply KVL to CE loop)
VCC- ICRC-VCE-VE = 0
12- 4RC-6-2 =0
Therefore RC = 1 KΩ
Calculation of R1 AND R2
𝑅2
VB =VCC x 𝑅
1 +𝑅2
We know that VB = VBE + VE

VB = 2 + 0.7 = 2.7V
𝑉𝐵 𝑅2
Therefore 𝑉𝐶𝐶
=𝑅
1 +𝑅2
2.7 𝑅2
=
12 𝑅1 +𝑅2
𝑅2
0.225 = 𝑅
1 +𝑅2
0.225R1 +0.225R2 = R2
R1 = 3.44R2
If R2 = 6.8 KΩ, then R1 = 23.3KΩ, Use R1 = 22KΩ
Use CE = 50µF or 47 µF (Electrolytic)
Also use CC = 0.1µF (ceramic)
Design of shifting network
The frequency of oscillations is determined by phase shifting network. The oscillating
frequency for the above circuit is given by
1
f0 =
2RC 6  4 K
RC
Where K= which is usually < 1
R
Let f0 = 2 KHz (Audio frequency range 20Hz to 20KHz) and R = 2.2 K

Page 26
RC 1K
Therefore K= = = 0.454
R 2.2 K
1
Therefore f0 =
2RC 6  4(0.454)
C = 0.0121 F; Use C = 0.01 F
Note:
The last resistor in the phase shifting network is chosen to be a 10K pot. This is to get an
overall phase shift of 180o at frequency of oscillations.
The minimum hfe required for the transistor to oscillate is
R R
hfe(min) = 23 + 29 x +4x C
RC R
Where RC = 1K and R = 2.2K (Phase shifting network)
2.2 K 1K
Therefore hfe(min) = 23 + 29 x +4x
1K 2.2 K
hfe(min) = 89
Procedure:
1. Connections are made as per the circuit diagram.
2. Switch ON the power supply and set the biasing voltage VCC =12V .
3. Adjust the 10KΩ pot to get a stable sinusoidal output and observe the sine wave form
on oscilloscope.
4. Measure the frequency of oscillations of the output from the oscilloscope, then compare
with theoretical value.
5. With respect to the output Vo, the waveforms at points TP1, TP2 and TP3, are observed
on oscilloscope. We can see the phase shift at each point being shifted by an angle 60 0,
1200, 1800.
6. Draw the waveform on graph sheet.
Result:
Theoretical frequency of oscillations = _________KHz
Practical frequency of oscillations = _________KH
Conclusion:

Page 27
EXPERIMENT NO -5
DARLINGTON EMMITTER FOLLOWER
AIM: To determination of gain, input and output impedance of BJT Darlington emitter
follower with and without bootstrapping.
APPARATUS REQUIRED:

2. Capacitors Ceramic 0.1F 01
--- ” --- 0.01F 03
Electrolytic 47F 01
6.8 K 01
Carbon 1 K 01
2.2 K 02
470  01
4. Regulated Power Supply 0-32 01
5. Signal Generator
6. Voltmeter
7. Ammeter
8. CRO and Probes --- 01
9. Bread Board -- 01
10. Connecting wires --- few
CIRCUIT DIAGRAM:

Page 28
Design:
Let VCC = 12 V D.C.; IC2 ≈ IE2 = 6mA, hfe1 = 50, hfe2 = 100;
Choose VCE2 = VCC / 2 = 12/2 = 6V;
IB2=IC2/hfe2 = 6000/100 = 60μA = IC1;
IB1 = IC1/hfe1= 60/50 = 1.2μA
RE = (VCC – VCE2)/IE2 =6V / 6mA = 1000 Ω

Assume R3 = 1K, then R3IB1 = 1.2 mV.
VAG = VAB1 + VBE1 + VBE2 + VE2

= R3IB1 + VBE1 + VBE2 + VE2
=1.2 mV + 0.7 V + 0.7 V + 6V
=7.4012 V
With R2 = 1 K, IR2 = VAG/R2 = 7.4012 mA=7401.2 μA, let R2 = 1 K

Therefore, IR1 = IR2 + IB1 =7401.2 + 1.2 = 7402.4 μA
R1= (VCC-VAG)/IR1 = 12-7.4012/7402.4 μA =621.258Ω; let R1 = 680 Ω
Choose CC1 = CC2 = 0.47 μF.
PROCEDURE:
To measure Voltage Gain
1. Connect the circuit as shown in the figure
2. Switch on the power supply and set VCC = +12 V.
3. Measure the DC Voltages using CRO or Multimeter and record.
VCE1 VBE1 VCE2 VBE2 VE2
Assumed 6V 0.7V 6V 0.7V 6V
Obtained
4. Apply a sine wave voltage from the Function Generator.

5. Observe the o/p Vo. Measure and record Vi and Vo. Compute and enter the voltage gain,
AV=VO/VI in the table.
Voltage gain with bootstrap
Vi Vi, max
Vo
Av

Page 29
Record Vi, Max, The maximum input you can apply for undistorted output as the
“Maximum Signal handling capacity” of the Emitter follower.
6. Repeat the experiment after disconnecting the capacitor CB in branch AB, i.e.; just remove
the Bootstrapping capacitor, CB. Now you have taken away the Bootstrapping.
Voltage gain without bootstrap
Vi Vi, max
Vo
Av
To measure Input Impedance Zi:

1. Connect the circuit as shown below.
2. Set the DRB to minimum (0 Ω). Apply a10 KHz sine wave signal of amplitude 1V (p-p) or
any suitable value to get an undistorted output.
3. Measure VO (p-p). Let VO = Va (say) with DRB value = 0
4. Increase DRB value in steps till VO = VA/2. The corresponding DRB value gives ZI.
5. Repeat the experiment by disconnecting CB, the bootstrapping capacitor.
6. Compare the two input impedance values you have measured.
To measure output impedance, Zo:

1. Connect the circuit as shown in figure

Page 30
2. Set the DRB to its maximum resistance value. Apply a 10 KHz sine wave of
amplitude1V (p-p) or any suitable value to get undistorted output
3. Measure VO (p-p), VO = VB without DRB connection or DRB value at Max.
4. Decrease DRB value in steps till VO = VB/2. The corresponding DRB value gives ZO.
5. In this part of the experiment, it is likely that the o/p wave form may get distorted
as the DRB value is decreased. Then, VI has to be set to a lower value and the steps
to be repeated. Note carefully that the answer will be wrong if you take readings
with distorted output.
6. Repeat the experiment by disconnecting the Bootstrapping capacitor.
RESULT:
1. Voltage Gain with Boot Strap. : ……….
2. Voltage Gain with Boot Strap. : ……….
3. Input Impedance, Zi, with Bootstrap. : ……….
4. Input Impedance, Zi, without Bootstrap. : ……….
5. Output Impedance, Z0, with Bootstrap. : ………
6. Output Impedance, Z0, without Bootstrap. : ……….
7. Current Gain, Ai, With Bootstrap. : ………

8. Current Gain, Ai, Without Bootstrap. : ……….
Vi = Zi × Ii, Vo =Zo × Io Ai = (Io/Ii) = AV × (Zi/Zo)
CONCLUSION:

Page 31
EXPERIMENT NO 6
Simplification & Realization of Boolean Expressions
Aim: Simplification, realization of Boolean expressions using logic gates/Universal gates.
Components Required:
Sl. No Name of the Component IC number Qty
1 AND gate 7408 2
2 OR gate 7432 2
3 Not gate 7404 2
4 EXOR gate 7486 2
5 NAND gate 7400 2
6 NOR gate 7402 2
7 EX-NOR gate 4077 1
8 Patch chords few
9 Trainer Kit
NOT GATE
OR GATE
AND GATE

Page 32
NAND GATE
NOR GATE
XOR GATE
EX-NOR GATE

Page 33
Implementation of Basic Gates Using Universal Gates
NAND gate as AND gate
Logic Diagram Truth Table
NAND gate as OR gate

NAND gate as NOT gate

NAND gate as NOR gate


Page 34
NAND gate as Ex-OR gate

NAND gate as Ex-NOR gate

NOR gate as AND gate


Page 35
NOR gate as OR gate
NOR gate as NOT gate

NOR gate as NAND gate


Page 36
NOR gate as Ex-NOR gate
NOR gate as Ex-OR gate


Page 37
Realize the following expressions in
(1) SOP form (sum of product) (2) POS form (product of sum)
SOP FORM
F(A,B,C,D) = ∑(5,7,9,11,13,15)
Simplification- SOP form using basic gates
Using NAND gates

Page 38
POS FORM
F(A,B,C,D) =∏(0,1,2,3,4,6,8,10,12,14)
Simplification- POS form Using basic gates
Using NAND gates

Page 39
Truth table:
Procedure:
INPUTS O/P
Dec
Eq A B C D
Y=(A+B)
1. Place the IC in the socket of the trainer kit. D
2. Complex Boolean Expressions are 0 0 0 0 0 0

simplified by using K maps.
1 0 0 0 1 0
3. Make the connections as shown in the 2 0 0 1 0 0
circuit diagram.
3 0 0 1 1 0
4. Apply different combinations of inputs
4 0 1 0 0 0
according to the truth table and verify the
outputs. 5 0 1 0 1 1
5. Repeat the above procedure for all the 6 0 1 1 0 0

circuit diagrams.
7 0 1 1 1 1
8 1 0 0 0 0
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 1
12 1 1 0 0 0
13 1 1 0 1 1
14 1 1 1 0 0
15 1 1 1 1 1
CONCLUSION:

Page 40
EXPERIMENT NO 7
Half/ Full Adder & Subtractor
Aim: Realization of half/Full adder and Half/Full Subtractors using logic gates.
Sl. No Name of the Component IC number Qty
1 AND gate 7408 1
2 OR gate 7432 1
3 Not gate 7404 1
4 EXOR gate 7486 3
5 NAND gate 7400 3
6 NOR gate 7402 3
7 Patch chords Few
8 Trainer Kit
Half Adder Using Basic Gates
Half Adder Using NAND Gates

Page 41
Full Adder:
Truth Table
Logic Diagram Using Basic Gates

Page 42
Using NAND Gates:
Half Subtractor
Truth Table Circuit Diagram
Dec INPUTS OUTPUTS

Eq
A B Diff Barrow
0 0 0 0 0
1 0 1 1 1
2 1 0 1 0
3 1 1 0 0
Using NAND gates

Page 43
Full Subtractor
Inputs Outputs
Truth Table Dec Equi
A B Bin Diff Borrow
0 0 0 0 0 0
1 0 0 1 1 1
2 0 1 0 1 1
3 0 1 1 0 1
4 1 0 0 1 0
5 1 0 1 0 0
6 1 1 0 0 0
7 1 1 1 1 1
Logic Diagram
Using NAND Gates

Page 44
Procedure:
1. Obtain the Boolean Expressions for Half/Full adder and subtractor (sum & Carry) by
writing the truth table and simplifying with the help of K-map.
2. Make the connections as shown in the logic diagram.
3. Apply different combinations of inputs according to the truth table and verify the
outputs.
4. Repeat the above procedure for all the circuit diagrams.
Conclusion:
EXPERIMENT NO 8
Parallel Adder/Subtractor and Code Conversion

Page 45
AIM: (1) Realization of Parallel adder/subtractor using 7483chip
(2) BCD to EXCESS-3 code conversion and vice versa
Aim: Realization of Parallel adder/subtractor using 7483chip

Components required:
Sl. No Component IC number Qty

1 EXOR gate 7486 1
2 4 bit parallel adder/subtractor 7483 1
3 Patch chords few
4 Trainer Kit
Pin diagram & Logic diagram
Block Diagram

Page 46
Procedure:
1. Make the connections as per logic diagram.
2. For addition, make Cin=0 and apply the 4 bits as input A and apply another set of 4-bits
as B. Observe the output at S3, S2 S1 S0 and carry generated at Cout.
3. Repeat the above steps for different inputs and tabulate the result.
4. For subtraction Cin is made 1.
5. Verify the difference. S3, S2 S1 S0 and Cout.
If Cout is 0, diff is negative and diff is 2‟s complement form.
If Cout is 1, diff is positive.
6. Repeat the above steps for different inputs and tabulate the result.
Readings:
Inputs Outputs
Cin
A4 A3 A2 A1 B4 B3 B2 B1 Carry S4 S3 S2 S1
Cout
1 0 0 1 1 0 0 1 1 0 0 1 0
0 for
addition 0 1 1 1 0 0 0 1 0 1 0 0 0
1 0 0 1 1 0 0 0 1 0 0 0 1
1 for
subtraction 0 0 0 1 0 0 1 1 0 1 1 1 0
Conclusion:

Page 47
Aim: Realization of BCD to Excess-3 code conversion and vice versa.
Truth table
BCD to Excess-3 Excess-3 to BCD
BCD (Inputs) Excess-3 (Outputs) Excess-3 (Inputs) BCD (Outputs)

A4 A3 A2 A1 X4 X3 X2 X1 X4 X3 X2 X1 S4 S3 S2 S1
0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0
0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1
0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0
0 0 1 1 0 1 1 0
0 1 1 0 0 0 1 1
0 1 0 0 0 1 1 1
0 1 1 1 0 1 0 0
0 1 0 1 1 0 0 0
1 0 0 0 0 1 0 1
0 1 1 0 1 0 0 1
1 0 0 1 0 1 1 0
0 1 1 1 1 0 1 0
1 0 1 0 0 1 1 1
1 0 0 0 1 0 1 1
1 0 1 1 1 0 0 0
1 0 0 1 1 1 0 0
1 1 0 0 1 0 0 1
Circuit Diagram
Procedure:

Page 48
1. Write Truth table for BCD to Excess-3 as well as Excess-3 to BCD conversion.
2. Obtain the simplified boolean expression using k-map.
3. Connections are made as per the logic diagram
 For BCD to Excess –3 code conversion 3 has to be added to input bits.

make Cin =0.
 For Excess-3 to BCD code conversion 3 has to be subtracted from the
input therefor Cin =1.
4. Apply different combinations of inputs and verify the truth table.
Conclusion
EXPERIMENT NO 9

Page 49
Binary to Gray code conversion
Aim: Realization of Binary to Gray code conversion and vice versa.
Sl.No Name of the component IC Number Quantity
1 EXOR gate 7486 1

2 NAND gate 7400 4
3 Patch chords Few
4 Trainer Kit
Binary to Gray code

G3 = ∑(8,9,10,11,12,13,14,15) G2 = ∑(4,5,6,7,8,9,10,11)
G1= ∑(2,3,4,5,10.,11,12,13) G0 = ∑(1,2,3,5,6,9,10,13,14)

Page 50
Truth Table:
Using XOR Gates:
BINARY GRAY CODE
Inputs Outputs
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
GRAY TO BINARY
Page 51
Truth Table:
GRAY CODE BINARY CODE
Inputs Outputs
G3 G2 G1 G0 B3 B2 B1 B0
Logic Diagram:
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
Procedure:
1. Write Truth table for Binary to Gray code as well as Gray code to Binary
conversion.

Page 52
2. Obtain the simplified boolean expression using k-map.
3. Connections are made as per the logic diagram
4. Apply different combinations of inputs and verify the truth table.
Conclusion
EXPERIMENT NO 10
Ring & Johnson Counters

Page 53
Aim: Design and testing of Ring counter/Johnson counter using IC-7495
RING COUNTER USING IC-7495
Name of the
Sl.No IC number
Component Quantity
1 Ring Counter 7495 1
2 NOT gate 7404 1
3 Patch chords few
4 Trainer Kit
Input Outputs
Clock
Q0 Q1 Q2 Q3
Pulse
t0 1 0 0 0
t1 0 1 0 0
t2 0 0 1 0
t3 0 0 0 1
t4 1 0 0 0
Procedure:
1. Connections are made as shown in the logic diagram.
2. The data 1 0 0 0 is applied at D0, D1, D2 & D3 respectively.
3. Keeping the mode M=1, one clock pulse is applied. The data 1 0 0 0 appears at
Q0, Q1, Q2 & Q3.
4. Keeping M=0, clock pulses are applied and truth table is verified.
.
JHONSON COUNTER USING IC-7495


Page 54
Input Outputs
Clock Q0 Q1 Q2 Q3
Pulse
t0 1 0 0 0
t1 1 1 0 0
t2 1 1 1 0
t3 1 1 1 1
t4 0 1 1 1
t5 0 0 1 1
t6 0 0 1 1
t7 0 0 0 1
t8 1 0 0 0
Procedure:
1. Connections are made as shown in the logic diagram.
2. The data 1 0 0 0 is applied at D3, D2, D1 & D0 respectively.
3. Keeping the mode M=1, one clock pulse is applied. The data 1 0 0 0 appears at
Q0, Q1, Q2 & Q3 respectively.
4. Keeping M=0, clock pulses are applied and truth table is verified.
Coclusion:
EXPERIMENT NO 11
Sequence Generator

Page 55
Aim: Design and testing of Sequence generator.

Take the sequence as: 100010011010111
Design: There are 15 bits, so there will be 15 states s=15. So at least 4 flip-flops are required.
Sl. Name of the
IC Number Quantity
No Component
1 Shift register 7495 1
2 Ex-OR 7486 1
3 NAND gate(3i/ps) 7410 1
4 Trainer Kit
5 Patch Chords few
Truth Table Simplification

Inputs Output
A B C D f
1 1 1 1 0
0 1 1 1 0
0 0 1 1 0
0 0 0 1 1
1 0 0 0 0
0 1 0 0 0
0 0 1 0 1
1 0 0 1 1
1 1 0 0 0
0 1 1 0 1
1 0 1 1 0
0 1 0 1 1
1 0 1 0 1
1 1 0 1 1
1 1 1 0 1

Page 56
Electronics Laboratory 2018
Procedure:
(1) The sequence is written such that no state repeats itself. The binary sequence is
repeated once in every 2N-1 clock cycles.
(2) The Expression for 'f ' is got using K-map.
(3) Rig up the circuit as shown in the figure.
(4) Initially let M = 1, clkp = cp, the initial state (A, B, C, D -1111) is loaded.
(5) Then make clks =Cp, M = 0, output is observed at MSB (A).
Note: When we observe the sequence, which is to be generated, the LSB is a 1, following bit
is 0. If 0 has to be generated, then input to that particular D-Flip Flop must be a 0. Therefore
f(QA, QB, QC, QD) has its first entry as 0.
Conclusion:
Dept. of Electrical and Electronics Engineering

Hirasugar Institute of Technology Page 57
EXPERIMENT NO 12
Mod-N Counter
Aim: Realization of 3-bit counters as a sequential circuit and mod-N counter design using
7476, 7490, 74192, 74193.
Sl.No Name of the Component IC Number Qty
1 Decade Counter 7490 1
2 Programmable 4-bit Sync 74192 1
up/down decade Counter
3 Programmable 4-bit Sync 74193 1
up/down Counter
4 Patch chords few
5 Trainer Kit
To realize a MOD-N counter using IC-7490

PIN DIAGRAM
INTERNAL DIAGRAM

Functional Table
Inputs Outputs
R1 R2 S1 S2 Qa Qb Qc Qd
H H L X L L L L
H H X L L L L L
X L H H 1 0 0 1
L X L X MOD-2 COUNTER
X L X L MOD-5 COUNTER
7490 AS MOD-2 COUNTER

Procedure:
1. Connections are as per the logic diagram.

2. Inputs are applied at R1, R2, S1 & S2.
3. Apply clock pulses one by one and verify the truth table.

PIN DETAILS OF IC-74192
MOD-6 UP COUNTER: Invalid state o110
MOD-9 DOWN COUNTER:

DESIGN A COUNTER WHICH CAN COUNT FROM 7 TO 9
NOTE After 1001, output becomes 0000
Procedure:
1. Connections are made as shown in the logic diagram with load pin open.
2. The present value is made available at the data inputs A, B, C and D.
3. The load pin is made low so that the present value appears at Qd, Qc, Qb and Qa.
4. The output of the gate is then connected to the load input.
5. Clock pulses are applied one by one and the truth table is verified.

MOD-N COUNTERS
To realize a MOD-N counter using IC-74193 with a given preset value, write down the
expected function table
Pin details of IC 74193(Synchronous counter)
FUNCTION TABLE
Inputs Outputs
Clr’ Load Up Down Qd Qc Qb Qa

H X X X 0 0 0 0
L L X X D C B A
L H Cp H COUNT UP
L H H Cp COUNT DOWN
L H H H NO CHANGE
Design a counter which counts from (6-12) Invalid state 1101

REALIZE A (15-6) COUNTER USING IC 74193
Invalid state---0101
Note:-Lo and Bo are used basically for cascading the counters
Procedure:
1. Connections are made as shown in the logic diagram with load pin open.
2. The present value is made available at the data inputs A, B, C and D.
3. The load pin is made low so that the present value appears at Qd, Qc, Qb and Qa.
4. The output of the gate is then connected to the load input.
5. Clock pulses are applied one by one and the truth table is verified.
Conclusion:


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S.J.P.

Hirasugar Institute of Technology, Nidasoshi

Tq: Hukkeri Dist: Belagavi

DEPARTMENT OF ELECTRICAL & ELECTRONICS

Name of the Lab: Electronics Laboratory

Prepared by: Prof. Sagar Sudhakar Birade

Dept. Electrical and Electronics Engineering.

Expt Date Date

Design and Testing of Full wave – centre tapped transformer

Dept. Electrical and Electronics Engineering.

Full Wave rectifier without Filter

Sl.No Name of the Component Quantity

Dept. Electrical and Electronics Engineering.

RL in  Vdc in Idc in mA Iac in mA Ripple Efficiency %Regulation

Dept. Electrical and Electronics Engineering.

For Full Wave rectifier with C-filter Vdc =Vm

Therefore transformer secondary voltage

PL =Vdc x IL(max) = 17 x 150x 10-3 = 2.55 watts

Choose RL = 150Ω by use of DRB

For Full wave rectifier with C-filter

Choose C= 470 µF /25V a standard value

Dept. Electrical and Electronics Engineering.

RL in  Idc in mA Iac in mA Ripple factor (γ)

6. Connect the circuit with Capacitor -filter as shown in the fig 4.

Dept. Electrical and Electronics Engineering.

Let output DC voltage required = 10V, and IL(max) = 150mA

Choose 230V/12V transformer

PL =Vdc x IL(max) = 10 x 150x 10-3 = 1.5 watts

Choose RL = 100Ω by use of DRB

Dept. Electrical and Electronics Engineering.

RL in  Vdc in Idc in mA Iac in mA Ripple Efficiency %Regulation

Dept. Electrical and Electronics Engineering.

For Full Wave rectifier with C-filter Vdc =Vm

Therefore transformer secondary voltage

PL =Vdc x IL(max) = 17 x 150x 10-3 = 2.55 watts

Choose RL = 150Ω by use of DRB

Dept. Electrical and Electronics Engineering.

RL in  Idc in mA Iac in mA Ripple

6. Connect the circuit with Capacitor -filter as shown in the fig 6.

Ripple Factor Efficiency % Regulation

Dept. Electrical and Electronics Engineering.

S.No. Name Quantity

h – Parameter model of CE transistor:

Dept. Electrical and Electronics Engineering.

1. Connect the circuit as shown in the circuit diagram.

Dept. Electrical and Electronics Engineering.

1. Connect the circuit as shown in the circuit diagram.

Calculations from Graph:

The h-parameters for a transistor in CE configuration are:

a. The Input Resistance (hie) _______________Ohms.

Dept. Electrical and Electronics Engineering.

S.No. Name Quantity

h – Parameter model of CB transistor:

Dept. Electrical and Electronics Engineering.

Dept. Electrical and Electronics Engineering.

Calculations from Graph:

The h-parameters are to be calculated from the following formulae:

a. The Input resistance (hib) __________________ Ohms.

Dept. Electrical and Electronics Engineering.

h – Parameter model of CB transistor:

Dept. Electrical and Electronics Engineering.

Dept. Electrical and Electronics Engineering.