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VHDL Concurrent Assignment Examples
VHDL Concurrent Assignment Examples
describes two wires in series. Automated synthesis tools will eliminate this unnecessary signal name.
This is not the same functionality that would result if this example was implemented as a sequentially
executed computer program. A computer program would execute the assignment of B to A first and then
assign the value of C to B second. In this way, B represents a storage element that is passed to A before
it is updated with C.
Each of the logical operators described in Sect. 3.1.2 can be used in conjunction with concurrent
signal assignments to create individual combinational logic circuits.
Example 3.1
SOP logic circuit: VHDL modeling using logical operators
26 • Chapter 3: Modeling Concurrent Functionality
Example 3.2
3-to-8 One-hot decoder: VHDL modeling using logical operators
3.2 Concurrent Signal Assignments with Logical Operators • 27
Let’s look at an example of how to design a 3-input, 7-segment decoder by hand. The first step in the
process is to create the truth table for the outputs that will drive the LEDs in the display. We’ll call these
outputs Fa, Fb, . . ., Fg. Example 3.3 shows how to construct the truth table for the 7-segment display
decoder. In this table, a logic 1 corresponds to the LED being ON.
Example 3.3
7-Segment display decoder: truth table
If we wish to design this decoder by hand, we need to create seven separate combinational logic
circuits. Each of the outputs (Fa–Fg) can be put into a 3-input K-map to find the minimized logic
expression. Example 3.4 shows the design of the decoder from the truth table in Example 3.3 by hand.
28 • Chapter 3: Modeling Concurrent Functionality
Example 3.4
7-Segment display decoder: logic synthesis by hand
This same functionality can be modeled in VHDL using concurrent signal assignments with logical
operators. Example 3.5 shows how to model the 7-segment decoder in VHDL using concurrent signal
assignments with logic operators. It should be noted that this example is somewhat artificial because a
design would typically not be minimized before modeling in VHDL. Instead, model would be entered at
the behavioral level, and then the CAD tool would be allowed to synthesize and minimize the final logic.
3.2 Concurrent Signal Assignments with Logical Operators • 29
Example 3.5
7-Segment display decoder: VHDL modeling using logical operators
Example 3.6
4-to-2 Binary encoder: logic synthesis by hand
In VHDL this can be implemented directly using logical operators. Example 3.7 shows how to model
the encoder in VHDL using concurrent signal assignments with logical operators.
3.2 Concurrent Signal Assignments with Logical Operators • 31
Example 3.7
4-to-2 Binary encoder: VHDL modeling using logical operators
Example 3.8
4-to-1 Multiplexer: VHDL modeling using logical operators
Example 3.9
1-to-4 Demultiplexer: VHDL modeling using logical operators
CONCEPT CHECK
CC3.2 Why does modeling combinational logic in its canonical form with concurrent signal
assignments with logical operators defeat the purpose of the modern digital design flow?
(A) It requires the designer to first create the circuit using the classical digital
design approach and then enter it into the HDL in a form that is essentially a
text-based netlist. This doesn’t take advantage of the abstraction capabilities
and automated synthesis in the modern flow.
(B) It cannot be synthesized because the order of precedence of the logical
operators in VHDL doesn’t match the precedence defined in Boolean algebra.
(C) The circuit is in its simplest form so there is no work for the synthesizer to do.
(D) It doesn’t allow an else clause to cover the outputs for any remaining input
codes not explicitly listed.