32-Bit Arm Cortex - M7 280 MHZ Mcus, 2-Mbyte Flash Memory, 1.4 Mbyte Ram, 46 Com. and Analog Interfaces, SMPS, Crypto
32-Bit Arm Cortex - M7 280 MHZ Mcus, 2-Mbyte Flash Memory, 1.4 Mbyte Ram, 46 Com. and Analog Interfaces, SMPS, Crypto
32-Bit Arm Cortex - M7 280 MHZ Mcus, 2-Mbyte Flash Memory, 1.4 Mbyte Ram, 46 Com. and Analog Interfaces, SMPS, Crypto
Datasheet
32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte Flash memory, 1.4 Mbyte
RAM, 46 com. and analog interfaces, SMPS, crypto
FBGA
Features
Includes ST state-of-the-art patented technology
LQFP64 TFBGA100
Core
(10 x 10 mm) (8 x 8 mm)
LQFP100 TFBGA216 • 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache:
(14 x 14 mm) (13x13 mm)
LQFP144 TFBGA225 16 Kbytes of data and 16 Kbytes of instruction cache allowing to fill one cache
(20x20 mm) (13x13 mm)
LQFP176 line in a single access from the 128-bit embedded Flash memory; frequency
(24 x 24 mm)
up to 280 MHz, MPU, 599 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
FBGA
Memories
• 2 Mbytes of Flash memory with read while write support, plus 1 Kbyte of OTP
UFBGA169 WLCSP132
(7 x 7 mm) (4.57 X 4.37 mm) memory
UFBGA176+25
(10x10 mm) • ~1.4 Mbytes of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM +
128 Kbytes of DTCM RAM for time critical routines), 1.18 Mbytes of user SRAM,
and 4 Kbytes of SRAM in Backup domain
• 2x Octo-SPI memory interfaces with on-the-fly decryption, I/O multiplexing and
support for serial PSRAM/NOR, Hyper RAM/Flash frame formats, running up to
140 MHz in SRD mode and up to 110 MHz in DTR mode
• Flexible external memory controller with up to 32-bit data bus:
– SRAM, PSRAM, NOR Flash memory clocked up to 125 MHz in
Synchronous mode
– SDRAM/LPSDR SDRAM
– 8/16-bit NAND Flash memories
Product summary • CRC calculation unit
STM32H7B3RI,
Security
STM32H7B3VI, • ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access
STM32H7B3QI, mode
STM32H7B3ZI,
STM32H7B3xI General-purpose input/outputs
STM32H7B3AI,
STM32H7B3II, • Up to 168 I/O ports with interrupt capability
STM32H7B3NI,
STM32H7B3LI
– Fast I/Os capable of up to 133 MHz
– Up to 164 5-V-tolerant I/Os
Low-power consumption
• Stop: down to 32 µA with full RAM retention
• Standby: 2.8 µA (Backup SRAM OFF, RTC/LSE ON, PDR OFF)
• VBAT: 0.8 µA (RTC and LSE ON)
Clock management
• Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
• External oscillators: 4-50 MHz HSE, 32.768 kHz LSE
• 3× PLLs (1 for the system clock, 2 for kernel clocks) with fractional mode
11 analog peripherals
• 2× ADCs with 16-bit max. resolution (up to 24 channels, up to 3.6 MSPS)
• 1× analog and 1x digital temperature sensors
• 1× 12-bit single-channel DAC (in SRD domain) + 1× 12-bit dual-channel DAC
• 2× ultra-low-power comparators
• 2× operational amplifiers (8 MHz bandwidth)
• 2× digital filters for sigma delta modulator (DFSDM), 1x with 8 channels/8 filters
and 1x in SRD domain with 2 channels/1 filter
Graphics
• LCD-TFT controller up to XGA resolution
• Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load
• Hardware JPEG Codec
• Chrom-GRC™ (GFXMMU)
Up to 19 timers and 2 watchdogs
• 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input (up to 280 MHz)
• 2× 16-bit advanced motor control timers (up to 280 MHz)
• 10× 16-bit general-purpose timers (up to 280 MHz)
• 3× 16-bit low-power timers (up to 280 MHz)
• 2× watchdogs (independent and window)
• 1× SysTick timer
• RTC with sub-second accuracy and hardware calendar
Cryptographic acceleration
• AES chaining modes: ECB,CBC,CTR,GCM,CCM for 128, 192 or 256
• HASH (MD5, SHA-1, SHA-2), HMAC
• 2x OTFDEC AES-128 in CTR mode for Octo-SPI memory encryption/decryption
• 1x 32-bit, NIST SP 800-90B compliant, true random generator
Debug mode
• SWD and JTAG interfaces
• 4 KB Embedded Trace Buffer
96-bit unique ID
All packages are ECOPACK2 compliant
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of the STM32H7B3xI
microcontrollers.
This document should be read in conjunction with the STM32H7B3xI reference manual (RM0455). The reference
manual is available from the STMicroelectronics website .
For information on the device errata with respect to the datasheet and reference manual, refer to the
STM32H7B3xI errata sheet (ES0478), available on the STMicroelectronics website .
For information on the Arm® Cortex®-M7 core, refer to the Cortex®-M7 Technical Reference Manual, available
from the www.arm.com website
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
2 Description
STM32H7B3xI devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to
280 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE
754 compliant) and single-precision data-processing instructions and data types. STM32H7B3xI devices support
a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.
STM32H7B3xI devices incorporate high-speed embedded memories with a dual-bank Flash memory of 2 Mbytes,
around 1.4 Mbyte of RAM (including 192 Kbytes of TCM RAM, 1.18 Mbytes of user SRAM and 4 Kbytes of
backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to four APB buses,
three AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and
external memory access.
All the devices offer two ADCs, two DACs (one dual and one single DAC), two ultra-low power comparators, a
low-power RTC, 12 general-purpose 16-bit timers, two PWM timers for motor control, three low-power timers,
a true random number generator (RNG), and a cryptographic acceleration cell and a HASH processor. The
devices support nine digital filters for external sigma delta modulators (DFSDM). They also feature standard and
advanced communication interfaces.
• Standard peripherals
– Four I2Cs
– Five USARTs, five UARTs and one LPUART
– Six SPIs, four I2Ss in full-duplex mode. To achieve audio class accuracy, the I2S peripherals can be
clocked via a dedicated internal audio PLL or via an external clock to allow synchronization.
– Two SAI serial audio interfaces, out of which one with PDM
– One SPDIFRX interface
– One single wire protocol master interface (SWPMI)
– One 16-bit parallel synchronous slave interface (PSSI) sharing the same interface as the digital
camera)
– Management Data Input/Output (MDIO) slaves
– Two SDMMC interfaces (one can be supplied from a supply voltage separate from that of all other I/Os)
– A USB OTG high-speed with full-speed capability (with the ULPI)
– One FDCAN plus one TT-CAN interface
– Chrom-ART Accelerator
– HDMI-CEC
• Advanced peripherals including
– A flexible memory control (FMC) interface
– Two octo-SPI memory interface with on-the-fly decryption (OTFDEC)
– A digital camera interface for CMOS sensors (DCMI)
– A graphic memory management unit (GFXMMU)
– An LCD-TFT display controller (LTDC)
– A JPEG hardware compressor/decompressor
Refer to Table 1. STM32H7B3xI features and peripheral counts for the list of peripherals available on each part
number.
STM32H7B3xI devices operate in the –40 to +85 °C ambient temperature range from a 1.62 to 3.6 V
power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see
Section 3.5.2 Power supply supervisor) and connecting the PDR_ON pin to VSS. Otherwise the supply voltage
must stay above 1.71 V with the embedded power voltage detector enabled.
The USB OTG_HS/FS interfaces can be supplied either by the integrated USB regulator or through a separate
supply input.
A dedicated supply input is available for one of the SDMMC interface for package with more than 100 pins. It
allows running from a different voltage level than all other I/Os.
A comprehensive set of power-saving mode allows the design of low-power applications.
The CPU and domain states can be directly monitored on some GPIOs configured as alternate functions.
STM32H7B3xI devices are offers in several packages ranging from 64 pins to 225 pins/balls. The set of included
peripherals changes with the device chosen.
These features make the STM32H7B3xI microcontrollers suitable for a wide range of applications:
• Motor drive and application control
• Medical equipment
• Industrial applications: PLC, inverters, circuit breakers
• Printers, and scanners
• Alarm systems, video intercom, and HVAC
• Home audio appliances
• Mobile applications, Internet of Things
• Wearable devices: smart watches.
Figure 1. STM32H7B3xI block diagram shows the general block diagram of the device family.
STM32H7B3QIY
STM32H7B3NIH
STM32H7B3VIH
STM32H7B3VIH
STM32H7B3LIH
STM32H7B3RIT
STM32H7B3VIT
STM32H7B3VIT
STM32H7B3ZIT
STM32H7B3ZIT
STM32H7B3IIK
STM32H7B3AII
STM32H7B3IIK
STM32H7B3IIT
STM32H7B3IIT
Peripherals
SRAM on AHB
SRAM in 128
(CD domain)
Kbytes
SRAM on AHB
32
(SRD domain)
ITCM RAM
64
TCM RAM in (instruction)
Kbytes DTCM RAM
128
(data)
Interface 1
NOR Flash
memory/RAM x x (2) - x(2) - x x(2) -
controller
Multiplexed I/O
FMC NOR Flash x x(2) x x(2) -
memory
16-bit NAND
x x(2) - x x(2) -
Flash memory
SDRAM
x x(2) - x x(2) -
controller
1 Quad- 1 Quad-
Octo-SPI interfaces(3) 2 2 (4) 2 (5) 1 2 2(4) 1
SPI SPI
General-
10
purpose
STM32H7B3xI
Advanced-
Timers 2
control (PWM)
Basic 2
Low-power 3
page 7/231
Window watchdog /
1/1
independent watchdog
DS13139 - Rev 7
STM32H7B3QIY
STM32H7B3NIH
STM32H7B3VIH
STM32H7B3VIH
STM32H7B3LIH
STM32H7B3RIT
STM32H7B3VIT
STM32H7B3VIT
STM32H7B3ZIT
STM32H7B3ZIT
STM32H7B3IIK
STM32H7B3AII
STM32H7B3IIK
STM32H7B3IIT
STM32H7B3IIT
Peripherals
Cryptographic accelerator 1
for external
On-the-fly
Octo-SPI 2 2 2(2) 2 2 2(2)
decryption
memory
I2C 4 3
FDCAN/TT-
1/1 1/1(2)
CAN
USB OTG_HS
ULPI, OTG_FS 1 1(9) 1 1(9) 1 1(9) 1 1 (9) 1 (10)
PHY
STM32H7B3xI
JPEG Codec 1
Chrom-ART Accelerator
1
(DMA2D)
page 8/231
STM32H7B3QIY
STM32H7B3NIH
STM32H7B3VIH
STM32H7B3VIH
STM32H7B3LIH
STM32H7B3RIT
STM32H7B3VIT
STM32H7B3VIT
STM32H7B3ZIT
STM32H7B3ZIT
STM32H7B3IIK
STM32H7B3AII
STM32H7B3IIK
STM32H7B3IIT
STM32H7B3IIT
Peripherals
HDMI CEC 1
DFSDM 2
Number of filters for DFSDM1/
8/1 7/1 8/1 7/1
DFSDM2
8 to 16 bits 2
ADCs Number of
24 24 20 (12) 24 18(12) 17(12) 16(12) 20(12) 16(12)
channels
12 bits 2
DACs Number of
3 (1 single channel + 1 dual-channel interfaces)
channels
Comparators 2 2(2) 2 1
Wakeup pins 6 4 6 4
TFBGA UFBGA LQFP UFBGA LQFP WLCSP TFBGA LQFP TFBGA UFBGA LQFP LQFP TFBGA LQFP LQFP
STM32H7B3xI
Packages
225 176+25 176 169 144 132 100 100 216 176+25 176 144 100 100 64
USART,
USART, I2C, SPI,
USART, I2C, SPI, USART, I2C, SPI, USB-DFU,
page 9/231
Bootloader I2C, SPI, USB- USART, I2C, SPI, USB-DFU USART, I2C, SPI, USB-DFU
USB-DFU, FDCAN FDCAN
USB-DFU DFU,
FDCAN
1. The devices with SMPS correspond to commercial code STM32H7B3xIxxQ.
DS13139 - Rev 7
2. For limitations on peripheral features depending on packages, check the available pins/balls in Table 7. STM32H7B3xI pin/ball definition.
3. To maximize the performance, the I/O high-speed at low-voltage feature (HSLV) must be activated when VDD < 2.7 V. This feature is not available
on all I/Os (see Table 89. OCTOSPI characteristics in SDR mode, and Table 90. OCTOSPI characteristics in DTR mode (with DQS)/Octal and
Hyperbus).
4. The I/O high-speed at low-voltage feature (HSLV) at VDD < 2.7 V is not available for OCTOSPIM_P2.
5. The two OCTOSPIs are available only in Muxed mode.
6. A tamper pin can be configured either as passive or active (not both).
7. SPI1, SPI2, SPI3 and SPI6 interfaces give the flexibility to work in an exclusive way in either SPI mode or I2S audio mode.
8. Dedicated I/O supply pad (VDDMMC) or external level shifter are not supported.
9. The ULPI interface is supported. PC2 and PC3 are available on PC2_C and PC3_C, respectively, by closing the internal analog switch (see
Table 7. STM32H7B3xI pin/ball definition).
10. The ULPI interface is not supported.
11. DCMI and PSSI cannot be used simultaneously since they share the same circuitry.
12. For limitations on fast pads or channels depending on packages, check to the available pins/balls in Table 7. STM32H7B3xI pin/ball definition.
13. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2 Power supply supervisor) and connecting PDR_ON
pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled.
14. The junction temperature is limited to 105 °C in VOS0 voltage range.
STM32H7B3xI
page 10/231
STM32H7B3xI
AHB1 AHB2
I-TCM D-TCM D-TCM CPU_AHBP
64KB 64KB 64KB PHY
AXI/AHB12 (280 MHz) DMA1 DMA2 OTG_FS SDMMC2 BDMA1 8ch
for DFSDM
AHBP 1 MB FLASH
ARM CPU DMA/
JTRST, JTDI, Cortex-M7 1 MB FLASH 8 Stream 8 Stream FIFO
FIFOs FIFOs FIFO
JTCK/SWCLK JTAG/SW 280 MHz 256 KB
JTDO/SWD, JTDO AXIM AXI_SRAM1
TRACECK ETM
384 KB
AXI_SRAM2 32-bit AHB BUS-MATRIX
TRACED[3:0] I-Cache D-Cache
384 KB
16KB 16KB
AXI_SRAM3
OCTOSPI1
OTFDEC1 common to ADC1&2
OCTOSPI1_signals
DMA ADC2 Up to 20 analog inputs
CHROM-ART
FIFO
OCTOSPIM
Analog Temp Sensor
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
CRC
LCD_VSYNC, LCD_DE, LCD_CLK LCD-TFT FIFO TIM2 4 channels, ETR as AF
OCTOSPI2
RNG
APB3 (140 MHz)
32b
OTFDEC2
HSEM
TIM13 1 channel as AF
HSYNC, VSYNC, PIXCLK, D[13:0] DCMI 16b
AHB2 280 MHz (max)
PDCK, DE, RDY, D[15:0] PSSI TIM14 1 channel as AF
16b
AHB/APB AHB1 280 MHz (max) smcard RX, TX, SCK, CTS,
DFSDM_CKOUT,
USART2
irDA RTS as AF
DFSDM_DATAIN[7:0], DFSDM1 8ftrs
DFSDM_CKIN[7:0] smcard RX, TX, SCK
USART3 CTS, RTS as AF
irDA
FIFO FIFO
TIM7 16b
MOSI, MISO, SCK, NSS /
SPI/I2S1 UART7 RX, TX as AF
SDO, SDI, CK, WS, MCK, as AF
SWPMI
A P B 10 MHz
SPI4
3
MOSI, MISO, SCK, NSS as AF SPI5 SPI2/I2S2 MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
smcard MOSI, MISO, SCK, NSS /
SPI3/I2S3
RX, TX, SCK, CTS, RTS as AF
irDA USART1
APB1 140 MHz (max)
smcard
RX, TX, SCK, CTS, RTS as AF
irDA USART6
I2C1/SMBUS SCL, SDA, SMBAL as AF
10 KB SRAM
Digital filter
DMA
RX, TX as AF UART9 Mux2 I2C2/SMBUS SCL, SDA, SMBAL as AF
smcard DAP
RX, TX, SCK, CTS, RTS as AF
irDA USART10
BDMA2 I2C3/SMBUS SCL, SDA, SMBAL as AF
2 compl. chan.(TIM15_CH1[1:2]N), TIM15
2 chan. (TIM_CH15[1:2], BKIN as AF 16b MDIOS MDC, MDIO
1 compl. chan.(TIM16_CH1N),
TIM16 32-bit AHB BUS-MATRIX RAM TT-FDCAN1 TX, RX
AHB4
FIFO
LPTIM1_IN1, LPTIM1_IN2,
PK[7:0] GPIO PORTK LPTIM1 16b LPTIM2_OUT as AF
OPAMPx_VINM
OPAMP1&2 OPAMPx_VINP
AHB4
@VDD33 OPAMPx_VOUT as AF
RCC VDD12
DFSDM_CKOUT, BBgen + POWER MNGT VDD
Reset & VDDMMC
DFSDM_DATAIN[1:0], DFSDM2 1ftr Digital Temp Sensor Voltage SMPS
PWRCTRL
Clock VSS
DFSDM_CKIN[1:0]
Control regulator Step-down VCAP, VDDLDO
IWDG VDDSMPS, VSSSMPS
COMPx_INP, COMPx_INM, COMP1&2 AHB/ 3.3 to 1.2V converter VLXSMPS, VFBSMPS
COMPx_OUT as AF APB
Tamper monitor Temp USB regulator
VDD50USB
VDD33USB
DAC2_OUT1 as AF DAC2 Monitor Vbat charging
LPTIM2
APB4
APB4
OSC32_OUT
SCL, SDA, SMBAL as AF I2C4 RTC RTC_TS
MOSI, MISO, SCK, NSS /
SPI6/I2S6 @VDD Backup registers RTC_TAMP[1:3]
SYSCFG
LS
3 Functional overview
3.3 Memories
3.6
VDDX(1)
VDD
VPOR
VPDR
0.3
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
1. VDDx refers to any power supply among VDDA, VDD33USB and VDD50USB.
2. VDD and VDDSMPS must be wired together into order to follow the same voltage sequence.
CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE
(Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex®-M7 core is set after returning from an
interrupt service routine.
The CPU domain can enter low-power mode (DStop or DStop2) when the processor, its subsystem and the
peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared and the power domains
are in DStop or DStop2 mode.
System power mode CD domain power mode SRD domain power mode
Some GPIO pins can be used to monitor CPU and domain power states:
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow interconnecting bus masters with bus slaves (see
Figure 3. STM32H7B3xI bus matrix).
AHBS
CPU ITCM
Cortex-M7 64 Kbytes
I$ D$ DTCM
16KB 16KB 128 Kbytes
DMA1 DMA2 SDMMC2 USBHS1 BDMA1
AXIM
AHBP
DMA1_PERIPH
DMA2_PERIPH
DMA2_MEM
DMA1_MEM
SDMMC1 MDMA DMA2D LTDC
AXI to AHB
AHB SRAM1
64 Kbytes
GFX-MMU AHB SRAM2 64
Kbytes
AHB3 APB3
AHB1
Flash Bank 1
1 Mbyte AHB2
FLIFT
Flash Bank 2
1 Mbyte APB1
FMC APB2
OTFDEC1 OCTOSPI1
OTFDEC2 OCTOSPI2
AXI SRAM1
256 Kbytes
AXI SRAM2
384 Kbytes 32-bit AHB bus matrix
AXI SRAM3 CD domain
384 Kbytes
64-bit AXI bus matrix
CD domain
Legend
Bus-interconnect matrix
TCM AHB AHB4 APB4
32-bit bus
STM32H7B3xI
AXI APB
SRD SRAM
64-bit bus Master interface 32 Kbytes
Bus multiplexer Slave interface Backup
32-bit AHB bus matrix SRAM
4 Kbytes
SRD domain
page 19/231
STM32H7B3xI
DMA controllers
Multichip package (MCP) combining any of the above mentioned memory types can also be supported.
The three 12-bit buffered DAC channels can be used to convert three digital signals into three analog voltage
signal outputs.
The following feature are supported:
• three DAC converters: one for each output channel
• 8-bit or 12-bit monotonic output
• left or right data alignment in 12-bit mode
• synchronized update capability
• noise-wave generation
• triangular-wave generation
• Triple DAC channel independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• external triggers for conversion
• input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected to different DMA
streams.
Max
Capture/ Max
DMA Comple- timer
Counter Counter interface
Timer type Timer Prescaler factor request compare mentary clock
resolution type clock
generation channels output (MHz)
(MHz) (1)
Any integer
Advanced- TIM1, Up, Down,
16-bit between 1 and Yes 4 Yes 140 280
control TIM8 Up/down
65536
Any integer
TIM2, Up, Down,
32-bit between 1 and Yes 4 No 140 280
TIM5 Up/down
65536
Any integer
TIM3, Up, Down,
16-bit between 1 and Yes 4 No 140 280
TIM4 Up/down
65536
Any integer
TIM12 16-bit Up between 1 and No 2 No 140 280
General 65536
purpose Any integer
TIM13,
16-bit Up between 1 and No 1 No 140 280
TIM14
65536
Any integer
TIM15 16-bit Up between 1 and Yes 2 1 140 280
65536
Any integer
TIM16,
16-bit Up between 1 and Yes 1 1 140 280
TIM17
65536
Any integer
TIM6,
Basic 16-bit Up between 1 and Yes 0 No 140 280
TIM7
65536
LPTIM1,
Low-power 1, 2, 4, 8, 16, 32,
LPTIM2, 16-bit Up No 0 No 140 280
timer 64, 128
LPTIM3
1. The maximum timer clock is up to 280 MHz depending on TIMPRE bit in the RCC_CFGR register and
CDPRE1/2 bits in RCC_CDCFGR register.
• Output compare
• PWM generation (edge- or center-aligned modes)
• One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If
configured as 16-bit PWM generators, they have full modulation capability (0-100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization
or event chaining.
The advanced-control timers support independent DMA request generation.
Four standard I2S interfaces (multiplexed with SPI1, SPI2, SPI3, SPI6) are available. They can be operated in
master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit
resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported.
When one or all I2S interfaces is/are configured in master mode, the master clock can be output to the external
DAC/codec at 256 times the sampling frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs
with DMA capability.
• 32 MDIO register addresses, each of which is managed using separate input and output data registers:
– 32 x 16-bit firmware read/write, MDIO read-only output data registers
– 32 x 16-bit firmware read-only, MDIO write-only input data registers
• Configurable slave (port) address
• Independently maskable interrupts/events:
– MDIO register write
– MDIO register read
– MDIO protocol error
• Able to operate in and wake up from STOP mode
4 Memory mapping
Refer to the product line reference manual (RM0455) for details on the memory mapping as well as the boundary
addresses for all peripherals.
5 Pin descriptions
BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD2
PB9
PB8
PB7
PB6
PB5
PB4
PB3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VBAT 1 48 VDD
PC13 2 47 VSS
PC14-OSC32_IN 3 46 VCAP
PC15-OSC32_OUT 4 45 PA13
PH0-OSC_IN 5 44 PA12
PH1-OSC_OUT 6 43 PA11
NRST 7 42 PA10
PC0 8 41 PA9
LQFP64
PC1 9 40 PA8
PC2 10 39 PC9
PC3 11 38 PC7
VSSA 12 37 PC6
VDDA 13 36 PB15
PA0 14 35 PB14
PA1 15 34 PB13
PA2 16 33 PB12
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PB10
VCAP
VSS
VDD
PA3
PA4
PA5
PA6
PA7
VDD33USB
VDDLDO
BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PE2 1 75 VDD
PE4 2 74 VDDLDO
PE5 3 73 VSS
VDD 4 72 VCAP
VBAT 5 71 PA13
PC13 6 70 PA12
PC14-OSC32_ON 7 69 PA11
PC15-OSC32_OUT 8 68 PA10
VSSMPS 9 67 PA9
VLXSMPS 10 66 PA8
VDDSMPS 11 65 PC9
VFBSMPS 12 64 PC8
LQFP100
PH0-OSC_IN 13 63 PC7
PH1-OSC_OUT 14 62 PC6
NRST 15 61 PD15
PC0 16 60 PD14
PC1 17 59 VDD
PC2_C 18 58 VSS
PC3_C 19 57 PD13
VDD 20 56 PD12
VSS 21 55 PD11
VSSA 22 54 PD10
VREF+ 23 53 PD9
VDDA 24 52 PD8
PA0 25 51 PB15
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PB10
VCAP
VSS
PB14
PA1
PA2
PA3
PB13
PA4
PA5
PA6
PA7
PB11
VDD
VDDLDO
PB12
BOOT0
PC12
PC10
PC11
PA15
PA14
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VCAP
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_ON 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT
LQFP100
13 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2_C 17 59 PD12
PC3_C 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VSS
VDD
PA4
PA5
PA6
PA7
PE11
PB11
1 2 3 4 5 6 7 8 9 10
A PE6 PE5 PE2 PB8 BOOT0 PB5 PD6 PD3 PD2 PC12
PC15-
PC14-
B OSC32_ PE3 PE0 PB7 PB3 PD4 PD1 PC11 PC10
OSC32_IN
OUT
C VSS VBAT PE4 PE1 PB4 PD7 PD0 PA15 PA14 PA13
D VSSSMPS VLXSMPS PDR_ON PB6 VSS VDD PD5 VCAP PA12 PA11
VDD33
E VDDSMPS VFBSMPS PB9 PC13 VDD VDDLDO VSS PA9 PA10
USB
VDD50
F PC1 NRST PC0 PC2_C VSS VDD PC6 PC9 PA8
USB
PH0- PH1-
G PA0 PC3_C PA3 VCAP PD14 PD15 PC7 PC8
OSC_IN OSC_OUT
H VDDA VSSA PA2 PC4 PE7 PE10 PD11 PD9 PD12 PD13
J VREF+ PA1 PA6 PC5 PB2 PE8 PB11 PB13 PD8 PD10
K PA4 PA5 PA7 PB0 PB1 PE9 PB10 PB12 PB14 PB15
1 2 3 4 5 6 7 8 9 10
PC14-
A PC13 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13
OSC32_IN
PC15-
B OSC32_ VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12
OUT
PH0-
C VSS PE4 PE1 PB5 PD6 PD3 PC12 PA9 PA11
OSC_IN
PH1-
D VDD PE5 PE0 BOOT0 PD7 PD4 PD0 PA8 PA10
OSC_OUT
E NRST PC2_C PE6 VSS VSS VSS VCAP PD1 PC9 PC7
VDD33
F PC0 PC1 PC3_C VDD VDD PDR_ON VCAP PC8 PC6
USB
G VSSA PA0 PA4 PC4 PB2 PE10 PE14 PD15 PD11 PB15
H VDDA PA1 PA5 PC5 PE7 PE11 PE15 PD14 PD10 PB14
J VSS PA2 PA6 PB0 PE8 PE12 PB10 PB13 PD9 PD13
K VDD PA3 PA7 PB1 PE9 PE13 PB11 PB12 PD8 PD12
1 2 3 4 5 6 7 8 9 10 11 12
A VSS VDD PC10 PD3 VSS PG10 VDD PB3 BOOT0 VCAP VDDLDO VDD
PC14-
VDD
B VDDLDO VSS PC12 PD4 PG11 VSS VDDMMC PB8 VSS VDD OSC32_
MMC
IN
PC15-
C PA12 VCAP PA15 PD0 PD5 PG12 PG14 PB6 PE1 PE6 OSC32_ VSS
OUT
D PA11 PA10 PA13 PC11 PD2 PG9 PG13 PB7 PDR_ON PE5 VBAT VSSSMPS
E PC7 PC9 PA8 PA14 PD1 PD7 PB4 PB9 PE3 PC13 VFBSMPS VLXSMPS
VDD33 VDD50
F PC6 PA9 PB10 PD6 PB5 PE0 PE4 NRST VSS VDDSMPS
USB USB
PH0-
G VDD VSS PD12 PD11 PE15 PE10 PA6 PA1 PC3 PC0 VDD
OSC_IN
PH1-
H PD15 PD13 PD8 PB15 PE14 PE8 PC4 PA2 VSS VDD PC1
OSC_OUT
J PD14 PD9 PB14 PB11 PE11 PE9 PB1 PC5 PA3 VDDA VREF+ PC2
K PD10 PB13 VDDLDO VSS PE12 VSS PF14 PB0 PA7 PA4 PA0 VSSA
L VDD PB12 VDD VCAP PE13 VDD PE7 PB2 VSS VDD PA5 VSS
VDDMMC
VDDLDO
PDR_ON
BOOT0
VCAP
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
VDD
VDD
VSS
VSS
PG9
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PE2 1 108 PA15
PE3 2 107 PA14
PE4 3 106 VDD
PE5 4 105 VDDLDO
PE6 5 104 VSS
VSS 6 103 VCAP
VDD 7 102 PA13
VBAT 8 101 PA12
PC13 9 100 PA11
PC14-OSC32_IN 10 99 PA10
PC15-OSC32_OUT 11 98 PA9
VSS 12 97 PA8
VDD 13 96 PC9
VSSSMPS 14 95 PC8
VLXSMPS 15 94 PC7
VDDSMPS 16 93 PC6
VFBSMPS 17 92 VDD
VSS 18 91 VDD33USB
VDD 19
LQFP144 90 VDD50USB
PF6 20 89 VSS
PF7 21 88 PG8
PF8 22 87 PG7
PF9 23 86 PG6
PF10 24 85 PD15
PH0-OSC_IN 25 84 PD14
PH1-OSC_OUT 26 83 PD13
NRST 27 82 PD12
PC0 28 81 PD11
PC1 29 80 VSS
PC2_C 30 79 VDD
PC3_C 31 78 PD10
VDD 32 77 PD9
VSS 33 76 PD8
VSSA 34 75 PB15
VREF+ 35 74 PB14
VDDA 36 73 PB13
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PF14
PF15
VSS
VDD
PE7
PE8
PE9
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VSS
VDDLDO
VDD
PB12
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PF11
PE11
PB11
VDDMMC
PDR_ON
BOOT0
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
VDD
VDD
VSS
PG9
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VCAP
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD33USB
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 91 PG6
PF7 19
LQPF144 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2_C 28 81 PD12
PC3_C 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VDD
PA3
PA4
PA5
PA6
PA7
PF11
PE11
PB11
VDDMMC
VDDLDO
PDR_ON
VDDLDO
BOOT0
VCAP
VCAP
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
VDD
VDD
VDD
VSS
VSS
PG9
VSS
VSS
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1 132 PA13
PE3 2 131 PA12
PE4 3 130 PA11
PE5 4
129 PA10
PE6 5
128 PA9
VSS 6
127 PA8
VDD 7
126 VDD
VBAT 8
125 PC9
PC13 9 124 PC8
PC14-OSC32_IN 10 123 PC7
PC15-OSC32_OUT 11 122 PC6
VSS 12 121 VDD33USB
VDD 13 120 VDD50USB
VSSSMPS 14 119 VSS
VLXSMPS 15 118 PG8
VDDSMPS 16 117 PG7
VFBSMPS 17 116 PG6
PF0 18 115 PG5
PF1 19 114 PG4
PF2 20 113 VDD
PF3 21 112 VSS
PF4 22 111 PG3
PF5 23 LQFP176
110 PG2
VSS 24 109 PK2
VDD 25 108 PK1
PF6 26 107 PK0
PF7 27 106 VSS
PF8 28 105 VDD
PF9 29 104 PJ11
PF10 30 103 PJ10
PH0-OSC_IN 31 102 PJ9
PH1-OSC_OUT 32 101 PJ8
NRST 33 100 VSS
PC0 34 99 VDD
PC1 35 98 PD15
PC2_C 36 97 PD14
PC3_C 37 96 PD13
VSSA 38 95 PD12
VREF+ 39 94 PD11
VDDA 40 93 VSS
PA0 41 92 VDD
PA1 42 91 PD10
PA2 43 90 PD9
VDD 44 89 PD8
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PF12
PF13
PF14
PF15
PG0
VSS
PG1
VDD
PE7
PE8
PE9
VSS
VSS
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VDDLDO
VDD
PB12
PB13
PB14
PB15
PA3
PA4
PA5
PA6
PA7
PF11
PE11
PB11
VDDMMC
PDR_ON
BOOT0
PG15
PG14
PG13
PG12
PG10
PC12
PC10
PG11
PC11
PA15
PA14
VDD
VDD
VDD
VSS
PG9
VSS
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PE1
PE0
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PI7
PI6
PI5
PI4
PI3
PI2
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1 132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4
129 PH14
PE6 5
128 PH13
VBAT 6
127 VDD
PI8 7
126 VSS
PC13 8
125 VCAP
PC14-OSC32_IN 9 124 PA13
PC15-OSC32_OUT 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDD33USB
PF4 20 113 VSS
PF5 21 112 PG8
VSS 22 111 PG7
VDD 23 LQFP176
110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
PF10 28 105 PD15
PH0-OSC_IN 29 104 PD14
PH1-OSC_OUT 30 103 VDD
NRST 31 102 VSS
PC0 32 101 PD13
PC1 33 100 PD12
PC2_C 34 99 PD11
PC3_C 35 98 PD10
VDD 36 97 PD9
VSSA 37 96 PD8
VREF+ 38 95 PB15
VDDA 39 94 PB14
PA0 40 93 PB13
PA1 41 92 PB12
PA2 42 91 VDD
PH2 43 90 VSS
PH3 44 89 PH12
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PH4
PH5
VSS
VDD
PC4
PC5
PB0
PB1
PB2
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE12
PE13
PE14
PE15
PB10
VCAP
VDD
PH6
PH7
PH8
PH9
PH10
PA3
PA4
PA5
PA6
PA7
PF11
PE11
PB11
PH11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A PE4 PE3 PE2 PG14 PE1 PE0 PB8 PB5 PB4 PB3 PD7 PC12 PA15 PA14 PA13
B PE5 PE6 PG13 PB9 PB7 PB6 PG15 PG11 PJ13 PJ12 PD6 PD0 PC11 PC10 PA12
C VBAT PI8 PI4 PK7 PK6 PK5 PG12 PG10 PJ14 PD5 PD3 PD1 PI3 PI2 PA11
D
PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 PJ15 PD4 PD2 PH15 PI1 PA10
PC14-
E PDR VDD
OSC32_ PF1 PI12 PI9 BOOT0 VDD VDD VDD VCAP PH13 PH14 PI0 PA9
_ON MMC
IN
PC15-
F OSC32_ VSS PI11 VDD VDD VSS VSS VSS VSS VSS VDD PK1 PK2 PC9 PA8
OUT
PH0-
G VDD33
OSC_ PF2 PI13 PI15 VDD VSS VSS PJ11 PK0 PC8 PC7
USB
IN
PH1-
H OSC_ PF3 PI14 PH4 VDD VSS VSS VDD PJ8 PJ10 PG8 PC6
OUT
J NRST PF4 PH5 PH3 VDD VSS VSS VDD PJ7 PJ9 PG7 PG6
K PF7 PF6 PF5 PH2 VDD VSS VSS VSS VSS VSS VDD PJ6 PD15 PB13 PD10
L PF10 PF9 PF8 PC3_C VSS VSS VDD VDD VDD VDD VCAP PD14 PB12 PD9 PD8
M VSSA PC0 PC1 PC2_C PB2 PF12 PG1 PF15 PJ4 PD12 PD13 PG3 PG2 PJ5 PH12
N VREF− PA1 PA0 PA4 PC4 PF13 PG0 PJ3 PE8 PD11 PG5 PG4 PH7 PH9 PH11
P VREF+ PA2 PA6 PA5 PC5 PF14 PJ2 PF11 PE9 PE11 PE14 PB10 PH6 PH8 PH10
R VDDA PA3 PA7 PB1 PB0 PJ0 PJ1 PE7 PE10 PE12 PE15 PE13 PB11 PB14 PB15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A VSS PI4 PB9 PB6 PG15 PK5 PG14 PG10 PG9 PD7 PD4 PD1 PC10 PI3 VSS
B PE3 PI5 PE0 PB8 PB4 PK6 PK3 PG11 PJ15 PD6 PD2 PC12 PA14 PH15 PH14
C PI8 PE4 PI6 PE1 BOOT0 PB3 PK4 PG12 PJ14 PD5 PD0 PA15 PI0 PA12 PA11
PC15-
D PC14- PE5 PI7 PDR_ON PB7 PK7 PG13 PJ13 PD3 PC11 PI2 PH13 VSS VDD50
OSC32_
OSC32_IN USB
OUT
E VSS VBAT PI9 PE6 PE2 VCAP PB5 VDD PJ12 VDDLDO PI1 PA13 PA10 PC9 PC7
MMC
VLX VFB
F PI10 PC13 VDDLDO VSS VDD VSS VDD VSS VCAP PA9 PC8 PC6 PG8
SMPS SMPS
VDD VSS
G PF1 PF0 PI11 VDD VDD VSS VDD VDD PA8 PG7 PG6 PG5 PG3
SMPS SMPS
PF2 PI12 PF4 PI14 PI13 VSS VSS VSS VSS VSS VDD33 PG4 PG2 PK2 PK1
H
USB
J PF3 PF5 PF6 PF7 PC2 VDD VDD VSS VDD VDD PJ11 PK0 PJ10 PJ9 PJ8
PF8 PF9 NRST VREF− VSSA VSS VDD VSS VDD VSS PD13 PD14 PD15 PJ6 PJ7
K
PH0- PH1-
L PC0 VREF+ VDDA PA4 PB1 VCAP PE12 VDDLDO PH12 PD8 PD10 PD11 PD12
OSC_IN OSC_OUT
VSS PC1 PF10 PH2 PH4 PC4 PI15 PF13 PE7 PE13 PH6 PH10 PB13 PB14 PB15
M
N PC2_C PC3_C PC3 PH3 PA5 PC5 PJ0 PF11 PF15 PE14 PE10 PJ5 PH9 PB12 PD9
P PA0 PA1 PA0_C PH5 PA6 PB0 PJ1 PJ4 PF14 PG1 PE9 PE15 PB11 PH8 PH11
R VSS PA2 PA1_C PA3 PA7 PB2 PJ2 PJ3 PF12 PG0 PE8 PE11 PB10 PH7 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13
A PE4 PE2 VDD VCAP PB6 VDDMMC VDD PG10 PD5 VDD PC12 PC10 PH14
PC15-
B OSC32_ PE3 VSS VDDLDO PB8 PB4 VSS PG11 PD6 VSS PC11 PA14 PH13
OUT
PC14-
C OSC32_IN PE6 PE5 PDR_ON PB9 PB5 PG14 PG9 PD4 PD1 PA15 VSS VDD
D VDD VSS PC13 PE1 PE0 PB7 PG13 PD7 PD3 PD0 PA13 VDDLDO VCAP
E VLXSMPS VSSSMPS VBAT PF1 PF3 BOOT0 PG15 PG12 PD2 PA10 PA9 PA8 PA12
F VDDSMPS VFBSMPS PF0 PF2 PF5 PF7 PB3 PG4 PC6 PC7 PC9 PC8 PA11
G VDD VSS PF4 PF6 PF9 NRST PF13 PE7 PG6 PG7 PG8 VDD50USB VDD33USB
PH0- PH1-
H OSC_IN OSC_OUT PF10 PF8 PC2 PA4 PF14 PE8 PG2 PG3 PG5 VSS VDD
J PC0 PC1 VSSA PC3 PA0 PA7 PF15 PE9 PE14 PD11 PD13 PD15 PD14
K PC3_C PC2_C PA0_C PA1 PA6 PC4 PG0 PE13 PH10 PH12 PD9 PD10 PD12
L VDDA VREF+ PA1_C PA5 PB1 PB2 PG1 PE12 PB10 PH11 PB13 VSS VDD
M VDD VSS PH3 VSS PB0 PF11 VSS PE10 PB11 VDDLDO VSS PD8 PB15
N PA2 PH2 PA3 VDD PC5 PF12 VDD PE11 PE15 VCAP VDD PB12 PB14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A VSS PB8 VDDLDO VCAP PB6 PB3 PG11 PG9 PD3 PD1 PA15 PA14 VDDLDO VCAP VSS
B PE4 PE3 PB9 PE0 PB7 PB4 PG13 PD7 PD5 PD2 PC12 PH14 PA13 PA8 PA12
C PC13 VSS PE2 PE1 BOOT0 PB5 PG14 PG10 PD4 PD0 PC11 PC10 PH13 PA10 PA11
PC15- VDD
D PC14- PE5 PDR_ON VSS PG15 PG12 PD6 VSS VDD PH15 PA9 PC8 PC7
OSC32_ MMC
OSC32_IN
OUT
VDD50
E VSS VBAT PE6 VDD VDD PC9 PC6
USB
VDD VFB
G PF2 VDD VSS VSS VSS VSS VSS PG8 PG7 PG4 PG2
SMPS SMPS
H PF6 PF4 PF5 PF3 VSS VSS VSS VSS VSS VDD PG3 PD14 PD13
PH0-
J OSC_IN
PF8 PF7 PF9 VSS VSS VSS VSS VSS PD15 PD11 VSS PD12
PH1-
K OSC_ VSS PF10 VDD VSS VSS VSS VSS VSS VSS PD9 PB15 PB14
OUT
M PC2 PC3 VREF+ VDDA VDD VSS PC5 PB1 VDD VSS PH7 PE14 PH11 PH9 PB12
N PC2_C PC3_C VSSA PH2 PA3 PA7 PF11 PE8 PG1 PF15 PF13 PB10 PH8 PH10 PH12
P PA0 PA1 PA1_C PH4 PA4 PA5 PB2 PG0 PE7 PB11 PF12 PE12 PE13 PE15 PH6
R VSS PA2 PA0_C PH3 PH5 PC4 PA6 PB0 PE10 PF14 PE9 PE11 VCAP VDDLDO VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
C VBAT PI7 PI6 PI5 VDD PDR_ON VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11
MMC
D PC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10
PC14-
E OSC32_ PF0 PI10 PI11 PH13 PH14 PI0 PA9
IN
PC15-
F OSC32_ VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP PC9 PA8
OUT
PH0-
G OSC_IN
VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
PH1-
H OSC_ PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD33 PG8 PC6
OUT USB
J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6
K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
M VSSA PC0 PC1 PC2_C PC3_C PB2 PG1 VSS VSS VCAP PH6 PH8 PH9 PD14 PD13
N VREF− PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10
P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15
Unless otherwise specified in brackets below the pin name, the pin
Pin name
function during and after reset is the same as the actual pin name
S Supply pin
I Input only pin
Pin type
I/O Input / output pin
ANA Analog-only Input
FT 5 V tolerant I/O
TT 3.3 V tolerant I/O
B Dedicated BOOT0 pin
I/O structure Bidirectional reset pin with
RST
embedded weak pull-up resistor
Option for TT and FT I/Os
_f I2C FM+ option
Unless otherwise specified by a note, all I/Os are set as floating inputs
Notes
during and after reset.
Alternate functions Functions selected through GPIOx_AFR registers
Pin functions
Additional functions Functions directly selected/enabled through peripheral registers
1. Refer to SYSCFG_CCCSR register in the device reference manual for how to set a group of I/Os in
High-speed low-voltage mode. Depending on the chosen I/Os (for example OCTOSPI), it can belong to
several groups of I/Os and several HSLVx bits need to be set (refer to Table Pin/ball definition). Take care
that the VDDIO_HSLV and/or VDDMMC_HSLV option bits must also be set.
2. Refer to the table Features and peripheral counts for the list of packages featuring a VDDMMC separate
supply pad.
UFBGA176+25
Pin name
TFBGA100
TFBGA216
LQFP144
LQFP176
LQFP64
TRACECLK,
SAI1_CK1, SPI4_SCK,
SAI1_MCLK_A,
1 A3 1 - A2 C3 1 E5 - A3 1 1 A2 1 A3 PE2 I/O FT_h2 -
OCTOSPIM_P1_IO2,
USART10_RX,
FMC_A23, EVENTOUT
TRACED0,
TIM15_BKIN,
- B3 2 E9 B2 B2 2 B1 - B3 2 2 A1 2 A2 PE3 I/O FT_h2 SAI1_SD_B, -
USART10_TX,
FMC_A19, EVENTOUT
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N,
2 C3 3 F9 A1 B1 3 C2 - C3 3 3 B1 3 A1 PE4 I/O FT_h2 SPI4_NSS, -
SAI1_FS_A, FMC_A20,
DCMI_D4/PSSI_D4,
LCD_B0, EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
TRACED2, SAI1_CK2,
DFSDM1_CKIN3,
TIM15_CH1,
SPI4_MISO,
3 A2 4 D10 C3 D3 4 D3 - D3 4 4 B2 4 B1 PE5 I/O FT_h2 -
SAI1_SCK_A,
FMC_A21, DCMI_D6/
PSSI_D6, LCD_G0,
EVENTOUT
TRACED3,
TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI,
SAI1_SD_A,
- A1 5 C10 C2 E3 5 E4 - E3 5 5 B3 5 B2 PE6 I/O FT_h2 -
SAI2_MCK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7/
PSSI_D7, LCD_G1,
EVENTOUT
- - 6 - B3 A1 6 F6 - - - - D5 - G6 VSS S - - -
4 E5 7 B11 A3 - 7 F7 - - - - C5 - F5 VDD S - - -
5 C2 8 D11 E3 E2 8 E2 1 B2 6 6 C1 6 C1 VBAT S - - -
TAMP_IN2/
TAMP_OUT3,
- - - - - - - C1 - - - - D2 7 C2 PI8 I/O FT EVENTOUT
RTC_OUT2,
WKUP4
TAMP_IN1/
TAMP_OUT2/
TAMP_OUT3,
6 E4 9 E10 D3 C1 9 F4 2 A2 7 7 D1 8 D1 PC13 I/O FT EVENTOUT
RTC_OUT1/
RTC_TS,
WKUP3
- - - C12 - C2 - A1 - - - - F7 - - VSS S - - -
PC14-
7 B1 10 B12 C1 D2 10 D1 3 A1 8 8 E1 9 E1 OSC32_IN I/O FT EVENTOUT OSC32_IN
(OSC32_IN)
PC15-
8 B2 11 C11 B1 D1 11 D2 4 B1 9 9 F1 10 F1 OSC32_OUT I/O FT EVENTOUT OSC32_OUT
(OSC32_OUT)
OCTOSPIM_P2_IO0,
UART4_RX,
FDCAN1_RX,
- - - - - - - E3 - - - - D3 11 E4 PI9 I/O FT_h2 -
FMC_D30,
LCD_VSYNC,
EVENTOUT
OCTOSPIM_P2_IO1,
FMC_D31, PSSI_D14,
- - - - - - - F3 - - - - E3 12 D5 PI10 I/O FT_h2 -
LCD_HSYNC,
EVENTOUT
OCTOSPIM_P2_IO2,
LCD_G6,
- - - - - - - G5 - - - - E4 13 F3 PI11 I/O FT WKUP5
OTG_HS_ULPI_DIR,
PSSI_D15, EVENTOUT
- - 12 - - D10 12 E1 - - - - F2 14 F2 VSS S - - -
9 D1 14 D12 E2 F2 14 G2 - - - - - - - VSSSMPS S - - -
10 D2 15 E12 E1 F1 15 F1 - - - - - - - VLXSMPS S - - -
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
11 E1 16 F12 F1 G1 16 G1 - - - - - - - VDDSMPS S - - -
12 E2 17 E11 F2 G2 17 F2 - - - - - - - VFBSMPS S - - -
I2C2_SDA,
- - - - F3 F4 18 G4 - - - 10 E2 16 D2 PF0 I/O FT_f OCTOSPIM_P2_IO0, -
FMC_A0, EVENTOUT
I2C2_SCL,
- - - - E4 F3 19 G3 - - - 11 H3 17 E2 PF1 I/O FT_f OCTOSPIM_P2_IO1, -
FMC_A1, EVENTOUT
I2C2_SMBA,
- - - - F4 G3 20 H1 - - - 12 H2 18 G2 PF2 I/O FT_h2 OCTOSPIM_P2_IO2, -
FMC_A2, EVENTOUT
OCTOSPIM_P2_IO3,
- - - - - - - H2 - - - - - - E3 PI12 I/O FT_h1 LCD_HSYNC, -
EVENTOUT
OCTOSPIM_P2_CLK,
- - - - - - - H5 - - - - - - G3 PI13 I/O FT_h1 LCD_VSYNC, -
EVENTOUT
OCTOSPIM_P2_NCLK,
- - - - - - - H4 - - - - - - H3 PI14 I/O FT_h1 -
LCD_CLK, EVENTOUT
OCTOSPIM_P2_IO3,
- - - - E5 H4 21 J1 - - - 13 J2 19 H2 PF3 I/O FT_h2 -
FMC_A3, EVENTOUT
OCTOSPIM_P2_CLK,
- - - - G3 H2 22 H3 - - - 14 J3 20 J2 PF4 I/O FT_h2 -
FMC_A4, EVENTOUT
OCTOSPIM_P2_NCLK,
- - - - F5 H3 23 J2 - - - 15 K3 21 K3 PF5 I/O FT_h2 -
FMC_A5, EVENTOUT
- F5 18 F11 B7 E1 24 H6 - C2 10 16 G2 22 H6 VSS S - - -
- F6 19 - A7 E4 25 J6 - D2 11 17 G3 23 H5 VDD S - - -
TIM16_CH1,
SPI5_NSS,
SAI1_SD_B,
- - 20 - G4 H1 26 J3 - - - 18 K2 24 K2 PF6 I/O FT_h1 -
UART7_Rx,
OCTOSPIM_P1_IO3,
EVENTOUT
TIM17_CH1,
SPI5_SCK,
SAI1_MCLK_B,
- - 21 - F6 J3 27 J4 - - - 19 K1 25 K1 PF7 I/O FT_h1 -
UART7_Tx,
OCTOSPIM_P1_IO2,
EVENTOUT
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
- - 22 - H4 J2 28 K1 - - - 20 L3 26 L3 PF8 I/O FT_h1 UART7_RTS, -
TIM13_CH1,
OCTOSPIM_P1_IO0,
EVENTOUT
TIM17_CH1N,
SPI5_MOSI,
SAI1_FS_B,
- - 23 - G5 J4 29 K2 - - - 21 L2 27 L2 PF9 I/O FT_h1 UART7_CTS, -
TIM14_CH1,
OCTOSPIM_P1_IO1,
EVENTOUT
TIM16_BKIN,
SAI1_D3, PSSI_D15,
- - 24 - H3 K3 30 M3 - - - 22 L1 28 L1 PF10 I/O FT_h1 OCTOSPIM_P1_CLK, -
DCMI_D11/PSSI_D11,
LCD_DE, EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
PH0-
13 G1 25 G11 H1 J1 31 L1 5 C1 12 23 G1 29 G1 I/O FT EVENTOUT OSC_IN
OSC_IN(PH0)
PH1-
14 G2 26 H12 H2 K1 32 L2 6 D1 13 24 H1 30 H1 OSC_OUT I/O FT EVENTOUT OSC_OUT
(PH1)
DFSDM1_CKIN0,
DFSDM1_DATIN4,
SAI2_FS_B, FMC_A25,
16 F3 28 G10 J1 L2 34 L3 8 F1 15 26 M2 32 M2 PC0 I/O FT_a OTG_HS_ULPI_STP, ADC12_INP10
LCD_G2,
FMC_SDNWE,
LCD_R5, EVENTOUT
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
ADC12_INP11,
SPI2_MOSI/I2S2_SDO,
ADC12_INN10,
17 F1 29 H11 J2 L3 35 M2 9 F2 16 27 M3 33 M3 PC1 I/O FT_ah0 SAI1_SD_A,
TAMP_IN3,
SDMMC2_CK,
WKUP6
OCTOSPIM_P1_IO4,
MDIOS_MDC,
LCD_G5, EVENTOUT
PWR_CSTOP,
DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
H5 M1 J5 ADC12_INP12,
- - - J12 (3) (3) - (3) 10 - - - - - - PC2 I/O FT_a OCTOSPIM_P1_IO2,
ADC12_INN11
OTG_HS_ULPI_DIR,
OCTOSPIM_P1_IO5,
FMC_SDNE0,
EVENTOUT
30 K2 N1 N1 ADC2_INP0,
18(4) F4(4) (4) - (3) (3) 36(4) (3) - E2(4) 17(4) 28(4) M4(4) 34(4) M4(4) PC2_C ANA TT_a -
ADC2_INN1
PWR_CSLEEP,
DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
OCTOSPIM_P1_IO0, ADC12_INP13,
- - - G9 J4(3) M2(3) - N3(3) 11 - - - - - - PC3 I/O FT_a
OTG_HS_ULPI_NXT, ADC12_INN12
OCTOSPIM_P1_IO6,
FMC_SDCKE0,
EVENTOUT
19(4) G4(4) 31(4) - K1(3) N2(3) 37(4) N2(3) - F3(4) 18(4) 29(4) M5(4) 35(4) L4(4) PC3_C ANA TT_a - ADC2_INP1
21 - 33 H9 G2 F6 - R1 - - - - - - J6 VSS S - -
22 H2 34 K12 J3 N3 38 K5 12 G1 19 31 M1 37 M1 VSSA S - -
- - - - - L4 - K4 - - - - N1 - N1 VREF- S - -
23 J1 35 J11 L2 M3 39 L4 - - 20 32 P1 38 P1 VREF+ S - -
24 H1 36 J10 L1 M4 40 L5 13 H1 21 33 R1 39 R1 VDDA S - -
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
SPI6_NSS/I2S6_WS,
USART2_CTS/ ADC1_INP16,
25 G3 37 K11 J5(3) P1(3) 41 P1(3) 14 G2 22 34 N3 40 N3 PA0 I/O FT_a
USART2_NSS, WKUP1
UART4_TX,
SDMMC2_CMD,
SAI2_SD_B,
EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
ADC1_INP0,
- - - - K3(3) R3(3) - P3(3) - - - - - - - PA0_C ANA TT_a -
ADC1_INN1
TIM2_CH2, TIM5_CH2,
LPTIM3_OUT,
TIM15_CH1N,
USART2_RTS,
ADC1_INP17,
26 J2 38 G8 K4(3) P2(3) 42 P2(3) 15 H2 23 35 N2 41 N2 PA1 I/O FT_ah1 UART4_RX,
ADC1_INN16
OCTOSPIM_P1_IO3,
SAI2_MCK_B,
OCTOSPIM_P1_DQS,
LCD_R2, EVENTOUT
TIM2_CH3, TIM5_CH3,
TIM15_CH1,
DFSDM2_CKIN1,
ADC1_INP14,
27 H3 39 H8 N1 R2 43 R2 16 J2 24 36 P2 42 P2 PA2 I/O FT_a USART2_TX,
WKUP2
SAI2_SCK_B,
MDIOS_MDIO,
LCD_R1, EVENTOUT
LPTIM1_IN2,
OCTOSPIM_P1_IO4,
- - - - N2 N4 - M4 - - - - F4 43 K4 PH2 I/O FT_h2 SAI2_SCK_B, -
FMC_SDCKE0,
LCD_R0, EVENTOUT
- - - - M1 G4 44 J7 - - - - - - - VDD S - - -
- - - L12 M2 F7 45 M1 - J1 - - F6 - K6 VSS S - - -
OCTOSPIM_P1_IO5,
SAI2_MCK_B,
- - - - M3 R4 - N4 - - - - G4 44 J4 PH3 I/O FT_ah2 -
FMC_SDNE0,
LCD_R1, EVENTOUT
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
- - - - - P4 - M5 - - - - H4 45 H4 PH4 I/O FT_fa -
PSSI_D14, LCD_G4,
EVENTOUT
I2C2_SDA, SPI5_NSS,
- - - - - R5 - P4 - - - - J4 46 J3 PH5 I/O FT_fa FMC_SDNWE, -
EVENTOUT
TIM2_CH4, TIM5_CH4,
OCTOSPIM_P1_CLK,
TIM15_CH2,
28 G5 40 J9 N3 N5 46 R4 17 K2 25 37 R2 47 R2 PA3 I/O FT_ah1 I2S6_MCK, ADC1_INP15
USART2_RX, LCD_B2,
OTG_HS_ULPI_D0,
LCD_B5, EVENTOUT
29 - 41 - M4 F8 47 K6 18 E6 26 38 L4 48 L5 VSS S - - -
30 - 42 - N4 H12 48 G7 19 K1 27 39 - 49 K5 VDD S - - -
TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK,
ADC1_INP18,
31 K1 43 K10 H6 P5 49 L6 20 G3 28 40 N4 50 N4 PA4 I/O TT_a SPI6_NSS/I2S6_WS,
DAC1_OUT1
DCMI_HSYNC/
PSSI_DE,
LCD_VSYNC,
EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
PWR_NDSTOP2,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
ADC1_INP19,
SPI1_SCK/I2S1_CK,
32 K2 44 L11 L4 P6 50 N5 21 H3 29 41 P4 51 P4 PA5 I/O TT_ah0 ADC1_INN18,
SPI6_SCK/I2S6_CK,
DAC1_OUT2
OTG_HS_ULPI_CK,
PSSI_D14, LCD_R4,
EVENTOUT
TIM1_BKIN,
TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
OCTOSPIM_P1_IO3,
SPI6_MISO/I2S6_SDI,
ADC12_INP3,
33 J3 45 G7 K5 R7 51 P5 22 J3 30 42 P3 52 P3 PA6 I/O TT_ah1 TIM13_CH1,
DAC2_OUT1
TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK/
PSSI_PDCK, LCD_G2,
EVENTOUT
TIM1_CH1N,
TIM3_CH2,
TIM8_CH1N,
DFSDM2_DATIN1,
SPI1_MOSI/I2S1_SDO, ADC12_INP7,
34 K3 46 K9 J6 N6 52 R5 23 K3 31 43 R3 53 R3 PA7 I/O FT_ah1 SPI6_MOSI/I2S6_SDO, ADC12_INN3,
TIM14_CH1, OPAMP1_VINM
OCTOSPIM_P1_IO2,
FMC_SDNWE,
LCD_VSYNC,
EVENTOUT
DFSDM1_CKIN2,
I2S1_MCK, ADC12_INP4,
35 H4 47 H7 K6 R6 53 M6 24 G4 32 44 N5 54 N5 PC4 I/O FT_a SPDIFRX1_IN2, OPAMP1_VOUT,
FMC_SDNE0, COMP1_INM
LCD_R7, EVENTOUT
SAI1_D3,
DFSDM1_DATIN2,
PSSI_D15,
ADC12_INP8,
SPDIFRX1_IN3,
36 J4 48 J8 N5 M7 54 N6 25 H4 33 45 P5 55 P5 PC5 I/O FT_ah1 ADC12_INN4,
OCTOSPIM_P1_DQS,
OPAMP1_VINM
FMC_SDCKE0,
COMP1_OUT,
LCD_DE, EVENTOUT
- - - L10 N7 K4 - - - - - - - - L7 VDD S - - -
- - - L9 M7 F9 - - - - - - M9 - L6 VSS S - - -
TIM1_CH2N,
TIM3_CH3,
TIM8_CH2N,
ADC12_INP9,
DFSDM2_CKOUT,
ADC12_INN5,
37 K4 49 K8 M5 R8 55 P6 26 J4 34 46 R5 56 R5 PB0 I/O FT_ah0 DFSDM1_CKOUT,
OPAMP1_VINP,
UART4_CTS, LCD_R3,
COMP1_INP
OTG_HS_ULPI_D1,
OCTOSPIM_P1_IO1,
LCD_G1, EVENTOUT
TIM1_CH3N,
TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN1, ADC12_INP5,
38 K5 50 J7 L5 M8 56 L7 27 K4 35 47 R4 57 R4 PB1 I/O FT_ah0
LCD_R6, COMP1_INM
OTG_HS_ULPI_D2,
OCTOSPIM_P1_IO0,
LCD_G0, EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
RTC_OUT2, SAI1_D1,
DFSDM1_CKIN1,
SAI1_SD_A,
39 J5 51 L8 L6 P7 57 R6 28 G5 36 48 M6 58 M5 PB2 I/O FT_ah1 SPI3_MOSI/I2S3_SDO, COMP1_INP
OCTOSPIM_P1_CLK,
OCTOSPIM_P1_DQS,
EVENTOUT
LCD_G2, LCD_R0,
- - - - - - - M7 - - - - - - G4 PI15 I/O FT -
EVENTOUT
LCD_R7, LCD_R1,
- - - - - - - N7 - - - - - - R6 PJ0 I/O FT -
EVENTOUT
OCTOSPIM_P2_IO4,
- - - - - - - P7 - - - - - - R7 PJ1 I/O FT_ah1 -
LCD_R2, EVENTOUT
OCTOSPIM_P2_IO5,
- - - - - - - R7 - - - - - - P7 PJ2 I/O FT_ah1 -
LCD_R3, EVENTOUT
UART9_RTS, LCD_R4,
- - - - - - - R8 - - - - - - N8 PJ3 I/O FT -
EVENTOUT
UART9_CTS, LCD_R5,
- - - - - - - P8 - - - - - - M9 PJ4 I/O FT -
EVENTOUT
SPI5_MOSI,
OCTOSPIM_P1_NCLK,
SAI2_SD_B,
- - 52 - M6 N7 58 N8 - - - 49 R6 59 P8 PF11 I/O FT_ah1 ADC1_INP2
FMC_SDNRAS,
DCMI_D12/PSSI_D12,
EVENTOUT
OCTOSPIM_P2_DQS, ADC1_INP6,
- - - - N6 P11 59 R9 - - - 50 P6 60 M6 PF12 I/O FT_ah2
FMC_A6, EVENTOUT ADC1_INN2
- - - - - F10 - K8 - - - 51 M8 61 K7 VSS S - - -
- - - - - L12 - K9 - - - 52 N8 62 L8 VDD S - - -
DFSDM1_DATIN6,
- - - - G7 N11 60 M8 - - - 53 N6 63 N6 PF13 I/O FT_ah2 I2C4_SMBA, FMC_A7, ADC2_INP2
EVENTOUT
DFSDM1_CKIN6,
ADC2_INP6,
- - 53 K7 H7 R10 61 P9 - - - 54 R7 64 P6 PF14 I/O FT_fah2 I2C4_SCL, FMC_A8,
ADC2_INN2
EVENTOUT
I2C4_SDA, FMC_A9,
- - 54 - J7 N10 62 N9 - - - 55 P7 65 M8 PF15 I/O FT_fh2 -
EVENTOUT
OCTOSPIM_P2_IO4,
- - - - K7 P8 63 R10 - - - 56 N7 66 N7 PG0 I/O FT_h2 UART9_RX, FMC_A10, -
EVENTOUT
- - 55 - - F12 64 - - - - - K8 - - VSS S - - -
- - 56 - - M5 65 - - - - - N10 - - VDD S - - -
OCTOSPIM_P2_IO5,
- - - - L7 N9 66 P10 - - - 57 M7 67 M7 PG1 I/O FT_h2 UART9_TX, FMC_A11, OPAMP2_VINM
EVENTOUT
TIM1_ETR,
DFSDM1_DATIN2,
UART7_Rx, OPAMP2_VOUT,
40 H5 57 L7 G8 P9 67 M9 - H5 37 58 R8 68 R8 PE7 I/O FT_ah2
OCTOSPIM_P1_IO4, COMP2_INM
FMC_D4/FMC_DA4,
EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_Tx,
41 J6 58 H6 H8 N8 68 R11 - J5 38 59 P8 69 N9 PE8 I/O FT_ah2 OCTOSPIM_P1_IO5, OPAMP2_VINM
FMC_D5/FMC_DA5,
COMP2_OUT,
EVENTOUT
TIM1_CH1,
DFSDM1_CKOUT,
UART7_RTS, OPAMP2_VINP,
- K6 59 J6 J8 R11 69 P11 - K5 39 60 P9 70 P9 PE9 I/O FT_ah2
OCTOSPIM_P1_IO6, COMP2_INP
FMC_D6/FMC_DA6,
EVENTOUT
TIM1_CH2N,
DFSDM1_DATIN4,
UART7_CTS,
- H6 60 G6 M8 R9 72 N11 - G6 40 63 R9 73 R9 PE10 I/O FT_ah2 COMP2_INM
OCTOSPIM_P1_IO7,
FMC_D7/FMC_DA7,
EVENTOUT
TIM1_CH2,
DFSDM1_CKIN4,
SPI4_NSS,
- - 61 J5 N8 R12 73 R12 - H6 41 64 P10 74 P10 PE11 I/O FT_ah2 SAI2_SD_B, COMP2_INP
OCTOSPIM_P1_NCS,
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK,
- - 62 K5 L8 P12 74 L9 - J6 42 65 R10 75 R10 PE12 I/O FT_h2 SAI2_SCK_B, -
FMC_D9/FMC_DA9,
COMP1_OUT,
LCD_B4, EVENTOUT
TIM1_CH3,
DFSDM1_CKIN5,
SPI4_MISO,
- - 63 L5 K8 P13 75 M10 - K6 43 66 N11 76 R12 PE13 I/O FT_h2 SAI2_FS_B, -
FMC_D10/FMC_DA10,
COMP2_OUT,
LCD_DE, EVENTOUT
TIM1_CH4,
SPI4_MOSI,
- - 64 H5 J9 M12 76 N10 - G7 44 67 P11 77 P11 PE14 I/O FT_h2 SAI2_MCK_B, -
FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
TIM1_BKIN,
USART10_CK,
- - 65 G5 N9 P14 77 P12 - H7 45 68 R11 78 R11 PE15 I/O FT_h2 FMC_D12/FMC_DA12, -
TIM1_BKIN_COMP12,
LCD_R7, EVENTOUT
TIM2_CH3,
LPTIM2_IN1,
I2C2_SCL,
SPI2_SCK/I2S2_CK,
42 K7 66 F5 L9 N12 78 R13 29 J7 46 69 R12 79 P12 PB10 I/O FT_f DFSDM1_DATIN7, -
USART3_TX,
OCTOSPIM_P1_NCS,
OTG_HS_ULPI_D3,
LCD_G4, EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
TIM2_CH4,
LPTIM2_ETR,
I2C2_SDA,
43 J7 67 J4 M9 P10 79 P13 - K7 47 70 R13 80 R13 PB11 I/O FT_f DFSDM1_CKIN7, -
USART3_RX,
OTG_HS_ULPI_D4,
LCD_G5, EVENTOUT
45 D5 69 K4 - M10 81 - 31 - 49 - - - K9 VSS S - - -
TIM12_CH1,
I2C2_SMBA,
SPI5_SCK,
- - - - - P15 - M11 - - - - M11 83 P13 PH6 I/O FT -
FMC_SDNE1,
DCMI_D8/PSSI_D8,
EVENTOUT
I2C3_SCL,
SPI5_MISO,
- - - - - M11 - R14 - - - - N12 84 N13 PH7 I/O FT_f FMC_SDCKE1, -
DCMI_D9/PSSI_D9,
EVENTOUT
TIM5_ETR,
I2C3_SDA, FMC_D16,
- - - - - N13 - P14 - - - - M12 85 P14 PH8 I/O FT_fh2 DCMI_HSYNC/ -
PSSI_DE, LCD_R2,
EVENTOUT
TIM12_CH2,
I2C3_SMBA,
- - - - - M14 - N13 - - - - M13 86 N14 PH9 I/O FT_h2 FMC_D17, DCMI_D0/ -
PSSI_D0, LCD_R3,
EVENTOUT
TIM5_CH1,
I2C4_SMBA,
- - - - K9 N14 - M12 - - - - L13 87 P15 PH10 I/O FT_h2 FMC_D18, DCMI_D1/ -
PSSI_D1, LCD_R4,
EVENTOUT
TIM5_CH2, I2C4_SCL,
FMC_D19, DCMI_D2/
- - - - L10 M13 - P15 - - - - L12 88 N15 PH11 I/O FT_fh2 -
PSSI_D2, LCD_R5,
EVENTOUT
TIM5_CH3, I2C4_SDA,
FMC_D20, DCMI_D3/
- - - - K10 N15 - L11 - - - - K12 89 M15 PH12 I/O FT_fh2 -
PSSI_D3, LCD_R6,
EVENTOUT
TIM1_BKIN,
OCTOSPIM_P1_NCLK,
I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK,
48 K8 72 L2 N12 M15 85 N14 33 K8 51 73 P12 92 L13 PB12 I/O FT_h1 -
FDCAN2_RX,
OTG_HS_ULPI_D5,
DFSDM2_DATIN1,
TIM1_BKIN_COMP12,
UART5_RX,
EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
TIM1_CH1N,
LPTIM2_OUT,
DFSDM2_CKIN1,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
USART3_CTS/
49 J8 73 K2 L11 L15 86 M13 34 J8 52 74 P13 93 K14 PB13 I/O FT_h0 USART3_NSS, -
FDCAN2_TX,
OTG_HS_ULPI_D6,
SDMMC1_D0,
DCMI_D2/PSSI_D2,
UART5_TX,
EVENTOUT
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
50 K9 74 J3 N13 K15 87 M14 35 H10 53 75 R14 94 R14 PB14 I/O FT_h0 -
DFSDM1_DATIN2,
USART3_RTS,
UART4_RTS,
SDMMC2_D0,
LCD_CLK, EVENTOUT
RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
51 K10 75 H4 M13 K14 88 M15 36 G10 54 76 R15 95 R15 PB15 I/O FT_h0 -
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2,
UART4_CTS,
SDMMC2_D1,
LCD_G7, EVENTOUT
DFSDM1_CKIN3,
USART3_TX,
52 J9 76 H3 M12 L14 89 L12 - K9 55 77 P15 96 L15 PD8 I/O FT_h2 SPDIFRX1_IN1, -
FMC_D13/FMC_DA13,
EVENTOUT
DFSDM1_DATIN3,
USART3_RX,
53 H8 77 J2 K11 K13 90 N15 - J9 56 78 P14 97 L14 PD9 I/O FT_h2 -
FMC_D14/FMC_DA14,
EVENTOUT
DFSDM1_CKOUT,
DFSDM2_CKOUT,
54 J10 78 K1 K12 L13 91 L13 - H9 57 79 N15 98 K15 PD10 I/O FT_h2 USART3_CK, -
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
- - 79 - - - 92 - - F4 - - - - - VDD S - - -
- - 80 - - H6 93 - - - - - J10 - - VSS S - - -
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/
55 H7 81 G4 J10 J13 94 L14 - G9 58 80 N14 99 N10 PD11 I/O FT_h2 USART3_NSS, -
OCTOSPIM_P1_IO0,
SAI2_SD_A, FMC_A16/
FMC_CLE, EVENTOUT
LPTIM1_IN1,
TIM4_CH1,
LPTIM2_IN1,
I2C4_SCL,
56 H9 82 G3 K13 J15 95 L15 - K10 59 81 N13 100 M10 PD12 I/O FT_fh2 USART3_RTS, -
OCTOSPIM_P1_IO1,
SAI2_FS_A, FMC_A17/
FMC_ALE, DCMI_D12/
PSSI_D12, EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
OCTOSPIM_P1_IO3,
57 H10 83 H2 J11 H15 96 K11 - J10 60 82 M15 101 M11 PD13 I/O FT_fh2 SAI2_SCK_A, -
UART9_RTS,
FMC_A18, DCMI_D13/
PSSI_D13, EVENTOUT
TIM4_CH3,
UART8_CTS,
60 G7 84 J1 J13 H14 97 K12 - H8 61 85 M14 104 L12 PD14 I/O FT_h2 -
UART9_RX, FMC_D0/
FMC_DA0, EVENTOUT
TIM4_CH4,
UART8_RTS,
61 G8 85 H1 J12 J12 98 K13 - G8 62 86 L14 105 K13 PD15 I/O FT_h2 -
UART9_TX, FMC_D1/
FMC_DA1, EVENTOUT
TIM8_CH2, LCD_R7,
- - - - - - - K14 - - - - - - K12 PJ6 I/O FT -
EVENTOUT
TRGIN, TIM8_CH2N,
- - - - - - - K15 - - - - - - J12 PJ7 I/O FT -
LCD_G0, EVENTOUT
- - - G1 - - 99 - - - - - - - - VDD S - - -
TIM1_CH3N,
TIM8_CH1,
- - - - - - 101 J15 - - - - - - H12 PJ8 I/O FT -
UART8_TX, LCD_G1,
EVENTOUT
TIM1_CH3,
TIM8_CH1N,
- - - - - - 102 J14 - - - - - - J13 PJ9 I/O FT -
UART8_RX, LCD_G2,
EVENTOUT
TIM1_CH2N,
TIM8_CH2,
- - - - - - 103 J13 - - - - - - H13 PJ10 I/O FT -
SPI5_MOSI, LCD_G3,
EVENTOUT
TIM1_CH2,
TIM8_CH2N,
- - - - - - 104 J11 - - - - - - G12 PJ11 I/O FT -
SPI5_MISO, LCD_G4,
EVENTOUT
TIM1_CH1N,
- - - - - - 107 J12 - - - - - - G13 PK0 I/O FT TIM8_CH3, SPI5_SCK, -
LCD_G5, EVENTOUT
TIM1_CH1,
TIM8_CH3N,
- - - - - - 108 H15 - - - - - - F12 PK1 I/O FT -
SPI5_NSS, LCD_G6,
EVENTOUT
TIM1_BKIN,
TIM8_BKIN,
- - - - - - 109 H14 - - - - - - F13 PK2 I/O FT TIM8_BKIN_COMP12, -
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT
TIM8_BKIN,
- - - - H9 G15 110 H13 - - - 87 L15 106 M13 PG2 I/O FT_h2 TIM8_BKIN_COMP12, -
FMC_A12, EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
TIM8_BKIN2,
- - - - H10 H13 111 G15 - - - 88 K15 107 M12 PG3 I/O FT_h2 TIM8_BKIN2_COMP12, -
FMC_A13, EVENTOUT
TIM1_BKIN2,
TIM1_BKIN2_COMP12,
- - - - F8 G14 114 H12 - - - 89 K14 108 N12 PG4 I/O FT_h2 -
FMC_A14/FMC_BA0,
EVENTOUT
TIM1_ETR, FMC_A15/
- - - - H11 F15 115 G14 - - - 90 K13 109 N11 PG5 I/O FT_h2 -
FMC_BA1, EVENTOUT
TIM17_BKIN,
OCTOSPIM_P1_NCS,
- - 86 - G9 F14 116 G13 - - - 91 J15 110 J15 PG6 I/O FT_h2 FMC_NE3, DCMI_D12/ -
PSSI_D12, LCD_R7,
EVENTOUT
SAI1_MCLK_A,
USART6_CK,
OCTOSPIM_P2_DQS,
- - 87 - G10 G13 117 G12 - - - 92 J14 111 J14 PG7 I/O FT_h2 -
FMC_INT, DCMI_D13/
PSSI_D13, LCD_CLK,
EVENTOUT
TIM8_ETR,
SPI6_NSS/I2S6_WS,
USART6_RTS,
- - 88 - G11 G12 118 F15 - - - 93 H14 112 H14 PG8 I/O FT_h2 -
SPDIFRX1_IN2,
FMC_SDCLK,
LCD_G7, EVENTOUT
- - 92 - - - - G10 - - - - - - - VDD S - - -
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
I2S2_MCK,
USART6_TX,
SDMMC1_D0DIR,
62 F8 93 F3 F9 E14 122 F14 37 F10 63 96 H15 115 H15 PC6 I/O FT_h0 FMC_NWAIT, SWPMI_IO
SDMMC2_D6,
SDMMC1_D6,
DCMI_D0/PSSI_D0,
LCD_HSYNC,
EVENTOUT
TRGIO, TIM3_CH2,
TIM8_CH2,
DFSDM1_DATIN3,
I2S3_MCK,
USART6_RX,
SDMMC1_D123DIR,
63 G9 94 E1 F10 D15 123 E15 38 E10 64 97 G15 116 G15 PC7 I/O FT_h0 -
FMC_NE1,
SDMMC2_D7,
SWPMI_TX,
SDMMC1_D7,
DCMI_D1/PSSI_D1,
LCD_G6, EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
TRACED1, TIM3_CH3,
TIM8_CH3,
USART6_CK,
UART5_RTS,
64 G10 95 - F12 D14 124 F13 - F9 65 98 G14 117 G14 PC8 I/O FT_h0 FMC_NE2/FMC_NCE, -
FMC_INT, SWPMI_RX,
SDMMC1_D0,
DCMI_D2/PSSI_D2,
EVENTOUT
MCO2, TIM3_CH4,
TIM8_CH4,
I2C3_SDA, I2S_CKIN,
UART5_CTS,
OCTOSPIM_P1_IO0,
65 F9 96 E2 F11 E13 125 E14 39 E9 66 99 F14 118 F14 PC9 I/O FT_fh0 -
LCD_G3,
SWPMI_SUSPEND,
SDMMC1_D1,
DCMI_D3/PSSI_D3,
LCD_B2, EVENTOUT
- - - - - - 126 - - - - - - - - VDD S - - -
MCO1, TIM1_CH1,
TIM8_BKIN2,
I2C3_SCL,
USART1_CK,
66 F10 97 E3 E12 B14 127 G11 40 D9 67 100 F15 119 F15 PA8 I/O FT_fh0 OTG_HS_SOF, -
UART7_RX,
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
TIM1_CH2,
LPUART1_TX,
I2C3_SMBA,
67 E9 98 F4 E11 D13 128 F12 41 C9 68 101 E15 120 E15 PA9 I/O FT_u SPI2_SCK/I2S2_CK, OTG_HS_VBUS
USART1_TX,
DCMI_D0/PSSI_D0,
LCD_R5, EVENTOUT
TIM1_CH3,
LPUART1_RX,
USART1_RX,
OTG_HS_ID,
68 E10 99 D2 E10 C14 129 E13 42 D10 69 102 D15 121 D15 PA10 I/O FT_u -
MDIOS_MDIO,
LCD_B4, DCMI_D1/
PSSI_D1, LCD_B1,
EVENTOUT
TIM1_CH4,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
69 D10 100 D1 F13 C15 130 C15 43 C10 70 103 C15 122 C15 PA11 I/O FT_u OTG_HS_DM
USART1_CTS/
USART1_NSS,
FDCAN1_RX, LCD_R4,
EVENTOUT
TIM1_ETR,
LPUART1_RTS,
SPI2_SCK/I2S2_CK,
UART4_TX,
70 D9 101 C1 E13 B15 131 C14 44 B10 71 104 B15 123 B15 PA12 I/O FT_u OTG_HS_DP
USART1_RTS,
SAI2_FS_B,
FDCAN1_TX, LCD_R5,
EVENTOUT
PA13(JTMS/ JTMS/SWDIO,
71 C10 102 D3 D11 B13 132 E12 45 A10 72 105 A15 124 A15 I/O FT -
SWDIO) EVENTOUT
72 D8 103 C2 D13 A14 133 F11 46 E7 73 106 F13 125 E11 VCAP S - - -
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
76 - - - - - - - - - - - - - - VDD33USB S - - -
TIM8_CH1N,
UART4_TX,
- - - - B13 C13 - D13 - - - - E12 128 E12 PH13 I/O FT_h2 FDCAN1_TX, -
FMC_D21, LCD_G2,
EVENTOUT
TIM8_CH2N,
UART4_RX,
FDCAN1_RX,
- - - - A13 B12 - B15 - - - - E13 129 E13 PH14 I/O FT_h2 -
FMC_D22, DCMI_D4/
PSSI_D4, LCD_G3,
EVENTOUT
TIM8_CH3N,
FMC_D23, DCMI_D11/
- - - - - D12 - B14 - - - - D13 130 D13 PH15 I/O FT_h2 -
PSSI_D11, LCD_G4,
EVENTOUT
TIM5_CH4, SPI2_NSS/
I2S2_WS, FMC_D24,
- - - - - - - C13 - - - - E14 131 E14 PI0 I/O FT_h2 -
DCMI_D13/PSSI_D13,
LCD_G5, EVENTOUT
- - - B2 - J9 - A15 - - - - G8 - - VSS S - - -
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
TIM8_BKIN2_COMP12,
- - - - - - - E11 - - - - D14 132 D14 PI1 I/O FT_h2 -
FMC_D25, DCMI_D8/
PSSI_D8, LCD_G6,
EVENTOUT
TIM8_CH4,
SPI2_MISO/I2S2_SDI,
- - - - - - - D12 - - - - C14 133 C14 PI2 I/O FT_h2 FMC_D26, DCMI_D9/ -
PSSI_D9, LCD_G7,
EVENTOUT
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
- - - - - - - A14 - - - - C13 134 C13 PI3 I/O FT_h2 -
FMC_D27, DCMI_D10/
PSSI_D10, EVENTOUT
PA14(JTCK/ JTCK/SWCLK,
77 C9 107 E4 B12 A12 138 B13 49 A9 76 109 A14 137 A14 I/O FT -
SWCLK) EVENTOUT
JTDI, TIM2_CH1/
TIM2_ETR,
HDMI_CEC,
SPI1_NSS/I2S1_WS,
78 C8 108 C3 C11 A11 139 C12 50 A8 77 110 A13 138 A13 PA15(JTDI) I/O FT SPI3_NSS/I2S3_WS, -
SPI6_NSS/I2S6_WS,
UART4_RTS, LCD_R3,
UART7_TX, LCD_B6,
EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
DFSDM1_CKIN5,
DFSDM2_CKIN0,
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX,
79 B10 109 A3 A12 C12 140 A13 51 B9 78 111 B14 139 B14 PC10 I/O FT_h0 -
OCTOSPIM_P1_IO1,
LCD_B1, SWPMI_RX,
SDMMC1_D2,
DCMI_D8/PSSI_D8,
LCD_R2, EVENTOUT
DFSDM1_DATIN5,
DFSDM2_DATIN0,
SPI3_MISO/I2S3_SDI,
USART3_RX,
80 B9 110 D4 B11 C11 141 D11 52 B8 79 112 B13 140 B13 PC11 I/O FT_h0 UART4_RX, -
OCTOSPIM_P1_NCS,
SDMMC1_D3,
DCMI_D4/PSSI_D4,
LCD_B4, EVENTOUT
TRACED3,
TIM15_CH1,
DFSDM2_CKOUT,
SPI6_SCK/I2S6_CK,
SPI3_MOSI/I2S3_SDO,
81 A10 111 B3 A11 B11 142 B12 53 C8 80 113 A12 141 A12 PC12 I/O FT_h0 -
USART3_CK,
UART5_TX,
SDMMC1_CK,
DCMI_D9/PSSI_D9,
LCD_R6, EVENTOUT
- - - - - J14 - - - - - - G7 - - VSS S - - -
DFSDM1_CKIN6,
UART4_RX,
FDCAN1_RX,
82 C7 112 C4 D10 C10 143 C11 - D8 81 114 B12 142 B12 PD0 I/O FT_h2 -
UART9_CTS, FMC_D2/
FMC_DA2, LCD_B1,
EVENTOUT
DFSDM1_DATIN6,
UART4_TX,
83 B8 113 E5 C10 A10 144 A12 - E8 82 115 C12 143 C12 PD1 I/O FT_h2 -
FDCAN1_TX, FMC_D3/
FMC_DA3, EVENTOUT
TRACED2, TIM3_ETR,
TIM15_BKIN,
UART5_RX, LCD_B7,
84 A9 114 D5 E9 B10 145 B11 54 B7 83 116 D12 144 D12 PD2 I/O FT_h0 -
SDMMC1_CMD,
DCMI_D11/PSSI_D11,
LCD_B2, EVENTOUT
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/
85 A8 115 A4 D9 A9 146 D10 - C7 84 117 D11 145 C11 PD3 I/O FT_h2 USART2_NSS, -
FMC_CLK, DCMI_D5/
PSSI_D5, LCD_G7,
EVENTOUT
USART2_RTS,
OCTOSPIM_P1_IO4,
86 B7 116 B4 C9 C9 147 A11 - D7 85 118 D10 146 D11 PD4 I/O FT_h1 -
FMC_NOE,
EVENTOUT
USART2_TX,
OCTOSPIM_P1_IO5,
87 D7 117 C5 A9 B9 148 C10 - B6 86 119 C11 147 C10 PD5 I/O FT_h1 -
FMC_NWE,
EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
88 - - - - - - - - - - - - - - VDD S - - -
SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
- A7 120 F6 B9 D9 149 B10 - C6 87 122 B11 150 B11 PD6 I/O FT_sh3 USART2_RX, -
OCTOSPIM_P1_IO6,
SDMMC2_CK,
FMC_NWAIT,
DCMI_D10/PSSI_D10,
LCD_B2, EVENTOUT
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
USART2_CK,
- C6 121 E6 D8 B8 150 A10 - D6 88 123 A11 151 A11 PD7 I/O FT_sh3 -
SPDIFRX1_IN0,
OCTOSPIM_P1_IO7,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
TRGOUT, LCD_G3,
- - - - - - - E9 - - - - - - B10 PJ12 I/O FT -
LCD_B0, EVENTOUT
LCD_B4, LCD_B1,
- - - - - - - D9 - - - - - - B9 PJ13 I/O FT -
EVENTOUT
- - - A5 - K6 151 - - - - - H7 - - VSS S - - -
- - - B5 A6 D5 152 E8 - - - - C8 - E9 VDDMMC S - - -
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX1_IN3,
OCTOSPIM_P1_IO6,
SAI2_FS_B,
- - 122 D6 C8 A8 153 A9 - - - 124 C10 152 D9 PG9 I/O FT_sh3 -
SDMMC2_D0,
FMC_NE2/FMC_NCE,
DCMI_VSYNC/
PSSI_RDY,
EVENTOUT
OCTOSPIM_P2_IO6,
SPI1_NSS/I2S1_WS,
LCD_G3, SAI2_SD_B,
- - 123 A6 A8 C8 154 A8 - - - 125 B10 153 C8 PG10 I/O FT_sh3 SDMMC2_D1, -
FMC_NE3, DCMI_D2/
PSSI_D2, LCD_B2,
EVENTOUT
LPTIM1_IN2,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN0,
OCTOSPIM_P2_IO7,
- - 124 B6 B8 A7 155 B8 - - - 126 B9 154 B8 PG11 I/O FT_sh3 -
SDMMC2_D2,
USART10_RX,
DCMI_D3/PSSI_D3,
LCD_B3, EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
LPTIM1_IN1,
OCTOSPIM_P2_NCS,
SPI6_MISO/I2S6_SDI,
USART6_RTS,
SPDIFRX1_IN1,
- - 125 C6 E8 D8 156 C8 - - - 127 B8 155 C7 PG12 I/O FT_sh3 -
LCD_B4,
SDMMC2_D3,
USART10_TX,
FMC_NE4, LCD_B1,
EVENTOUT
TRACED0,
LPTIM1_OUT,
SPI6_SCK/I2S6_CK,
USART6_CTS/
USART6_NSS,
- - 126 D7 D7 B7 157 D8 - - - 128 A8 156 B3 PG13 I/O FT_sh3 -
SDMMC2_D6,
USART10_CTS/
USART10_NSS,
FMC_A24, LCD_R0,
EVENTOUT
TRACED1,
LPTIM1_ETR,
SPI6_MOSI/I2S6_SDO,
USART6_TX,
- - 127 C7 C7 C7 158 A7 - - - 129 A7 157 A4 PG14 I/O FT_sh3 OCTOSPIM_P1_IO7, -
SDMMC2_D7,
USART10_RTS,
FMC_A25, LCD_B0,
EVENTOUT
OCTOSPIM_P2_IO6,
- - - - - - - B7 - - - - - - D8 PK3 I/O FT_h1 -
LCD_B4, EVENTOUT
OCTOSPIM_P2_IO7,
- - - - - - - C7 - - - - - - D7 PK4 I/O FT_h1 -
LCD_B5, EVENTOUT
OCTOSPIM_P2_NCS,
- - - - - - - A6 - - - - - - C6 PK5 I/O FT_h1 -
LCD_B6, EVENTOUT
OCTOSPIM_P2_DQS,
- - - - - - - B6 - - - - - - C5 PK6 I/O FT_h1 -
LCD_B7, EVENTOUT
- - 128 B7 - K8 - G8 - - - - - - - VSS S - - -
- - 129 - - - - - - - - - - - G5 VDD S - - -
- - - B8 - - - - - - - - - - - VDDMMC - - -
USART6_CTS/
USART6_NSS,
OCTOSPIM_P2_DQS,
- - - - E7 D7 161 A5 - - - 132 B7 160 B7 PG15 I/O FT_h1 USART10_CK, -
FMC_SDNCAS,
DCMI_D13/PSSI_D13,
EVENTOUT
JTDO/TRACESWO,
TIM2_CH2,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
PB3(JTDO/
89 B6 130 A8 F7 A6 162 C6 55 A7 89 133 A10 161 A10 I/O FT_h0 SPI6_SCK/I2S6_CK, -
TRACESWO)
SDMMC2_D2,
CRS_SYNC,
UART7_RX,
EVENTOUT
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
NJTRST, TIM16_BKIN,
TIM3_CH1,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
90 C5 131 E7 B6 B6 163 B5 56 A6 90 134 A9 162 A9 PB4(NJTRST) I/O FT_h0 SPI2_NSS/I2S2_WS, -
SPI6_MISO/I2S6_SDI,
SDMMC2_D3,
UART7_TX,
EVENTOUT
TIM17_BKIN,
TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI/I2S6_SDO,
91 A6 132 F7 C6 C6 164 E7 57 C5 91 135 A6 163 A8 PB5 I/O FT_h0 -
FDCAN2_RX,
OTG_HS_ULPI_D7,
LCD_B5,
FMC_SDCKE1,
DCMI_D10/PSSI_D10,
UART5_RX,
EVENTOUT
TIM16_CH1N,
TIM4_CH1, I2C1_SCL,
HDMI_CEC, I2C4_SCL,
USART1_TX,
LPUART1_TX,
FDCAN2_TX,
92 D4 133 C8 A5 A5 165 A4 58 B5 92 136 B6 164 B6 PB6 I/O FT_f -
OCTOSPIM_P1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1,
DCMI_D5/PSSI_D5,
UART5_TX,
EVENTOUT
TIM17_CH1N,
TIM4_CH2,
I2C1_SDA, I2C4_SDA,
USART1_RX,
LPUART1_RX,
93 B5 134 D8 D6 B5 166 D6 59 A5 93 137 B5 165 B5 PB7 I/O FT_fa PVD_IN
DFSDM1_CKIN5,
FMC_NL,
DCMI_VSYNC/
PSSI_RDY,
EVENTOUT
TIM16_CH1,
TIM4_CH3,
DFSDM1_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
95 A4 136 B9 B5 A2 168 B4 61 B4 95 139 A5 167 A7 PB8 I/O FT_fsh3 UART4_RX, -
FDCAN1_RX,
SDMMC2_D4,
SDMMC1_D4,
DCMI_D6/PSSI_D6,
LCD_B6, EVENTOUT
TIM17_CH1,
TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA, SPI2_NSS/
I2S2_WS, I2C4_SDA,
96 E3 137 E8 C5 B3 169 A3 62 A4 96 140 B4 168 B4 PB9 I/O FT_fsh3 -
SDMMC1_CDIR,
UART4_TX,
FDCAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
SDMMC1_D5,
DCMI_D7/PSSI_D7,
LCD_B7, EVENTOUT
LPTIM1_ETR,
TIM4_ETR,
LPTIM2_ETR,
UART8_RX,
97 B4 138 F8 D5 B4 170 B3 - D4 97 141 A4 169 A6 PE0 I/O FT_h2 -
SAI2_MCK_A,
FMC_NBL0, DCMI_D2/
PSSI_D2, LCD_R0,
EVENTOUT
LPTIM1_IN2,
UART8_TX,
- C4 139 C9 D4 C4 171 C4 - C4 98 142 A3 170 A5 PE1 I/O FT_h2 FMC_NBL1, DCMI_D3/ -
PSSI_D3, LCD_R6,
EVENTOUT
TIM8_BKIN,
SAI2_MCK_A,
TIM8_BKIN_COMP12,
- - - - - - - A2 - - - - D4 173 C3 PI4 I/O FT_h2 -
FMC_NBL2, DCMI_D5/
PSSI_D5, LCD_B4,
EVENTOUT
TIM8_CH1,
SAI2_SCK_A,
FMC_NBL3,
- - - - - - - B2 - - - - C4 174 D3 PI5 I/O FT_h2 -
DCMI_VSYNC/
PSSI_RDY, LCD_B5,
EVENTOUT
TIM8_CH2,
SAI2_SD_A,
- - - - - - - C3 - - - - C3 175 D6 PI6 I/O FT_h2 FMC_D28, DCMI_D6/ -
PSSI_D6, LCD_B6,
EVENTOUT
TIM8_CH3,
SAI2_FS_A, FMC_D29,
- - - - - - - D4 - - - - C2 176 D4 PI7 I/O FT_h2 -
DCMI_D7/PSSI_D7,
LCD_B7, EVENTOUT
- - - - - K12 - - - - - - J6 - - VSS S - - -
- - - - - G8 - - - - - - D7 - - VSS S - - -
- - - - - G9 - - - - - - D8 - - VSS S - - -
- - - - - H7 - - - - - - F8 - - VSS S - - -
- - - - - H8 - - - - - - G12 - - VSS S - - -
- - - - - - - - - - - - F9 - - VSS S - - -
- - - - - H9 - - - - - - H9 - - VSS S - - -
- - - - - J8 - - - - - - H10 - - VSS S - - -
- - - - - K9 - - - - - - J7 - - VSS S - - -
- - - - - R15 - - - - - - J8 - - VSS S - - -
UFBGA176+25
Pin name
TFBGA100
TFBGA216
Pin I/O Additional
LQFP100
LQFP144
LQFP176
LQFP64
(function Alternate functions
type structure functions
after reset)
- - - - - - - - - - - - G6 - - VSS S - - -
- - - - - - - - - - - - K6 - - VSS S - - -
- - - - - - - - - - - - K7 - - VSS S - - -
DFSDM1/2/
CEC/DCMI/ I2C4/LCD/
CEC/SPI1/ SDMMC1/ LPUART1/ FDCAN1/2/FMC/
DFSDM1/ PSSI/ DFSDM1/2/ MDIOS/
I2S1/SPI2/ SPI2/I2S2/ SAI2/ LCD/ CRS/FMC/LCD/ FMC/LCD/
Port LPTIM2/3/ DFSDM1/2/ I2C4/ OCTOSPIM_P1/ COMP/DCMI/
LPTIM1/ PDM_SAI1/ I2S2/SPI3/ SPI3/I2S3/ SDMMC1/ OCTOSPIM_P1/2/ OCTOSPIM_P1/ MDIOS/
SYS LPUART1/ I2C1/2/3/4/ OCTOSPIM_P1/ SDMMC2/ PSSI/LCD/ LCD/UART5 SYS
TIM1/2/16/17 TIM3/4/5/12/15 I2S3/ SPI6/I2S6/ SPDIFRX1/ SDMMC2/ OTG1_FS/OTG1_HS/ SDMMC1/
OCTOSPIM_P1/2/ LPTIM2/ SAI1/SPI3/I2S3/ SWPMI1/ TIM1
SPI4/5/ UART7/ SPI6/I2S6/ SPDIFRX1/ SAI2/SDMMC2/TIM8 TIM1/8
TIM8 TIM15/ UART4 TIM1/8/
SPI6/I2S6 USART1/2/3/6 UART4/5/8 TIM13/14
USART1 UART7/9/
USART10
USART2_
NSS
DFSDM2_ USART2_
PA2 - TIM2_CH3 TIM5_CH3 - TIM15_CH1 - SAI2_SCK_B - - - MDIOS_MDIO - LCD_R1 EVENTOUT
CKIN1 TX
DFSDM2_
SPI1_MOSI/ SPI6_MOSI/
PA7 - TIM1_CH1N TIM3_CH2 TIM8_CH1N - - TIM14_CH1 OCTOSPIM_P1_IO2 - FMC_SDNWE - LCD_VSYNC EVENTOUT
Port A
I2S1_SDO I2S6_SDO
DATIN1
USART1_
SPI2_NSS/ FDCAN1_
PA11 - TIM1_CH4 - LPUART1_CTS - UART4_RX CTS/ - - - - - LCD_R4 EVENTOUT
I2S2_WS RX
USART1_NSS
STM32H7B3xI
JTMS/
PA13 - - - - - - - - - - - - - - EVENTOUT
SWDIO
JTCK/
PA14 - - - - - - - - - - - - - - EVENTOUT
page 69/231
SWCLK
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
OTG_HS_
PB0 - TIM1_CH2N TIM3_CH3 TIM8_CH2N DFSDM2_CKOUT - DFSDM1_CKOUT - UART4_CTS LCD_R3 OCTOSPIM_P1_IO1 - - LCD_G1 EVENTOUT
ULPI_D1
OTG_HS_ OCTOSPIM_
PB1 - TIM1_CH3N TIM3_CH4 TIM8_CH3N - - DFSDM1_DATIN1 - - LCD_R6 - - LCD_G0 EVENTOUT
ULPI_D2 P1_IO0
SPI3_MOSI/ OCTOSPIM_
PB2 RTC_OUT2 - SAI1_D1 - DFSDM1_CKIN1 - SAI1_SD_A - OCTOSPIM_P1_CLK - - - - EVENTOUT
I2S3_SDO P1_DQS
OCTOSPIM_
PB6 - TIM16_CH1N TIM4_CH1 - I2C1_SCL HDMI_CEC I2C4_SCL USART1_TX LPUART1_TX FDCAN2_TX DFSDM1_DATIN5 FMC_SDNE1 DCMI_D5/PSSI_D5 UART5_TX EVENTOUT
P1_NCS
DCMI_VSYNC/
PB7 - TIM17_CH1N TIM4_CH2 - I2C1_SDA - I2C4_SDA USART1_RX LPUART1_RX - - DFSDM1_CKIN5 FMC_NL - EVENTOUT
Port B
PSSI_RDY
PB8 - TIM16_CH1 TIM4_CH3 DFSDM1_CKIN7 I2C1_SCL - I2C4_SCL SDMMC1_CKIN UART4_RX FDCAN1_RX SDMMC2_D4 - SDMMC1_D4 DCMI_D6/PSSI_D6 LCD_B6 EVENTOUT
SPI2_NSS/
PB9 - TIM17_CH1 TIM4_CH4 DFSDM1_DATIN7 I2C1_SDA I2C4_SDA SDMMC1_CDIR UART4_TX FDCAN1_TX SDMMC2_D5 I2C4_SMBA SDMMC1_D5 DCMI_D7/PSSI_D7 LCD_B7 EVENTOUT
I2S2_WS
OTG_HS_
PB11 - TIM2_CH4 - LPTIM2_ETR I2C2_SDA - DFSDM1_CKIN7 USART3_RX - - - - - LCD_G5 EVENTOUT
ULPI_D4
OCTOSPIM_ OTG_HS_
SPI2_NSS/
PB12 - TIM1_BKIN - I2C2_SMBA DFSDM1_DATIN1 USART3_CK - FDCAN2_RX DFSDM2_DATIN1 - TIM1_BKIN_COMP12 UART5_RX EVENTOUT
I2S2_WS
P1_NCLK ULPI_D5
SPI2_MISO/
PB14 - TIM1_CH2N TIM12_CH1 TIM8_CH2N USART1_TX DFSDM1_DATIN2 USART3_RTS UART4_RTS SDMMC2_D0 - - - - LCD_CLK EVENTOUT
I2S2_SDI
SPI2_MOSI/
PB15 RTC_REFIN TIM1_CH3N TIM12_CH2 TIM8_CH3N USART1_RX DFSDM1_CKIN2 - UART4_CTS SDMMC2_D1 - - - - LCD_G7 EVENTOUT
I2S2_SDO
STM32H7B3xI
page 70/231
Table 10. Port C alternate functions
DS13139 - Rev 7
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
DFSDM1/2/
I2C4/LCD/
CEC/SPI1/ SDMMC1/ CRS/FMC/LCD/
DFSDM1/ CEC/DCMI/PSSI/ MDIOS/
I2S1/SPI2/ DFSDM1/2/I2C4/ SPI2/I2S2/ LPUART1/ FDCAN1/2/FMC/LCD OCTOSPIM_P1/ FMC/LCD/
Port LPTIM2/3/ DFSDM1/2/ OCTOSPIM_P1/ COMP/DCMI/
LPTIM1/ PDM_SAI1/ I2S2/SPI3/ OCTOSPIM_P1/ SPI3/I2S3/ SAI2/SDMMC1/ /OCTOSPIM_P1/2/ OTG1_FS/ MDIOS/
SYS LPUART1/ I2C1/2/3/4/ SDMMC2/ PSSI/LCD/ LCD/UART5 SYS
TIM1/2/16/17 TIM3/4/5/12/15 I2S3/ SAI1/SPI3/I2S3/ SPI6/I2S6/ SPDIFRX1/SPI6/ SDMMC2/ OTG1_HS/ SDMMC1/
OCTOSPIM_P1/2/ LPTIM2/TIM15/ SWPMI1/ TIM1
SPI4/5/ UART4 UART7/ I2S6/UART4/5/8 SPDIFRX1/TIM13/14 SAI2/SDMMC2/ TIM1/8
TIM8 USART1 TIM1/8/
SPI6/I2S6 USART1/2/3/6 TIM8
UART7/9/
USART10
OTG_HS_
PC0 - - - DFSDM1_CKIN0 - - DFSDM1_DATIN4 - SAI2_FS_B FMC_A25 LCD_G2 FMC_SDNWE - LCD_R5 EVENTOUT
ULPI_STP
OCTOSPIM_
SPI2_MOSI/
PC1 TRACED0 - SAI1_D1 DFSDM1_DATIN0 DFSDM1_CKIN4 SAI1_SD_A - - SDMMC2_CK - MDIOS_MDC - LCD_G5 EVENTOUT
I2S2_SDO
P1_IO4
OTG_HS_ OCTOSPIM_
SPI2_MISO/
PC2 PWR_CSTOP - - DFSDM1_CKIN1 - DFSDM1_CKOUT - - OCTOSPIM_P1_IO2 FMC_SDNE0 - - EVENTOUT
I2S2_SDI
ULPI_DIR P1_IO5
OTG_HS_ OCTOSPIM_
SPI2_MOSI/
PC3 PWR_CSLEEP - - DFSDM1_DATIN1 - - - - OCTOSPIM_P1_IO0 FMC_SDCKE0 - - EVENTOUT
I2S2_SDO
ULPI_NXT P1_IO6
OCTOSPIM_
PC5 - - SAI1_D3 DFSDM1_DATIN2 PSSI_D15 - - - - SPDIFRX1_IN3 - FMC_SDCKE0 COMP1_OUT LCD_DE EVENTOUT
P1_DQS
DCMI_D0/
PC6 - - TIM3_CH1 TIM8_CH1 DFSDM1_CKIN3 I2S2_MCK - USART6_TX SDMMC1_D0DIR FMC_NWAIT SDMMC2_D6 - SDMMC1_D6 LCD_HSYNC EVENTOUT
PSSI_D0
DCMI_D1/
Port C
PC7 TRGIO - TIM3_CH2 TIM8_CH2 DFSDM1_DATIN3 - I2S3_MCK USART6_RX SDMMC1_D123DIR FMC_NE1 SDMMC2_D7 SWPMI_TX SDMMC1_D7 LCD_G6 EVENTOUT
PSSI_D1
FMC_NE2/ DCMI_D2/
PC8 TRACED1 - TIM3_CH3 TIM8_CH3 - - - USART6_CK UART5_RTS FMC_INT SWPMI_RX SDMMC1_D0 - EVENTOUT
FMC_NCE PSSI_D2
SWPMI_ DCMI_D3/
PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - - UART5_CTS OCTOSPIM_P1_IO0 LCD_G3 SDMMC1_D1 LCD_B2 EVENTOUT
SUSPEND PSSI_D3
SPI3_SCK/ DCMI_D8/
PC10 - - - DFSDM1_CKIN5 DFSDM2_CKIN0 - USART3_TX UART4_TX OCTOSPIM_P1_IO1 LCD_B1 SWPMI_RX SDMMC1_D2 LCD_R2 EVENTOUT
I2S3_CK PSSI_D8
SPI3_MISO/ DCMI_D4/
PC11 - - - DFSDM1_DATIN5 DFSDM2_DATIN0 - USART3_RX UART4_RX OCTOSPIM_P1_NCS - - SDMMC1_D3 LCD_B4 EVENTOUT
I2S3_SDI PSSI_D4
PC13 - - - - - - - - - - - - - - - EVENTOUT
PC14 - - - - - - - - - - - - - - - EVENTOUT
PC15 - - - - - - - - - - - - - - - EVENTOUT
STM32H7B3xI
page 71/231
Table 11. Port D alternate functions
DS13139 - Rev 7
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
DFSDM1/2/
I2C4/LCD/
CEC/SPI1/ SDMMC1/ LPUART1/
DFSDM1/ CEC/DCMI/PSSI/ FDCAN1/2/FMC/LC CRS/FMC/LCD/ MDIOS/
I2S1/SPI2/ DFSDM1/2/I2C4/ SPI2/I2S2/ SAI2/ FMC/LCD/ COMP/
Port LPTIM2/3/ DFSDM1/2/ D/OCTOSPIM_P1/2/ OCTOSPIM_P1/ OCTOSPIM_P1/
LPTIM1/ PDM_SAI1/ I2S2/SPI3/ OCTOSPIM_P1/ SPI3/I2S3/ SDMMC1/ MDIOS/ DCMI/
SYS LPUART1/ I2C1/2/3/4/ SDMMC2/ OTG1_FS/ SDMMC2/ LCDUART5 SYS
TIM1/2/16/17 TIM3/4/5/12/15 I2S3/ SAI1/SPI3/I2S3/ SPI6/I2S6/ SPDIFRX1/ SDMMC1/ PSSI/LCD/
OCTOSPIM_P1/2/ LPTIM2/TIM15/ SPDIFRX1/ OTG1_HS/SAI2/ SWPMI1/
SPI4/5/ UART4 UART7/ SPI6/I2S6/ TIM1/8 TIM1
TIM8 USART1 TIM13/14 SDMMC2/TIM8 TIM1/8/
SPI6/I2S6 USART1/2/3/6 UART4/5/8
UART7/9/
USART10
FMC_D2/
PD0 - - - DFSDM1_CKIN6 - - - - UART4_RX FDCAN1_RX - UART9_CTS - LCD_B1 EVENTOUT
FMC_DA2
FMC_D3/
PD1 - - - DFSDM1_DATIN6 - - - - UART4_TX FDCAN1_TX - - - - EVENTOUT
FMC_DA3
DCMI_D11/
PD2 TRACED2 - TIM3_ETR - TIM15_BKIN - - - UART5_RX LCD_B7 - - SDMMC1_CMD LCD_B2 EVENTOUT
PSSI_D11
SPI3_MOSI/ DCMI_D10/
PD6 - - SAI1_D1 DFSDM1_CKIN4 DFSDM1_DATIN1 SAI1_SD_A USART2_RX - - OCTOSPIM_P1_IO6 SDMMC2_CK FMC_NWAIT LCD_B2 EVENTOUT
I2S3_SDO PSSI_D10
SPI1_MOSI/
PD7 - - - DFSDM1_DATIN4 - DFSDM1_CKIN1 USART2_CK - SPDIFRX1_IN0 OCTOSPIM_P1_IO7 SDMMC2_CMD FMC_NE1 - - EVENTOUT
I2S1_SDO
FMC_D13/
Port D
FMC_D14/
PD9 - - - DFSDM1_DATIN3 - - - USART3_RX - - - - - - EVENTOUT
FMC_DA14
FMC_D15/
PD10 - - - DFSDM1_CKOUT DFSDM2_CKOUT - - USART3_CK - - - - - LCD_B3 EVENTOUT
FMC_DA15
FMC_A16/
USART3_CTS/
PD11 - - - LPTIM2_IN2 I2C4_SMBA - - - OCTOSPIM_P1_IO0 SAI2_SD_A - - - EVENTOUT
USART3_NSS
FMC_CLE
FMC_A17/ DCMI_D12/
PD12 - LPTIM1_IN1 TIM4_CH1 LPTIM2_IN1 I2C4_SCL - - USART3_RTS - OCTOSPIM_P1_IO1 SAI2_FS_A - - EVENTOUT
FMC_ALE PSSI_D12
DCMI_D13/
PD13 - LPTIM1_OUT TIM4_CH2 - I2C4_SDA - - - - OCTOSPIM_P1_IO3 SAI2_SCK_A UART9_RTS FMC_A18 - EVENTOUT
PSSI_D13
FMC_D0/
PD14 - - TIM4_CH3 - - - - - UART8_CTS - - UART9_RX - - EVENTOUT
FMC_DA0
FMC_D1/
PD15 - - TIM4_CH4 - - - - - UART8_RTS - - UART9_TX - - EVENTOUT
FMC_DA1
STM32H7B3xI
page 72/231
Table 12. Port E alternate functions
DS13139 - Rev 7
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
CEC/DCMI/
CEC/SPI1/ SDMMC1/ LPUART1/ DFSDM1/2/
DFSDM1/ PSSI/ DFSDM1/2/ FDCAN1/2/FMC/LC CRS/FMC/LCD/
I2S1/SPI2/ SPI2/I2S2/ SAI2/ I2C4/LCD/MDIOS/ FMC/LCD/
Port LPTIM2/3/ DFSDM1/2/ I2C4/ D/OCTOSPIM_P1/2/ OCTOSPIM_P1/
LPTIM1/ PDM_SAI1/ I2S2/SPI3/ SPI3/I2S3/ SDMMC1/ OCTOSPIM_P1/ MDIOS/ COMP/DCMI/ LCD/
SYS LPUART1/ I2C1/2/3/4/ OCTOSPIM_P1/ SDMMC2/ OTG1_FS/ SYS
TIM1/2/16/17 TIM3/4/5/12/15 I2S3/ SPI6/I2S6/ SPDIFRX1/ SDMMC2/SWPMI1/ SDMMC1/ PSSI/LCD/TIM1 UART5
OCTOSPIM_P1/2/ LPTIM2/ SAI1/SPI3/I2S3/ SPDIFRX1/ OTG1_HS/SAI2/
SPI4/5/ UART7/ SPI6/I2S6/ TIM1/8/UART7/9/ TIM1/8
TIM8 TIM15/ UART4 TIM13/14 SDMMC2/TIM8
SPI6/I2S6 USART1/2/3/6 UART4/5/8 USART10
USART1
DCMI_D2/
PE0 - LPTIM1_ETR TIM4_ETR - LPTIM2_ETR - - - UART8_Rx - SAI2_MCK_A - FMC_NBL0 LCD_R0 EVENTOUT
PSSI_D2
DCMI_D3/
PE1 - LPTIM1_IN2 - - - - - - UART8_Tx - - - FMC_NBL1 LCD_R6 EVENTOUT
PSSI_D3
DCMI_D4/
PE4 TRACED1 - SAI1_D2 DFSDM1_DATIN3 TIM15_CH1N SPI4_NSS SAI1_FS_A - - - - - FMC_A20 LCD_B0 EVENTOUT
PSSI_D4
DCMI_D6/
PE5 TRACED2 - SAI1_CK2 DFSDM1_CKIN3 TIM15_CH1 SPI4_MISO SAI1_SCK_A - - - - - FMC_A21 LCD_G0 EVENTOUT
PSSI_D6
TIM1_BKIN2_ DCMI_D7/
PE6 TRACED3 TIM1_BKIN2 SAI1_D1 - TIM15_CH2 SPI4_MOSI SAI1_SD_A - - - SAI2_MCK_B FMC_A22 LCD_G1 EVENTOUT
COMP12 PSSI_D7
FMC_D4/
PE7 - TIM1_ETR - DFSDM1_DATIN2 - - - UART7_RX - - OCTOSPIM_P1_IO4 - - - EVENTOUT
FMC_DA4
FMC_D5/
Port E
FMC_D6/
PE9 - TIM1_CH1 - DFSDM1_CKOUT - - - UART7_RTS - - OCTOSPIM_P1_IO6 - - - EVENTOUT
FMC_DA6
FMC_D7/
PE10 - TIM1_CH2N - DFSDM1_DATIN4 - - - UART7_CTS - - OCTOSPIM_P1_IO7 - - - EVENTOUT
FMC_DA7
FMC_D8/
PE11 - TIM1_CH2 - DFSDM1_CKIN4 - SPI4_NSS - - - - SAI2_SD_B OCTOSPIM_P1_NCS - LCD_G3 EVENTOUT
FMC_DA8
FMC_D9/ COMP1_
PE12 - TIM1_CH3N - DFSDM1_DATIN5 - SPI4_SCK - - - - SAI2_SCK_B - LCD_B4 EVENTOUT
FMC_DA9 OUT
FMC_D10/
PE13 - TIM1_CH3 - DFSDM1_CKIN5 - SPI4_MISO - - - - SAI2_FS_B - COMP2_OUT LCD_DE EVENTOUT
FMC_DA10
FMC_D11/
PE14 - TIM1_CH4 - - SPI4_MOSI - - - - SAI2_MCK_B - - LCD_CLK EVENTOUT
FMC_DA11
FMC_D12/
PE15 - TIM1_BKIN - - - - - - - - USART10_CK TIM1_BKIN_COMP12 LCD_R7 EVENTOUT
FMC_DA12
STM32H7B3xI
page 73/231
Table 13. Port F alternate functions
DS13139 - Rev 7
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
DFSDM1/2/
CEC/DCMI/
LPUART1/ I2C4/LCD/
DFSDM1/ PSSI/ CEC/SPI1/ SDMMC1/SPI2/
DFSDM1/2/I2C4/ SAI2/ FDCAN1/2/FMC/LCD/ CRS/FMC/LCD/ MDIOS/ FMC/LCD/ COMP/
Port LPTIM2/3/ DFSDM1/2/ I2S1/SPI2/ I2S2/SPI3/
LPTIM1/ PDM_SAI1/ OCTOSPIM_P1/ SDMMC1/ OCTOSPIM_P1/2/ OCTOSPIM_P1/ OCTOSPIM_P1/ MDIOS/ DCMI/ LCD/
SYS LPUART1/ I2C1/2/3/4/ I2S2/SPI3/ I2S3/SPI6/ SYS
TIM1/2/16/17 TIM3/4/5/12/15 SAI1/SPI3/I2S3/ SPDIFRX1/ SDMMC2/SPDIFRX1/ OTG1_FS/OTG1_HS/ SDMMC2/ SDMMC1/ PSSI/LCD/ UART5
OCTOSPIM_P1/2/ LPTIM2/ I2S3/SPI4/5/ I2S6/UART7/
UART4 SPI6/I2S6/ TIM13/14 SAI2/SDMMC2/TIM8 SWPMI1/TIM1/8/ TIM1/8 TIM1
TIM8 TIM15/ SPI6/I2S6 USART1/2/3/6
UART4/5/8 UART7/9/
USART1
USART10
OCTOSPIM_
PF5 - - - - - - - - - - - FMC_A5 - - EVENTOUT
P2_NCLK
DCMI_D11/
PF10 - TIM16_BKIN SAI1_D3 - PSSI_D15 - - - - OCTOSPIM_P1_CLK - - - LCD_DE EVENTOUT
PSSI_D11
OCTOSPIM_ DCMI_D12/
PF11 - - - - - SPI5_MOSI - - - SAI2_SD_B - FMC_SDNRAS - EVENTOUT
P1_NCLK PSSI_D12
OCTOSPIM_
PF12 - - - - - - - - - - - FMC_A6 - - EVENTOUT
P2_DQS
STM32H7B3xI
page 74/231
Table 14. Port G alternate functions
DS13139 - Rev 7
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
DFSDM1/2/
CEC/DCMI/ I2C4/LCD/
CEC/SPI1/ SDMMC1/ LPUART1/
PSSI/ DFSDM1/2/ CRS/FMC/LCD/ MDIOS/
DFSDM1/LPTIM2/3/ I2S1/SPI2/ SPI2/I2S2/ SAI2/ FDCAN1/2/FMC/LCD FMC/LCD/
Port DFSDM1/2/ I2C4/ OCTOSPIM_P1/ OCTOSPIM_P1/ COMP/DCMI/
LPTIM1/ PDM_SAI1/ LPUART1/ I2S2/SPI3/ SPI3/I2S3/ SDMMC1/ /OCTOSPIM_P1/2/ MDIOS/ LCD/
SYS I2C1/2/3/4/ OCTOSPIM_P1/ OTG1_FS/ SDMMC2/ PSSI/LCD/ SYS
TIM1/2/16/17 TIM3/4/5/12/15 OCTOSPIM_P1/2/ I2S3/ SPI6/I2S6/ SPDIFRX1/ SDMMC2/SPDIFRX1/ SDMMC1/ UART5
LPTIM2/ SAI1/SPI3/I2S3/ OTG1_HS/SAI2/ SWPMI1/ TIM1
TIM8 SPI4/5/ UART7/ SPI6/I2S6/ TIM13/14 TIM1/8
TIM15/ UART4 SDMMC2/TIM8 TIM1/8/
SPI6/I2S6 USART1/2/3/6 UART4/5/8
USART1 UART7/9/
USART10
TIM8_BKIN_
PG2 - - - TIM8_BKIN - - - - - - - FMC_A12 - - EVENTOUT
COMP12
TIM8_BKIN2_
PG3 - - - TIM8_BKIN2 - - - - - - - FMC_A13 - - EVENTOUT
COMP12
TIM1_BKIN2_ FMC_A14/
PG4 - TIM1_BKIN2 - - - - - - - - - - - EVENTOUT
COMP12 FMC_BA0
FMC_A15/
PG5 - TIM1_ETR - - - - - - - - - - - - EVENTOUT
FMC_BA1
DCMI_D12/
PG6 - TIM17_BKIN - - - - - - - - OCTOSPIM_P1_NCS - FMC_NE3 LCD_R7 EVENTOUT
PSSI_D12
DCMI_D13/
PG7 - - - - - - SAI1_MCLK_A USART6_CK - OCTOSPIM_P2_DQS - - FMC_INT LCD_CLK EVENTOUT
PSSI_D13
Port G
SPI6_NSS/
PG8 - - - TIM8_ETR - - USART6_RTS SPDIFRX1_IN2 - - - FMC_SDCLK - LCD_G7 EVENTOUT
I2S6_WS
SPI1_NSS/ DCMI_D2/
PG10 - - - OCTOSPIM_P2_IO6 - - - - LCD_G3 SAI2_SD_B SDMMC2_D1 FMC_NE3 LCD_B2 EVENTOUT
I2S1_WS PSSI_D2
SPI1_SCK/ DCMI_D3/
PG11 - LPTIM1_IN2 - - - - - SPDIFRX1_IN0 OCTOSPIM_P2_IO7 SDMMC2_D2 USART10_RX - LCD_B3 EVENTOUT
I2S1_CK PSSI_D3
SPI6_MISO/
PG12 - LPTIM1_IN1 - OCTOSPIM_P2_NCS - - USART6_RTS SPDIFRX1_IN1 LCD_B4 SDMMC2_D3 USART10_TX - - LCD_B1 EVENTOUT
I2S6_SDI
SPI6_MOSI/
PG14 TRACED1 LPTIM1_ETR - - - - USART6_TX - OCTOSPIM_P1_IO7 SDMMC2_D7 USART10_RTS - - LCD_B0 EVENTOUT
I2S6_SDO
USART6_CTS/
DCMI_D13/
PG15 - - - - - - - - OCTOSPIM_P2_DQS - - - - EVENTOUT
PSSI_D13
USART6_NSS
STM32H7B3xI
page 75/231
Table 15. Port H alternate functions
DS13139 - Rev 7
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
DFSDM1/2/
CEC/DCMI/
LPUART1/ I2C4/LCD/
DFSDM1/ PSSI/ CEC/SPI1/ SDMMC1/SPI2/ CRS/FMC/LCD/
DFSDM1/2/I2C4/ SAI2/ FDCAN1/2/FMC/LCD MDIOS/ FMC/LCD/
Port LPTIM2/3/ DFSDM1/2/ I2S1/SPI2/ I2S2/SPI3/I2S3/ OCTOSPIM_P1/
LPTIM1/ PDM_SAI1/ OCTOSPIM_P1/ SDMMC1/ /OCTOSPIM_P1/2/ OCTOSPIM_P1/ MDIOS/ COMP/DCMI/ LCD/
SYS LPUART1/ I2C1/2/3/4/ I2S2/SPI3/ SPI6/I2S6/ OTG1_FS/ SYS
TIM1/2/16/17 TIM3/4/5/12/15 SAI1/SPI3/I2S3/ SPDIFRX1/ SDMMC2/SPDIFRX1/ SDMMC2/ SDMMC1/ PSSI/LCD/TIM1 UART5
OCTOSPIM_P1/2/ LPTIM2/ I2S3/SPI4/5/ UART7/ OTG1_HS/SAI2/
UART4 SPI6/I2S6/ TIM13/14 SWPMI1/TIM1/8/ TIM1/8
TIM8 TIM15/ SPI6/I2S6 USART1/2/3/6 SDMMC2/TIM8
UART4/5/8 UART7/9/
USART1
USART10
PH0 - - - - - - - - - - - - - - - EVENTOUT
PH1 - - - - - - - - - - - - - - - EVENTOUT
OTG_HS_
PH4 - - - - I2C2_SCL - - - - LCD_G5 - - PSSI_D14 LCD_G4 EVENTOUT
ULPI_NXT
DCMI_D8/
PH6 - - TIM12_CH1 - I2C2_SMBA SPI5_SCK - - - - - - FMC_SDNE1 - EVENTOUT
PSSI_D8
DCMI_D9/
PH7 - - - - I2C3_SCL SPI5_MISO - - - - - - FMC_SDCKE1 - EVENTOUT
PSSI_D9
DCMI_HSYNC/
PH8 - - TIM5_ETR - I2C3_SDA - - - - - - - FMC_D16 LCD_R2 EVENTOUT
Port H
PSSI_DE
DCMI_D0/
PH9 - - TIM12_CH2 - I2C3_SMBA - - - - - - - FMC_D17 LCD_R3 EVENTOUT
PSSI_D0
DCMI_D1/
PH10 - - TIM5_CH1 - I2C4_SMBA - - - - - - - FMC_D18 LCD_R4 EVENTOUT
PSSI_D1
DCMI_D2/
PH11 - - TIM5_CH2 - I2C4_SCL - - - - - - - FMC_D19 LCD_R5 EVENTOUT
PSSI_D2
DCMI_D3/
PH12 - - TIM5_CH3 - I2C4_SDA - - - - - - - FMC_D20 LCD_R6 EVENTOUT
PSSI_D3
DCMI_D4/
PH14 - - - TIM8_CH2N - - - - UART4_RX FDCAN1_RX - - FMC_D22 LCD_G3 EVENTOUT
PSSI_D4
DCMI_D11/
PH15 - - - TIM8_CH3N - - - - - - - - FMC_D23 LCD_G4 EVENTOUT
PSSI_D11
STM32H7B3xI
page 76/231
Table 16. Port I alternate functions
DS13139 - Rev 7
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
CEC/DCMI/
SDMMC1/ LPUART1/ FDCAN1/2/FMC/L DFSDM1/2/
PSSI/ CEC/SPI1/ CRS/FMC/LCD/
DFSDM1/2/I2C4/ SPI2/I2S2/ SAI2/ CD/ I2C4/LCD/MDIOS/ FMC/LCD/
Port DFSDM1/LPTIM2/3/ DFSDM1/2/ I2S1/SPI2/ OCTOSPIM_P1/
LPTIM1/ PDM_SAI1/ OCTOSPIM_P1/ SPI3/I2S3/ SDMMC1/ OCTOSPIM_P1/2/ OCTOSPIM_P1/ MDIOS/ COMP/DCMI/
SYS LPUART1/ I2C1/2/3/4/ I2S2/SPI3/ OTG1_FS/ LCD/UART5 SYS
TIM1/2/16/17 TIM3/4/5/12/15 SAI1/SPI3/I2S3/ SPI6/I2S6/ SPDIFRX1/ SDMMC2/ SDMMC2/SWPMI1/ SDMMC1/ PSSI/LCD/TIM1
OCTOSPIM_P1/2/TIM8 LPTIM2/ I2S3/SPI4/5/ OTG1_HS/SAI2/
UART4 UART7/ SPI6/I2S6/ SPDIFRX1/ TIM1/8/UART7/9/ TIM1/8
TIM15/ SPI6/I2S6 SDMMC2/TIM8
USART1/2/3/6 UART4/5/8 TIM13/14 USART10
USART1
SPI2_NSS/
DCMI_D13/
PI0 - - TIM5_CH4 - - - - - - - - FMC_D24 LCD_G5 EVENTOUT
PSSI_D13
I2S2_WS
SPI2_SCK/ DCMI_D8/
PI1 - - - TIM8_BKIN2 - - - - - - TIM8_BKIN2_COMP12 FMC_D25 LCD_G6 EVENTOUT
I2S2_CK PSSI_D8
DCMI_D9/
SPI2_MISO/
PI2 - - - TIM8_CH4 - - - - - - - FMC_D26 LCD_G7 EVENTOUT
I2S2_SDI
PSSI_D9
SPI2_MOSI/ DCMI_D10/
PI3 - - - TIM8_ETR - - - - - - - FMC_D27 - EVENTOUT
I2S2_SDO PSSI_D10
DCMI_D5/
PI4 - - - TIM8_BKIN - - - - - - SAI2_MCK_A TIM8_BKIN_COMP12 FMC_NBL2 LCD_B4 EVENTOUT
PSSI_D5
DCMI_VSYNC/
PSSI_
PI5 - - - TIM8_CH1 - - - - - - SAI2_SCK_A - FMC_NBL3 LCD_B5 EVENTOUT
RDY
DCMI_D6/
PI6 - - - TIM8_CH2 - - - - - - SAI2_SD_A - FMC_D28 LCD_B6 EVENTOUT
Port I
PSSI_D6
DCMI_D7/
PI7 - - - TIM8_CH3 - - - - - - SAI2_FS_A - FMC_D29 LCD_B7 EVENTOUT
PSSI_D7
PI8 - - - - - - - - - - - - - - - EVENTOUT
LCD_
PI9 - - - OCTOSPIM_P2_IO0 - - - - UART4_RX FDCAN1_RX - - FMC_D30 - EVENTOUT
VSYNC
LCD_
PI10 - - - OCTOSPIM_P2_IO1 - - - - - - - - FMC_D31 PSSI_D14 EVENTOUT
HSYNC
OTG_HS_
PI11 - - - OCTOSPIM_P2_IO2 - - - - - LCD_G6 - - PSSI_D15 - EVENTOUT
ULPI_DIR
STM32H7B3xI
page 77/231
Table 17. Port J alternate functions
DS13139 - Rev 7
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
CEC/DCMI/ DFSDM1/2/
LPUART1/ FDCAN1/2/FMC/LC
PSSI/ CEC/SPI1/ SDMMC1/SPI2/ CRS/FMC/LCD/ I2C4/LCD/MDIOS/
DFSDM1/LPTIM2/3/ DFSDM1/2/I2C4/ SAI2/ D/ FMC/LCD/ COMP/
Port DFSDM1/2/ I2S1/SPI2/ I2S2/SPI3/I2S3/ OCTOSPIM_P1/ OCTOSPIM_P1/
LPTIM1/ PDM_SAI1/ LPUART1/ OCTOSPIM_P1/ SDMMC1/ OCTOSPIM_P1/2/ MDIOS/ DCMI/ LCD/
SYS I2C1/2/3/4/ I2S2/SPI3/ SPI6/I2S6/ OTG1_FS/ SDMMC2/ SYS
TIM1/2/16/17 TIM3/4/5/12/15 OCTOSPIM_P1/2/ SAI1/SPI3/I2S3/ SPDIFRX1/ SDMMC2/ SDMMC1/ PSSI/LC UART5
LPTIM2/ I2S3/SPI4/5/ UART7/ OTG1_HS/SAI2/ SWPMI1/TIM1/8/
TIM8 UART4 SPI6/I2S6/ SPDIFRX1/ TIM1/8 D/TIM1
TIM15/ SPI6/I2S6 USART1/2/3/6 SDMMC2/TIM8 UART7/9/
UART4/5/8 TIM13/14
USART1 USART10
CEC/DCMI/
LPUART1/ FDCAN1/2/FMC/LC DFSDM1/2/
PSSI/ CEC/SPI1/ SDMMC1/SPI2/
DFSDM1/LPTIM2/3/ DFSDM1/2/I2C4/ SAI2/ D/ CRS/FMC/LCD/ I2C4/LCD/MDIOS/ FMC/LCD/ COMP/
Port DFSDM1/2/ I2S1/SPI2/ I2S2/SPI3/I2S3/
LPTIM1/ PDM_SAI1/ LPUART1/ OCTOSPIM_P1/ SDMMC1/ OCTOSPIM_P1/2/ OCTOSPIM_P1/ OCTOSPIM_P1/ MDIOS/ DCMI/ LCD/
SYS I2C1/2/3/4/ I2S2/SPI3/ SPI6/I2S6/ SYS
TIM1/2/16/17 TIM3/4/5/12/15 OCTOSPIM_P1/2/ SAI1/SPI3/I2S3/ SPDIFRX1/ SDMMC2/ OTG1_FS/OTG1_HS/ SDMMC2/SWPMI1/ SDMMC1/ PSSI/LC UART5
LPTIM2/ I2S3/SPI4/5/ UART7/
TIM8 UART4 SPI6/I2S6/ SPDIFRX1/ SAI2/SDMMC2/TIM8 TIM1/8/UART7/9/ TIM1/8 D/TIM1
TIM15/ SPI6/I2S6 USART1/2/3/6
UART4/5/8 TIM13/14 USART10
USART1
STM32H7B3xI
PK3 - - - OCTOSPIM_P2_IO6 - - - - - - - - - - LCD_B4 EVENTOUT
Port K
6 Electrical characteristics
Figure 19. Pin loading conditions Figure 20. Pin input voltage
C = 50 pF V IN
VDDSMPS VDDSMPS
10 μF 4.7 μ F 2.2 μH
VLXSMPS SMPS
Switched Mode
4.7 μF 4.7 μF
100 pF or 200 pF Power Supply
VFBSMPS step down
converter
VSSSMPS
SMPS enabled SMPS disabled
VCAP1/2
2.2 μF 100 nF(1) Core domain
LDO
VCAP3 Voltage
LDO enabled LDO disabled
VDDLDO regulator
100nF
VDD
Two different possible use cases PDR_ON
POR/PDR
VDDMMC VDDMMC
100
1 μF
nF 100 nF VDDMMC
IOs
VDD VDD
4.7 μF
100 nF(1) VDD
domain
VSS
Power switch
BKUP
IOs
5V VDD50USB
USB regulator
3.3V
4.7 μF VDD33USB
1 μF
1 μF 100 nF USB FS
IOs
Two different possible use cases
VDDA VDDA
Analog domain
1 μF 100 nF
47W
VREF+ VREF+
1 μF 1 μF 100 nF VREF-
VSSA
Three different possible use cases
LDO ON SMPS ON
IDD_VBAT IDD_VBAT
VBAT VBAT
VDDMMC VDDMMC
IDD IDD
VDD VDD
VDDLDO VDDSMPS
VDDA VDDA
Min(VDD, VDDA,
Input voltage on FT_xxx pins VSS−0.3 VDD33USB, VDDMMC, V
VBAT) +4.0(2)(3)
VIN(1) Input voltage on TT_xx pins VSS−0.3 4.0 V
|ΔVDDX| Variations between different VDDX power pins of the same domain - 50 mV
1. VIN maximum value must always be respected. Refer to Table 64. I/O current injection susceptibility for the maximum
allowed injected current values.
2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
3. This formula has to be applied on power supplies related to the I/O structure described by the pin definition table.
ΣIVDD Total current into sum of all VDD power lines (source)(1) 620
ΣIVSS Total current out of sum of all VSS ground lines (sink)(1) 620
IVDD Maximum current into each VDD power pin (source)(1) 100
IVSS Maximum current out of each VSS ground pin (sink)(1) 100
Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5 −5/+0
IINJ(PIN)(3)(4)
Injected current on PA4, PA5 −0/0
ΣIINJ(PIN) Total injected current (sum of all I/Os and control pins)(5) ±25
1. All main power (VDD, VDDA, VDDSMPS, VDDLDO, VDD33USB, VDDMMC) and ground (VSS, VSSA) pins must always be
connected to the external power supplies, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 19. Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
1.62(1) - 3.6
VDDLDO Supply voltage for the internal regulator VDDLDO ≤ VDD
1.2(2) - 3.6
BOOT0 0 - 9
Min(VDD,
VIN I/O Input voltage VDDA,
All I/O except BOOT0 VDD33USB,
−0.3 -
and TT_xx VDDMMC)
+3.6 V <
5.5 V(3)
VOS3 (max frequency
0.95 1.0 1.05
88 MHz)
VOS2 (max frequency
1.05 1.10 1.15
160 MHz)
Internal regulator ON (LDO or SMPS)(4)
VOS1 (max frequency
1.15 1.20 1.25
225 MHz)
VOS0 (max frequency
VCORE 1.25 1.30 1.35
280 MHz)
VOS3 (max frquency
0.97 1.0 1.05
88 MHz)
1. When a reset occurs, the functionality is guaranteed down to VPDRmax or to the specified VDDmin when the PDR is
OFF. The PDR can only be switched OFF though the PDR_ON pin that is not available in all packages (refer to
Table 7. STM32H7B3xI pin/ball definition)
2. Only for power-up sequence when the SMPS step-down converter is configured to supply the LDO.
3. This formula has to be applied on power supplies related to the I/O structures described by the pin definition table.
4. At startup, the external VCORE voltage must remain higher or equal to 1.10 V before disabling the internal regulator (LDO).
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Section 7.11 Thermal characteristics).
fcec_ker_ck HDMI_CEC 66 66 66 44
fsai_a_ker_ck
SAI1 150 150 80 80
fsai_b_ker_ck
fadp_clk USBOTG 48 48 48 48
fulpi_ck USB1ULPI 66 66 66 66
fadc_ker_ck ADC1/2 50 50 50 50
frtc_ker_ck RTC 1 1 1 1
1. Guaranteed by design.
2. The maximum kernel clock frequencies can be limited by the maximum peripheral clock frequency (refer each peripheral
electrical characteristics).
Power scale VCORE source Max TJ (°C) Max frequency (MHz) Min VDD (V)
ESR
R Leak
Average current for a 40 °C rise: rated current for which the temperature of the inductor is raised 40°C
IRMS 1.4 A
by DC current
The SMPS current consumption can be determined using the following formula based on the maximum LDO
current consumption provided in Section 6.3.7 Supply current characteristics:
IDDSMPS = IDDLDO × VCORE ÷ VDD × efficency
where
IDDLDO is the current in LDO configuration given in the following tables
VCORE is the digital core supply (VCAP)
Efficiency is defined in the following curves.
Figure 24. SMPS efficicency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode,
TJ = 30 °C
Efficiency (%)
100
90
50
40
30
Current (mA)
1 10 100 1000
Figure 25. SMPS efficiency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode,
TJ = 130 °C
Efficiency (%)
100
90
40
30 Current (mA)
1 10 100 1000
Figure 26. SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5),
TJ = 30 °C
Efficiency (%)
100
90
80
70
20
10
0 Current (mA)
0.01 0.1 1 10 100
Figure 27. SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5),
TJ = 130 °C
Efficiency (%)
100
90
80
70
20
10
0 Current (mA)
0.01 0.1 1 10 100
Figure 28. SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5),
TJ = 30 °C
Efficiency (%)
100
90
80
70
20
10
0 Current (mA)
0.01 0.1 1 10 100
Figure 29. SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5),
TJ = 130 °C
Efficiency (%)
100
90
80
70
20
10
0 Current (mA)
0.01 0.1 1 10 100
tRSTTEMPO (1)
Reset temporization after POR released - - 377 550 µs
1. Guaranteed by design.
VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA = 3.3 V 08FFF810 - 08FFF812
Table 33. Inrush current and inrush electric charge characteristics for LDO and SMPS
1. The typical values are given for VDDLDO = VDDSMPS = 3.3 V and for typical decoupling capacitor values of CEXT and COUT.
2. The product consumption on VDDCORE is not taken into account in the inrush current and inrush electric charge.
Symbol Parameter Conditions Min Typ Max Unit
1. The inrush current and inrush electric charge on VDDLDO are not present in Bypass mode or when the
SMPS supplies VDDCORE.
2. The maximum value is given for the maximum decoupling capacitor CEXT.
3. The inrush current and inrush electric charge on VDDSMPS is not present if the external component (L or
COUT) is not present, that is if the SMPS is not used.
4. The maximum value is given for the maximum decoupling capacitor COUT and the minimum VDDSMPS
voltage.
5. The inrush current and inrush electric charge due to the transition from 1.2 V to the final VOUT value (1.8 V
or 2.5 V) is not taken into account.
Table 34. Typical and maximum current consumption in Run mode, code with data processing running from ITCM,
regulator ON
Data are in DTCM for best computation performance. In this case, the cache has no influence on consumption.
Max(1)(2)
frcc_cpu_ck Typ Typ
Symbol Parameter Conditions TJ = TJ = TJ = TJ = unit
(MHz) LDO SMPS
25 °C 85 °C 105 °C 130 °C
Table 35. Typical and maximum current consumption in Run mode, code with data processing running from Flash
memory, cache ON
Max(1)(2)
frcc_cpu_ck Typ Typ
Symbol Parameter Conditions TJ = TJ= TJ = TJ = unit
(MHz) LDO(1) SMPS(1)
25 °C 85 °C 105 °C 130 °C
Table 36. Typical and maximum current consumption in Run mode, code with data processing running from Flash
memory, cache OFF
Max(1)(2)
frcc_cpu_ck Typ Typ
Symbol Parameter Conditions TJ = TJ = TJ = TJ = Unit
(MHz) LDO(1) SMPS(1)
25 °C 85 °C 105 °C 130 °C
Max(1)(2)
frcc_cpu_ck Typ Typ
Symbol Parameter Conditions TJ = TJ = TJ = TJ = Unit
(MHz) LDO(1) SMPS(1)
25 °C 85 °C 105 °C 130 °C
VOS1 160 68.0 32.0 73 96 114 152
Table 37. Typical consumption in Run mode and corresponding performance versus code position
1. System in Run mode, CPU domain is DStop or DStop2 mode with memories of the CPU domain shut-off
enable or disable.
Max(1)(2)
frcc_cpu_ck Typ Typ
Symbol Parameter Conditions TJ = TJ = TJ = TJ= Unit
(MHz) LDO SMPS
25 °C 85 °C 105 °C 130 °C
Max(1)(2)
Typ Typ
Symbol Parameter Conditions TJ = TJ = TJ = TJ= Unit
LDO SMPS
25 °C 85 °C 105 °C 130 °C
SVOS3
0.540 0.487 2.33 14.36 24.52 46.29
Main(3)
Flash memory in low- power SVOS3 LP 0.495 0.193 2.27 14.21 24.28 45.94
mode, memory shut-off disable
SVOS4 0.370 0.137 1.59 10.58 18.52 35.90
SVOS5 0.245 0.090 0.98 7.18 13.10 26.61
SVOS3
0.560 0.504 2.39 14.62 24.93 47.01
Main(3)
Flash memory in normal mode, SVOS3 LP 0.515 0.209 2.33 14.47 24.69 46.65
memory shut-off disable
SVOS4 0.390 0.153 1.65 10.84 18.93 36.62
SVOS5 0.245 0.090 1.04 7.43 13.51 27.32
Stop, DStop
SVOS3
0.530 0.481 2.31 14.23 24.27 45.71
Main(3)
Flash memory in low- power SVOS3 LP 0.480 0.186 2.25 14.09 24.04 45.36
IDD(Stop) mode, memory shut-off enable mA
SVOS4 0.360 0.134 1.57 10.49 18.32 35.41
SVOS5 0.230 0.085 0.96 6.95 12.59 25.26
SVOS3
0.550 0.498 2.37 14.50 24.68 46.43
Main(3)
Flash memory in normal mode, SVOS3 LP 0.500 0.204 2.31 14.35 24.45 46.07
memory shut-off enable
SVOS4 0.380 0.151 1.63 10.75 18.73 36.13
SVOS5 0.230 0.085 1.02 7.21 13.00 25.97
SVOS3
0.161 0.343 0.32 1.67 2.86 5.58
Main(3)
Flash memory in low- power SVOS3 LP 0.115 0.046 0.28 1.62 2.80 5.50
Stop, DStop2 mode, memory shut-off disable
SVOS4 0.095 0.037 0.20 1.23 2.19 4.43
SVOS5 0.090 0.032 0.14 0.93 1.75 3.80
Max(1)(2)
Typ Typ
Symbol Parameter Conditions TJ = TJ = TJ = TJ= Unit
LDO SMPS
25 °C 85 °C 105 °C 130 °C
SVOS3
0.146 0.337 0.30 1.55 2.63 5.04
Main(3)
IDD(Stop) Stop, DStop2 Flash memory in low -power SVOS3 LP 0.100 0.040 0.26 1.51 2.58 4.96 mA
mode, memory shut-off enable
SVOS4 0.085 0.033 0.19 1.15 2.01 3.98
SVOS5 0.075 0.028 0.12 0.80 1.46 3.02
Typ LDO
Symbol Parameter Conditions Unit
SVOS3 LP SVOS4 SVOS5
OFF OFF 1.97 2.76 3.02 3.30 4.0 11.0 22.0 57.0
Supply current in ON OFF 2.78 3.69 4.02 4.40 5.4 13.0 25.0 64.0
IDD
Standby mode, µA
(Standby) OFF ON 2.46 3.37 3.73 4.07 5.0 12.2 23.3 59.0
IWDG OFF
ON ON 3.27 4.30 4.73 5.17 6.4 14.2 26.3 66.0
3. These values are given for PDR ON. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced
(refer to Section 6.3.5 Embedded reset and power control block characteristics).
Supply current in ON OFF 0.85 0.93 1.05 1.14 1.5 3.6 7.5 20.0
IDD (VBAT) µA
VBAT mode OFF ON 0.50 0.63 0.74 0.84 1.2 3.1 5.9 16
ON ON 1.34 1.54 1.76 1.91 2.5 4.8 8.8 22.0
IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3
IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3
IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3
IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3
IDD(Typ)
Peripheral Unit
VOS0 VOS1 VOS2 VOS3
APB4 Bridge 0.10 0.10 0.10 0.10 µA/MHz
Table 45. Peripheral current consumption in Stop, Standby and VBAT mode
CPU clock
tWUSLEEP(3) Wakeup from Sleep - 5.00 5.00
cycles
SVOS3 Main, HSI, Flash memory in normal mode 4.2 6
SVOS3 Main, HSI, Flash memory in low-power mode 8.3 11
SVOS3 LP, HSI, Flash memory in normal mode 5.0 7
SVOS3 LP, HSI, Flash memory in low-power mode 9.0 12
SVOS4, HSI, Flash memory in normal mode 15.7 19
SVOS4, HSI, Flash memory in low-power mode 19.7 25
SVOS5, HSI, Flash memory in normal mode 35.0 43
SVOS5, HSI, Flash memory in low-power mode 35.0 43
tWUDSTOP(3) Wakeup from DStop
SVOS3 Main, CSI, Flash memory in normal mode 42.5 52
SVOS3 Main, CSI, Flash memory in low power mode 48.0 58 µs
SVOS3 LP, CSI, Flash memory in normal mode 43.3 53
SVOS3 LP, CSI, Flash memory in low power mode 48.8 59
SVOS4, CSI, Flash memory in normal mode 54.0 65
SVOS4, CSI, Flash memory in low-power mode 59.5 72
SVOS5, CSI, Flash memory in normal mode 74.8 90
SVOS5, CSI, Flash memory in low-power mode 74.8 90
SVOS3 LP, HSI, Flash memory in low-power mode 9.7 13
Wakeup from DStop2, clock kept SVOS4, HSI, Flash memory in low-power mode 20.4 26
tWUDSTOP2(3)
running
SVOS5, HSI, Flash memory in low-power mode 35.7 44
1. Guaranteed by design.
2. The rise and fall times for a digital input signal are not specified. However the VHSEH and VHSEL conditions must be fulfilled.
3. The DC component of the signal must ensure that the signal peaks are located between VDD and VSS.
V HSEH
90 %
10 %
V HSEL
tr(HSE) tW(HSE) t
tf(HSE) tW(HSE)
T HSE
External fHSE_ext
IL
clock source OS C _IN
STM32
fLSE_ext User external clock source frequency External digital/analog clock - 32.768 1000 kHz
tw(LSEH)/ tw(LSEL) OSC32_IN high or low time External digital clock 250 - - ns
1. Guaranteed by design.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
V LSEH
90 %
10 %
V LSEL
tr(LSE) tW(LSE) t
tf(LSE) tW(LSE)
T LSE
External fLSE_ext
OSC32 _IN IL
clock source
STM32
During startup(3) - - 4
VDD=3 V, Rm=30 Ω
- 0.35 -
CL=10 pF at 4 MHz
VDD=3 V, Rm=30 Ω
- 0.40 -
CL=10 pF at 8 MHz
VDD=3 V, Rm=30 Ω
- 0.65 -
CL=10 pF at 32 MHz
VDD=3 V, Rm=30 Ω
- 0.95 -
CL=10 pF at 48 MHz
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range
(typical), designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator (see Figure 32. Typical application with an 8 MHz crystal). CL1 and CL2 are usually the same size. The
crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. The
PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin
and board capacitance) when sizing CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
Resonator with
integrated capacitors
C L1
OSC_ IN fH S E
Bias
8 MHz RF controlled
resonator
gain
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers.
2. Guaranteed by design.
3. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
Resonator with
integrated capacitors CL1
OSC32_IN fHSE
Bias
32.768 kHz
RF controlled
resonator
gain
OSC32_OUT
STM32
CL2
1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.
HSI48 oscillator frequency drift with VDD (reference is VDD = 3 to 3.6 V - 0.025 0.05
ΔVDD(HSI48)(2) %
3.3 V) VDD = 1.62 to 3.6 V - 0.05 0.1
at 1 % of target frequency - 4 8
tstab(HSI) HSI oscillator stabilization time µs
at 5 % of target frequency - - 4
IDD(HSI) HSI oscillator power consumption - - 300 400 µA
TRIM CSI user trimming step Other trimming are a multiple of 16 (not
−0,43 0.00 0.75 %
including multiple of 32)
DuCy(CSI) Duty Cycle - 45 - 55 %
TJ = 0 to 85 °C −3.7(3) - 4,5(3)
∆TEMP (CSI) CSI oscillator frequency drift over temperature %
TJ = −40 to 130 °C −11(3) - 7,5(3)
∆VDD(CSI) CSI oscillator frequency drift over VDD VDD = 1.62 to 3.6 V −0.06 - 0.06 %
fLSI LSI frequency TJ = –40 to 110 °C, VDD = 1.62 to 3.6 V 29,76(2) - 33,6(2) kHz
VOS0 1 - 280(2)
VOS1 1 - 225(2)
fPLL_P_OUT PLL multiplier output clock P, Q, R
VOS2 1 - 160(2) MHz
VOS3 1 - 88(2)
fVCO_OUT PLL VCO output - 128 - 560(3)
Flash memory
The characteristics are given at TJ = –40 to 130 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
Value
Symbol Parameter Conditions Unit
Min(1)
Level/
Symbol Parameter Conditions
Class
As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as possible to the MCU to
the pins exposed to noise (connected to tracks longer than 50 mm on PCB).
0.1 to 30 MHz 12
30 to 130 MHz 17
VDD = 3.6 V, TA = 25 °C, LQFP144 package, conforming to dBµV
SEMI Peak level 130 MHz to 1 GHz 15
IEC61967-2
1 GHz to 2 GHz 14
EMI Level 3.5 -
Maximum
Symbol Ratings Conditions Packages Class Unit
value
Static latchup
Two complementary static tests are required on six parts to assess the latchup performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Functional susceptibility
Symbol Description Unit
Negative injection Positive injection
PF2, PI12 0 NA
PG1, PE9, PB0, PA7, PC4, PC5, PE7, PE8, PA4, PA5, PA6, PF2, PI12, PC2_C,
IINJ 0 0 mA
PC3_C, PA0_C, PA1_C, BOOT0
All other I/Os 5 NA
VIL I/O input low-level voltage except BOOT0 1.62 V < VDDIOx < 3.6 V - - 0.4VDD−0.1(2) V
VIH I/O input high level voltage except BOOT0 1.62 V < VDDIOx < 3.6 V 0.47VDD+0.25(2) - - V
All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than
the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in
Figure 34. VIL/VIH for all I/Os except BOOT0.
In the user application, the number of I/O pins which can drive current must be limited to respect the absolute
maximum rating specified in Section 6.2 Absolute maximum ratings. In particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU
sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 20. Current characteristics).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk
on VSS cannot exceed the absolute maximum rating ΣIVSS (see Table 20. Current characteristics).
Table 66. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8
The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19. Voltage
characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the
absolute maximum ratings ΣIIO.
Symbol Parameter Conditions(1) Min Max Unit
CMOS port(2)
VOL Output low level voltage IIO=8 mA - 0.4
2.7 V≤ VDD ≤3.6 V
CMOS port(2)
VOH Output high level voltage IIO= −8 mA VDD−0.4 -
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOL (1)
Output low level voltage IIO=8 mA - 0.4
2.7 V≤ VDD ≤3.6 V
TTL port(2)
VOH (1)
Output high level voltage IIO=-8 mA 2.4 -
2.7 V≤ VDD ≤3.6 V
V
(1)
IIO=20 mA
VOL Output low level voltage - 1.3
2.7 V≤ VDD ≤3.6 V
IIO=−20 mA
VOH(1) Output high level voltage VDD−1.3 -
2.7 V≤ VDD ≤3.6 V
IIO= 4 mA
VOL(1) Output low level voltage - 0.4
1.62 V≤ VDD ≤3.6 V
VOH (1) Output high level voltage IIO= −4 mA 1.62 V≤VDD<3.6 V VDD−0.4 -
IIO= 20 mA
- 0.4
2.3 V≤ VDD≤3.6 V
VOLFM+ (1)
Output low level voltage for an FTf I/O pin in FM+ mode
IIO= 10 mA
- 0.4
1.62 V≤ VDD ≤3.6 V
1. Guaranteed by design.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
Table 67. Output voltage characteristics for PC13, PC14, PC15 and PI8
The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 19. Voltage
characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the
absolute maximum ratings ΣIIO.
VOL Output low level voltage CMOS port(2) IIO=8 mA, 2.7 V≤ VDD ≤ 3.6 V - 0.4
VOL(1) Output low level voltage TTL port(2) IIO = 8 mA, 2.7 V≤ VDD ≤ 3.6 V - 0.4
VOH(1) Output high level voltage TTL port(2) IIO=−8 mA, 2.7 V ≤ VDD ≤ 3.6 V 2.4 -
VOL(1) Output low level voltage IIO=20 mA, 2.7 V ≤ VDD ≤ 3.6 V - 1.3 V
VOH (1) IIO = −20 mA, 2.7 V ≤ VDD ≤ 3.6 V
Output high level voltage VDD−1.3 -
VOL(1) Output low level voltage IIO = 4 mA, 1.62 V ≤ VDD ≤ 3.6 V - 0.4
VOH (1) Output high level voltage IIO = −4 mA, 1.62 V ≤ VDD < 3.6 V VDD−0.4 -
1. Guaranteed by design.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
Output high to low level fall time and output low to C=30 pF, 1.62 V≤VDD≤2.7 V - 7.5
01 tr/tf (3) ns
high level rise time
C=10 pF, 2.7 V≤VDD≤3.6 V - 2.8
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3 T, skew ≤ 1/20 T, 45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
5. Reserved for output clock only.
Fmax (2)
Maximum frequency C=30 pF, 1.62 V≤VDD≤2.7 V(4) - 80 MHz
1. Guaranteed by design.
2. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3 T, skew ≤ 1/20 T, 45%<Duty cycle<55%
3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
4. Compensation system enabled.
5. Reserved for output clock only.
VF(NRST)(1) NRST Input filtered pulse 1.71 V < VDD < 3.6 V - - 50
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10%).
V DD
External
reset circuit (1)
R PU
NRST (2) Internal Reset
Filter
0.1 µF
STM32
tw(NE)
FMC_NE
FMC_NOE
FMC_NWE
tv(A_NE) t h(A_NOE)
FMC_A[25:0] Address
tv(BL_NE) t h(BL_NOE)
FMC_NBL[1:0]
t h(Data_NE)
tsu(Data_NOE) th(Data_NOE)
tsu(Data_NE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE) tw(NWE) t h(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)
FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FMC_D[15:0] Data
t v(NADV_NE)
tw(NADV)
FMC_NADV(1)
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
tw(NE)
FMC_NE
tv(NOE_NE) t h(NE_NOE)
FMC_NOE
t w(NOE)
FMC_NWE
tv(A_NE) th(A_NOE)
FMC_A[25:16] Address
tv(BL_NE) th(BL_NOE)
FMC_NBL[1:0] NBL
th(Data_NE)
tsu(Data_NE)
t v(A_NE) tsu(Data_NOE) th(Data_NOE)
t v(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
th(NE_NWAIT)
tsu(NWAIT_NE)
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck + 0.5 -
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck + 0.5 -
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
In all timing tables, Tfmc_ker_ck is the kernel clock period, with the following FMC_CLK maximum values:
• For 2.7 V < VDD < 3.6 V, FMC_CLK = 125 MHz at 20 pF
• For 1.8 V < VDD < 1.9 V, FMC_CLK = 100 MHz at 20 pF
• For 1.62 V < VDD<1.8 V, FMC_CLK = 100 MHz at 15 pF
FMC_CLK
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx
t d(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
td(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_CLK
Data latency = 0
td(CLKL-NExL) td(CLKH-NExH)
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:16]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
td(CLKH-NBLH)
FMC_NBL
tw(CLK) tw(CLK)
FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:0]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
FMC_D[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) t h(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
tw(CLK) tw(CLK)
FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:0]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-Data) td(CLKL-Data)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
FMC_NWE
td(ALE-NOE) th(NOE-ALE)
FMC_NOE (NRE)
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) th(NWE-ALE)
FMC_NWE
FMC_NOE (NRE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
Figure 45. NAND controller waveforms for common memory read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)
FMC_NWE
tw(NOE)
FMC_NOE
tsu(D-NOE) th(NOE-D)
FMC_D[15:0]
Figure 46. NAND controller waveforms for common memory write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) tw(NWE) th(NOE-ALE)
FMC_NWE
FMC_NOE
td(D-NWE)
tv(NWE-D) th(NWE-D)
FMC_D[15:0]
Table 83. Switching characteristics for NAND Flash memory read cycles
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
FMC_SDNWE
tsu(SDCLKH_Data) th(SDCLKH_Data)
FMC_SDCLK
td(SDCLKL_AddC)
td(SDCLKL_AddR) th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE) th(SDCLKL_SNDE)
FMC_SDNE[1:0]
td(SDCLKL_NRAS) th(SDCLKL_NRAS)
FMC_SDNRAS
td(SDCLKL_NCAS) th(SDCLKL_NCAS)
FMC_SDNCAS
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_SDNWE
td(SDCLKL_Data)
td(SDCLKL_NBL) th(SDCLKL_Data)
FMC_NBL[3:0]
(n/2)*t(CLK)/ (n/2)*t(CLK)/
tw(CLKH) -
OCTOSPI clock high (n+1) (n+1)+1
PRESCALER[7:0] = n = 2,4,6,8
and low time (n/2+1)*t(CLK)/ (n/2+1)*t(CLK)/
tw(CLKL) -
(n+1) −1 (n+1)
2.7 V < VDD < 3.6 V 2 - -
ts(IN)(4) Data input setup time
1.62 V < VDD < 3.6 V 2 - - ns
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
Data input D0 D1 D2
Table 90. OCTOSPI characteristics in DTR mode (with DQS)/Octal and Hyperbus
(n/2)*t(CLK)/ (n/2)*t(CLK)/
tw(CLKH) -
OCTOSPI clock high (n+1) (n+1)+1
PRESCALER[7:0] = n = 2,4,6,8
and low time (n/2+1)*t(CLK)/ (n/2+1)*t(CLK)/ ns
tw(CLKL) -
(n+1)−1 (n+1)
tv(CLK) Clock valid time - - - t(CLK)+1
t(CLK)/2−0.5
th(CLK) Clock hold time - - -
t(CLK)/2
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output D0 D1 D2 D3 D4 D5
Data input D0 D1 D2 D3 D4 D5
NCLK
VOD(CLK)
CLK
tw(CS)
NCS
CLK, NCLK
RWDS
Command address
Memory drives DQ[7:0] and RWDS.
Host drives DQ[7:0] and the memory drives RWDS.
tw(CS)
NCS
CLK, NCLK
Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)
Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B
Negative reference
VREF-(2) - VSSA
voltage
BOOST =
0.12 - 50
11
BOOST =
0.12 - 25
10
fADC ADC clock frequency 1,62 V ≤VDDA ≤ 3.6 V MHz
BOOST =
0.12 - 12.5
01
BOOST =
- - 6.25
00
Resolution = 16
bits, fADC = 36 MHz SMP = 1.5 - - 3.60
VDDA > 2.5 V TJ =
90 °C
Resolution = 16
fADC = 37 MHz SMP = 2.5 - - 3.35
bits
Resolution = 14
Sampling rate for fADC = 50 MHz SMP = 2.5 - - 5.00
bits
Direct channels
Resolution = 12
fADC=50 MHz SMP = 2.5 - - 5.50
bits TJ =
Resolution = 10 125 °C
fADC=50 MHz SMP=1.5 - - 7.10
bits
Resolution = 16
TJ = 90 °C - -
bits
Resolution = 14
- -
bits
fS(3) Sampling rate for MSPS
Slow channels, Resolution = 12
fADC=10 MHz SMP=1.5 - - 1.00
BOOST = 00, fADC = bits TJ =
10 MHz 125 °C
Resolution = 10
- -
bits
Resolution = 8
- -
bits
tTRIG External trigger period Resolution = 16 bits - - 10 1/fADC
Conversion voltage
VAIN(4) - 0 - VREF+ V
range
conversion
tSTAB ADC power-up time LDO already started 1 - -
cycle
Offset and linearity
tCAL - 165010
calibration time
tOFF_CAL Offset calibration time - 1280
fADC=3.125 MHz - 80 -
1. Guaranteed by design.
2. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.
3. These values are valid UFBGA176+25 and one ADC. The values for other packages and multiple ADCs
might be different
4. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches).
5. The tolerance is 10 LSBs for 16-bit resolution, 4 LSBs for 14-bit resolution, and 2 LSBs for 12-bit, 10-bit and
8-bit resolutions.
1. Guaranteed by design.
2. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC
performance.
3. Fast channels correspond for ADCx_INPx to PA6, PB1, PC4, PF11, PF13 and for ADCx_INNx to PA7, PB0,
PC5, PF12, PF14
4. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.
CLK
Mux Sampling(1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1. The sampling time defines the minimum sampling clock cycles (SMP) to be programmed in the ADC (refer to the product reference manual for details).
1. ADC clock frequency = 25 MHz, ADC resolution = 16 bits, VDDA=VREF+=3.3 V and BOOST=11.
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be
avoided as this significantly reduces the accuracy of the conversion being performed on another analog input.
It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative
currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.15 I/O current
injection characteristics does not affect the ADC accuracy.
VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
VSSA
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VDD STM32
VAIN VT
Cparasitic 0.6 V CADC(1)
IL ± 250 nA
1. Refer to Table 92. ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this,
fADC should be reduced.
Figure 57. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32
VREF+(1)
1 µF // 100 nF
VDDA
1 µF // 100 nF
VSSA/VREF-(1)
1. VREF+ input is not available on all package (refer to Table 1. STM32H7B3xI features and peripheral counts)
whereas VREF– is available only on UFBGA176+25, TFBGA225 with SMPS and TFBGA216. When VREF- is
not available, it is internally connected to VSSA.
Figure 58. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32
VREF+/VDDA(1)
1 µF // 100 nF
VREF-/VSSA(1)
1. VREF+ input is not available on all package (refer to Table 1. STM32H7B3xI features and peripheral counts)
whereas VREF– is available only on UFBGA176+25, TFBGA225 with SMPS and TFBGA216. When VREF- is
not available, it is internally connected to VSSA.
connected to VSSA 5 - -
RL Resistive Load DAC output buffer ON
connected to VDDA 25 - - kΩ
VDDA
DAC output buffer ON 0.2 -
VDAC_OUT Voltage on DAC_OUT output −0.2 V
DAC output buffer OFF 0 - VREF+
tTRIM Middle code offset trim time Minimum time to verify the each code 50 - - µs
2. In buffered mode, the output can overshoot above the final value for low input code (starting from the
minimum value).
3. Refer to Table 65. I/O static characteristics.
4. TON is the refresh phase duration, while TOFF is the hold phase duration. Refer to the product reference
manual for more details.
Offset1 Offset error at code 0x001(4) DAC output buffer OFF, CL ≤ 50 pF, no RL - - ±5 LSB
VREF+ = 3.6 V - - ±5
Offset error at code 0x800 after
OffsetCal DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 kΩ LSB
factory calibration VREF+ = 1.8 V - - ±7
Buffered/Non-buffered DAC
Buffer(1)
R L
12-bit DAC_OUTx
digital to
analog
converter
C L
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring
the BOFFx bit in the DAC_CR register.
Tcoeff
Tcoeff Temperature coefficient −40 °C < TJ < +130 °C - - - VREFINT + ppm/ °C
100
DC - - 60 -
PSRR Power supply rejection dB
100KHz - - 40 -
CL=0.5 µF - - 300 -
CL=1.5 µF - - 650 -
Control of maximum
DC current drive on
IINRUSH - - 8 - mA
VREFBUF_OUT during startup
phase(4)
ILOAD = 0 µA - - 15 25
VREFBUF consumption from
IDDA(VREFBUF) ILOAD = 500 µA - - 16 30 µA
VDDA
ILOAD = 4 mA - - 32 50
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.
TS_CAL1 Temperature sensor raw data acquired value at 30 °C, VDDA=3.3 V 0x08FF F814 - 0x08FF F816
TS_CAL2 Temperature sensor raw data acquired value at 130 °C, VDDA=3.3 V 0x08FF F818 - 0x08FF F81A
TJ =−40 °C to 30 °C −13 - 4
TTOTAL_ERROR(2) Temperature offset measurement, all VOS °C
TJ =30 °C to 130 °C −7 - 2
VOS2 0 - 0
TVDD_CORE Additional error due to supply variation °C
VOS0, VOS1, VOS3 −1 - 1
tTRIM Calibration time - - - 2 ms
tWAKE_UP Wake-up time from off state until DTS ready bit is set - - 67 116.00 μs
1. Guaranteed by design.
VBRS in PWR_CR3= 0 - 5 -
RBC Battery charging resistor KΩ
VBRS in PWR_CR3= 1 - 1.5 -
1. Guaranteed by design.
VBG (2)
Scaler input voltage - -
High-speed mode - 2 5
Comparator startup time to reach propagation
tSTART Medium mode - 5 20 µs
delay specification
Ultra-low-power mode - 15 80
High-speed mode - 50 80 ns
Propagation delay for 200 mV step with
Medium mode - 0.5 0.9
100 mV overdrive µs
Ultra-low-power mode - 2.5 7
tD (3)
High-speed mode - 50 120 ns
Propagation delay for step > 200 mV with
Medium mode - 0.5 1.2
100 mV overdrive only on positive inputs µs
Ultra-low-power mode - 2.5 7
Voffset Comparator offset error Full common mode range - ±5 ±20 mV
No hysteresis - 0 -
Low hysteresis 4 10 22
Vhys Comparator hysteresis mV
Medium hysteresis 8 20 37
High hysteresis 16 30 52
3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal
resistance between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.
DFSDM
fDFSDMCLK 1.62 V < VDD < 3.6 V - - fSYSCLK
clock
SPI mode (SITP[1:0]=0,1), External clock mode
- - 20 (fDFSDMCLK/4)
fCKIN (1/ Input clock (SPICKSEL[1:0]=0),
TCKIN) frequency SPI mode (SITP[1:0]=0,1), Internal clock mode MHz
- - 20 (fDFSDMCLK/4)
(SPICKSEL[1:0]≠0)
Output
fCKOUT clock 1.62 < VDD < 3.6 V - - 20
frequency
Even
Output division,CKOUTDIV[7:0] 45 50 55
clock = n, 1, 3, 5, ...
DuCyCKOUT 1.62 < VDD < 3.6 V %
frequency Odd
duty cycle (((n/ (((n/2+1)/ (((n/
division,CKOUTDIV[7:0]
2+1)/(n−1))*100)−5 (n−1))*100) 2+1)/(n−1))*100)+5
= n, 2, 4, 6, ...
SPI mode
Input clock (SITP[1:0]=0,1),
twh(CKIN)
high and External clock mode - TCKIN/2 - 0.5 TCKIN/2 -
twl(CKIN)
low time (SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
SPI mode
(SITP[1:0]=0,1),
Data input
tsu External clock mode - 4 - -
setup time
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
ns
SPI mode
(SITP[1:0]=0,1),
Data input
th External clock mode - 0.5 - -
hold time
(SPICKSEL[1:0]=0),
1.62 < VDD < 3.6 V
CKINy
(SPICKSEL=0)
SPI timing : SPICKSEL = 0
twl twh tr tf
tsu th
SITP = 00
DATINy
tsu th
SITP = 01
SPICKSEL=3
CKOUT
SPICKSEL=2
SPI timing : SPICKSEL = 1, 2, 3
SPICKSEL=1
twl twh tr tf
tsu th
SITP = 0
DATINy
tsu th
SITP = 1
SITP = 2
DATINy
Manchester timing
SITP = 3
recovered clock
recovered data 0 0 1 1 0
6.3.31 Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 108. DCMI characteristics for DCMI are derived
from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in
Table 22. General operating conditions and Table 23. Maximum allowed clock frequencies, with the following
configuration:
• DCMI_PIXCLK polarity: falling
tsu(HSYNC),
DCMI_HSYNC/ DCMI_VSYNC input setup time 3 - ns
tsu(VSYNC)
th(HSYNC),
DCMI_HSYNC/ DCMI_VSYNC input hold time 1 - -
th(VSYNC)
1. Guaranteed by design.
1/DCMI_PIXCLK
DCMI_PIXCLK
tsu(HSYNC) th(HSYNC)
DCMI_HSYNC
tsu(VSYNC) th(HSYNC)
DCMI_VSYNC
tsu(DATA) th(DATA)
DATA[0:13]
tc(PDCK)
tw(PDCKH) tw(PDCKL)
tf(PDCK) tr(PDCK)
PSSI_PDCK
CKPOL = 0
(input)
CKPOL = 1
tov(DATA) toh(DATA)
PSSI D[15:0]
Invalid data OUT Valid data OUT Invalid data OUT
(output)
PSSI_DE
DEPOL = 0
(output)
tov(DE) toh(DE)
DEPOL = 1
PSSI_RDY
RDYPOL = 0
(input)
tsu(RDY) th(RDY)
RDYPOL = 1
MSv65388V1
tc(PDCK)
tw(PDCKH) tw(PDCKL)
tf(PDCK) tr(PDCK)
PSSI_PDCK
CKPOL = 0
(input)
CKPOL = 1
tsu(DATA)
thDATA)
PSSI D[15:0]
Invalid data IN Valid data IN Invalid data IN
(input)
tsu(DE)
th(DE)
PSSI_DE
DEPOL = 0
(output)
DEPOL = 1
tov(RDY) toh(RDY)
PSSI_RDY
RDYPOL = 0
(input)
RDYPOL = 1
MSv65389V1
fCLK LTDC clock output frequency 2.7 V < VDD < 3.6 V - 133 MHz
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC) tv(HSYNC)
LCD_HSYNC
tv(DE) th(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
Pixel Pixel Pixel
LCD_G[0:7] 1 2 N
LCD_B[0:7]
th(DATA)
HSYNC Horizontal Horizontal
Active width
width back porch back porch
One line
tCLK
LCD_CLK
tv(VSYNC) tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]
One frame
AHB/APBx prescaler=1 or 2 or 4,
1 - tTIMxCLK
fTIMxCLK = 280 MHz
tres(TIM) Timer resolution time
AHB/APBx prescaler>4, fTIMxCLK =
1 - tTIMxCLK
140 MHz
Timer external clock frequency on
fEXT 0 fTIMxCLK/2 MHz
CH1 to CH4 fTIMxCLK = 280 MHz
ResTIM Timer resolution - 16/32 bit
1. The maximum timer frequency on APB1 or APB2 is up to 280 MHz, by setting the TIMPRE bit in the RCC_CFGR register. If
APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx_d2.
2. Guaranteed by design.
Standard-mode - 2
Analog Filtre ON, DNF=0 9
fI2CCLK I2CCLK frequency Fast-mode MHz
Analog Filtre OFF, DNF=1 9
The SDA and SCL I/O requirements are met with the following restrictions:
• The SDA and SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDDIOx is disabled, but still present.
• The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load CLoad
supported in Fm+, which is given by these formulas:
tr(SDA/SCL)=0.8473xRPxCLoad
RP(min)= (VDD-VOL(max))/IOL(max)
Where RP is the I2C lines pull-up. Refer to Section 6.3.16 I/O port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics:
tAF Maximum pulse width of spikes that are suppressed by analog filter 50(2) 260(3) ns
1. Guaranteed by design.
2. Spikes whose width is lower than tAF(min) are filtered.
3. Spikes whose width is higer than tAF(max) are not filtered.
Master mode 35
Slave receiver mode 93.0
fCK USART clock frequency - - MHz
Slave mode transmitter mode, 2.7 V < VDD < 3.6 V 29.0
Slave mode transmitter mode, 1.62 V < VDD < 3.6 V 22.0
tw(SCKH) -
, CK high and low time Master mode 1/fck/2−2 1/fck/2 1/fck/2+2
tw(SCKL)
tv(SO) Slave mode transmitter mode, 1.62 V < VDD < 3.6 V - 15.5 22
ns
tv(SO) Data output valid time Slave mode transmitter mode, 2.7 V < VDD < 3.6 V - 15.5 17
High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH)
tsu(RX) tw(SCKL) tr(SCK)/tf(SCK)
RX
INPUT MSB IN BIT6 IN LSB IN
th(RX)
TX
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX)
MSv65386V1
NSS
input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)
CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(TX) tw(SCKL) tv(TX) th(TX) tf(SCK) tdis(TX)
TX output First bit OUT Next bits OUT Last bit OUT
th(RX)
tsu(RX)
MSv65387V1
Slave mode transmitter/full duplex, 2.7 < VDD < 3.6 V 45/31(3)
NSS input
tc(SCK) th(NSS)
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
Figure 69. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tc(SCK)
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
High
NSS input
tc(SCK)
CPHA=0
SCK Output
CPOL=0
CPHA=0
CPOL=1
CPHA=1
SCK Output
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
MSB OUT BIT1 OUT LSB OUT
OUTPUT
tv(MO) th(MO)
Master TX - 50/33(3)
Master RX - 40
fCK I2S clock frequency MHz
Slave TX - 31/18.5(3)
Slave RX - 50
tv(WS) WS valid time Master mode - 5.5
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 8 -
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 7.5 -
1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X(output)
tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X(transmit)
Slot n Slot n+2
tsu(SD_MR) th(SD_MR)
SAI_SD_X(receive) Slot n
1/fSCK
SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X(input)
tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X(transmit)
Slot n Slot n+2
tsu(SD_SR) th(SD_SR)
SAI_SD_X(receive) Slot n
tMDC)
td(MDIO)
tsu(MDIO) th(MDIO)
CK
tOVD tOHD
D, CMD(output)
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
RPUI Embedded USB_DP pull-up value during idle - 900 1250 1600
RPUR Embedded USB_DP pull-up value during reception - 1400 2300 3200 Ω
1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics that are degraded in the 2.7 to
3.0 V voltage range.
2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is
already included in the embedded driver.
Clock
tSC tHC
Control In
(ULPI_DIR,ULPI_NXT)
tSD tHD
data In
(8-bit)
tDC tDC
Control out
(ULPI_STP)
tDD
data out
(8-bit)
tc(TCK)
TCK
tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO) toh(TDO)
TDO
tc(SWCLK)
SWCLK
tov(SWDIO) toh(SWDIO)
SWDIO
(transmit)
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
SEATING PLANE
C A2
0.25 mm
A
GAUGE PLANE
A1
c
ccc C
A1
D K
D1 L
D3 L1
48 33
32
49
E1
E3
E
64 17
PIN 1 1 16
IDENTIFICATION e
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
48 33
0.3
49 0.5 32
12.7
10.3
10.3
64 17
1.2
1 16
7.8
12.7
Product identification(1)
ES32H7B3
RIT6
Date code
Y WW
Revision code
Pin 1 indentifier
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples
in production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
SEATING PLANE
C
0.25 mm
A
A2
A1
GAUGE PLANE
c
ccc C
A1
L
K
D1
L1
D3
75 51
76 50
b
E1
E3
E
100 26
PIN 1 1 25
IDENTIFICATION
e
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.000 - - 0.4724 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc - - 0.080 - - 0.0031
75 51
76 50
0.5
0.3
16.7 14.3
100 26
1.2
1 25
12.3
16.7
Product identification(1)
ES32H7B3
Revision code
VIT6Q
Date code
Y WW
Pin 1
indentifier
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples
in production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
ddd C
SEATING
PLANE
A1
A
A2
A1 ball
index
B
D1 A1 ball area
identifier
e D
F
A
B
C
G
D
E
E1
E
F
G
e
H A
J
K
10 9 8 7 6 5 4 3 2 1
eee C A B
fff C
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.100 - - 0.0433
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
b 0.350 0.400 0.450 0.0138 0.0157 0.0177
D 7.850 8.000 8.150 0.3091 0.3150 0.3209
D1 - 7.200 - - 0.2835 -
E 7.850 8.000 8.150 0.3091 0.3150 0.3209
E1 - 7.200 - - 0.2835 -
e - 0.800 - - 0.0315 -
F - 0.400 - - 0.0157 -
G - 0.400 - - 0.0157 -
ddd - - 0.100 - - 0.0039
eee - - 0.150 - - 0.0059
fff - - 0.080 - - 0.0031
Dpad
Dsm
Table 130. TFBGA100 - Recommended PCB design rules (0.8 mm pitch BGA)
Pitch 0.8
Dpad 0.400 mm
0.470 mm typical
Dsm
(depends on the soldermask registration tolerance)
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm
Product identification(1)
ES32H7B3
Date code
Y WW
Ball 1
indentifier
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples
in production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
DETAIL A
e2 E E
e A
D D aaa
A2
(4x)
BOTTOM VIEW TOP VIEW
SIDE VIEW
A3 BUMP
b
FRONT VIEW
eee Z
b (132x) Z
ccc Z X Y
ddd Z SEATING PLANE
DETAIL A
ROTATED 90
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 0.58 - - 0.023
A1 - 0.17 - - 0.007 -
A2 - 0.38 - - 0.015 -
A3 - 0.025 - - 0.001 -
b 0.21 0.24 0.27 0.008 0.009 0.011
D 4.54 4.57 4.60 0.179 0.180 0.181
E 4.35 4.37 4.39 0.171 0.172 0.173
e - 0.35 - - 0.014 -
e1 - 3.85 - - 0.152 -
e2 - 3.50 - - 0.138 -
Dpad
Dsm
Pitch 0.35 mm
Dpad 0,200 mm
Dsm 0.200 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.250 mm
Stencil thickness 0.080 mm
Ball 1 indentifier
Product
identification(1)
E7B3QIY6Q
Revision code
Date code
Y WW R
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples
in production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
A A2
A1 c
0.25 mm
ccc C GAUGE PLANE
A1
D
L
D1 K
L1
D3
108 73
109
72
b
E3 E1 E
37
144
PIN 1 1 36
IDENTIFICATION
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740
D1 19.800 20.000 20.200 0.7795 0.7874 0.7953
D3 - 17.500 - - 0.689 -
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 - 17.500 - - 0.689 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1.35
108 73
109 0.35 72
0.5
19.9 17.85
22.6
144 37
1 36
19.9
22.6
Product identification(1)
ES32H7B3ZIT6U
Revision code
Date code
Y WW
Pin 1
indentifier
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples
in production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
C Seating plane
c
A1
A2
0.25 mm
gauge plane
k
A1
L
HD L1
PIN 1 D
IDENTIFICATION
ZE
E
HE
ZD
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 - 1.450 0.0531 - 0.0571
b 0.170 - 0.270 0.0067 - 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 23.900 - 24.100 0.9409 - 0.9488
HD 25.900 - 26.100 1.0197 - 1.0276
ZD - 1.250 - - 0.0492 -
E 23.900 - 24.100 0.9409 - 0.9488
HE 25.900 - 26.100 1.0197 - 1.0276
ZE - 1.250 - - 0.0492 -
e - 0.500 - - 0.0197 -
L1 - 1.000 - - 0.0394 -
k 0° - 7° 0° - 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. L dimension is measured at gauge plane at 0.25 mm above the seating plane.
1.2
176 133
1 0.5 132
0.3
26.7
21.8
44 89
45 88
1.2
21.8
26.7
Product identification(1)
ES32H7B3IIT6
Revision code
Date code
Y WW
Pin 1
indentifier
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples
in production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
Z Seating plane
ddd Z
A2
A1 A
D1 A1 ball A1 ball X
identifier index area D
e F
A
G
E1 E
e
Y
R
15 1
BOTTOM VIEW Øb (216 balls) TOP VIEW
Ø eee M Z Y X
Ø fff M Z
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A - - 1.200 - - 0.0472
A2 - 0.760 - - 0.0299 -
1. Values in inches are converted from mm and rounded to four decimal digits.
2. • The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or
other feature of package body or integral heat slug.
• A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact
shape of each corner is optional.
Dpad
Dsm
Pitch 0.8 mm
Dpad 0.400 mm
0.470 mm typ. (depends on the soldermask registration
Dsm
tolerance)
Stencil opening 0.400 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.120 mm
Product
identification(1) ES32H7B3
Revision code
NIH6
R
Date code
Y WW
Ball 1 indentifier
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples
in production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
eee M C A B
fff M C A1 corner index area
b (225 balls) D
14 12 10 8 6 4 2
15 13 11 9 7 5 3 1
A
B
C
D
e E
F
G
E1 H E
J
K
L
M
G N
P
R
F e
D1
BOTTOM VIEW TOP VIEW
Seating plane
C eee C
A2 A1 A
SIDE VIEW
1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heat slug.
2. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner.
Exact shape of each corner is optional
A1 0.150 - - 0.0059 - -
A2 - 0.760 - - 0.0299 -
e - 0.800 - - 0.0315 -
F - 0.900 - - 0.0354 -
G - 0.900 - - 0.0354 -
ddd - - 0.100 - - 0.0039
Dpad
Dsm
Table 138. TFBGA225 - Recommended PCB design rules (0.8 mm pitch BGA)
Pitch 0.8 mm
Dpad 0.400 mm
Dsm 0.470 mm typ.
Stencil opening 0.400 mm
Stencil thickness 0.100 mm
Product identification(1)
ES32H7B3
Date code
Y WW
Ball 1
indentifier
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples
in production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
Z Seating plane
A2 A4
ddd Z
A
A3 A1
b
SIDE VIEW A1 ball A1 ball
identifier index area X
E
E1
e F
A
F
D1 D
e
Y
N
13 1
A1 - - 0.110 - - 0.0043
A2 - 0.130 - - 0.0051 -
A4 - 0.320 - - 0.0126 -
1. Values in inches are converted from mm and rounded to four decimal digits.
2. • Ultra Thin profile: 0.50 < A ≤ 0.65 mm / Fine pitch: e < 1.00 mm pitch.
• The total profile height (dim A) is measured from the seating plane to the top of the component
• The maximum total package height is calculated by the following methodology:
• A Max = A1 Typ + A2 Typ + A4 Typ + √ (A1²+A2²+A4² tolerance values)
3. The typical balls diameters before mounting is 0.20 mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datum A and B. For each ball there
is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datum A and B as
defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball
there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis
perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained
entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones.
Dpad
Dsm
Table 140. UFBGA169 - recommended PCB design rules (0.5 mm pitch BGA)
Pitch 0.5 mm
Dpad 0.27 mm
0.35 mm typ. (depends on the soldermask registration
Dsm
tolerance)
Solder paste 0.27 mm aperture diameter
Ball 1
indentifier
Product identification(1)
32H7B3
AII6Q
Date code
Y WW Revision code
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples
in production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
Seating plane
C A4
ddd C
A
A2 A3 b A1
A1 ball A
A1 ball index E
identifier area
E1
e F
A
F
D1 D
e
B
R
15 1
Øb (176 + 25 balls)
BOTTOM VIEW TOP VIEW
Ø eee M C A B
Ø fff M C
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Ultra thin profile: 0.50 < A Max \u0001 0.65mm / Fine pitch: e < 1.00mm. The total profile height (Dim.A) is measured from
the seating plane “C” to the top of the component.
3. The tolerance of position that controls the location of the pattern of balls with respect to datum A and B. For each ball there
is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datum A and B as
defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
4. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball
there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis
perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained
entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones.
Dpad
Dsm
Table 142. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA)
Pitch 0.65 mm
Dpad 0.300 mm
0.400 mm typ. (depends on the soldermask registration
Dsm
tolerance)
Stencil opening 0.300 mm aperture diameter
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Product identification(1)
ES32H7B3
Date code
Ball 1 Y WW
indentifier
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples
in production. ST’s Quality department must be contacted prior to any decision to use these engineering
samples to run a qualification activity.
Where:
• TAmax is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax),
• PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.
PI/Omax represents the maximum power dissipation on output pins where:
PI/Omax = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.
8 Ordering information
Device family
STM32 = Arm-based 32-bit microcontroller
Product type
H = High performance
Device subfamily
7B3 = STM32H7B3 with cryptographic accelerator
Pin count
R = 64 pins
V = 100 pins/balls
Q = 132 balls
Z = 144 pins
A = 169 balls
I = 176 or 176 + 25 pins/balls
N = 216 balls
L = 225 balls
Package
T = LQFP ECOPACK2
K = UFBGA 0.65 mm pitch ECOPACK2
I = UFBGA 0.5 mm pitch ECOPACK2
H = TFBGA ECOPACK2
Y = WLCSP ECOPACK2
Temperature range
6 = Industrial temperature range, –40 to 85 °C
Option
Q = with SMPS
Blank = without SMPS
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (such as speed and package) or for further information on any aspect of this device,
contact your nearest ST sales office.
Revision history
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1 Arm® Cortex®-M7 with FPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Memory protection unit (MPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.2 Secure access mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.3 Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.4 SMPS step-down converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 Low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8 General-purpose input/outputs (GPIOs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11 Chrom-ART Accelerator (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Chrom-GRC™ (GFXMMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15 Cyclic redundancy check calculation unit (CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.16 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.17 Octo-SPI memory interface (OCTOSPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.18 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.19 Analog temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.20 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.21 VBAT operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.22 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
List of tables
Table 1. STM32H7B3xI features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3. Overview of low-power mode monitoring pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 7. STM32H7B3xI pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 8. Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 9. Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 10. Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 11. Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 12. Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 13. Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 14. Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 15. Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 16. Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 17. Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 18. Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 19. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 20. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 21. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 22. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 23. Maximum allowed clock frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 24. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 25. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 26. Characteristics of SMPS step-down converter external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 27. SMPS step-down converter characteristics for external usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 28. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 29. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 30. Embedded reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 31. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 32. USB regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 33. Inrush current and inrush electric charge characteristics for LDO and SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 34. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator
ON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 35. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory,
cache ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 36. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory,
cache OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 37. Typical consumption in Run mode and corresponding performance versus code position . . . . . . . . . . . . . . . . . 97
Table 38. Typical current consumption in Autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 39. Typical current consumption in Sleep mode, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 40. Typical current consumption in System Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 41. Typical current consumption RAM shutoff in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 42. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 43. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 44. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 45. Peripheral current consumption in Stop, Standby and VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 46. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 47. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 48. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 49. 4-50 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 50. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
List of figures
Figure 1. STM32H7B3xI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. STM32H7B3xI bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4. LQFP64 (STM32H7B3xI without SMPS) pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 5. LQFP100 (STM32H7B3xI with SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 6. LQFP100 (STM32H7B3xI without SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7. TFBGA100 (STM32H7B3xI with SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 8. TFBGA100 (STM32H7B3xI without SMPS) pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 9. WLCSP132 (STM32H7B3xI with SMPS) ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 10. LQFP144 (STM32H7B3xI with SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 11. LQFP144 (STM32H7B3xI without SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 12. LQFP176 (STM32H7B3xI with SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 13. LQFP176 (STM32H7B3xI without SMPS) pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 14. TFBGA216 (STM32H7B3xI without SMPS) ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 15. TFBGA225 (STM32H7B3xI with SMPS) ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 16. UFBGA169 (STM32H7B3xI with SMPS) ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. UFBGA176+25 (STM32H7B3xI with SMPS) ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18. UFBGA176+25 (STM32H7B3xI without SMPS) ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 19. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 21. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 22. Current consumption measurement scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 23. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 24. SMPS efficicency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode, TJ = 30 °C. . . . . . . . . 88
Figure 25. SMPS efficiency vs load current in Run, Sleep and Stop mode with SVOS3 MR mode, TJ = 130 °C . . . . . . . . 88
Figure 26. SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 30 °C . . 89
Figure 27. SMPS efficiency vs load current in Stop and DStop modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 130 °C . 89
Figure 28. SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 30 °C . 90
Figure 29. SMPS efficiency vs load current in Stop and DStop2 modes (SVOS3 LP mode, SVOS4, SVOS5), TJ = 130 °C. 90
Figure 30. High-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 31. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Figure 34. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Figure 35. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 36. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 37. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 38. Asynchronous multiplexed PSRAM/NOR read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 39. Synchronous multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 40. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 41. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 42. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 43. NAND controller waveforms for read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 44. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 45. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 46. NAND controller waveforms for common memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 47. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 48. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 49. OctoSPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 50. OctoSPI timing diagram - DTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 51. OctoSPI Hyperbus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 52. OctoSPI Hyperbus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143