STM8S903K3

STM8S903K3 STM8S903F3
16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, 1 Kbyte RAM, 640

bytes EEPROM,10-bit ADC, 2 timers, UART, SPI, I²C
- Switch-off peripheral clocks individually
• Permanently active, low consumption power-on

and power-down reset
Interrupt management
• Nested interrupt controller with 32 interrupts
LQFP32 7x7 UFQFPN32 5x5 SDIP32 400 mils
• Up to 28 external interrupts on 7 vectors
Timers
• Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
• 16-bit general purpose timer, with 3 CAPCOM
channels (IC, OC or PWM)
• 8-bit basic timer with 8-bit prescaler
TSSOP20 UFQFPN20 3x3 SO20W 300 mils
• Auto wakeup timer

Features • Window and independent watchdog timers
Core Communications interfaces
• 16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
• UART with clock output for synchronous
operation, Smartcard, IrDA, LIN master mode
• Extended instruction set • SPI interface up to 8 Mbit/s

Memories
• I C interface up to 400 Kbit/s
2
• Program memory: 8 Kbytes Flash; data retention Analog to digital converter (ADC)
20 years at 55 °C after 10 kcycles
• 10-bit, ±1 LSB ADC with up to 7 muxed channels
• Data memory: 640 bytes true data EEPROM;
endurance 300 kcycles
+ 1 internal channel, scan mode and analog
watchdog
• RAM: 1 Kbytes • Internal reference voltage measurement
Clock, reset and supply management I/Os
• 2.95 to 5.5 V operating voltage • Up to 28 I/Os on a 32-pin package including 21
• Flexible clock control, 4 master clock sources:
high sink outputs
• Highly
- Low power crystal resonator oscillator robust I/O design, immune against current
- External clock input

injection
- Internal, user-trimmable 16 MHz RC Development support

- Internal low power 128 kHz RC • Embedded single wire interface module (SWIM)
for fast on-chip programming and non intrusive
• Clock security system with clock monitor debugging
• Power management: Unique ID: 96-bit key including lot number

- Low power modes (wait, active-halt, halt)
June 2012 DocID15590 Rev 8 1/116
www.st.com
Contents STM8S903K3 STM8S903F3
Contents
1 Introduction ..............................................................................................................8
2 Description ...............................................................................................................9
3 Block diagram ........................................................................................................10
4 Product overview ...................................................................................................11
4.1 Central processing unit STM8 .....................................................................................11
4.2 Single wire interface module (SWIM) and debug module (DM) ..................................11
4.3 Interrupt controller .......................................................................................................12
4.4 Flash program and data EEPROM memory ................................................................12
4.5 Clock controller ............................................................................................................13
4.6 Power management ....................................................................................................14
4.7 Watchdog timers ..........................................................................................................14
4.8 Auto wakeup counter ...................................................................................................15
4.9 Beeper ........................................................................................................................15
4.10 TIM1 - 16-bit advanced control timer .........................................................................15
4.11 TIM5 - 16-bit general purpose timer ..........................................................................16
4.12 TIM6 - 8-bit basic timer ..............................................................................................16
4.13 Analog-to-digital converter (ADC1) ............................................................................16
4.14 Communication interfaces .........................................................................................17
4.14.1 UART1 ...............................................................................................17
4.14.2 SPI .....................................................................................................18
4.14.3 I²C ......................................................................................................18
5 Pinout and pin description ...................................................................................19
5.1 STM8S903F3 TSSOP20/SO20 pinout ........................................................................20
5.2 STM8S903F3 UFQFPN20 pinout ................................................................................21
5.3 TSSOP/SO/UFQFPN20 pin description ......................................................................22
5.4 STM8S903K3 UFQFPN32/LQFP32/SDIP32 pinout ....................................................23
5.5 UFQFPN/LQFP/SDIP32 pin description ......................................................................24
5.6 Alternate function remapping .......................................................................................26
6 Memory and register map .....................................................................................27
6.1 Memory map ................................................................................................................27
6.2 Register map ...............................................................................................................28
6.2.1 I/O port hardware register map ............................................................28
6.2.2 General hardware register map ...........................................................29
6.2.3 CPU/SWIM/debug module/interrupt controller registers .....................38
7 Interrupt vector mapping ......................................................................................41
8 Option bytes ...........................................................................................................43
8.1 STM8S903K3/F3 alternate function remapping bits ....................................................45
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STM8S903K3 STM8S903F3 Contents
9 Unique ID ................................................................................................................49
10 Electrical characteristics ....................................................................................50
10.1 Parameter conditions .................................................................................................50
10.1.1 Minimum and maximum values .........................................................50
10.1.2 Typical values .....................................................................................50
10.1.3 Typical curves ....................................................................................50
10.1.4 Loading capacitor ...............................................................................50
10.1.5 Pin input voltage .................................................................................50
10.2 Absolute maximum ratings ........................................................................................51
10.3 Operating conditions ..................................................................................................53
10.3.1 VCAP external capacitor ....................................................................54
10.3.2 Supply current characteristics ............................................................55
10.3.3 External clock sources and timing characteristics .............................65
10.3.4 Internal clock sources and timing characteristics ...............................67
10.3.5 Memory characteristics ......................................................................69
10.3.6 I/O port pin characteristics .................................................................70
10.3.7 Reset pin characteristics ....................................................................78
10.3.8 SPI serial peripheral interface ............................................................81
2
10.3.9 I C interface characteristics ...............................................................84
10.3.10 10-bit ADC characteristics ................................................................85
10.3.11 EMC characteristics .........................................................................89
11 Package information ............................................................................................92
11.1 32-pin LQFP package mechanical data .....................................................................92
11.2 32-lead UFQFPN package mechanical data .............................................................94
11.3 20-lead UFQFPN package mechanical data .............................................................95
11.4 UFQFPN recommended footprint ..............................................................................97
11.5 SDIP32 package mechanical data .............................................................................98
11.6 20-pin TSSOP package mechanical data ................................................................100
11.7 20-pin SO package mechanical data .......................................................................101
11.8 Thermal characteristics ............................................................................................102
11.8.1 Reference document ........................................................................103
11.8.2 Selecting the product temperature range .........................................103
12 Ordering information .........................................................................................104
12.1 STM8S903K3/F3 FASTROM microcontroller option list ..........................................104
13 STM8 development tools ..................................................................................110
13.1 Emulation and in-circuit debugging tools .................................................................110
13.2 Software tools ..........................................................................................................110
13.2.1 STM8 toolset ....................................................................................111
13.2.2 C and assembly toolchains ..............................................................111
13.3 Programming tools ..................................................................................................111
14 Revision history .................................................................................................112
DocID15590 Rev 8 3/116

List of tables STM8S903K3 STM8S903F3
List of tables
Table 1. STM8S903K3/F3 access line features .......................................................................................9
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ..................................14
Table 3. TIM timer features ....................................................................................................................16
Table 4. Legend/abbreviations for pinout tables ...................................................................................19
Table 5. TSSOP20/SO20/UFQFPN20 pin description ...........................................................................24
Table 6. UFQFPN32/LQFP32/SDIP32 pin description ...........................................................................24
Table 7. I/O port hardware register map ................................................................................................28
Table 8. General hardware register map ................................................................................................43
Table 9. CPU/SWIM/debug module/interrupt controller registers .........................................................54
Table 10. Interrupt mapping ...................................................................................................................41
Table 11. Option bytes .........................................................................................................................112
Table 12. Option byte description ...........................................................................................................43
Table 13. STM8S903K3 alternate function remapping bits [7:2] for 32-pin packages ...........................45
Table 14. STM8S903F3 alternate function remapping bits [7:2] for 20-pin packages ...........................46
Table 15. STM8S903K3 alternate function remapping bits [1:0] for 32-pin packages .........................102
Table 16. STM8S903F3 alternate function remapping bits [1:0] for 20-pin packages ...........................48
Table 17. Unique ID registers (96 bits) .................................................................................................112
Table 18. Voltage characteristics ...........................................................................................................51
Table 19. Current characteristics ...........................................................................................................51
Table 20. Thermal characteristics ..........................................................................................................52
Table 21. General operating conditions .................................................................................................53
Table 22. Operating conditions at power-up/power-down ......................................................................54
Table 23. Total current consumption with code execution in run mode at VDD = 5 V .............................55
Table 24. Total current consumption with code execution in run mode at VDD = 3.3 V ..........................56
Table 25. Total current consumption in wait mode at VDD = 5 V ............................................................57
Table 26. Total current consumption in wait mode at VDD = 3.3 V .........................................................57
Table 27. Total current consumption in active halt mode at VDD = 5 V ..................................................58
Table 28. Total current consumption in active halt mode at VDD = 3.3 V ...............................................59
Table 29. Total current consumption in halt mode at VDD = 5 V .............................................................60
Table 30. Total current consumption in halt mode at VDD = 3.3 V ..........................................................60
Table 31. Wakeup times .........................................................................................................................60
Table 32. Total current consumption and timing in forced reset state ....................................................61
Table 33. Peripheral current consumption .............................................................................................62
Table 34. HSE user external clock characteristics .................................................................................65
Table 35. HSE oscillator characteristics .................................................................................................65
Table 36. HSI oscillator characteristics ..................................................................................................67
Table 37. LSI oscillator characteristics ...................................................................................................68
Table 38. RAM and hardware registers ..................................................................................................69
Table 39. Flash program memory/data EEPROM memory ....................................................................69
Table 40. I/O static characteristics .........................................................................................................70
Table 41. Output driving current (standard ports) ..................................................................................72
Table 42. Output driving current (true open drain ports) ........................................................................73
Table 43. Output driving current (high sink ports) ..................................................................................73
Table 44. NRST pin characteristics ........................................................................................................78
Table 45. SPI characteristics ..................................................................................................................81
2
Table 46. I C characteristics ..................................................................................................................84
Table 47. ADC characteristics ................................................................................................................85
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STM8S903K3 STM8S903F3 List of tables
Table 48. ADC accuracy with RAIN < 10 k , VDD= 5 V .........................................................................86

Table 49. ADC accuracy with RAIN < 10 k RAIN, VDD = 3.3 V ..............................................................87
Table 50. EMS data ................................................................................................................................89
Table 51. EMI data .................................................................................................................................90
Table 52. ESD absolute maximum ratings .............................................................................................91
Table 53. Electrical sensitivities .............................................................................................................91
Table 54. 32-pin low profile quad flat package mechanical data .........................................................102
Table 55. 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data .............................94
Table 56. 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package mechanical data ....96
Table 57. 32-lead shrink plastic DIP (400 ml) package mechanical data ..............................................99
Table 58. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data .......................................................101
Table 59. 20-lead, plastic small outline (300 mils) mechanical data ....................................................101
Table 60. Thermal characteristics ........................................................................................................102
Table 61. Document revision history ....................................................................................................112
DocID15590 Rev 8 5/116

List of figures STM8S903K3 STM8S903F3
List of figures
Figure 1. Block diagram .........................................................................................................................10
Figure 2. Flash memory organization ....................................................................................................13
Figure 3. STM8S903F3 TSSOP20/SO20 pinout ...................................................................................23
Figure 4. STM8S903F3 UFQFPN20 pinout ...........................................................................................23
Figure 5. STM8S903K3 UFQFPN32/LQFP32 pinout ............................................................................23
Figure 6. STM8S903K3 SDIP32 pinout .................................................................................................24
Figure 7. Memory map ...........................................................................................................................27
Figure 8. Pin loading conditions .............................................................................................................50
Figure 9. Pin input voltage .....................................................................................................................51
Figure 10. fCPUmax versus VDD ..............................................................................................................54
Figure 11. External capacitor CEXT .......................................................................................................55
Figure 12. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz .............................................62
Figure 13. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V ....................................................63
Figure 14. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................63
Figure 15. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz ..............................................64
Figure 16. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V .....................................................64
Figure 17. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................64
Figure 18. HSE external clocksource .....................................................................................................65
Figure 19. HSE oscillator circuit diagram ...............................................................................................66
Figure 20. Typical HSI frequency variation vs VDD @ 4 temperatures ..................................................68
Figure 21. Typical LSI frequency variation vs VDD @ 4 temperatures ...................................................68
Figure 22. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................71
Figure 23. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................72
Figure 24. Typical pull-up current vs VDD @ 4 temperatures .................................................................72
Figure 25. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................74
Figure 26. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................74
Figure 27. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................75
Figure 28. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................75
Figure 29. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................76
Figure 30. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................76
Figure 31. Typ. VDD - VOH@ VDD = 5 V (standard ports) .......................................................................77
Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ...................................................................77
Figure 33. Typ. VDD - VOH@ VDD = 5 V (high sink ports) .......................................................................78
Figure 34. Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) ....................................................................78
Figure 35. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................79
Figure 36. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................80
Figure 37. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................80
Figure 38. Recommended reset pin protection ......................................................................................81
Figure 39. SPI timing diagram - slave mode and CPHA = 0 ..................................................................83
Figure 40. SPI timing diagram - slave mode and CPHA = 1 ..................................................................83
(1)
Figure 41. SPI timing diagram - master mode ...................................................................................84
2
Figure 42. Typical application with I C bus and timing diagram ............................................................85
Figure 43. ADC accuracy characteristics ...............................................................................................88
Figure 44. Typical application with ADC ................................................................................................88
Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................92
Figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................94
Figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................95
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STM8S903K3 STM8S903F3 List of figures
Figure 48. Recommended footprint for on-board emulation ..................................................................97

Figure 49. Recommended footprint without on-board emulation ...........................................................98
Figure 50. 32-lead shrink plastic DIP (400 ml) package ........................................................................98
Figure 51. 20-pin, 4.40 mm body, 0.65 mm pitch .................................................................................101
Figure 52. 20-lead, plastic small outline (300 mils) package ...............................................................101
Figure 53. STM8S903K3/F3 ordering information scheme ..................................................................104
DocID15590 Rev 8 7/116

Introduction STM8S903K3 STM8S903F3
1 Introduction
This datasheet contains the description of the device features, pinout, electrical characteristics,
mechanical data and ordering information.
• For complete information on the STM8S microcontroller memory, registers and peripherals,
please refer to the STM8S microcontroller family reference manual (RM0016).
• For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
• For information on the debug and SWIM (single wire interface module) refer to the STM8
SWIM communication protocol and debug module user manual (UM0470).
• For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
8/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Description
2 Description
The STM8S903K3 and STM8S903F3 8-bit microcontrollers offer 8 Kbytes Flash program
memory, plus integrated true data EEPROM. The STM8S microcontroller family reference
manual (RM0016) refers to devices in this family as low-density. They provide the following
benefits: performance, robustness, and reduced system cost.
Device performance and robustness are ensured by advanced core and peripherals made
in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs
with separate clock source, and a clock security system.
The system cost is reduced thanks to an integrated true data EEPROM for up to 300
kwrite/erase cycles and a high system integration level with internal clock oscillators, watchdog
and brown-out reset.
Full documentation is offered as well as a wide choice of development tools.
Table 1: STM8S903K3/F3 access line features

Device STM8S903K3 STM8S903F3
Pin count 32 20
(1) (2)
Max. number of GPIOs 28 16
(I/Os)
Ext. interrupt pins 28 16
Timer CAPCOM 7
channels
Timer complementary 3 2
outputs
A/D converter channels 7 5
High sink I/Os 21 12
Low density Flash 8K

program memory(bytes)
(3)
Data EEPROM (bytes) 640
RAM (bytes) 1K
2
Peripheral set Multipurpose timer (TIM1), SPI, I C, UART window WDG,
independent WDG, ADC, PWM timer (TIM5), 8-bit timer (TIM6)
(1)
Including 21 high sink outputs
(2)
Including 12 high sink outputs
(3)
No read-while-write (RWW) capability
DocID15590 Rev 8 9/116

Block diagram STM8S903K3 STM8S903F3
3 Block diagram
Figure 1: Block diagram
Reset block XTAL 1-16 MHz

Clock controller
Reset Reset
RC int. 16 MHz
Detector
POR BOR RC int. 128 kHz
Clock to peripherals and core
Window WDG
STM8 core
Independent WDG
Single wire Debug/SWIM 8 Kbytes

debug interf.
program
Flash
640 bytes
data EEPROM
Address and data bus
400 Kbit/s I 2C 1 Kbytes

RAM
8 Mbit/s SPI
Up to
4 CAPCOM
16-bit advanced control
LIN master UART1 channels
timer (TIM1)
SPI emul. + 3 complementar
outputs
16-bit general purpose
Up to
Timer (TIM5)
3 CAPCOM
channels
8-bit basic timer
Up to 7 ADC1 (TIM6)
channels
1/2/4 kHz Beeper AWU timer

beep
10/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Product overview
4 Product overview
The following section intends to give an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1 Central processing unit STM8

The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers

• Harvard architecture
• 3-stage pipeline
• 32-bit wide program memory bus - single cycle fetching for most instructions
• Xandandread-modify-write
Y 16-bit index registers - enabling indexed addressing modes with or without offset
type data manipulations
• 8-bit accumulator
• 24-bit program counter - 16-Mbyte linear memory space
• 16-bit stack pointer - access to a 64 K-level stack
• 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
• 20 addressing modes
• Indexed
space
indirect addressing mode for look-up tables located anywhere in the address
• Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
• 80 instructions with 2-byte average instruction size
• Standard data movement and logic/arithmetic functions
• 8-bit by 8-bit multiplication
• 16-bit by 8-bit and 16-bit by 16-bit division
• Bit manipulation
• Data transfer between stack and accumulator (push/pop) with direct stack access
• Data transfer using the X and Y registers or direct memory-to-memory transfers
4.2 Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-circuit
debugging and fast memory programming.
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Product overview STM8S903K3 STM8S903F3
SWIM
Single wire interface module for direct access to the debug module and memory programming.
The interface can be activated in all device operation modes. The maximum data transmission
speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator.
Beside memory and peripherals, also CPU operation can be monitored in real-time by means
of shadow registers.
• R/W to RAM and peripheral registers in real-time
• R/W access to all resources by stalling the CPU
• Breakpoints on all program-memory instructions (software breakpoints)
• Two advanced breakpoints, 23 predefined configurations
4.3 Interrupt controller
• Nested interrupts with three software priority levels
• 32 interrupt vectors with hardware priority
• Up to 28 external interrupts on 7 vectors including TLI
• Trap and reset interrupts
4.4 Flash program and data EEPROM memory
• 8 Kbytes of Flash program single voltage Flash memory
• 640 bytes true data EEPROM
• User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional
overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of memory
known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page
(64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
• Main program memory: Up to 8 Kbytes minus UBC
• User-specific boot code (UBC): Configurable up to 8 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
12/116 DocID15590 Rev 8

program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2: Flash memory organization
Data Data memory area ( 640 bytes)

EEPROM
memory
Option bytes
Programmable
UBC area area from 64
Remains write protected during IAP bytes(1 page)
up to 8 Kbytes
(in 1 page steps)
Low density
Flash program
memory
(8 Kbytes)
Program memory area
Write access possible for IAP
Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated,
any attempt to toggle its status triggers a global erase of the program and data memory. Even
if no protection can be considered as totally unbreakable, the feature provides a very high
level of protection for a general purpose microcontroller.
4.5 Clock controller

The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and ensures
clock robustness.
Features
• Clock prescaler: To get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
• Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock source
is ready. The design guarantees glitch-free switching.
• Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• Master
clock:
clock sources: Four different clock sources can be used to drive the master
- 1-16 MHz high-speed external crystal (HSE)

DocID15590 Rev 8 13/116
- Up to 16 MHz high-speed user-external clock (HSE user-ext)

- 16 MHz high-speed internal RC oscillator (HSI)
- 128 kHz low-speed internal RC (LSI)
• Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz
clock (HSI/8). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
• Clock security system (CSS): This feature can be enabled by software. If an HSE clock
failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an
interrupt can optionally be generated.
• Configurable
application.
main clock output (CCO): This outputs an external clock for use by the
Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Bit Peripheral Bit Peripheral Bit Peripheral Bit Peripheral
clock clock clock clock
PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved CKEN23 ADC
PCKEN16 IM5 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU
PCKEN15 Reserved PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved

2
PCKEN14 TIM6 PCKEN10 I C PCKEN24 Reserved PCKEN20 Reserved
4.6 Power management

For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
• Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
• Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake up
unit (AWU). The main voltage regulator is kept powered on, so current consumption is
higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup
is triggered by the internal AWU interrupt, external interrupt or reset.
• Active halt mode with regulator off: This mode is the same as active halt with regulator
on, except that the main voltage regulator is powered off, so the wake up time is slower.
• Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral
clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by
external event or reset.
4.7 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to
the applications.
14/116 DocID15590 Rev 8

Activation of the watchdog timers is controlled by option bytes or by software. Once activated,
the watchdogs cannot be disabled by the user program without performing a reset.
Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually generated
by external interferences or by unexpected logical conditions, which cause the application
program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to
64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8 Auto wakeup counter

• Used for auto wakeup from active halt mode
• Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
• LSI clock can be internally connected to TIM1 input capture channel 1 for calibration
4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit AFR7.
4.10 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
• 16-bit up, down and up/down autoreload counter with 16-bit prescaler
• Four independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse mode
output
DocID15590 Rev 8 15/116

• Synchronization
TIM5 or TIM6
module to control the timer with external signals or to synchronise with
• Break input to force the timer outputs into a defined state

• Three complementary outputs with adjustable dead time
• Encoder mode
• Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11 TIM5 - 16-bit general purpose timer
• 16-bit autoreload (AR) up-counter
• 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
• 3 individually configurable capture/compare channels
• PWM mode
• Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
• Synchronization
TIM1 or TIM6
module to control the timer with external signals or to synchronize with
4.12 TIM6 - 8-bit basic timer

• 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
• Clock source: CPU clock
• Interrupt source: 1 x overflow/update
• Synchronization
TIM1 or TIM5.
module to control the timer with external signals or to synchronize with
Table 3: TIM timer features

Timer Counter Prescaler Counting CAPCOM Complementary Ext. Timer
size mode channels outputs trigger synchronization/
(bits) chaining
TIM1 16 Any integer from 1 Up/down 4 3 Yes Yes
to 65536
TIM5 16 Any power of 2 Up 3 0 No

from 1 to 32768
TIM6 8 Any power of 2 Up 0 0 No

from 1 to 128
4.13 Analog-to-digital converter (ADC1)

The STM8S903K3 family products contain a 10-bit successive approximation A/D converter
(ADC1) with up to 7 external and 1 internal multiplexed input channels and the following main
features:
• Input voltage range: 0 to VDD
16/116 DocID15590 Rev 8

• Conversion time: 14 clock cycles

• Single and continuous and buffered continuous conversion modes
• Buffer size (n x 10 bits) where n = number of input channels
• Scan mode for single and continuous conversion of a sequence of channels
• Analog watchdog capability with programmable upper and lower thresholds
• Internal reference voltage on channel AIN7
• Analog watchdog interrupt
• External trigger input
• Trigger from TIM1 TRGO
• End of conversion (EOC) interrupt
Internal bandgap reference voltage
Channel AIN7 is internally connected to the internal bandgap reference voltage. The internal
bandgap reference is constant and can be used, for example, to monitor VDD. It is independent
of variations in VDD and ambient temperature TA.
4.14 Communication interfaces

The following communication interfaces are implemented:
• UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode, IrDA
mode, single wire mode, LIN2.1 master capability
• SPI : Full and half-duplex, 8 Mbit/s
• I²C: Up to 400 Kbit/s
4.14.1 UART1
Main features
• One Mbit/s full duplex SCI
• SPI emulation
• High precision baud rate generator
• Smartcard emulation
• IrDA SIR encoder decoder
• LIN master mode
• Single wire half duplex mode
Asynchronous communication (UART mode)
• Full duplex communication - NRZ standard format (mark/space)
• following
Programmable transmit and receive baud rates up to 1 Mbit/s (f /16) and capable of
CPU
any standard baud rate regardless of the input frequency
• Separate enable bits for transmitter and receiver
• TwoAddress
receiver wakeup modes:
- bit (MSB)
- Idle line (interrupt)
DocID15590 Rev 8 17/116

• Transmission error detection with interrupt generation

• Parity control
Synchronous communication
• Full duplex synchronous transfers
• SPI master operation
• 8-bit data communication
• Maximum speed: 1 Mbit/s at 16 MHz (f CPU/16)
LIN master mode

• Emission: Generates 13-bit synch break frame
• Reception: Detects 11-bit break frame
4.14.2 SPI
• Maximum speed: 8 Mbit/s (f /2) both for master and slave
MASTER
• Full duplex synchronous transfers

• Simplex synchronous transfers on two lines with a possible bidirectional data line
• Master or slave operation - selectable by hardware or software
• CRC calculation
• 1 byte Tx and Rx buffer
• Slave/master selection input pin
4.14.3 I²C
• I²C Clock
master features:
- generation
- Start and stop generation
• I²C Programmable
slave features:
- I2C address detection
- Stop bit detection
• Generation and detection of 7-bit/10-bit addressing and general call
• Supports different communication speeds:
- Standard speed (up to 100 kHz)
- Fast speed (up to 400 kHz)
18/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Pinout and pin description
5 Pinout and pin description

Table 4: Legend/abbreviations for pinout tables
Type I= Input, O = Output, S = Power supply
Level Input CM = CMOS
Output HS = High sink
Output speed
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control Input float = floating, wpu = weak pull-up

configuration
Output T = True open drain, OD = Open drain, PP =
Push pull
Reset state
Bold X (pin state after internal reset release).
Unless otherwise specified, the pin state is the same during the reset
phase and after the internal reset release.
DocID15590 Rev 8 19/116

Pinout and pin description STM8S903K3 STM8S903F3
5.1 STM8S903F3 TSSOP20/SO20 pinout

Figure 3: STM8S903F3 TSSOP20/SO20 pinout
TIM5_CH1[UART1_CK]BEEP/PD4(HS) 1 20 PD3(HS)/AIN4/TIM5_CH2/ADC_ETR
AIN5/UART1_TX/PD5(HS) 2 19 PD2(HS)/AIN3[TIM5_CH3]
AIN6/UART1_RX/PD6(HS) 3 18 PD1(HS)/SWIM
NRST 4 17 PC7(HS)/SPI_MISO[TIM1_CH2]
OSCIN/PA1 5 16 PC6(HS)/SPI_MOSI[TIM1_CH1]
OSCOUT/PA2 6 15 PC5(HS)/SPI_SCK[TIM5_CH1]
VSS 7 14 PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
VCAP 8 13 PC3(HS)/TIM1_CH3[TLI][TIM1_CH1N]
VDD 9 12 PB4(T)/I2C_SCL[ADC_ETR]
[SPI_NSS]/TIM5_CH3/PA3(HS) 10 11 PB5(T)/[TIM1_BKIN]I2C_SDA
1. (HS) high sink capability.

2. (T) true open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (if the same alternate function is shown twice, it
indicates an exclusive choice not a duplication of the function).
20/116 DocID15590 Rev 8

5.2 STM8S903F3 UFQFPN20 pinout

Figure 4: STM8S903F3 UFQFPN20 pinout
PD4 (HS)/BEEP / TIM5_CH1/UART1_CK

PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR
PD2(HS)/AIN3/[TIM5_CH3]
PD5(HS)/AIN5/UART1_TX
PD6(HS)/AIN6/UART1_RX
20 19 18 17 16
NRST 1 15
PD1(HS)/SWIM
OSCIN/PA1 2 14 PC7(HS)/SPI_MISO/[TIM1_CH2]
OSCOUT/PA2 3 13 PC6(HS)/SPI_MOSI/[TIM1_CH1]
VSS 4 12 PC5 (HS)/SPI_SCK/[TIM5_CH1]
VCAP 5 11 PC4(HS)/TIM1_CH4/CLK_CCO/AIN2/[TIM1_CH2N]
6 7 8 9 10
[UART1_TX]/[SPI_NSS]/TIM5_CH3/(HS) PA3
VDD
[ADC_ETR]/I2C_SCL/(T)PB4
[TIM1_BKIN]/I2C_SDA/(T)PB5
[TIM1_CH1N]/[TLI]/TIM1_CH3/(HS)PC3

DocID15590 Rev 8 21/116

5.3 Pin description TSSOP20_SO20_UFQFPN20
Table 5: TSSOP20/SO20/UFQFPN20 pin description

Input Output Main Default alternate function Alternate function after remap
TSSOP UFQFPN Pin name Type
function [option bit]
SO20 20 floating wpu Ext. High Speed OD PP (after
(1)
interrupt sink reset)
4 1 NRST I/O X Reset
(2)
5 2 PA1/ OSCIN I/O X X X O1 X X Port Resonator/ crystal in
A1
6 3 PA2/ OSCOUT I/O X X X O1 X X Port Resonator/ crystal out

A2
7 4 VSS S Digital ground
8 5 VCAP S 1.8 V regulator capacitor
9 6 VDD S Digital power supply
10 7 PA3/ TIM5_CH3 [SPI_NSS] I/O X X X HS O3 X X Port Timer 52 channel 3 SPI master/ slave select [AFR1]/
[UART1_TX] A3 UART1 data transmit [AFR1:0]
(3) 2
11 8 PB5/ I2C_SDA [TIM1_BKIN] I/O X X O1 T Port I C data Timer 1 - break input [AFR4]
B5
(3) 2
12 9 PB4/ I2C_SCL [ADC_ETR] I/O X X O1 T Port I C clock ADC external trigger [AFR4]
B4
13 10 PC3/ I/O X X X HS O3 X X Port Timer 1 - channel 3 Top level interrupt [AFR3] Timer
TIM1_CH3/TLI/[TIM1_CH1N ] C3 1 inverted channel 1 [AFR7]
14 11 PC4/ TIM1_CH4/ I/O X X X HS O3 X X Port Timer 1 - channel 4 Analog input 2 [AFR2]Timer 1

CLK_CCO/AIN2/[TIM1_CH2N] C4 /configurable clock output inverted channel 2 [AFR7]
15 12 PC5/SPI_SCK [TIM5_CH1] I/O X X X HS O3 X X Port SPI clock Timer 5 channel 1 [AFR0]

C5
16 13 PC6/ SPI_MOSI [TIM1_CH1] I/O X X X HS O3 X X Port PI master out/slave in Timer 1 channel 1 [AFR0]
C6
17 14 PC7/ SPI_MISO [TIM1_CH2] I/O X X X HS O3 X X Port SPI master in/ slave out Timer 1 channel 2[AFR0]
C7
(4)
18 15 PD1/ SWIM I/O X X X HS O4 X X Port SWIM data interface
D1
19 16 PD2/AIN3/ [TIM5_CH3] I/O X X X HS O3 X X Port Analog input 3 [AFR2] Timer 52

D2 - channel 3 [AFR1]
20 17 PD3/ AIN4/ TIM5_CH2/ I/O X X X HS O3 X X Port Analog input 4 Timer 52 -

ADC_ETR D3 channel 2/ADC external
trigger
1 18 PD4/ TIM5_CH1/ BEEP I/O X X X HS O3 X X Port Timer 5 - channel 1/BEEP UART clock [AFR2]
[UART1_CK] D4 output
2 19 PD5/ AIN5/ UART1_TX I/O X X X HS O3 X X Port Analog input 5/ UART1

D5 data transmit
3 20 PD6/ AIN6/ UART1_RX I/O X X X HS O3 X X Port Analog input 6/ UART1

D6 data receive
(1)
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see section
"Absolute maximum ratings").
(2)
When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
(3)
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented)
(4)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
22/116 DocID15590 Rev 8

5.4 STM8S903K3 UFQFPN32/LQFP32/SDIP32 pinout

Figure 5: STM8S903K3 UFQFPN32/LQFP32 pinout
PD4 (HS)/BEEP/TIM5_CH1 [UART1_CK]

PD3 (HS)/AIN4/TIM5_CH2/ADC_ETR
PD0 (HS)/ TIM1_BKIN [CLK_CCO]

PD2 (HS)[AIN3] [TIM5_CH3]
PD7 (HS)/TLI [ TIM1_CH4]
PD6 (HS)/AIN6/UART1_RX
PD5 (HS)/AIN5/UART1_TX
PD1 (HS)/SWIM
32 31 30 29 28 27 26 25
NRST 1 24 PC7 (HS)/SPI_MISO [TIM1_CH2]
OSCIN/PA1 2 23 PC6 (HS)/SPI_MOSI [TIM1_CH1]
OSCOUT/PA2 3 22 PC5 (HS)/SPI_SCK [TIM5_CH1]
VSS 4 21 PC4 (HS)/TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N]
VCAP 5 20 PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
VDD 6 19 PC2 (HS)/TIM1_CH2 [TIM1_CH3N]
[UART1_TX] [SPI_NSS] TIM5_CH3/(HS) PA3 7 18 PC1 (HS)/TIM1_CH1/UART1_CK [TIM1_CH2N]
[UART1_RX] PF4 8 17 PE5/SPI_NSS [TIM1_CH1N]
9 10 11 12 13 14 15 16
PB7
PB6
[TIM1_BKIN] I C_SDA/(T) PB5
[ADC_ETR] I C_SCL/(T) PB4
TIM1_ETR/AIN3/(HS) PB3
TIM1_CH3N/AIN2/(HS) PB2
2
2

DocID15590 Rev 8 23/116

Figure 6: STM8S903K3 SDIP32 pinout
AIN4/TIM5_CH2/ADC_ETR/PD3(HS) 1 32 PD2(HS)[AIN3][TIM5_CH3]
TIM5_CH1[UART1_CK]BEEP/PD4(HS) 2 31 PD1(HS)/SWIM
AIN5/UART1_TX/PD5(HS) 3 30 PD0(HS)/TIM1_BKIN[CLK_CCO]
AIN6/UART1_RX/PD6(HS) 4 29 PC7(HS)/SPI_MISO[TIM1_CH2]
[TIM1_CH4]TLI/PD7(HS) 5 28 PC6(HS)/SPI_MOSI[TIM1_CH1]
NRST 6 27 PC5(HS)/SPI_SCK[TIM5_CH1]
OSCIN/PA1 7 26 PC4(HS)/TIM1_CH4/CLK_CCO[AIN2][TIM1_CH2N]
OSCOUT/PA2 8 25 PC3(HS)/TIM1_CH3[TLI][TIM1_CH1N]
VSS 9 24 PC2(HS)/TIM1_CH2[TIM1_CH3N]
VCAP 10 23 PC1(HS)/TIM1_CH1/UART1_CK[TIM1_CH2N]
VDD 11 22 PE5/SPI_NSS[TIM1_CH1N]
[UART1_TX][SPI_NSS]/TIM5_CH3/PA3(HS) 12 21 PB0(HS)/AIN0/TIM1_CH1N
[UART1_RX]/PF4 13 20 PB1(HS)/AIN1/TIM1_CH2N
PB7 14 19 PB2(HS)/AIN2/TIM1_CH3N
PB6 15 18 PB3(HS)[AIN3]TIM1_ETR
[TIM1_BKIN]I2C_SDA/PB5(T) 16 17 PB4(T)/I2C_SCL[ADC_ETR]

5.5 Pin description
Table 6: UFQFPN32/LQFP32/SDIP32 pin description

SDIP UFQFPN/ Pin name Type
32 LQFP32 floating wpu Ext. High Speed OD PP (after
(1)
6 1 NRST I/O X Reset
(2)
7 2 PA1/ OSCIN I/O X X X O1 X X Port Resonator/ crystal in
A1
8 3 PA2/ OSCOUT I/O X X X O1 X X Port Resonator/ crystal out

A2
9 4 VSS S Digital ground
10 5 VCAP S 1.8 V regulator capacitor
11 6 VDD S Digital power supply
12 7 PA3/ TIM5_CH3 [SPI_NSS] I/O X X X HS O3 X X Port Timer 52 channel 3 SPI master/ slave select
[UART1_TX] A3 [AFR1]/ UART1 data transmit
[AFR1:0]
13 8 PF4 [UART1_RX] I/O X X O1 X X Port UART1 data receive [AFR1:0]

F4
14 9 PB7 I/O X X X O1 X X Port

B7
24/116 DocID15590 Rev 8

SDIP UFQFPN/ Pin name Type
32 LQFP32 floating wpu Ext. High Speed OD PP (after
(1)
15 10 PB6 I/O X X X O1 X X Port

B6
(3) 2
16 11 PB5/ I2C_SDA [TIM1_BKIN] I/O X X O1 T Port I C data Timer 1 - break input [AFR4]
B5
(3) 2
17 12 PB4/ I2C_SCL [ADC_ETR] I/O X X O1 T Port I C clock ADC external trigger [AFR4]
B4
18 13 PB3/ AIN3/TIM1_ETR I/O X X X HS O3 X X Port Analog input 3/ Timer 1

B3 external trigger
19 14 PB2/ AIN2/ TIM1_CH3N I/O X X X HS O3 X X Port Analog input 2/ Timer 1 -

B2 inverted channel 3


22 17 PE5/ SPI_NSS [TIM1_CH1N] I/O X X X HS O3 X X Port SPI master/ slave select Timer 1 - inverted channel 1
E5 [AFR1:0]
23 18 PC1/ TIM1_CH1/ UART1_CK I/O X X X HS O3 X X Port Timer 1 - channel 1 Timer 1 - inverted channel 2
[TIM1_CH2N] C1 UART1 clock [AFR1:0]
24 19 PC2/ TIM1_CH2 [TIM1_CH3N] I/O X X X HS O3 X X Port Timer 1 - channel 2 Timer 1 - inverted channel 3
C2 [AFR1:0]
25 20 PC3/ TIM1_CH3/TLI/[TIM1_CH1N I/O X X X HS O3 X X Port Timer 1 - channel 3 Top level interrupt [AFR3] Timer
] C3 1 inverted channel 1 [AFR7]
26 21 PC4/ TIM1_CH4/ I/O X X X HS O3 X X Port Timer 1 - channel 4 Analog input 2 [AFR2]Timer 1

CLK_CCO/AIN2/[TIM1_CH2N] C4 /configurable clock output inverted channel 2 [AFR7]
27 22 PC5/SPI_SCK [TIM5_CH1] I/O X X X HS O3 X X Port SPI clock Timer 5 channel 1 [AFR0]

C5
28 23 PC6/ SPI_MOSI [TIM1_CH1] I/O X X X HS O3 X X Port PI master out/slave in Timer 1 channel 1 [AFR0]
C6
29 24 PC7/ SPI_MISO [TIM1_CH2] I/O X X X HS O3 X X Port SPI master in/ slave out Timer 1 channel 2[AFR0]
C7
30 25 PD0/ TIM1_BKIN [CLK_CCO] I/O X X X HS O3 X X Port Timer 1 - break input Configurable clock output
D0 [AFR5]
(4)
31 26 PD1/ SWIM I/O X X X HS O4 X X Port SWIM data interface
D1
32 27 PD2/AIN3/ [TIM5_CH3] I/O X X X HS O3 X X Port Analog input 3 [AFR2] Timer 52

D2 - channel 3 [AFR1]
1 28 PD3/ AIN4/ TIM5_CH2/ ADC_ETR I/O X X X HS O3 X X Port Analog input 4 Timer 52 -

D3 channel 2/ADC external
trigger
2 29 PD4/ TIM5_CH1/ BEEP I/O X X X HS O3 X X Port Timer 5 - channel 1/BEEP UART clock [AFR2]
[UART1_CK] D4 output
3 30 PD5/ AIN5/ UART1_TX I/O X X X HS O3 X X Port Analog input 5/ UART1

D5 data transmit
4 31 PD6/ AIN6/ UART1_RX I/O X X X HS O3 X X Port Analog input 6/ UART1

D6 data receive
5 32 PD7/ TLI [TIM1_CH4] I/O X X X HS O3 X X Port Top level interrupt Timer 1 - channel 4 [AFR6]
D7
(1)
I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the total driven current must respect the absolute maximum ratings ( see section
"Absolute maximum ratings").
(2)
When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and cannot be used for waking up the device. In this mode, the output state of PA1 is not driven. It is
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
(3)
In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are not implemented)
(4)
The PD1 pin is in input pull-up during the reset phase and after internal reset release.
DocID15590 Rev 8 25/116

5.6 Alternate function remapping

As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. When the remapping option is active, the default alternate function is no
longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO
section of the family reference manual, RM0016).
26/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Memory and register map
6 Memory and register map

6.1 Memory map
Figure 7: Memory map
0x00 0000
RAM
(1 Kbyte)
513 bytes stack

0x00 03FF
0x00 0800
Reserved
0x00 3FFF
0x00 4000
640 bytes data EEPROM
0x00 427F
0x00 4280
Reserved
0x00 47FF
0x00 4800 Option bytes
0x00 480A
0x00 480B Reserved
0x00 4864
0x00 4865
0x00 4870
Unique ID
0x00 4871
Reserved
0x00 4FFF
0x00 5000
GPIO and periph. reg.
0x00 57FF
0x00 5800
Reserved
0x00 7EFF
0x00 7F00
CPU/SWIM/debug/ITC
registers
0x00 7FFF
0x00 8000
32 interrupt vectors
0x00 807F
0x00 8080 Flash program memory
0x00 9FFF
(8 Kbytes)
0x00 A000
Reserved
DocID15590 Rev 8 27/116

Memory and register map STM8S903K3 STM8S903F3
6.2 Register map
6.2.1 I/O port hardware register map
Table 7: I/O port hardware register map

Reset
Address Block Register label Register name
status
0x00 5000 PA_ODR Port A data output latch register 0x00
(1)
0x00 5001 PA_IDR Port A input pin value register 0xXX
0x00 5002 Port A PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x00
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005 PB_ODR Port B data output latch register 0x00

(1)
0x00 5006 PB_IDR Port B input pin value register 0xXX
0x00 5007 Port B PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A PC_ODR Port C data output latch register 0x00

(1)
0x00 500B PB_IDR Port C input pin value register 0xXX
0x00 500C Port C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F PD_ODR Port D data output latch register 0x00

(1)
0x00 5010 PD_IDR Port D input pin value register 0xXX
0x00 5011 Port D PD_DDR Port D data direction register 0x00
0x00 5012 PD_CR1 Port D control register 1 0x02
0x00 5013 PD_CR2 Port D control register 2 0x00
0x00 5014 PE_ODR Port E data output latch register 0x00

(1)
0x00 5015 PE_IDR Port E input pin value register 0xXX
Port E
0x00 5016 PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
28/116 DocID15590 Rev 8

Reset
Address Block Register label Register name
status
0x00 5018 Port E PE_CR2 Port E control register 2 0x00
0x00 5019 PF_ODR Port F data output latch register 0x00

(1)
0x00 501A PF_IDR Port F input pin value register 0xXX
0x00 501B Port F PF_DDR Port F data direction register 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00
(1)
Depends on the external circuitry.
6.2.2 General hardware register map
Table 8: General hardware register map

Address Block Register label Register name Reset
status
Reserved area (60 bytes)
0x00 501E to
0x00 5059
Flash FLASH_CR1 Flash control register 1 0x00

0x00 505A
FLASH_CR2 Flash control register 2 0x00

0x00 505B
FLASH_NCR2 Flash complementary control register 2 0xFF

0x00 505C
FLASH _FPR Flash protection register 0x00

0x00 505D
FLASH _NFPR Flash complementary protection register 0xFF

0x00 505E
FLASH _IAPSR Flash in-application programming status 0x00

0x00 505F
register

0x00 5060 to
0x00 5061
Flash FLASH _PUKR Flash program memory unprotection 0x00

0x00 5062
register
Reserved area (1 byte)

0x00 5063
DocID15590 Rev 8 29/116


status
Flash FLASH _DUKR Data EEPROM unprotection register 0x00
0x00 5064

0x00 5065 to
0x00 509F
ITC EXTI_CR1 External interrupt control register 1 0x00

0x00 50A0
EXTI_CR2 External interrupt control register 2 0x00

0x00 50A1

0x00 50A2 to
0x00 50B2
RST RST_SR Reset status register (1)

0x00 50B3 0xXX

0x00 50B4 to
0x00 50BF
CLK CLK_ICKR Internal clock control register 0x01

0x00 50C0
CLK_ECKR External clock control register 0x00

0x00 50C1
Reserved area (1 byte)

0x00 50C2
CLK CLK_CMSR Clock master status register 0xE1

0x00 50C3
CLK_SWR Clock master switch register 0xE1

0x00 50C4
CLK_SWCR Clock switch control register 0xXX

0x00 50C5
CLK_CKDIVR Clock divider register 0x18

0x00 50C6
CLK_PCKENR1 Peripheral clock gating register 1 0xFF

0x00 50C7
CLK_CSSR Clock security system register 0x00

0x00 50C8
CLK_CCOR Configurable clock control register 0x00

0x00 50C9
CLK_PCKENR2 Peripheral clock gating register 2 0xFF

0x00 50CA
30/116 DocID15590 Rev 8


status
CLK_HSITRIMR HSI clock calibration trimming register 0x00
0x00 50CC
CLK_SWIMCCR SWIM clock control register 0bXXXX

0x00 50CD
XXX0

0x00 50CE to
0x00 50D0
WWDG WWDG_CR WWDG control register 0x7F

0x00 50D1
WWDG_WR WWDR window register 0x7F

0x00 50D2

0x00 50D3 to
00 50DF
IWDG IWDG_KR IWDG key register (2)

0x00 50E0 0xXX
IWDG_PR IWDG prescaler register 0x00

0x00 50E1
IWDG_RLR IWDG reload register 0xFF

0x00 50E2

0x00 50E3 to
0x00 50EF
AWU AWU_CSR1 AWU control/status register 1 0x00

0x00 50F0
AWU_APR AWU asynchronous prescaler buffer 0x3F

0x00 50F1
register
AWU_TBR AWU timebase selection register 0x00

0x00 50F2
BEEP BEEP_CSR BEEP control/status register 0x1F

0x00 50F3

0x00 50F4 to
0x00 50FF
SPI SPI_CR1 SPI control register 1 0x00

0x00 5200
SPI_CR2 SPI control register 2 0x00

0x00 5201
DocID15590 Rev 8 31/116


status
SPI_ICR SPI interrupt control register 0x00
0x00 5202
SPI_SR SPI status register 0x02

0x00 5203
SPI_DR SPI data register 0x00

0x00 5204
SPI_CRCPR SPI CRC polynomial register 0x07

0x00 5205
SPI_RXCRCR SPI Rx CRC register 0xFF

0x00 5206
SPI_TXCRCR SPI Tx CRC register 0xFF

0x00 5207

0x00 5208 to
0x00 520F
2 2
I C I2C_CR1 I C control register 1 0x00
0x00 5210
2
I2C_CR2 I C control register 2 0x00
0x00 5211
2
I2C_FREQR I C frequency register 0x00
0x00 5212
2
I2C_OARL I C Own address register low 0x00
0x00 5213
2
I2C_OARH I C Own address register high 0x00
0x00 5214
Reserved
0x00 5215
2
I2C_DR I C data register 0x00
0x00 5216
2
I2C_SR1 I C status register 1 0x00
0x00 5217
2
I2C_SR2 I C status register 2 0x00
0x00 5218
2
I2C_SR3 I C status register 3 0x0x
0x00 5219
2
I2C_ITR I C interrupt control register 0x00
0x00 521A
2
I2C_CCRL I C Clock control register low 0x00
0x00 521B
32/116 DocID15590 Rev 8


status
2
I2C_CCRH I C Clock control register high 0x00
0x00 521C
2
I2C_TRISER I C TRISE register 0x02
0x00 521D
2
I2C_PECR I C packet error checking register 0x00
0x00 521E

0x00 521F to
0x00 522F
UART1 UART1_SR UART1 status register 0xC0

0x00 5230
UART1_DR UART1 data register 0xXX

0x00 5231
UART1_BRR1 UART1 baud rate register 1 0x00

0x00 5232
UART1_BRR2 UART1 baud rate register 2 0x00

0x00 5233
UART1_CR1 UART1 control register 1 0x00

0x00 5234

0x00 5235

0x00 5236

0x00 5237

0x00 5238
UART1_GTR UART1 guard time register 0x00

0x00 5239
UART1_PSCR UART1 precaler register 0x00

0x00 523A

0x00 523B to
0x00 523F
TIM1 TIM1_CR1 TIM1 control register 1 0x00

0x00 5250
TIM1_CR2 TIM1 control register 2 0x00

0x00 5251
DocID15590 Rev 8 33/116


status
TIM1_SMCR TIM1 slave mode control register 0x00
0x00 5252
TIM1_ETR TIM1 external trigger register 0x00

0x00 5253
TIM1_IER TIM1 interrupt enable register 0x00

0x00 5254
TIM1_SR1 TIM1 status register 1 0x00

0x00 5255

0x00 5256
TIM1_EGR TIM1 event generation register 0x00

0x00 5257
TIM1_CCMR1 TIM1 capture/compare mode register 1 0x00

0x00 5258

0x00 5259

0x00 525A

0x00 525B
TIM1_CCER1 0x00
0x00 525C TIM1 capture/compare enable register 1
TIM1_CCER2 0x00
0x00 525D TIM1 capture/compare enable register 2
TIM1_CNTRH TIM1 counter high 0x00

0x00 525E
TIM1_CNTRL TIM1 counter low 0x00

0x00 525F
TIM1_PSCRH TIM1 prescaler register high 0x00

0x00 5260
TIM1_PSCRL TIM1 prescaler register low 0x00

0x00 5261
TIM1_ARRH TIM1 auto-reload register high 0xFF

0x00 5262
TIM1_ARRL TIM1 auto-reload register low 0xFF

0x00 5263
TIM1_RCR TIM1 repetition counter register 0x00

0x00 5264
TIM1_CCR1H TIM1 capture/compare register 1 high 0x00

0x00 5265
34/116 DocID15590 Rev 8


status
TIM1_CCR1L TIM1 capture/compare register 1 low 0x00
0x00 5266

0x00 5267

0x00 5268

0x00 5269

0x00 526A

0x00 526B

0x00 526C
TIM1_BKR TIM1 break register 0x00

0x00 526D
TIM1_DTR TIM1 dead-time register 0x00

0x00 526E
TIM1_OISR TIM1 output idle state register 0x00

0x00 526F

0x00 5270 to
0x00 52FF

0x00 5300

0x00 5301

0x00 5302

0x00 5303

0x00 5304

0x00 5305

0x00 5306

0x00 5307
DocID15590 Rev 8 35/116


status
0x00 5308

0x00 5309
TIM5_CCER1 0x00
0x00 530A TIM5 capture/compare enable register 1
TIM5_CCER2 0x00
0x00 530B TIM5 capture/compare enable register 2
TIM5_CNTRH TIM5 counter high 0x00

00 530C0x
TIM5_CNTRL TIM5 counter low 0x00

0x00 530D
TIM5_PSCR TIM5 prescaler register 0x00

0x00 530E
TIM5_ARRH TIM5 auto-reload register high 0xFF

0x00 530F
TIM5_ARRL TIM5 auto-reload register low 0xFF

0x00 5310

0x00 5311

0x00 5312

0x00 5313

0x00 5314

0x00 5315

0x00 5316

0x00 5317 to
0x00 533F

0x00 5340

0x00 5341

0x00 5342
36/116 DocID15590 Rev 8


status
0x00 5343
TIM6_SR TIM6 status register 0x00

0x00 5344

0x00 5345
TIM6_CNTR TIM6 counter 0x00

0x00 5346
TIM6_PSCR TIM6 prescaler register 0x00

0x00 5347
TIM6_ARR TIM6 auto-reload register 0xFF

0x00 5348

0x00 5349 to
0x00 53DF
ADC1 ADC _DBxR ADC data buffer registers 0x00

0x00 53E0 to
0x00 53F3

0x00 53F4 to
0x00 53FF
ADC1 ADC _CSR ADC control/status register 0x00

0x00 5400
cont’d
ADC_CR1 ADC configuration register 1 0x00
0x00 5401

0x00 5402

0x00 5403
ADC_DRH ADC data register high 0xXX

0x00 5404
ADC_DRL ADC data register low 0xXX

0x00 5405
ADC_TDRH ADC Schmitt trigger disable register high 0x00

0x00 5406
ADC_TDRL ADC Schmitt trigger disable register low 0x00

0x00 5407
ADC_HTRH ADC high threshold register high 0x03

0x00 5408
DocID15590 Rev 8 37/116


status
ADC_HTRL ADC high threshold register low 0xFF
0x00 5409
ADC_LTRH ADC low threshold register high 0x00

0x00 540A
ADC_LTRL ADC low threshold register low 0x00

0x00 540B
ADC_AWSRH ADC analog watchdog status register high 0x00

0x00 540C
ADC_AWSRL ADC analog watchdog status register low 0x00

0x00 540D
ADC _AWCRH ADC analog watchdog control register high 0x00

0x00 540E
ADC_AWCRL ADC analog watchdog control register low 0x00

0x00 540F

0x00 5410 to
0x00 57FF
(1)
Depends on the previous reset source.
(2)
Write only register.
6.2.3 CPU/SWIM/debug module/interrupt controller registers
Table 9: CPU/SWIM/debug module/interrupt controller registers

Address Block Register label Register name Reset status
0x00 7F00 A Accumulator 0x00
0x00 7F01 PCE Program counter extended 0x00
0x00 7F02 PCH Program counter high 0x00
0x00 7F03 PCL Program counter low 0x00

(1)
0x00 7F04 CPU XH X index register high 0x00
0x00 7F05 XL X index register low 0x00
0x00 7F06 YH Y index register high 0x00
0x00 7F07 YL Y index register low 0x00
0x00 7F08 SPH Stack pointer high 0x03
38/116 DocID15590 Rev 8


0x00 7F09 SPL Stack pointer low 0xFF
0x00 7F0A CCR Condition code register 0x28
0x00 7F0B to
0x00 7F5F
0x00 7F60 CPU CFG_GCR Global configuration register 0x00
0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF

ITC
0x00 7F78 to
0x00 7F79
0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00
0x00 7F81 to
0x00 7F8F
0x00 7F90 DM_BK1RE DM breakpoint 1 register extended 0xFF

byte
0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF
0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF
0x00 7F93 DM_BK2RE DM breakpoint 2 register extended 0xFF

byte
0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF

DM
0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF
0x00 7F96 DM_CR1 DM debug module control register 1 0x00
0x00 7F97 DM_CR2 DM debug module control register 2 0x00
0x00 7F98 DM_CSR1 DM debug module control/status 0x10

register 1
0x00 7F99 DM_CSR2 DM debug module control/status 0x00

register 2
DocID15590 Rev 8 39/116


0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B to Reserved area (5 bytes)

0x00 7F9F
(1)
Accessible by debug module only
40/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Interrupt vector mapping
7 Interrupt vector mapping

Table 10: Interrupt mapping
IRQ Source Description Wakeup from Wakeup from Vector address
no. block halt mode active-halt
mode
RESET Reset Yes Yes 0x00 8000
TRAP Software interrupt - - 0x00 8004
0 TLI External top level interrupt - - 0x00 8008
1 AWU Auto wake up from halt - Yes 0x00 800C
2 CLK Clock controller - - 0x00 8010

(1) (1)
3 EXTI0 Port A external interrupts Yes Yes 0x00 8014
4 EXTI1 Port B external interrupts Yes Yes 0x00 8018
5 EXTI2 Port C external interrupts Yes Yes 0x00 801C
6 EXTI3 Port D external interrupts Yes Yes 0x00 8020
7 EXTI4 Port E external interrupts Yes Yes 0x00 8024
8 EXTI5 Port F 0x00 8028
9 Reserved - - 0x00 802C
10 SPI End of transfer Yes Yes 0x00 8030
11 TIM1 TIM1 update/ overflow/ underflow/ - - 0x00 8034

trigger/ break
12 TIM1 TIM1 capture/ compare - - 0x00 8038
13 TIM5 TIM5 update/ overflow/ trigger - - 0x00 803C
14 TIM5 TIM5 capture/ compare - - 0x00 8040
15 Reserved - - 0x00 8044
16 Reserved - - 0x00 8048
17 UART1 Tx complete - - 0x00 804C
18 UART1 Receive register DATA FULL - - 0x00 8050

2 2
19 I C I C interrupt Yes Yes 0x00 8054
20 Reserved - - 0x00 8058
21 Reserved - - 0x00 805C
DocID15590 Rev 8 41/116

Interrupt vector mapping STM8S903K3 STM8S903F3
IRQ Source Description Wakeup from Wakeup from Vector address

no. block halt mode active-halt
mode
22 ADC1 ADC1 end of conversion/ analog - - 0x00 8060
watchdog interrupt
23 TIM6 TIM6 update/ overflow/ trigger - - 0x00 8064
24 Flash EOP/ WR_PG_DIS - - 0x00 8068
Reserved 0x00 806C to

0x00 807C
(1)
Except PA1
42/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Option bytes
8 Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in the table below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP
option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 11: Option bytes
Addr. Option Option Option bits Factory

name byte no. default
7 6 5 4 3 2 1 0 setting
0x4800 Read-out OPT0 ROP [7:0] 0x00

protection
(ROP)
0x4801 User boot OPT1 UBC [7:0] 0x00

code(UBC)
0x4802 NOPT1 NUBC [7:0] 0xFF
0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00
function
0x4804 remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF
(AFR)
0x4805h Miscell. OPT3 Reserved HSI LSI_ EN IWDG WWDG WWDG 0x00
option TRIM _HW _HW _HALT
0x4806 NOPT3 Reserved NHSI NLSI_ NIWDG NWWDG NWW 0xFF

TRIM EN _HW _HW G_HALT
0x4807 Clock OPT4 Reserved EXT CLK CKAWU PRS C1 PRS C0 0x00
option SEL
0x4808 NOPT4 Reserved NEXT NCKA NPRSC1 NPR 0xFF

CLK WUSEL SC0
0x4809 HSE clock OPT5 HSECNT [7:0] 0x00

startup
0x480A NOPT5 NHSECNT [7:0] 0xFF
Table 12: Option byte description
Option byte no. Description
OPT0
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
DocID15590 Rev 8 43/116

Option bytes STM8S903K3 STM8S903F3
Note: Refer to the family reference manual (RM0016) section on

Flash/EEPROM memory readout protection for details.
OPT1
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 defined as UBC, memory write-protected
0x02: Pages 0 to 1 defined as UBC, memory write-protected.
Page 0 and 1 contain the interrupt vectors.
...
0x7F: Pages 0 to 126 defined as UBC, memory write-protected
Other values: Pages 0 to 127 defined as UBC, memory
write-protected
Note: Refer to the family reference manual (RM0016) section on
Flash write protection for more details.
OPT2
AFR[7:0]
Refer to following section for alternate function remapping decriptions
of bits [7:2] and [1:0] respectively.
OPT3
HSITRIM:High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN:Low speed internal clock enable

0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog

0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation

0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
44/116 DocID15590 Rev 8

0: No reset generated on halt if WWDG active

1: Reset generated on halt if WWDG active
OPT4
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL:Auto wake-up unit/clock

0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler

0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
OPT5
HSECNT[7:0]:HSE crystal oscillator stabilization time
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
8.1 STM8S903K3/F3 alternate function remapping bits
Table 13: STM8S903K3 alternate function remapping bits [7:2] for 32-pin packages
(1)
OPT2
AFR7 Alternate function remapping option 7
(2)
0: AFR7 remapping option inactive: Default alternate functions .
1: Port C3 alternate function = TIM1_CH1N; port C4 alternate
function = TIM1_CH2N.
(2)
0: AFR6 remapping option inactive: Default alternate function .
1: Port D7 alternate function = TIM1_CH4.
DocID15590 Rev 8 45/116

(1)

(2)
1: Port D0 alternate function = CLK_CCO.
(2)
1: Port B4 alternate function = ADC_ETR; port B5 alternate function
= TIM1_BKIN.
(2)
1: Port C3 alternate function = TLI.
(2)
1: Port C4 alternate function = AIN2; port D2 alternate function =
AIN3; port D4 alternate function = UART1_CK.
(1)
Do not use more than one remapping option in the same port.
(2)
Refer to pinout description.
Table 14: STM8S903F3 alternate function remapping bits [7:2] for 20-pin packages
(1)
OPT2
(2)
0: AFR7 remapping option inactive: Default alternate functions
1: Port C3 alternate function = TIM1_CH1N; port C4 alternate
function = TIM1_CH2N.
Reserved.
Reserved.
(2)
1: Port B4 alternate function = ADC_ETR; port B5 alternate function
= TIM1_BKIN.
46/116 DocID15590 Rev 8

(1)
(2)
1: Port C3 alternate function = TLI.
Reserved.
(1)
(2)
Table 15: STM8S903K3 alternate function remapping bits [1:0] for 32-pin packages
AFR1 option bit AFR0 option bit I/O port Alternate function mapping
value value
0 0 AFR1 and AFR0 remapping options inactive:

(1)
Default alternate functions
0 1 PC5 TIM5_CH1
PC6 TIM1_CH1
PC7 TIM1_CH2
1 0 PA3
SPI_NSS
PD2 TIM5_CH3
PD2 TIM5_CH3
PC5 TIM5_CH1
PC6 TIM1_CH1
PC7 TIM1_CH2
1 1 PC2 TIM1_CH3N
PC1 TIM1_CH2N
PE5 TIM1_CH1N
PA3 UART1_TX
PF4 UART1_RX
(1)
DocID15590 Rev 8 47/116

Table 16: STM8S903F3 alternate function remapping bits [1:0] for 20-pin packages
AFR1 option bit AFR0 option bit I/O port Alternate function mapping
value value
0 0 AFR1 and AFR0 remapping options inactive:

(1)
Default alternate functions
0 1 PC5 TIM5_CH1
PC6 TIM1_CH1
PC7 TIM1_CH2
1 0 PA3
SPI_NSS
PD2 TIM5_CH3
PD2 TIM5_CH3
PC5 TIM5_CH1
PC6 TIM1_CH1
PC7 TIM1_CH2
1 1 PC2 —
PC1 —
PE5 TIM1_CH1N
PA3 UART1_TX
PF4 UART1_RX
(1)
48/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Unique ID
9 Unique ID
The devices feature a 96-bit unique device identifier which provides a reference number that
is unique for any device and in any context. The 96 bits of the identifier can never be altered
by the user.
The unique device identifier can be read in single bytes and may then be concatenated using
a custom algorithm.
The unique device identifier is ideally suited:
• For use as serial numbers
• For use as security keys to increase the code security in the program memory while using
and combining this unique ID with software cryptograhic primitives and protocols before
programming the internal memory.
• To activate secure boot processes
Table 17: Unique ID registers (96 bits)
Address Content Unique ID bits
description 7 6 5 4 3 2 1 0
0x4865 X co-ordinate U_ID[7:0]
0x4866 on the wafer U_ID[15:8]
0x4867 Y co-ordinate U_ID[23:16]
0x4868 on the wafer U_ID[31:24]
0x4869 Wafer number U_ID[39:32]
0x486A U_ID[47:40]
0x486B U_ID[55:48]
0x486C U_ID[63:56]
0x486D Lot number U_ID[71:64]
0x486E U_ID[79:72]
0x486F U_ID[87:80]
0x4870 U_ID[95:88]
DocID15590 Rev 8 49/116

Electrical characteristics STM8S903K3 STM8S903F3
10 Electrical characteristics
10.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
10.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on characterization,
the minimum and maximum values refer to sample tests and represent the mean value plus
or minus three times the standard deviation (mean ± 3 ).
10.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 ).
10.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not
tested.
10.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in the following figure.
Figure 8: Pin loading conditions
STM8 pin
50 pF
10.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in the following figure.
50/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Electrical characteristics
Figure 9: Pin input voltage
STM8 pin
VIN
10.2 Absolute maximum ratings

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 18: Voltage characteristics

Symbol Ratings Min Max Unit
VDDx - VSS (1) -0.3 6.5
Supply voltage
VIN (2) VSS - 0.3 6.5 V

Input voltage on true open drain pins
(2) VSS - 0.3 VDD + 0.3

Input voltage on any other pin
|VDDx - VDD| - 50
Variations between different power pins
|VSSx - VSS| mV
Variations between all the different ground - 50
pins
VESD See "Absolute

Electrostatic discharge voltage
maximum ratings
(electrical sensitivity)"
(1)
All power (VDD) and ground (VSS) pins must always be connected to the external power supply
(2)
IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
Table 19: Current characteristics

Symbol Ratings (1) Unit
Max
IVDD (2) 100 mA

Total current into VDD power lines (source)
DocID15590 Rev 8 51/116

Symbol Ratings (1) Unit

Max
(2) 80
IVSS Total current out of VSS ground lines (sink)
IIO 20
Output current sunk by any I/O and control pin
Output current source by any I/Os and control pin - 20
(3) (4)
IINJ(PIN) ±4
Injected current on NRST pin
Injected current on OSCIN pin ±4
(5) ±4
Injected current on any other pin
(3)
I INJ(PIN) (5) ± 20
Total injected current (sum of all I/O and control pins)
(1)
Data based on characterization results, not tested in production.
(2)
All power (VDD) and ground (VSS) pins must always be connected to the external supply.
(3)
IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain
pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
(4)
ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on
another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins
which may potentially inject negative current. Any positive injection current within the limits specified for
IINJ(PIN) and IINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.
(5)
When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum
of the positive and negative injected currents (instantaneous values). These results are based on
characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 20: Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150
°C
TJ Maximum junction temperature 150
52/116 DocID15590 Rev 8

10.3 Operating conditions
Table 21: General operating conditions

Symbol Parameter Conditions Min Max Unit
fCPU Internal CPU clock frequency 0 16 MHz
VDD Standard operating voltage 2.95 5.5 V

(1)
VCAP CEXT: capacitance of external
470 3300 nF
capacitor
(2)
ESR of external capacitor at 1 MHz - 0.3
ESL of external capacitor - 15 nH

(3)
PD Power dissipation at TA = 85 °C TSSOP20 - 182 mW
for suffix 6
SO20W - 1000
UFQFPN20 - 198
LQFP32 - 333
UFQFPN32 - 526
SDIP32 - 333
Power dissipation at TA = 125 TSSOP20 - 45

°C for suffix 3
SO20W - 250
UFQFPN20 - 49
LQFP32 - 83
UFQFPN32 - 132
SDIP32 - 83
TA Ambient temperature for 6 suffix Maximum power dissipation -40 85 °C

version
Ambient temperature for 3 suffix Maximum power dissipation -40 125

version
TJ Junction temperature range 6 suffix version -40 105
3 suffix version -40 130
(1)
Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
dependency on temperature, DC bias and frequency in addition to other factors. The parameter maximum
value must be respected for the full application range.
(2)
This frequency of 1 MHz as a condition for VCAP parameters is given by design of internal regulator
DocID15590 Rev 8 53/116

(3)
To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/ JA (see Thermal characteristics).
Figure 10: fCPUmax versus VDD
f
CPU (MHz)
Functionality
not 16
guaranteed
in this area 12 Functionality guaranteed
@TA-40 to 125 °C
8
4
0
2.95 4.0 5.0 5.5
Supply voltage
Table 22: Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Typ Max Unit
tVDD VDD rise time rate 2 ∞ µs/V
(1)
VDD fall time rate 2 ∞
tTEMP Reset release delay VDD rising 1.7 ms
VIT+ Power-on reset 2.6 2.7 2.85 V

threshold
VIT- Brown-out reset 2.5 2.65 2.8

threshold
VHYS(BOR) Brown-out reset 70 mV

hysteresis
(1)
Reset is always generated after a tTEMP delay. The application must ensure that VDD is
still above the minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed.
10.3.1 VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit
the series inductance to less than 15 nH.
54/116 DocID15590 Rev 8

Figure 11: External capacitor CEXT
C
ESR ESL
Rleak
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
10.3.2 Supply current characteristics

The current consumption is measured as described in Pin input voltage.
10.3.2.1 Total current consumption in run mode

The MCU is placed under the following conditions:
• All I/O pins in input mode with a static value at VDD or VSS (no load)
• All peripherals are disabled (clock stopped by peripheral clock gating registers) except if
explicitly mentioned.
Subject to general operating conditions for VDD and TA.
Table 23: Total current consumption with code execution in run mode at VDD = 5 V
Symbol Parameter Conditions Typ (1) Unit

Max
HSE crystal osc. (16 MHz) 2.3 -

fCPU = fMASTER =
HSE user ext. clock (16 MHz) 2 2.35
16 MHz
HSI RC osc. (16 MHz) 1.7 2
Supply current fCPU = fMASTER/128 = HSE user ext. clock (16 MHz) 0.86 -
in run mode, 125 kHz
HSI RC osc. (16 MHz) 0.7 0.87
code executed
from RAM fCPU = fMASTER/128 =
IDD(RUN) HSI RC osc. (16 MHz/8) 0.46 0.58 mA
15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.41 0.55
128 kHz
Supply current HSE crystal osc. (16 MHz) 4.5 -

in run mode, fCPU = fMASTER =
HSE user ext. clock (16 MHz) 4.3 4.75
code executed 16 MHz
from Flash HSI RC osc. (16 MHz) 3.7 4.5
Supply current fCPU = fMASTER =

(2)
in run mode, HSI RC osc. (16 MHz/8) 0.84 1.05
IDD(RUN) 2 MHz mA
code executed
from Flash
DocID15590 Rev 8 55/116


Max
fCPU = fMASTER/128 =
HSI RC osc. (16 MHz) 0.72 0.9
125 kHz
HSI RC osc. (16 MHz/8) 0.46 0.58
15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.42 0.57
128 kHz
(1)
(2)
Default clock configuration measured with all peripherals off.
Table 24: Total current consumption with code execution in run mode at VDD = 3.3 V
Max

fCPU = fMASTER =
HSE user ext. clock (16 MHz) 2 2.3
16 MHz
HSI RC osc. (16 MHz) 1.5 2
Supply current fCPU = fMASTER/ HSE user ext. clock (16 MHz) 0.81 -
in run mode, 128 = 125 kHz
HSI RC osc. (16 MHz) 0.7 0.87
code executed
from RAM fCPU = fMASTER/
HSI RC osc. (16 MHz/8) 0.46 0.58
128 = 15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.41 0.55
128 kHz
IDD(RUN) mA
HSE crystal osc. (16 MHz) 4 -
fCPU = fMASTER =
16 MHz
HSI RC osc. (16 MHz) 3.7 4.5
Supply current f
CPU = fMASTER = (2)
in run mode, HSI RC osc. (16 MHz/8) 0.84 1.05
code executed 2 MHz
from Flash
fCPU = fMASTER/
HSI RC osc. (16 MHz) 0.72 0.9
128 = 125 kHz
fCPU = fMASTER/ HSI RC osc. (16 MHz/8) 0.46 0.58
56/116 DocID15590 Rev 8


Max
128 = 15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.42 0.57
128 kHz
(1)
(2)
10.3.2.2 Total current consumption in wait mode

Table 25: Total current consumption in wait mode at VDD = 5 V
Max

fCPU = fMASTER =
16 MHz
HSI RC osc. (16 MHz) 0.89 1.1
Supply HSI RC osc. (16 MHz) 0.7 0.88
IDD(WFI) current in 125 kHz mA
wait mode
(2)
HSI RC osc. (16 MHz/8) 0.45 0.57
15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.4 0.54
128 kHz
(1)
(2)
Table 26: Total current consumption in wait mode at VDD = 3.3 V

Max
HSE crystal osc.

1.1 -
fCPU = fMASTER = (16 MHz)
Supply current
IDD(WFI) mA
in wait mode 16 MHz HSE user ext. clock
1.1 1.3
(16 MHz)
DocID15590 Rev 8 57/116


Max
HSI RC osc.
0.89 1.1
(16 MHz)
fCPU = fMASTER/ 128 = HSI RC osc.

0.7 0.88
125 kHz (16 MHz)
fCPU = fMASTER/ 128 = HSI RC osc.

(2) 0.45 0.57
15.625 kHz (16 MHz/8)
fCPU = fMASTER= LSI RC osc.

0.4 0.54
128 kHz (128 kHz)
(1)
(2)
10.3.2.3 Total current consumption in active halt mode

Table 27: Total current consumption in active halt mode at VDD = 5 V
Conditions Max Max
Main at 85 at 125
Symbol Parameter voltage (3) Typ °C °C Unit
Flash mode Clock source
regulator (1) (1)
(2)
(MVR)
Supply current HSE crystal osc.
IDD(AH) in active halt On Operating mode 1030 - -
mode (16 MHz)
Supply current LSI RC osc.

IDD(AH) in active halt On Operating mode 200 260 300
mode (128 kHz)
Supply current HSE crystal osc.

IDD(AH) in active halt On Power-down mode 970 - - A
mode (16 MHz)

IDD(AH) in active halt On Power-down mode 150 200 230
mode (128 kHz)

IDD(AH) in active halt Off Operating mode 66 85 110
mode (128 kHz)
58/116 DocID15590 Rev 8

Conditions Max Max

Main at 85 at 125
Symbol Parameter voltage (3) Typ °C °C Unit
Flash mode Clock source
regulator (1) (1)
(2)
(MVR)
IDD(AH) in active halt Power-down mode 10 20 40
mode (128 kHz)
(1)
Data based on characterization results, not tested in production
(2)
Configured by the REGAH bit in the CLK_ICKR register.
(3)
Configured by the AHALT bit in the FLASH_CR1 register.
Table 28: Total current consumption in active halt mode at VDD = 3.3 V
Conditions
Max at Max at
Main
Symbol Parameter Typ 85 °C 125 °C Unit
voltage (3)
Flash mode Clock source (1) (1)
regulator
(2)
(MVR)
Supply current HSE crystal
IDD(AH) in active halt On Operating mode osc. (16 MHz) 550 - - A
mode
LSI RC osc.
IDD(AH) Supply current Operating mode 200 260 290
(128 kHz)
in active halt
mode HSE crystal
IDD(AH) On 970 - -
osc. (16 MHz)
Power-down
mode LSI RC osc. A
IDD(AH) 150 200 230
(128 kHz)
Supply current
IDD(AH) in active halt Operating mode LSI RC osc. 66 80 105
mode
Off Power-down (128 kHz)
IDD(AH) 10 18 35
mode
(1)
(2)
(3)
DocID15590 Rev 8 59/116

10.3.2.4 Total current consumption in halt mode

Table 29: Total current consumption in halt mode at VDD = 5 V
Symbol Parameter Conditions Typ Max at Max at Unit

(1) (1)
85 °C 125 °C
Supply current in Flash in operating mode, HSI

63 75 105
halt mode clock after wakeup
IDD(H) A
Flash in power-down mode, HSI
6.0 20 55
clock after wakeup
(1)
Table 30: Total current consumption in halt mode at VDD = 3.3 V
Symbol Parameter Conditions Typ Max at Max at Unit

(1) (1)
85 °C 125 °C
Supply current in Flash in operating mode, HSI

60 75 100
halt mode clock after wakeup
IDD(H) A
Flash in power-down mode, HSI
4.5 17 30
clock after wakeup
(1)
10.3.2.5 Low power mode wakeup times

Table 31: Wakeup times

Max
Wakeup time from See

0 to 16 MHz - (2)
note
tWU(WFI) wait mode to run
(3)
mode fCPU = fMASTER = 16 MHz 0.56 -
Wakeup time active MVR voltage HSI

Flash in operating
(6) (6)
halt mode to run regulator (5)
(after 1 2 s
(3) (4)
mode
mode on wakeup)
tWU(AH)
Wakeup time active MVR voltage Flash in HSI
halt mode to run regulator power-down (after (6)
3 -
(3) (4) (5)
mode on mode wakeup)
60/116 DocID15590 Rev 8


Max
Wakeup time active MVR voltage HSI

Flash in operating
halt mode to run regulator (after (6)
(5) 48 -
(3) (4)
mode
mode off wakeup)
Wakeup time active MVR voltage Flash in HSI

halt mode to run regulator power-down (after (6)
50 -
(3) (4) (5)
mode off mode wakeup)
(5)
Wakeup time from Flash in operating mode 52 -
tWU(H) halt mode to run
(5)
(3) Flash in power-down mode 54 -
mode
(1)
Data guaranteed by design, not tested in production.
(2)
tWU(WFI) = 2 x 1/fmaster + 6 x 1/fCPU.
(3)
Measured from interrupt event to interrupt vector fetch.
(4)
(5)
(6)
Plus 1 LSI clock depending on synchronization.
10.3.2.6 Total current consumption and timing in forced reset state

Table 32: Total current consumption and timing in forced reset state
Max
IDD(R) Supply current in reset VDD = 5 V 400 -

(2) A
state VDD = 3.3 V 300 -
tRESETBL Reset pin release to

- 150 s
vector fetch
(1)
(2)
Characterized with all I/Os tied to VSS.
10.3.2.7 Current consumption of on-chip peripherals

DocID15590 Rev 8 61/116

HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V
Table 33: Peripheral current consumption

Symbol Parameter Typ. Unit
(1)
IDD(TIM1) TIM1 supply current 210 µA
(1)
IDD(TIM5) TIM5 supply current 130
(1)
IDD(TIM6) TIM6 timer supply current 50
(2)
IDD(UART1) UART1 supply current 120
(2)
IDD(SPI) SPI supply current 45
2 2 (2)
IDD(I C) I C supply current 65
(3)
IDD(ADC1) ADC1 supply current when converting 1000
(1)
Data based on a differential IDD measurement between reset configuration and timer
counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in
production.
(2)
Data based on a differential IDD measurement between the on-chip peripheral when kept
under reset and not clocked and the on-chip peripheral when clocked and not kept under
reset. No I/O pads toggling. Not tested in production.
(3)
Data based on a differential IDD measurement between reset configuration and continuous
A/D conversions. Not tested in production.
10.3.2.8 Current consumption curves

The following figures show typical current consumption measured with code executing in
RAM.
Figure 12: Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz
62/116 DocID15590 Rev 8

Figure 13: Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V
Figure 14: Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz
DocID15590 Rev 8 63/116

Figure 15: Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz
Figure 16: Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V
Figure 17: Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz
64/116 DocID15590 Rev 8

10.3.3 External clock sources and timing characteristics
HSE user external clock

Table 34: HSE user external clock characteristics

fHSE_ext User external clock source
0 16 MHz
frequency
(1)
VHSEH OSCIN input pin high level
0.7 x VDD VDD + 0.3 V
voltage
(1)
V
VHSEL OSCIN input pin low level
VSS 0.3 x VDD
voltage
ILEAK_HSE OSCIN input leakage current VSS < VIN < VDD -1 +1 A
(1)
Figure 18: HSE external clocksource
V
HSEH
V HSEL
fHSE
External clock
source
OSCIN
STM8
HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 35: HSE oscillator characteristics

fHSE External high speed
1 - 16 MHz
oscillator frequency
DocID15590 Rev 8 65/116


RF Feedback resistor - 220 - kΩ
(1)
C Recommended load
(2) - - 20 pF
capacitance
IDD(HSE) HSE oscillator power

C = 20 pF, 6 (startup)
consumption - - (3)
fOSC = 16 MHz 1.6 (stabilized)
mA
C = 10 pF, 6 (startup)
- - (3)
fOSC =16 MHz 1.2 (stabilized)
gm Oscillator
5 - - mA/V
transconductance
(4)
tSU(HSE) Startup time VDD is stabilized - 1 - ms
(1)
C is approximately equivalent to 2 x crystal Cload.
(2)
The oscillator selection can be optimized in terms of supply current using a high quality resonator with
small Rm value. Refer to crystal manufacturer for more details
(3)
(4)
tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16
MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Figure 19: HSE oscillator circuit diagram
Rm
f HSE to core
CO
Lm RF
CL1
Cm OSCIN gm
Resonator
Consumption
control
Resonator
CL2 OSCOUT
STM8
HSE oscillator critical g m equation

2 2
gmcrit= (2 × × fHSE) × Rm(2Co + C)
66/116 DocID15590 Rev 8

Rm: Notional resistance (see crystal specification)

Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1= CL2 = C: Grounded external capacitance
gm >> gmcrit
10.3.4 Internal clock sources and timing characteristics

High speed internal RC oscillator (HSI)
Table 36: HSI oscillator characteristics

fHSI Frequency - 16 - MHz
ACCHSI Accuracy of HSI User-trimmed with

oscillator CLK_HSITRIMR register for
(3)
- - 1.0
given VDD and TA
(1)
conditions
(2)
Accuracy of HSI VDD = 5 V, TA = 25°C -1 - 1
%
oscillator (factory
VDD = 5 V,
calibrated) -2.0 - 2.0
25 °C ≤ TA ≤ 85 °C
2.95 ≤ VDD≤ 5.5 V, (2) (2)

-3.0 - 3.0
-40 °C ≤ TA ≤ 125 °C
tsu(HSI) HSI oscillator

wakeup time (3)
- - 1.0 s
including
calibration
IDD(HSI) HSI oscillator

(2)
power - 170 250 A
consumption
(1)
Refer to application note.
(2)
(3)
Guaranteed by design, not tested in production.
DocID15590 Rev 8 67/116

Figure 20: Typical HSI frequency variation vs VDD @ 4 temperatures
Low speed internal RC oscillator (LSI)

Table 37: LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit
fLSI Frequency 110 128 150 kHz
tsu(LSI) LSI oscillator wake-up time - - 7 s
IDD(LSI) LSI oscillator power consumption - 5 - A
Figure 21: Typical LSI frequency variation vs VDD @ 4 temperatures
68/116 DocID15590 Rev 8

10.3.5 Memory characteristics
RAM and hardware registers
Table 38: RAM and hardware registers

Symbol Parameter Conditions Min Unit
(1) (2)
VRM Data retention mode Halt mode (or reset) VIT-max V
(1)
Minimum supply voltage without losing data stored in RAM (in halt mode or under reset)
or in hardware registers (only in halt mode). Guaranteed by design, not tested in production.
(2)
Refer to the Operating conditions section for the value of VIT-max
Flash program memory/data EEPROM memory
Table 39: Flash program memory/data EEPROM memory

Symbol Parameter Conditions (1) Typ Max Unit
Min
VDD Operating voltage

(all modes, execution/ fCPU ≤ 16 MHz 2.95 - 5.5 V
write/erase)
tprog Standard programming time

(including erase) for
- 6 6.6
byte/word/block (1 byte/
4 bytes/64 bytes)
ms
Fast programming time for
- 3 3.33
1 block (64 bytes)
terase Erase time for 1 block

- 3 3.33
(64 bytes)
(2)
NRW Erase/write cycles
TA = +85 °C 10 k - -
(program memory)
cycles
Erase/write cycles
(2) TA = +125 °C 300 k 1M -
(data memory)
tRET Data retention (program

and data memory) after 10k
TRET = 55°C 20 - - years
erase/write cycles at
TA = +55 °C
DocID15590 Rev 8 69/116

Symbol Parameter Conditions (1) Typ Max Unit

Min
Data retention (data

memory) after 300k
TRET = 85°C 1 - -
erase/write cycles at
TA = +125 °C
IDD Supply current (Flash

programming or erasing - 2 - mA
for 1 to 128 bytes)
(1)
(2)
The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes
even when a write/erase operation addresses a single byte.
10.3.6 I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All unused
pins must be kept at a fixed voltage: using the output mode of the I/O for example or an
external pull-up or pull-down resistor.
Table 40: I/O static characteristics

VIL VDD = 5 V 0.3 x
Input low level voltage -0.3 V -
VDD
V
VIH 0.7 x VDD +
Input high level voltage -
VDD 0.3
Vhys (1)
- 700 - mV
Hysteresis
Rpu VDD = 5 V, VIN = VSS 30 55 80 k

Pull-up resistor
tR, tF Fast I/Os

Rise and fall time - - 35
(3)
Load = 50 pF
(10 % - 90 %)
Standard and high sink
ns
I/Os - - 125
(3)
Load = 50 pF
(3)
Fast I/Os - - 20
70/116 DocID15590 Rev 8


Load = 20 pF
Standard and high sink

I/Os - - 50
(3)
Load = 20 pF
Ilkg VSS ≤ VIN ≤VDD - - ±1

(2)
A
Digital input leakage current
Ilkg ana VSS ≤ VIN ≤ VDD - - ±250

(2)
nA
Analog input leakage current
Ilkg(inj) Injection current ±4 mA

Leakage current in adjacent - - ±1
(2)
A
I/O
(1)
Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not
tested in production.
(2)
Data based on characterisation results, not tested in production.
(3)
Data guaranteed by design.
Figure 22: Typical VIL and VIH vs VDD @ 4 temperatures
DocID15590 Rev 8 71/116

Figure 23: Typical pull-up resistance vs VDD @ 4 temperatures
Figure 24: Typical pull-up current vs VDD @ 4 temperatures
Table 41: Output driving current (standard ports)

Output low level with 8 pins sunk IIO= 10 mA,
- 2.0
VDD = 5 V
VOL
Output low level with 4 pins sunk IIO = 4 mA,
(1)
- 1.0 V
VDD = 3.3 V
Output high level with 8 pins sourced IIO = 10 mA,

VOH 2.8 -
VDD = 5 V
72/116 DocID15590 Rev 8


Output high level with 4 pins sourced IIO = 4 mA,
(1)
2.1 -
VDD = 3.3 V
(1)
Table 42: Output driving current (true open drain ports)

Symbol Parameter Conditions Max Unit
VOL IIO = 10 mA, VDD = 5 V 1 .0

Output low level with 2 pins sunk
IIO = 10 mA, VDD = 3.3 (1)

VOL Output low level with 2 pins sunk 1.5 V
V
VOL IIO = 20 mA, VDD = 5 V 2.0

(1)
Output low level with 2 pins sunk
(1)
Table 43: Output driving current (high sink ports)

IIO = 10 mA,
VOL Output low level with 8 pins sunk - 0.8 V
VDD = 5 V
IIO = 10 mA,
Output low level with 4 pins sunk - 1.0
(1)
VDD = 3.3 V
VOL
IIO = 20 mA,
Output low level with 4 pins sunk - 1.5
(1)
VDD = 5 V
IIO = 10 mA,
Output high level with 8 pins sourced 4.0 - V
VDD = 5 V
IIO = 10 mA,
VOH Output high level with 4 pins sourced 2.1
(1)
-
VDD = 3.3 V
IIO = 20 mA,
Output high level with 4 pins sourced 3.3
(1)
-
VDD = 5 V
(1)
DocID15590 Rev 8 73/116

Figure 25: Typ. VOL @ VDD = 5 V (standard ports)
Figure 26: Typ. VOL @ VDD = 3.3 V (standard ports)
74/116 DocID15590 Rev 8

Figure 27: Typ. VOL @ VDD = 5 V (true open drain ports)
Figure 28: Typ. VOL @ VDD = 3.3 V (true open drain ports)
DocID15590 Rev 8 75/116

Figure 29: Typ. VOL @ VDD = 5 V (high sink ports)
Figure 30: Typ. VOL @ VDD = 3.3 V (high sink ports)
76/116 DocID15590 Rev 8

Figure 31: Typ. VDD - VOH@ VDD = 5 V (standard ports)
Figure 32: Typ. VDD - VOH @ VDD = 3.3 V (standard ports)
DocID15590 Rev 8 77/116

Figure 33: Typ. VDD - VOH@ VDD = 5 V (high sink ports)
Figure 34: Typ. VDD - VOH@ VDD = 3.3 V (high sink ports)
10.3.7 Reset pin characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 44: NRST pin characteristics

VIL(NRST)
NRST input low
-0.3 - 0.3 x VDD V
(1)
level voltage
78/116 DocID15590 Rev 8


VIH(NRST)
NRST input high
IOL=2 mA 0.7 x VDD - VDD + 0.3
(1)
level voltage
VOL(NRST)
NRST output low
- - 0.5
(1)
level voltage
RPU(NRST)
NRST pull-up
30 55 80 k
(2)
resistor
tI FP(NRST)
NRST input filtered
- - 75
(3)
pulse
ns
tIN FP(NRST)
NRST input not
500 - -
(3)
filtered pulse
tOP(NRST)
NRST output
20 - - s
(3)
pulse
(1)
(2)
The RPU pull-up equivalent resistor is based on a resistive transistor
(3)
Figure 35: Typical NRST VIL and VIH vs VDD @ 4 temperatures
DocID15590 Rev 8 79/116

Figure 36: Typical NRST pull-up resistance vs VDD @ 4 temperatures
Figure 37: Typical NRST pull-up current vs VDD @ 4 temperatures
The reset network shown in the following figure protects the device against parasitic resets.
The user must ensure that the level on the NRST pin can go below VIL(NRST) max. (see Table
40: I/O static characteristics ), otherwise the reset is not taken into account internally.
For power consumption sensitive applications, the external reset capacitor value can be
reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry,
attention must be taken to the charge/discharge time of the external capacitor to fulfill the
external devices reset timing conditions. Minimum recommended capacity is 100 nF.
80/116 DocID15590 Rev 8

Figure 38: Recommended reset pin protection
VDD STM8
RPU
External
NRST Filter Internal reset
reset
circuit
0.1 μF
(optional)
10.3.8 SPI serial peripheral interface

Unless otherwise specified, the parameters given in the following table are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions.
tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 45: SPI characteristics

Symbol Parameter (1) Min Max Unit
Conditions
fSCK1/ SPI clock Master mode

0 8 MHz
tc(SCK) frequency
fSCK1/ fSCK1/ tc(SCK) SPI clock frequency

(2)
0 7 MHz
tc(SCK)
tr(SCK) SPI clock rise and Capacitive load: C = 30 pF

25
tf(SCK) fall time
(3)
tsu(NSS) NSS setup time Slave mode 4x
tMASTER
(3)
th(NSS) NSS hold time Slave mode 70
(3)
tw(SCKH) SCK high and low Master mode tSCK/ tSCK/ ns
(3)
tw(SCKL) time 2 - 15 2 +15
(3)
tsu(MI) Data input setup Master mode 5
(3)
tsu(SI) time Slave mode 5
(3)
th(MI) Data input hold Master mode 7
(3)
th(SI) time Slave mode 10
DocID15590 Rev 8 81/116

Symbol Parameter (1) Min Max Unit

Conditions
(3) (4)
ta(SO) Data output Slave mode 3x
access time tMASTER
(3) (5)
tdis(SO) Data output Slave mode
25
disable time
(3)
tv(SO) Data output valid Slave mode
(2)
65
time (after enable edge)
(3)
tv(MO) Data output valid Master mode
30
(3)
th(SO) Data output hold Slave mode
(2)
27
(3)
th(MO) Data output hold Master mode
(2)
11
(1)
Parameters are given by selecting 10 MHz I/O output frequency.
(2)
Data characterization in progress.
(3)
Values based on design simulation and/or characterization results, and not tested in
production.
(4)
Min time is for the minimum time to drive the output and the max time is for the maximum
time to validate the data.
(5)
Min time is for the minimum time to invalidate the output and the max time is for the
maximum time to put the data in Hi-Z.
82/116 DocID15590 Rev 8

Figure 39: SPI timing diagram - slave mode and CPHA = 0
NSS input
tSU(NSS) tc(SCK) th(NSS)
CPHA= 0
SCK Input
CPOL=0
tw(SCKH)
CPHA= 0 tw(SCKL)
CPOL=1
tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
th(SI)
ai14134
Figure 40: SPI timing diagram - slave mode and CPHA = 1
NSS input
tSU(NSS) tc(SCK) th(NSS)
CPHA=1
SCK Input
CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1
tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI) th(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
ai14135
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
DocID15590 Rev 8 83/116

(1)
Figure 41: SPI timing diagram - master mode
High
NSS input
SCK output tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
SCK output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MS BIN BI T6 IN LSB IN
th(MI)
MOSI
M SB OUT B I T1 OUT LSB OUT
OUTUT
tv(MO) th(MO)
ai14136b
1. Measurement points are made at CMOS levels: 0.3 VDD and 0.7 VDD.
2
10.3.9 I C interface characteristics
2
Table 46: I C characteristics
Symbol Parameter 2 2 (1) Unit
Standard mode I C Fast mode I C
(2) (2) (2) (2)

Min Max Min Max
tw(SCLL) SCL clock low time 4.7 - 1.3 -

s
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -

(3) (4) (3)
th(SDA) SDA data hold time 0 - 0 900
tr(SDA)
SDA and SCL rise time - 1000 - 300 ns
tr(SCL)
tf(SDA)
SDA and SCL fall time - 300 - 300
tf(SCL)
th(STA) START condition hold time 4.0 - 0.6 -

s
tsu(STA) Repeated START condition setup time 4.7 - 0.6 -
84/116 DocID15590 Rev 8

Symbol Parameter 2 2 (1) Unit

Standard mode I C Fast mode I C
(2) (2) (2) (2)

Min Max Min Max
tsu(STO) STOP condition setup time 4.0 - 0.6 -
tw(STO:STA) STOP to START condition time

4.7 - 1.3 - s
(bus free)
Cb Capacitive load for each bus line - 400 - 400 pF
(1) 2
fMASTER, must be at least 8 MHz to achieve max fast I C speed (400kHz)
(2) 2
Data based on standard I C protocol requirement, not tested in production
(3)
The maximum hold time of the start condition has only to be met if the interface does not stretch the
low time
(4)
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
2
Figure 42: Typical application with I C bus and timing diagram
VDD VDD
4.7kΩ 4.7kΩ
STM8S
100Ω SDA
I2C bus 100Ω SCL
REPEATED
START
START
tsu(STA) tw(STO:STA)
SDA
START
tf(SDA) tr(SDA) tsu(SDA) th(SDA) STOP

SCL
th(STA) tw(SCLH) tw(SCLL) tr(SCL) tf(SCL) tsu(STO)
ai17490
1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD.
10.3.10 10-bit ADC characteristics

Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.
Table 47: ADC characteristics

fADC ADC clock frequency VDD =2.95 to 5.5 V 1 - 4 MHz
DocID15590 Rev 8 85/116


VDD =4.5 to 5.5 V 1 - 6
(1)
VAIN Conversion voltage range VSS - VDD V
VBGREF Internal bandgap reference VDD =2.95 to 5.5 V 1.19 1.22 1.25 V
voltage
CADC Internal sample and hold - 3 - pF

capacitor
(1)
tS Minimum sampling time fADC = 4 MHz - 0.75 - µs
fADC = 6 MHz - 0.5 -
tSTAB Wake-up time from standby - 7 - µs
tCONV Minimum total conversion fADC = 4 MHz 3.5 µs

time (including sampling time,
10-bit resolution) fADC = 6 MHz 2.33 µs
14 1/fADC
(1)
During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged
by the external source. The internal resistance of the analog source must allow the
capacitance to reach its final voltage level within tS. After the end of the sample time tS,
changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tS depend on programming.
Table 48: ADC accuracy with RAIN < 10 k , VDD= 5 V

(1)
Symbol Parameter Conditions Typ Max Unit
(2)
|ET| Total unadjusted error fADC = 2 MHz 1.6 3.5 LSB
fADC = 4 MHz 2.2 4
fADC = 6 MHz 2.4 4.5

(2)
|EO| Offset error fADC = 2 MHz 1.1 2.5
fADC = 4 MHz 1.5 3
fADC = 6 MHz 1.8 3

(2)
|EG| Gain error fADC = 2 MHz 1.5 3
fADC = 4 MHz 2.1 3
fADC = 6 MHz 2.2 4

(2)
|ED| Differential linearity error fADC = 2 MHz 0.7 1.5
fADC = 4 MHz 0.7 1.5
86/116 DocID15590 Rev 8

(1)
fADC = 6 MHz 0.7 1.5

(2)
|EL| Integral linearity error fADC = 2 MHz 0.6 1.5
fADC = 4 MHz 0.8 2
fADC = 6 MHz 0.8 2
(1)
(2)
ADC accuracy vs. negative injection current: Injecting negative current on any of the
analog input pins should be avoided as this significantly reduces the accuracy of the
conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in the I/O
port pin characteristics section does not affect the ADC accuracy.
Table 49: ADC accuracy with RAIN < 10 k RAIN, VDD = 3.3 V
(1)
|ET| Total unadjusted error fADC = 2 MHz 1.6 3.5 LSB
fADC = 4 MHz 1.9 4
|EO| Offset error fADC = 2 MHz 1 2.5
fADC = 4 MHz 1.5 2.5
|EG| Gain error fADC = 2 MHz 1.3 3
fADC = 4 MHz 2 3
|ED| Differential linearity error fADC = 2 MHz 0.7 1
fADC = 4 MHz 0.7 1.5
|EL| Integral linearity error fADC = 2 MHz 0.6 1.5
fADC = 4 MHz 0.8 2
(1)
DocID15590 Rev 8 87/116

Figure 43: ADC accuracy characteristics
1. Example of an actual transfer curve.

2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer
curves.
EO = Offset error: deviation between the first actual transition and the first ideal one.
EG = Gain error: deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: maximum deviation between actual steps and the ideal
one.
EL = Integral linearity error: maximum deviation between any actual transition and the end
point correlation line.
Figure 44: Typical application with ADC
VDD STM8
VT
VAIN RAIN 0.6 V
AINx 10-bit A/D
conversion
VT IL
CAIN CADC
0.6 V ± 1 µA
88/116 DocID15590 Rev 8

10.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.
10.3.11.1 Functional EMS (electromagnetic susceptibility)

While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
• FESD: Functional electrostatic discharge (positive and negative) is applied on all pins of
the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2
standard.
• through
FTB: A burst of fast transient voltage (positive and negative) is applied to V and V
DD
a 100 pF capacitor, until a functional disturbance occurs. This test conforms with
SS
the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table
below based on the EMS levels and classes defined in application note AN1709 (EMC design
guide for STMicrocontrollers).
10.3.11.2 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring. See application note AN1015 (Software techniques
for improving microcontroller EMC performance).
Table 50: EMS data

Symbol Parameter Conditions Level/
class
VFESD Voltage limits to be
applied on any I/O pin to VDD = 3.3 V, TA = 25 °C, fMASTER = 16 MHz (1)
2/B
induce a functional (HSI clock), conforming to IEC 61000-4-2
disturbance
VEFTB Fast transient voltage

burst limits to be applied
through 100 pF on VDD VDD= 3.3 V, TA = 25 °C ,fMASTER = 16 MHz
(1)
4/A
and VSS pins to induce a (HSI clock),conforming to IEC 61000-4-4
functional disturbance
DocID15590 Rev 8 89/116

(1)
Data obtained with HSI clock configuration, after applying HW recommendations described
in AN2860 (EMC guidelines for STM8S microcontrollers).
10.3.11.3 Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports),
the product is monitored in terms of emission. This emission test is in line with the norm SAE
IEC 61967-2 which specifies the board and the loading of each pin.
Table 51: EMI data
Conditions
(1)
Max fHSE/fCPU
Symbol Parameter Unit
General Monitored
conditions frequency band 16 MHz/ 16 MHz/
8 MHz 16 MHz
Peak level VDD = 5 V

0.1 MHz to
TA = 25 °C 5 5
30 MHz
LQFP32
package
30 MHz to
Conforming to 4 5 dB V
130 MHz
SEMI SAE IEC
61967-2
130 MHz to
5 5
1 GHz
SAE EMI
SAE EMI level 2.5 2.5
level
(1)
10.3.11.4 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, DLU and LU) using specific measurement methods, the
product is stressed to determine its performance in terms of electrical sensitivity. For more
details, refer to the application note AN1181.
10.3.11.5 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied
to the pins of each sample according to each pin combination. The sample size depends on
the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated:
90/116 DocID15590 Rev 8

Human body model. This test conforms to the JESD22-A114A/A115A standard. For more
details, refer to the application note AN1181.
Table 52: ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum Unit

(1)
value
VESD(HBM)
Electrostatic discharge TA = 25°C, conforming to
voltage JESD22-A114 A 4000
(Human body model)
V
VESD(CDM)
Electrostatic discharge TA LQFP32 package =
voltage 25°C, conforming to IV 1000
(Charge device model) SD22-C101
(1)
10.3.11.6 Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:
• A supply overvoltage (applied to each power supply pin)
• Aoncurrent injection (applied to each input, output and configurable I/O pin) are performed
each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 53: Electrical sensitivities

(1)
Symbol Parameter Conditions Class
LU Static latch-up class TA = 25 °C A
TA = 85 °C A
TA = 125 °C A
(1)
Class description: A Class is an STMicroelectronics internal specification. All its limits
are higher than the JEDEC specifications, that means when a device belongs to class A it
exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international
standard).
DocID15590 Rev 8 91/116

Package information STM8S903K3 STM8S903F3
11 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
® ®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
11.1 32-pin LQFP package mechanical data

Figure 45: 32-pin low profile quad flat package (7 x 7)
ccc C
D
D1
D3 A
A2
24 17
16
25 L1
b
E3 E1 E
32
9
L
Pin 1 A1 K
identification 1 8 c
5V_ME
Table 54: 32-pin low profile quad flat package mechanical data
(1)
Dim. mm inches
Min Typ Max Min Typ Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
92/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Package information
(1)
Dim. mm inches
D3 5.600 0.2205
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.600 0.2205
e 0.800 0.0315
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc 0.100 0.0039
(1)
Values in inches are converted from mm and rounded to 4 decimal digits
DocID15590 Rev 8 93/116

11.2 32-lead UFQFPN package mechanical data

Figure 46: 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5)
AOB8_ME
1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint
life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended
to connect and solder this backside pad to PCB ground.
4. Dimensions are in millimeters.
Table 55: 32-lead, ultra thin, fine pitch quad flat no-lead package mechanical data
(1)
Dim. mm inches
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 0 0.020 0.050 0.0008 0.0020
A3 0.200 0.0079
94/116 DocID15590 Rev 8

(1)
Dim. mm inches
b 0.180 0.250 0.300 0.0071 0.0098 0.0118
D 4.850 5.000 5.150 0.1909 0.1969 0.2028
D2 3.200 3.450 3.700 0.1260 0.1457
E 4.850 5.000 5.150 0.1909 0.1969 0.2028
E2 3.200 3.450 3.700 0.1260 0.1358 0.1457
e 0.500 0.0197
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd 0.080 0.0031
(1)
Values in inches are converted from mm and rounded to 4 decimal digits.
11.3 20-lead UFQFPN package mechanical data

Figure 47: 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3)
Pin 1 E
TOP VIEW
L1
D ddd
L4
e
10 A3
L2
5 11 e
b
E
1 15
20 16
L3 A1
A
BOTTOM VIEW
SIDE VIEW
103_A0A5_ME
DocID15590 Rev 8 95/116

1. Drawing is not to scale.
Table 56: 20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package
mechanical data
(1)
Dim. mm inches
D 3.000 0.1181
E 3.000 0.1181
A 0.500 0.550 0.600 0.0197 0.0217 0.0236
A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 0.152 0.0060
e 0.500 0.0197
L1 0.500 0.550 0.600 0.0197 0.0217 0.0236
L2 0.300 0.350 0.400 0.0118 0.0138 0.0157
L3 0.150 0.0059
L4 0.200 0.0079
b 0.180 0.250 0.300 0.0071 0.0098 0.0118
ddd 0.050 0.0020
(1)
Values in inches are converted from mm and rounded to 4 decimal digits.
96/116 DocID15590 Rev 8

11.4 UFQFPN recommended footprint

Figure 48: Recommended footprint for on-board emulation
0.5mm
0.8mm
[0.032"]
4mm
[0.157"]
0.5mm
1.65mm [0.065"] 0.9mm

[0.035"]
0.3mm [0.012"]
4mm [0.157"]
ai15319
Bottom view
1. Drawing is not to scale
DocID15590 Rev 8 97/116

Figure 49: Recommended footprint without on-board emulation
1. Drawing is not to scale

2. Dimensions are in millimeters
11.5 SDIP32 package mechanical data

Figure 50: 32-lead shrink plastic DIP (400 ml) package
E1
A2 A
A1 L
B1 B e
C eA
eB
32 17
1 16
76_ME
98/116 DocID15590 Rev 8

Table 57: 32-lead shrink plastic DIP (400 ml) package mechanical data
(1)
Dim. mm inches
A 3.556 3.759 5.080 0.1400 0.1480 0.2000
A1 0.508 0.0200
A2 3.048 3.556 4.572 0.1200 0.1400 0.1800
B 0.356 0.457 0.584 0.0140 0.0180 0.0230
B1 0.762 1.016 1.397 0.0300 0.0400 0.0550
C 0.203 0.254 0.356 0.0079 0.0100 0.0140
D 27.430 27.940 28.450 1.0799 1.1000 1.1201
E 9.906 10.410 11.050 0.3900 0.4098 0.4350
E1 7.620 8.890 9.398 0.3000 0.3500 0.3700
e 1.778 0.0700
eA 10.160 0.4000
eB 12.700 0.5000
L 2.540 3.048 3.810 0.1000 0.1200 0.1500
(1)
DocID15590 Rev 8 99/116

11.6 20-pin TSSOP package mechanical data

Figure 51: 20-pin, 4.40 mm body, 0.65 mm pitch
20 11
c
E1 E
1 10
aaa CP
A1 L
A A2
L1
b e
YA_ME
Table 58: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data

(1)
Dim. mm inches
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
D 6.400 6.500 6.600 0.2520 0.2559 0.2598
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1 4.300 4.400 4.500 0.1693 0.1732 0.1772
e 0.650 0.0256
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
100/116 DocID15590 Rev 8

(1)
Dim. mm inches
k 0.0° 8.0° 0.0° 8.0°
aaa 0.100 0.0039
(1)
11.7 20-pin SO package mechanical data

Figure 52: 20-lead, plastic small outline (300 mils) package
D
20 11 h x 45°
C
E H
1 10
ddd
B e A1
A1 k L
Z7_ME
Table 59: 20-lead, plastic small outline (300 mils) mechanical data
(1)
Dim. mm inches
A 2.350 2.650 0.0925 0.1043
A1 0.100 0.300 0.0039 0.0118
B 0.330 0.510 0.013 0.0201
C 0.230 0.320 0.0091 0.0126
D 12.600 13.000 0.4961 0.5118
E 7.400 7.600 0.2913 0.2992
e 1.270 0.0500
DocID15590 Rev 8 101/116

(1)
Dim. mm inches
H 10.000 10.650 0.3937 0.4193
h 0.250 0.750 0.0098 0.0295
L 0.400 1.270 0.0157 0.0500
k 0.0° 8.0° 0.0° 8.0°
ddd 0.100 0.0039
(1)
11.8 Thermal characteristics

The maximum chip junction temperature (TJ max) must never exceed the values given in
Operating conditions.
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using
the following equation:
TJmax = TAmax + (PDmax x JA )
Where:
• TAmax is the maximum ambient temperature in °C
• is the package junction-to-ambient thermal resistance in °C/W
JA
• P is the sum of P and P (PDmax = P + P )

Dmax INTmax I/Omax INTmax I/Omax
• Ppower. is the product of I andV , expressed in Watts. This is the maximum chip internal
INTmax DD DD
• P represents the maximum power dissipation on output pins

I/Omax
Where:
PI/Omax = (VOL*IOL) + ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and VOH/IOH
of the I/Os at low and high level in the application.
Table 60: Thermal characteristics

(1)
Symbol Parameter Value Unit
JA 110
Thermal resistance junction-ambient °C/W
TSSOP20 - 4 x 4 mm
JA 20
SO20W - 300 mils
102/116 DocID15590 Rev 8

(1)
Symbol Parameter Value Unit
JA 101
UFQFPN20 - 3 x 3 mm
JA 60
LQFP32 - 7 x 7 mm
JA 38 °C/W
Thermal resistance junction-ambient
UFQFPN32 - 5 x 5 mm
JA 60 °C/W
Thermal resistance junction-ambient
SDIP32 - 400 mils
(1)
Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural
convection environment.
11.8.1 Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural convection
(still air). Available from www.jedec.org.
11.8.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code.
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
• Maximum ambient temperature TAmax= 75 °C (measured according to JESD51-2)
• I = 8 mA, V = 5 V
DDmax DD
• Maximum 20 I/Os used at the same time in output at low level with
IOL = 8 mA, VOL= 0.4 V
PINTmax = 8 mA x 5 V = 400 mW
Amax
• PDmax = 400 mW + 64 mW
Thus: PDmax = 464 mW
TJmax for LQFP32 can be calculated as follows, using the thermal resistance JA:
TJmax = 75 °C + (60 °C/W x 464 mW) = 75 °C + 27.8 °C = 102.8 °C

This is within the range of the suffix 6 version parts (-40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6.
DocID15590 Rev 8 103/116

Ordering information STM8S903K3 STM8S903F3
12 Ordering information
Figure 53: STM8S903K3/F3 ordering information scheme
Example: STM8 S 903 K 3 T 6 TR
Product class
STM8 microcontroller
Family type
S = Standard
Sub-family type
903 = 903 sub-family
Pin count
K = 32 pins
F = 20 pins
Program memory size

3 = 8 Kbytes
Package type 1
B = SDIP
T = LQFP
U = UFQFPN
P = TSSOP
M = SO
Temperature range
3 = -40 °C to 125 °C
6 = -40 °C to 85 °C
Package pitch
Blank = 0.5 or 0.65 mm (2)
C = 0.8 mm (3)
Packing
No character = Tray or tube
TR = Tape and reel
1. A dedicated ordering information scheme will be released if, in the future, memory
programming service (FastROM) is required. The letter "P" will be added after STM8S.
Three unique letters identifying the customer application code will also be visible in the
codification. Example: STM8SP903K3MACTR.
2. UFQFPN, TSSOP, and SO packages.
3. LQFP package.
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please go to www.st.com or contact the ST
Sales Office nearest to you.
12.1 STM8S903K3/F3 FASTROM microcontroller option list

(last update: April 2010)
104/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Ordering information
Customer ...........................................................................................................
Address ...........................................................................................................
Contact ...........................................................................................................
Phone no. ...........................................................................................................
Reference FASTROM code name is assigned by STMicroelectronics

FASTROM code
Preferable format for programing code is .Hex (.s19 is accepted)

If data EEPROM programing is required, a seperate file must be sent with the requested data.
Important: See the option byte section in the datasheet for authorized option byte
combinations and a detailed explanation. Do not use more than one remapping option
in the same port. It is forbidden to enable both AFR1 and AFR0.
Device type/memory size/package
FASTROM device 8 Kbyte
TSSOP20 [ ] STM8S903F3
SO20 [ ] STM8S903F3
UFQFPN20 [ ] STM8S903F3
LQFP32 [ ] STM8S903K3
UFQFPN32 [ ] STM8S903K3
Conditioning (check only one option)

[ ] Tape & reel or [ ] Tray
Special marking (check only one option)

[ ] No [ ] Yes
Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character counts
are:
LQFP32: 2 lines of 7 characters max: "_ _ _ _ _ _ _" and "_ _ _ _ _ _ _"
TSSOP20: 1 line of 10 characters max: "_ _ _ _ _ _ _ _ _ _"
SO20: 1 line of 13 characters max: "_ _ _ _ _ _ _ _ _ _ _ _ _"
UFQFPN32: 1 line of 7 characters max: "_ _ _ _ _ _ _"
UFQFPN20: 1 line of 4 characters max: "_ _ _ _ "
Three characters are reserved for code identification.
Temperature range
[ ] -40°C to +85°C or [ ] -40°C to +125°C
DocID15590 Rev 8 105/116

Padding value for unused program memory (check only one option)
[ ]0xFF Fixed value
[ ]0x83 TRAP instruction opcode
[ ]0x75 Illegal opcode (causes a reset when executed)
OPT0 memory readout protection (check only one option)

[ ] Disable or [ ] Enable
OPT1 user boot code area (UBC)

0x(_ _) fill in the hexadecimal value, refering to the datasheet and the binary format below.
UBC, bit0
[ ] 0: Reset
[ ] 1: Set
UBC bit1
[ ] 0: Reset
[ ] 1: Set
UBC bit2
[ ] 0: Reset
[ ] 1: Set
UBC bit3
[ ] 0: Reset
[ ] 1: Set
UBC bit4
[ ] 0: Reset
[ ] 1: Set
UBC bit5
[ ] 0: Reset
[ ] 1: Set
UBC bit6
[ ] 0: Reset
[ ] 1: Set
UBC bit7
[ ] 0: Reset
[ ] 1: Set
Note: If the UBC area is not used, please select all bits at reset states.
OPT2 alternate function remapping for STM8S903K3

106/116 DocID15590 Rev 8

AFR1, AFR0
[ ] 00: Remapping options inactive. Default alternate
(check only one option) functions used. Refer to pinout description.
[ ] 01: Port C5 alternate function = TIM5_CH1, port
C6 alternate function = TIM1_CH1, and port C7
alternate function = TIM1_CH2.
[ ] 10: Port A3 alternate function = SPI_NSS and
port D2 alternate function = TIM5_CH3.
[ ] 11: Port D2 alternate function = TIM5_CH3, port
C5 alternate function = TIM5_CH1, port C6
alternate function = TIM1_CH1, port C7 alternate
function = TIM1_CH2, port C2 alternate function =
TIM1_CH3N, port C1 alternate function =
TIM1_CH2N, port E5 alternate function =
TIM1_CH1N, port A3 alternate function =
UART1_TX, and port F4 alternate function =
UART1_RX.
AFR2
[ ] 0: Remapping option inactive. Default alternate
[ ] 1: Port C4 alternate function = AIN2, port D2
alternate function = AIN3, port D4 alternate function
= UART1_CK.
AFR3
[ ] 1: Port C3 alternate function = TLI.
AFR4
[ ] 1: Port B4 alternate function = ADC_ETR, port
B5 alternate function = TIM1_BKIN.
AFR5
[ ] 1: Port D0 alternate function = CLK_CCO.
AFR6
[ ] 1: Port D7 alternate function = TIM1_CH4.
AFR7
[ ] 1: Port C3 alternate function = TIM1_CH1N, port
C4 alternate function = TIM1_CH2N.
DocID15590 Rev 8 107/116

OPT2 alternate function remapping for STM8S903F3

AFR1, AFR0
[ ] 00: Remapping options inactive. Default alternate
[ ] 01: Port C5 alternate function = TIM5_CH1, port
C6 alternate function = TIM1_CH1, and port C7
alternate function = TIM1_CH2.
[ ] 10: Port A3 alternate function = SPI_NSS and
port D2 alternate function = TIM5_CH3.
[ ] 11: Port D2 alternate function = TIM5_CH3, port
C5 alternate function = TIM5_CH1, port C6
alternate function = TIM1_CH1, port C7 alternate
function = TIM1_CH2, port E5 alternate function =
TIM1_CH1N, port A3 alternate function =
UART1_TX, and port F4 alternate function =
UART1_RX.
AFR2
Reserved
AFR3
[ ] 1: Port C3 alternate function = TLI.
AFR4
[ ] 1: Port B4 alternate function = ADC_ETR, port
B5 alternate function = TIM1_BKIN.
AFR5
Reserved
AFR6
Reserved
AFR7
[ ] 1: Port C3 alternate function = TIM1_CH1N, port
C4 alternate function = TIM1_CH2N.
OPT3 watchdog
WWDG_HALT
[ ] 0: No reset generated on halt if WWDG active
(check only one option)
[ ] 1: Reset generated on halt if WWDG active
WWDG_HW
[ ] 0: WWDG activated by software
[ ] 1: WWDG activated by hardware
108/116 DocID15590 Rev 8

IWDG_HW
[ ] 0: IWDG activated by software
[ ] 1: IWDG activated by hardware
LSI_EN
[ ] 0: LSI clock is not available as CPU clock source
[ ] 1: LSI clock is available as CPU clock source
HSITRIM
[ ] 0: 3-bit trimming supported in CLK_HSITRIMR register
[ ] 1: 4-bit trimming supported in CLK_HSITRIMR register
OPT4 wakeup
PRSC
[ ] for 16 MHz to 128 kHz prescaler
CKAWUSEL
[ ] LSI clock source selected for AWU
[ ] HSE clock with prescaler selected as clock source for for
AWU
EXTCLK
[ ] External crystal connected to OSCIN/OSCOUT
[ ] External clock signal on OSCIN
OPT5 crystal oscillator stabilization HSECNT (check only one option)

[ ] 2048 HSE cycles
[ ] 128 HSE cycles
[ ] 8 HSE cycles
[ ] 0.5 HSE cycles
OPT6 is reserved
Comments: ...........................................................................................................
Supply operating range in ...........................................................................................................

the application:
Notes: ...........................................................................................................
DocID15590 Rev 8 109/116

STM8 development tools STM8S903K3 STM8S903F3
13 STM8 development tools

Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation boards
and a low-cost in-circuit debugger/programmer.
13.1 Emulation and in-circuit debugging tools

The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8
application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers
new advanced debugging capabilities including profiling and coverage to help detect and
eliminate bottlenecks in application execution and dead code when fine tuning an application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to order
exactly what you need to meet your development requirements and to adapt your emulation
system to support existing and future ST microcontrollers.
STice key features

• Occurrence and time profiling and code coverage (new features)
• Advanced breakpoints with up to 4 levels of conditions
• Data breakpoints
• Program and data trace recording up to 128 KB records
• Read/write on the fly of memory during emulation
• In-circuit debugging/programming via SWIM protocol
• 8-bit probe analyzer
• 1 input and 2 output triggers
• Power supply follower managing application voltages between 1.62 to 5.5 V
• Modularity that allows you to specify the components you need to meet your development
requirements and adapt to future requirements
• Supported by free software tools that include integrated development environment (IDE),
programming software interface and assembler for STM8.
13.2 Software tools

STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
110/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 STM8 development tools
13.2.1 STM8 toolset

STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
• Seamless integration of C and ASM toolsets
• Full-featured debugger
• Project management
• Syntax highlighting editor
• Integrated programming interface
• Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
13.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
• Cosmic C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes
of code. For more information, see www.cosmic-software.com.
• Raisonance C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
• STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which
allows you to assemble and link your application source code.
13.3 Programming tools

During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to include
a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated
programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
DocID15590 Rev 8 111/116

Revision history STM8S903K3 STM8S903F3
14 Revision history
Table 61: Document revision history
Date Revision Changes
30-Apr-2009 1 Initial revision
03-Jun-2009 2 Added bullet point concerning unique identifier to Features

section on cover page.
Highlighted internal reference voltage in Analog-to-digital
converter (ADC1) section.
Updated wpu and PP status of PB5/12C_SDA[TIM1_BKIN]
and PB4/12C_SCL[ADC_ETR] pins in Pin description.
Updated Figure 7: Memory map.
Added Unique ID section.
Added TBD values to Table 45: SPI characteristics.
Added max values to Table 48: ADC accuracy with RAIN < 10
k , VDD= 5 V and Table 49: ADC accuracy with RAIN < 10
k RAIN, VDD = 3.3 V .
22-Apr-2010 3 Added SO20W, TSSOP20, SDIP32, and UFQFPN32 packages.

Added STM8S903F3 part number.
Updated datasheet status to full datasheet.
Updated definition of alternate function remapping option in
Table 4: Legend/abbreviations for pinout tables .
Updated Px_IDR reset value in Table 7: I/O port hardware
register map table.
Removed ESR low limit and update high limit for CEXT
conditions in Table 21: General operating conditions.
Operating conditions: updated VCAP and ESR low limit, added
ESL parameter, as well as PD in Table 21: General operating
conditions.
Functional EMS (electromagnetic susceptibility): changed ESD
to FESD (functional ESD); added name of AN1709; replaced
IEC 1000 with IEC 61000.
Designing hardened software to avoid noise problems replaced
IEC 1000 with IEC 61000, added title of AN1015, and added
footnote to Table 50: EMS data.
Electromagnetic interference (EMI) replaced J 1752/3 with IEC
61967-2 and updated data of Table 51: EMI data.
Removed note 3 related to Accuracy of HSI oscillator.
112/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Revision history
Updated JA in Table 15: STM8S903K3 alternate function

remapping bits [1:0] for 32-pin packages. Changed JA to
60°C/W in Selecting the product temperature range section.
Ordering information: replaced package pitch digit by
VFQFPN/UFQFPN package, and added footnote regarding
possible future release of a dedicated ordering information
scheme. Added SO20W, TSSOP20, SDIP32, and UFQFPN32.
Added STM8S903K3/F3 FASTROM microcontroller option list.
30-Apr-2010 4 Modified PD at TA = 85 °C for SO20W in Table 21: General

operating conditions.
08-Sep-2010 5 Removed VFQFPN32 package.

Updated "reset state" of Table 4: Legend/abbreviations for
pinout tables in Pinout and pin description.
Table 5: TSSOP20/SO20/UFQFPN20 pin description: updated
pins 13/25/20, 14/26/21, 19/32/27, 1/2/29, 2/3/30, and 3/4/31;
added footnote to PD1/SWIM pin.
General hardware register map: standardized all reset state
values; updated the reset state values of RST_SR,
CLK_SWCR, CLK_HSITRIMR, CLK_SWIMCCR, IWDG_KR,
and ADC_DRx registers in the "General hardware register
map" table.
Changed title of Table 13: STM8S903K3 alternate function
remapping bits [7:2] for 32-pin packages.
Added Table 14: STM8S903F3 alternate function remapping
bits [7:2] for 20-pin packages.
Changed title of Table 15: STM8S903K3 alternate function
remapping bits [1:0] for 32-pin packages.
Added Table 16: STM8S903F3 alternate function remapping
bits [1:0] for 20-pin packages.
Reset pin characteristics: replaced 0.01 µF with 0.1 µF in the
"Recommended reset pin protection" diagram.
Added
#unique_58/title_4B4D811961B64279B556EDC351811802
Updated footnote 1 in Table 48: ADC accuracy with RAIN <
10 k , VDD= 5 V and Table 49: ADC accuracy with RAIN <
10 k RAIN, VDD = 3.3 V .
#unique_77/CD14: updated existing footnote and added three
additional footnotes.
DocID15590 Rev 8 113/116

Revision history STM8S903K3 STM8S903F3
Updated "special marking" and "OPT2 alternate function

remapping" sections in the STM8S903K3/F3 FASTROM
microcontroller option list.
28-Jul-2011 6
Added note for OPT1 option list.
Updated OPT2 option list for STM8S903K3 and created OPT2
option list for STM8S903F3 in STM8S903K3/F3 FASTROM
microcontroller option list.
Updated UART1 interrupt vector addresses in table Table 10:
Interrupt mapping
Updated note related to true open-drain outputs in Table 5:
TSSOP20/SO20/UFQFPN20 pin description and Table 5:
TSSOP20/SO20/UFQFPN20 pin description.
Added UFQFPN20 package.
Remove CLK_CANCCR register from Table 8: General
hardware register map .
Added note for Px_IDR registers in Table 7: I/O port hardware
register map.
Updated title of Ordering information.
Removed Typical HSI accuracy curve in High speed internal
RC oscillator (HSI).
Updated value of recommended external capacitor to 100 nF
inReset pin characteristics.
Updated disclaimer.
04-Apr-2012 7
Internal reference voltage renamed internal bandgap reference
voltage.
Updated notes related to VCAP in Table 21: General operating
conditions.
Added values of tR/tF for 50 pF load capacitance, and updated
note in Table 40: I/O static characteristics.
Updated typical and maximum values of RPU in Table 40: I/O
static characteristics and Table 44: NRST pin characteristics.
Changed SCK input to SCK output in SPI serial peripheral
interface
Modified Figure 47: 20-lead, ultra thin, fine pitch quad flat
no-lead package outline (3 x 3)to add package top view.
13-Jun-2012 8
Restored Figure 44: Typical application with ADC
114/116 DocID15590 Rev 8

STM8S903K3 STM8S903F3 Revision history
Modified Figure 47: 20-lead, ultra thin, fine pitch quad flat
no-lead package outline (3 x 3) to add package top view.
DocID15590 Rev 8 115/116

STM8S903K3 STM8S903F3
Please Read Carefully
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STM8S903K3 STM8S903F3

16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, 1 Kbyte RAM, 640

• Permanently active, low consumption power-on

• Auto wakeup timer

• Extended instruction set • SPI interface up to 8 Mbit/s

- External clock input

- Internal, user-trimmable 16 MHz RC Development support

• Power management: Unique ID: 96-bit key including lot number

2/116 DocID15590 Rev 8

DocID15590 Rev 8 3/116

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Table 48. ADC accuracy with RAIN < 10 k , VDD= 5 V .........................................................................86

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Figure 48. Recommended footprint for on-board emulation ..................................................................97

DocID15590 Rev 8 7/116

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Table 1: STM8S903K3/F3 access line features

Ext. interrupt pins 28 16

A/D converter channels 7 5

High sink I/Os 21 12

Low density Flash 8K

DocID15590 Rev 8 9/116

Reset block XTAL 1-16 MHz

Clock to peripherals and core

Single wire Debug/SWIM 8 Kbytes

400 Kbit/s I 2C 1 Kbytes

1/2/4 kHz Beeper AWU timer

10/116 DocID15590 Rev 8

4.1 Central processing unit STM8

Architecture and registers

DocID15590 Rev 8 11/116

12/116 DocID15590 Rev 8

Data Data memory area ( 640 bytes)

Read-out protection (ROP)

4.5 Clock controller

- 1-16 MHz high-speed external crystal (HSE)

- Up to 16 MHz high-speed user-external clock (HSE user-ext)

Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

PCKEN16 IM5 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU

PCKEN15 Reserved PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved

4.6 Power management

4.7 Watchdog timers

14/116 DocID15590 Rev 8

Window watchdog timer

Independent watchdog timer

4.8 Auto wakeup counter

4.10 TIM1 - 16-bit advanced control timer

DocID15590 Rev 8 15/116

• Break input to force the timer outputs into a defined state

4.12 TIM6 - 8-bit basic timer

Table 3: TIM timer features

TIM5 16 Any power of 2 Up 3 0 No

TIM6 8 Any power of 2 Up 0 0 No

4.13 Analog-to-digital converter (ADC1)

16/116 DocID15590 Rev 8

• Conversion time: 14 clock cycles

4.14 Communication interfaces

DocID15590 Rev 8 17/116

• Transmission error detection with interrupt generation

LIN master mode

• Full duplex synchronous transfers

18/116 DocID15590 Rev 8

5 Pinout and pin description