XR-2212

Precision
...the analog plus company TM Phase-Locked Loop

June 1997-3
FEATURES APPLICATIONS

Quadrature VCO Outputs
Frequency Synthesis

Wide Frequency Range (0.01Hz to 300kHz)
Data Synchronization

Wide Supply Voltage Range (4.5V to 20V)
FM Detection

TTL/HCMOS Compatible (VCC = 5VDC)
Tracking Filters

Wide Dynamic Range (2mV to 3Vrms)
FSK Demodulation

Adjustable Tracking Range (
1% to
80%)

Excellent Temp. Stability 20ppm/°C, Typ.

GENERAL DESCRIPTION
The XR-2212 is an ultra-stable monolithic phase-locked FM detection, and tracking filter applications. The wide
loop (PLL) system especially designed for data input dynamic range, large operating voltage range, large
communications and control system applications. Its on frequency range, and HCMOS and TTL compatibility
board reference and uncommitted operational amplifier, contribute to the usefulness and wide applicability of this
together with a typical temperature stability of better than device.
20ppm/°C, make it ideally suited for frequency synthesis,

ORDERING INFORMATION

Operating
Part No. Package Temperature Range
XR-2212M 16 Lead 300 Mil CDIP -55°C to +125°C
XR-2212CP 16 Lead 300 Mil PDIP 0°C to +70°C
XR-2212P 16 Lead 300 Mil PDIP -40°C to +85°C

BLOCK DIAGRAM
VCC GND

Pre Amplifier 1 4

INP 2 Phase 10 0-DET O

Detector
0-DET I 16
15 VCOQO
TIM C1 14
VCO 3 VCOOC
TIM C2 13 Amp
5 VCOOV

TIM R 12 VREF 11 VREF

PINP 9
Op Amp 8 OUT
NINP 7
6 COMP
Figure 1. XR-2212 Block Diagram

Rev. 2.01
1979
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538  (510) 668-7000  FAX (510) 668-7017
1
XR-2212
PIN CONFIGURATION

VCC 1 16 0-DET I
INP 2 15 VCOQO
VCOOC 3 14 TIM C1
GND 4 13 TIM C2
VCOOV 5 12 TIM R
COMP 6 11 VREF
NINP 7 10 0-DET O
OUT 8 9 PINP

16 Lead PDIP, CDIP (0.300”)

PIN DESCRIPTION
Pin # Symbol Type Description
1 VCC Positive Power Supply.
2 INP I Receive Analog Input.
3 VCOOC O VCO Current Output.
4 GND Ground Pin.
5 VCOOV O VCO Voltage Source Output.
6 COMP I Uncommitted Amplifier, Frequency Compensation Input.
7 NINP I Inverted Input. Uncommitted amplifier.
8 OUT O Uncommitted Amplifier Output.
9 PINP I Positive Input. Uncommitted amplifier.
10 0-DET O O Phase Detector Output.
11 VREF O Internal Voltage Reference. The value of VREF is VCC /2 -650mV.
12 TIM R I Timing Resistor Input. This pin connects to the timing resistor of the VCO.
13 TIM C2 I Timing Capacitor Input. The timing capacitor connects between this pin and pin 14.
14 TIM C1 I Timing Capacitor Input. The timing capacitor connects between this pin and pin 13.
15 VCOQO O VCO Quadrature Output.
16 0-DET I I Phase Detector Input.

Rev. 2.01
2
 XR-2212
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = +12V, TA = + 25°C, R0 = 30k
, C0 = 0.033F, unless otherwise specified. See
Figure 3 for component designation.

XR-2212M/2212P XR-2212CP
P
Parameter
t Min. Typ. Max. Min. Typ. Max. U it
Units C diti
Conditions

General Characteristics
Supply Voltage 4.5 15 4.5 15 V
Supply Current 6 10 6 12 mA R0 > 10k
., See Figure 5
Oscillator Section
Frequency Accuracy +1 +3 +1 % Deviation from f0 = 1/R0C0
Frequency Stability R1 = R
Temperature1 +20 +50 +20 ppm/°C See Figure 9
Power Supply 0.05 0.5 0.05 %/V VCC = 12 + 1V, See Figure 8
0.2 0.2 %/V VCC = 5 + 0.5V, See Figure 8
Upper Frequency Limit 100 300 300 kHz R0 = 8.2k
, C0 = 400pF
Lowest Practical Operating 0.01 0.01 Hz R0 = 2M
, C0 = 50F
F
Frequency

Timing Resistor, R0 See Figure 5

Operating Range 5 2000 5 2000 k

Recommended Range 15 100 15 100 k
See Figure 8 and Figure 9
Oscillator Outputs
Voltage Output Measured at Pin 5
Positive Swing, VOH 11 11 V
Negative Swing, VOL 0.4 0.8 0.5 V
Current Sink Capability 1 1 mA
Current Output Measured at Pin 3
Peak Current Swing 100 150 150 A
Output Impedance 1 1 M

Quadrature Output Measured at Pin 15
Output Swing 0.6 0.6 V
DC Level 0.3 0.3 V Referenced to Pin 11
Output Impedance 3 3 k

Loop Phase Detector Section Measured at Pin 10
Peak Output Current +150 +200 +300 +100 +200 +300 A
Output Offset Current +1 +2 A
Output Impedance 1 1 M

Maximum Swing +4 +5 +4 +5 V Referenced to Pin 11

Notes
1 For XR-2212P the parameters, although guaranteed over the recommended operating conditions, are not 100% tested in
production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.

Rev. 2.01
3
XR-2212
ELECTRICAL CHARACTERISTICS (CONT’D)

XR-2212M/2212P XR-2212CP
Parameter Units Conditions
Min. Typ. Max. Min. Typ. Max.
Input Preamp Section Measured at Pin 2
Input Impedance 20 20 k

Input Signal to Cause Limiting 2 10 2 mV rms
Op Amp Section
Voltage Gain 55 70 55 70 dB RL = 5.1k
, RF = R
Input Bias Current 0.1 1 0.1 1 A
Offset Voltage +5 +20 +5 +20 mV
Slew Rate 2 2 V/sec
Internal Reference Measured at Pin 11
Voltage Level 4.9 5.3 5.7 4.75 5.3 5.85 V
Output Impedance 100 100
AC Small Signal
Maximum Source Current 80 80
A

Notes
1 For XR-2212P the parameters, although guaranteed over the recommended operating conditions, are not 100% tested in
production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.

Specifications are subject to change without notice

ABSOLUTE MAXIMUM RATINGS

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Power Dissipation:
Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms Ceramic Package: . . . . . . . . . . . . . . . . . . . . . . . 750mW
Derate Above TA = + 25°C . . . . . . . . 6mW/°C
Plastic Package: . . . . . . . . . . . . . . . . . . . . . . . . 625mW
Derate Above TA = + 25°C . . . . . . . . 5mW/°C

SYSTEM DESCRIPTION
The XR-2212 is a complete PLL system with buffered external components. The PLL output is directly
inputs and outputs, an internal reference, and an compatible with CMOS, HCMOS and TTL logic families
uncommitted op amp. Two VCO outputs are pinned out; as well as microprocessor peripheral systems.
one sources current, the other sources voltage. This
enables operation as a frequency synthesizer using an The precision PLL system operates over a supply voltage
external programmable divider. The op amp section can range of 4.5V to 20V, a frequency range of 0.01Hz to
be used as an audio preamplifier for FM detection or as a 300kHz, and accepts input signals in the range of 2mV to
high speed sense amplifier (comparator) for FSK 3V rms. Temperature stability of the VCO is typically
demodulation. The center frequency, bandwidth, and better than 20 ppm/°C with the optimum timing resistor
tracking range of the PLL are controlled independently by value.

Rev. 2.01
4
 XR-2212

Loop
Pre Filter
Amp

Signal +
Input Phase
Detector
-
Op Amp
0-DET
Input

VCO AMP
Voltage
Output VCO

Phase
VCO Quadrature
Current
Output
Output

Figure 2. Functional Block Diagram of XR-2212 Precision PLL System

VCC

6 RL
5.6K

ÁÁ
2 10 9 CO
Phase 8
Detector

ÁÁ
7 Demod
0.1
F C1 Output
Input RF
Signal
16 RC

0.1
F R3 11
Internal
Reference
0.1
F
R1
5 12
%N VCO

External R0
Divider 14 13
(Optional)
CO

Figure 3. Generalized Circuit Connection for FM Detection, Signal

Tracking or Frequency Synthesis

Rev. 2.01
5
XR-2212

Phase
Detector 1
Input Vcc
Loop
Phase
Detector Reference
Output Output
16 Voltage
10 11
Signal
Input
2

30K 30K

Input Preamplifier Phase Detector Internal Voltage Reference

2K
2K VCO Non
Out Inv
Inp Amp
Timing A A1 Out
5 9
Capacitor 8
13 C0 3 Inv
14 VCO Inp
5K 5K Quad
A A1 Out VCO
7
15 Current
6
Output

Comp
5K 5K

Op Amp
Timing 4 GND
12
Resistor RO

Figure 4. Simplified Circuit Schematic of XR-2212

Rev. 2.01
6
 XR-2212
TYPICAL CHARACTERISTICS

20
10
R0=5k

15
Supply Current (mA)

RL = 5K R0=10k

RL = 10K

C 0 ( F )
10 R0=20k

RL > 100K 0.1
R0=40k

R0=80k

0 R0=160k

0.01
4 6 8 10 12 14 16 18 20 22 24
100 1000 10,000
Supply Voltage VCC (V)
f0 (Hz)

Figure 5. Typical Supply Current vs. Figure 6. VCO Frequency vs.

VCC (Logic Outputs Open Circuited) Timing Resistor

1000
1.02
C0=0.001F f0 = 1kHz
5
5 R > 10R0 1
1.01
Normalized Frequency

4
C0=0.0033F 2
C0=0.01F 3
1.00
R0 (k
)

4
100 3
C0=0.033F
0.99 CURVE R0
1 5K
2 2 10K
C0=0.1F 0.98 3 30K
4 100K
C0=0.33F 1 5 300K
0.97
10 4 6 8 10 12 14 16 18 20 22 24
0 1000 10,000
VCC (V)
f0 (Hz)

Figure 7. VCO Frequency vs. Figure 8. Typical f0 vs. Power

Timing Capacitor Supply Characteristics

Rev. 2.01
7
XR-2212

+1.0

Normalized Frequency Drift (% of f o )

R0=10K 1MΩ

+0.5
500K
R0=50K
0
R0=500K 50K

-0.5 VCC=12V 10K

R0=1MΩ R1=12R0
f0=1kHz
-1.0
-50 -25 0 25 50 75 100 125
Temperature (C)

Figure 9. Typical Center Frequency Drift vs. Temperature

DESCRIPTION OF CIRCUIT CONTROLS

Signal Input (Pin 2): Signal is AC coupled to this terminal. Op Amp Output (Pin 8): The op amp output is an open-
The internal impedance at Pin 2 is 20k
. Recommended collector type gain stage and requires a pull-up resistor,
input signal level is in the range of 10mV to 5V RL, to VCC for proper operation. For most applications, the
peak-to-peak. recommended value of RL is in 5k
to 10k
range.

VCO Current Output (Pin 3): This is a high impedance Phase Detector Output (Pin 10): This terminal provides
(M
) current output terminal which can provide +100A a high-impedance output for the loop phase-detector. The
drive capability with a voltage swing equal to VCC. This PLL loop filter is formed by R1 and C1 connected to Pin 10
output can directly interface with CMOS or NMOS logic (see Figure 3). With no input signal, or with no
families. phase-error within the PLL, the DC level at Pin 10 is very
nearly equal to VREF. The peak voltage swing available at
VCO Voltage Output (Pin 5): This terminal provides a the phase detector output is equal to $VREF.
low- impedance (
50
) buffered output for the VCO. It Reference Voltage, VREF (Pin 11): This pin is internally
can directly interface with low-power Schottley TTL. For biased at the reference voltage level. VREF:VREF = VCC/2
interfacing with standard TTL circuits, a 750
pull-down - 650mV. The DC voltage level at this pin forms an internal
resistor from Pin 5 to ground is required. For operation of reference for the voltage levels at Pins 10, 12 and 16. Pin
the PLL without an external divider, Pin 5 can be DC 1 must be bypassed to ground with a 0.1F capacitor, for
coupled to Pin 16. proper operation of the circuit.
VCO Control Input (Pin 12): VCO free-running
Op Amp Compensation (Pin 6): The op amp section is frequencies determined by external timing resistor, R0,
frequency compensated by connecting an external connected from this terminal to ground. For optimum
capacitor from Pin 6 to the amplifier output (Pin 8). For temperature stability, R0 must be in the range of 10K
to
unity-gain compensation a 20pF capacitor is 100k
(see Figure 9).
recommended. VCO Frequency Adjustment: VCO can be fine-tuned
Op Amp Inputs (Pins 7 and 9): These are the inverting by connecting a potentiometer, RX, in series with R0 at Pin
and the non-inverting inputs for the op amp section. The 12 (see Figure 11).
common-mode range of the op amp inputs is from +1V to This terminal is a low-impedance point, and is internally
(VCC - 1.5) volts. biased at a DC level equal to VREF. The maximum timing

Rev. 2.01
8
 XR-2212
current drawn from Pin 12 must be limited to <3 mA for is connected to this pin. The DC level of the sensing
proper operation of the circuit. threshold for the phase detector is referenced to VREF. If
VCO Timing Capacitor (Pins 13 and 14): VCO frequency the signal is capacitively coupled to Pin 16, then this pin
is inversely proportional to the external timing capacitor, must be biased from Pin 11, through an external resistor,
C0, connected across these terminals (see Figure 6). C0 RB (RB [ 10kW). The peak voltage swing applied to Pin
must be nonpolar, and in the range of 200pF to 10mF. 16 must not exceed (VCC - 1.5) volts.

VCO Quadrature Output (Pin 15): The low-level ([ PHASE-LOCKED LOOP PARAMETERS
0.6Vpp) output at this pin is at quadrature phase (i.e. 90°
phase-offset) with the other VCO outputs at Pins 3 and 5.
The DC level at Pin 15 is approximately 300mV above Transfer Characteristics
VREF. The quadrature output can be used with an external Figure 10 shows the basic frequency to voltage
multiplier as a “lock detect” circuit. In order not to degrade characteristics of XR-2212. With no input signal present,
oscillator performance, the output at Pin 15 must be filtered phase detector output voltage is approximately
buffered with an external high impedance low equal to the internal reference voltage, VREF at Pin 11.
capacitance amplifier. When not in use, Pin 15 should be The PLL can track an input signal over its tracking
left open-circuited. bandwidth, shown in the figure. The frequencies fTL and
Phase Detector Input (Pin 16): Voltage output of the fTH represent the lower and the upper edge of the tracking
VCO (Pin 5) or the output of an external frequency divider range, f0 represents the VCO center frequency.

Tracking
2VR Bandwidth
Df Df
Phase Detector Output (Pin 10)

VR

0
fTL fO fTH Frequency

Input Signal Frequency

Figure 10. Phase Detector Output Voltage (Pin 10) as a Function of Input Signal Frequency
Note
Output Voltage is Referenced to Internal Reference Voltage VREF at Pin 11

Rev. 2.01
9
XR-2212
Design Equations 8. Total Loop Gain, KT
(See Figure 3 and Figure 10 for definition of KT = 2pKO K0 = 4/C0R1 rad/sec/volt
components.)
9. Peak Phase-Detector Current, IA; available at Pin 10.
1. VCO Center Frequency, f0: f0 = 1/R0C0 Hz IA = VREF (volts)/25mA
2. Internal Reference Voltage, VREF (measured at
Pin 11) APPLICATION INFORMATION
VREF = VCC/2 - 650mV
3. Loop Low-Pass Filter Time Constant, t : t = R1C1
FM Demodulation
4. Loop Damping, j:

+ 0.25 Ǹ NC 0
C1
XR-2212 can be used as a linear FM demodulator for both
narrow-band and wide-band FM signals. The generalized
circuit connection for this application is shown in
Figure 11, where the VCO output (Pin 5) is directly
where N is the external frequency divider modular
connected to the phase detector input (Pin 16). The
(See 2). If no divider is used, N = 1.
demodulated signal is obtained at phase detector output
5. Loop Tracking Bandwidth, $Df/f0: Df/f0 = R0/R1 (Pin 10). In the circuit connection of Figure 10, the op amp
6. Phase Detector Conversion Gain, KO: (KO is the section of XR-2212 is used as a buffer amplifier to provide
differential DC voltage across Pins 10 and 11, per unit both additional voltage amplification as well as current
of phase error at phase-detector input) drive capability. Thus, the demodulated output signal
KO = -2VREF/p volts/radian available at the op amp output (Pin 8) is fully buffered from
the rest of the circuit.
7. VCO Conversion Gain, K0: (K0 is the amount of
change in VCO frequency, per unit of DC voltage In the circuit of Figure 11, R0C0 set the VCO center
change at Pin 10. It is the reciprocal of the slope of frequency, R1 sets the tracking bandwidth, C1 sets the
conversion characteristics shown in Figure 10). low-pass filter time constant. Op amp feedback resistors
K0 = -1/VREFC0R1 Hz/V RF and RC set the voltage gain of the amplifier section.

Rev. 2.01
10
 XR-2212

VCC

0.1mF
1 VCC 6 RL
30pF
2 10 5K
Phase 9 8
Detector Demod
0.1mF C1 7 Output
FM RF
Input 16
4
RC
11
Internal
Reference
0.1mF

R1
5 12
VCO

R0
14 13

CO

Rx Fine Tune

Figure 11. Circuit Connection for FM Demodulation

Design Instructions d) Choose R1 to determine the tracking bandwidth, Df

(see design equation 5). The tracking bandwidth, Df,
The circuit of Figure 11 can be tailored to any FM
should be set significantly wider than the maximum
demodulation application by a choice of the external
components R0, R1, RC, RF, C0 and C1. For a given FM input FM signal deviation, DfSM. Assuming the
center frequency and frequency deviation, the choice of tracking bandwidth to be “N” times larger than
these components can be calculated as follows, using the DfSM, one can re-unite design equation 5 as:
design equations and definitions given on page 10.
a) Choose VCO center frequency f0 to be the same as Df + R 0 + N Df SM
FM carrier frequency. f0 R1 f0
b) Choose value of timing resistor R0, to be in the range
of 10kW to 100kW. This choice is arbitrary. The Table 2. lists recommended values of N, for various
recommended value is R0 + 20kW. The final value values of the maximum deviation of the input FM
of R0 is normally fine-tuned with the series signal.
potentiometer, RX.
c) Calculate value of C0 from design equation (1) or from e) Calculate C1 to set loop damping (see design
Figure 7: equation 4). Normally, ς = 1/2 is recommended.
C0 = 1/R0f0 Then, C1 = C0/4 for ς = 1/2.

Rev. 2.01
11
XR-2212
% Deviation of FM Recommended Value of R0 /R1 = (3)(0.0746) = 0.224
Signal (DfSM/f0) Bandwidth Ratio, N or:
(N = Df/DfSM) R1 = 89.3kW.
1% or less 10 Step e): Calculate C1 = (C0 /4) = 186pF.
1% to 3% 5 Step f): Calculate RC and RF to get $4V peak
1% to 5% 4 output swing: Let RF = 100kW. Then,
5% to 10% 3 RC = 80.6kW.
10% to 30% 2 Note: All values except R0 can be rounded-off to nearest
30% to 50% 1.5 standard value.

FREQUENCY SYNTHESIS
Table 2.
Figure 12 shows the generalized circuit connection for
Recommended values of bandwidth ratio, N, for various frequency synthesis. In this application an external
values of FM signal frequency deviation. (Note: N is the frequency divider is connected between the VCO output
ratio of tracking bandwidth Df to max. signal frequency (Pin 5) and the phase-detector input (Pin 16). When the
deviation, DfSM). circuit is in lock, the two signals going into the
phase-detector are at the same frequency, or fS = f1/N
f) Calculate RC and RF to set peak output signal
where N is the modulus of the external frequency divider.
amplitude. Output signal amplitude, VOUT, is given
Conversely, the VCO output frequency, f1 is equal to NfS.
as:
In the circuit configuration of Figure 12, the external
VOUT + ǒDf Ǔ( V )ǒR ǓǒR ) R Ǔ
SM
REF
1 C F
timing components, R0 and C0, set the VCO free running
f
0 R 0 R C
frequency; R1 sets the tracking bandwidth and C1 sets the
In most applications, RF = 100kW is recommended; loop damping, i.e., the low-pass filter time constant (see
then RC, can be calculated from the above equation design equations).
to give desired output swing. The output amplifier can The total tracking range of the PLL (see Figure 10),
also be used as a unity-gain voltage follower, by open should be chosen to accommodate the lowest and the
circuiting RC (i.e., RC = ∞). highest frequency, fmax and fmin, to be synthesized. A
Note: All calculated component values except R0 can be
recommended choice for most applications is to choose a
rounded-off to the nearest standard value, and R0 can be
tracking half-bandwidth Df, such that:
varied to fine-tune center frequency, through a series Df
fmax - fmin
potentiometer, RX , (See Figure 11). If a variable input frequency and a variable counter
modulus N is used, then the maximum and the minimum
Design Example values of output frequency will be:
Demodulator for FM signal with 67kHz carrier frequency fmax = Nmax (fS )max and fmin = Nmin (fS )min
with $5kHz frequency deviation. Supply voltage is +12V If a fixed output frequency is desired, i.e. N and fS are
and required peak output swing is $4V. fixed, then a $10% tracking bandwidth is recommended.
Step a) f0 is chosen as 67kHz. Excessively large tracking bandwidth may cause the PLL
to lock on the harmonics of the input signals; and the small
Step b) Choose R0 = 20kW (18kW fixed resistor in tracking range increases the “lock-up” or acquisition time.
series with 5kW potentiometer).
Step c) Calculate C0; from design equation (1). Design Instructions
C0 = 746pF For a given performance requirement, the circuit of
Step d) Calculate R1. For given FM deviation, Figure 12 can be optimized as follows:
DfSM/f0 = 0.0746, and N = 3 from Table 2. a) Choose center frequency, f0, to be equal to the output
Then: frequency to be synthesized. If a range of output

Rev. 2.01
12
 XR-2212
frequencies is desired, set f0 to be at mid-point of the If a single fixed output frequency is desired, set R1 to
desired range. get:
b) Choose timing resistor R0 to be in the range of 15k
Df = 0.1 f0
to 100k
. This choice is arbitrary. R0 can be fine
tuned with a series potentiometer, RX. e) Calculate C1 to obtain desired loop damping. (See
design equation 4). For most applications, ς = 1/2 is
c) Choose timing capacitor, C0 from Figure 7 or
recommended, thus:
Equation 1.
d) Calculate R1 to set tracking bandwidth (see C0 = NC0 /4
Figure 10 and design equation 5). If a range of output Note
frequencies are desired, set R1 to get: All component values except R0 can be rounded off to the
Df = fmax - fmin nearest standard value.

VCC

0.1F

1 VCC 6
2 10
Phase 9 8
Detector
0.1F 7
Input C1
Signal
4 16

74LS90 11
or Internal
%N
Similar Reference

FO= F1/N 0.1F

Output R1
5 12
VCO
F1 = Nfs
R0
1K 14 13

CO

Figure 12. Circuit Connection for Frequency Synthesizer

Rev. 2.01
13
XR-2212
INPUT SENSITIVITY
The input to the XR-2212 may sometimes be too sensitive V IN minimum (peak) + V a–V b +
to noise conditions on the input line. Figure 13 illustrates
a method of de-sensitizing the XR-2212 from such noisy 20, 000
DV " 2.8V offset + VREF + or
line conditions by the use of a resistor, Rx, connected from (20, 000 ) RX)
pin 2 to ground. The value of Rx is chosen by the equation
and the desired minimum signal threshold level. ǒ
RX + 20, 000 VREF * 1
DV
Ǔ
VIN minimum (peak) input voltage must exceed this value
to be detected (equivalent to adjusting V threshold).

Vcc

To Phase
Detector
Input
ÎÎ 2
Va Vb

Rx 20K 20K

ÎÎ
ÎÎ
VREF 11

Figure 13. Desensitizing Input Stage

Rev. 2.01
14
 XR-2212

16 LEAD CERAMIC DUAL-IN-LINE

(300 MIL CDIP)
Rev. 1.00

16 9

1 8

D E1

Base A1
Plane A

Seating L
Plane
e c
B B1 α

INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX

A 0.100 0.200 2.54 5.08

A1 0.015 0.060 0.38 1.52
B 0.014 0.026 0.36 0.66
B1 0.045 0.065 1.14 1.65
c 0.008 0.018 0.20 0.46
D 0.740 0.840 18.80 21.34
E1 0.250 0.310 6.35 7.87
E 0.300 BSC 7.62 BSC
e 0.100 BSC 2.54 BSC
L 0.125 0.200 3.18 5.08
α 0° 15° 0° 15°
Note: The control dimension is the inch column

Rev. 2.01
15
XR-2212

16 LEAD PLASTIC DUAL-IN-LINE

(300 MIL PDIP)
Rev. 1.00

16 9
E1
1 8

D E

A2
Seating A
Plane L C
A1 α
B
e B1 eA
eB

INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX

A 0.145 0.210 3.68 5.33

A1 0.015 0.070 0.38 1.78
A2 0.115 0.195 2.92 4.95
B 0.014 0.024 0.36 0.56
B1 0.030 0.070 0.76 1.78
C 0.008 0.014 0.20 0.38
D 0.745 0.840 18.92 21.34
E 0.300 0.325 7.62 8.26
E1 0.240 0.280 6.10 7.11
e 0.100 BSC 2.54 BSC
eA 0.300 BSC 7.62 BSC
eB 0.310 0.430 7.87 10.92
L 0.115 0.160 2.92 4.06
α 0° 15° 0° 15°

Note: The control dimension is the inch column

Rev. 2.01
16
 XR-2212

Notes

Rev. 2.01
17
XR-2212

Notes

Rev. 2.01
18
 XR-2212

Notes

Rev. 2.01
19
XR-2212

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.

Copyright 1979 EXAR Corporation

Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Rev. 2.01
20