Verilog Creating Analog Behavioral Models
Verilog Creating Analog Behavioral Models
February 2003
TABLE OF CONTENTS
Incisive Verification Platform ........................................................................................................................................1
2 Introduction ..................................................................................................................................................................1
8 References ................................................................................................................................................................22
CADENCE INCISIVE VERIFICATION PLATFORM
Verifying today’s complex ICs requires the speed and efficiency that can be provided only in a unified verification
methodology. The Cadence Incisive™ verification platform enables the development of a unified methodology from system
design to system design-in for all design domains. A unified verification methodology consists of many different tools,
technologies and processes all working together in a common environment. The Incisive verification platform provides the
tools, technologies, a common user environment, and the support needed to develop a unified methodology. This
application note details specific topics for using the tools and technologies in the Incisive platform to help create a unified
methodology to verify your design.
2 INTRODUCTION
Analog Behavioral Modeling deals with creating and simulating models based on a desired external circuit behavior. Models
are best used to represent circuit block behavior and not simply replicate individual transistor characteristics. Models can be
as complex as necessary. Often, initial behavioral models need to carry only the basic properties, such as an operational
amplifier might have voltage swings, impedances, and gain. In other cases, there might be a need to model slew rates,
differential signals and bandwidth properties. Adjustable parameters can be added to model and preview design tradeoffs in
a circuit. The more complex a model is, the more impact it will have on the simulation time and convergence. It is important
to consider what tradeoffs are important and necessary before starting to write a model. Creating a detailed macro-model is
often an important first step in determining what to model, rather than using a trial and error approach. There are six main
reasons to consider modeling:
• Design exploration
• Verify connectivity
• Verify functionality
• Speed up simulations
• Reuse in future designs
• To create a portable design IP
Modeling is best when used early in the design cycle.
Analog behavioral modeling is part of a wider design methodology called “top-down design.” This may seem obvious, but
there are a number of aspects that require careful consideration to take full advantage of modeling. Top-down design starts
with creating a hierarchical design. This is a common design practice today, especially for large designs. However, the key
is to make all circuit blocks in the hierarchy pin-to-pin compatible so that each can be represented by either a model or an
actual transistor-level circuit block. Later, the views can be toggled between model and transistor for mixed-level simulation.
One of the biggest advantages of using modeling is to take well-behaved transistor-level circuit blocks that are slow to
simulate, and switch them to a model to shorten simulation time. Sub-circuit blocks not in the signal path, such as PLLs, lend
themselves well to being run as a model because they have well-behaved feedback properties. In other cases, modeling the
entire design might be of interest to run system-like simulations for architectural exploration while designing the IC. With
hierarchical design, it is possible to create models at any level of the hierarchy. Generally, the higher the level of modeling,
the faster the simulation runs. In addition, it is also possible to represent digital functional and behavioral models in Verilog-
A. Where there is only a small number of digital blocks, it is advantageous to represent these in Verilog-A. This cuts down
on the overhead of having a mixed-mode simulator. In other cases, where there is a large Verilog-A, models lend
themselves well to creating basic signal sources and measurement blocks in testbenches. This is especially true for wireless
systems where pseudo-random signal sources can be easily set up and where measurement blocks can calculate Bit Error
Rates (BER) or plot Eye Diagrams after a long simulation.
Another important aspect of modeling is “bottom-up” modeling—taking finished transistor-level circuit block results and
exactly modeling them. This may require some effort and characterization. Sometimes the behavioral model is simply a
1. Differentiator: ddt(x)
- Time derivative of its argument Example: Basic Sinusoidal VCO
- For second derivative, use ! y = ddt(x), then z = ddt(y)
module vco(out,in);
voltage out,in;
2. Integrator: idt(x) parameter real k = 1M;
- Time integral of its argument, with optional initial condition real phase, freq;
Example: y = idt(x) + c;
analog begin
freq = k*V(in);
3. Circular Integrator: idtmod(x) example phase = idtmod(freq,0,1);
- Time integral of its argument, passed through a V(out) <+ cos(2*`M_PI*phase);
modulus operation $bound_step(1/(10*freq));
end
- Periodic integration
endmodule
endmodule
analog begin
@(cross(V(ref)), +1)
if (state > -1) state = state – 1;
@(cross(V(vco)), +1)
if (state < 1) state = state +1;
I(out) <+ transition(Iout*state);
end
endmodule
1. If-else: The If-else is a binary conditional set of statements under control of specified conditional expressions.
if (expression1) statement1;
else if (expression2) statement2;
else statement3;
Example:
if (x >= 1) y = 3;
else if (x <= 1) y = 2;
else y = 1;
Result: y is binned between 1, 2, and 3 dependent on x
2. The case expression controls of a series of statements to run depending on what the expression is equal to.
case (expression)
value1: statement1;
value2: statement2;
value3: statement3;
default: statement;
endcase
Example:
y = 2;
case(y)
1 : x = 5;
2 : x = 1;
default : y = 10;
endcase
Result: case 2 is selected where x=1
3. The repeat loop statement runs for a fixed number of times as determined by the constant_value.
repeat (constant_value) statement;
Example: repeat (5) begin I = I + 1; total = total + 1; end
Result: The loop will repeat 5 times and total will = 5.
4. The while loop statement is used when you want to leave the loop when an expression is no longer valid.
while (expression) statement;
Example: while (x>y) begin count = count + 1; end
Result: Conditionally, when x is greater than y, count will increment 1 each time.
2. $discontinuity(): Used to make a model discontinuity at current point. A discontinuity(0) announces a discontinuity in a
descriptive equation. A discontinuity(1) indicates a discontinuity in the first derivative (slope) of the equation.
Examples:
analog begin
@(timer(0, wavelength)) begin
slope = +1;
wstart = $abstime;
discontinuity(1) " “1” done for a negative to positive slope change
end
analog
@(cross(V(pin, nin) – 1, 0.01n) discontinuity (0); " “0” used in an equation
3. $abstime, $temperature, $vt, $vt(): These are environment functions that provide information about the current
simulation environment.
Examples:
therm_volt = `P_K * $temperature / (`P_Q * emis_coef); //ambient temperature in degees Kelvin
V(out) <+ sin (2 * `M_PI * freq * $abstime); // at current simulation time
$strobe(“Simulation time = %e”, $abstime); // at current simulation time
thermal_voltage = $vt; // at current simulation temperature
vt_temp = $vt(76); //thermal voltage at 76 degees Kelvin
5. $bound_step(): Limits the timestep for the simulation, but does not force a point at any particular time.
Example: $bound_step(10n);
Icubefn(x,100K)
sinefn(x)
cubefn(x)
It is important to limit the timestep and frequency where there are fast transitions (<1pS), or high pole frequencies (>1THz)
which will cause very tiny timesteps and long simulation times. Consider realistic rise and fall times (>1nS) and bandwidth
responses (<10MHz), which may help reduce the simulation time. It is possible that just one circuit block with a high
frequency oscillation can have a dramatic impact, pulling the whole simulation down. Timestep and breakpoint controls can
also be helpful improving the waveshaping accuracy. Both time and voltage tolerances can also be used to window-in
thresholds and avoid overstepping sharp nonlinearities. This is explained in detail in the Verilog-A user’s guide.
An example of timestep and breakpoint controls:
1. Input threshold detection: @(cross(expression, direction, time_tolerance, voltage_tolerance)) statement;
2. DC state & transient edge: @(above(expression, time_tolerance, voltage_tolerance)) statement;
3. Output timestep control: @(timer(next_time)) statement; or $bound_step(time_increment);
The modeling of a switch is a good example whether to use a sharp or smooth transition. When
a switch is ideal, it could cause trouble working correctly in all conditions. A good practice is to
include realistic effects for impedances and sweep characteristics. Table 1, below, shows some
of the tradeoffs.
power supply
In+
INPUT Gain Output OUTPUT
In-
VREF
TRANSFER
Cubic
Clipped
Ideal
Digital
Hyperbolic
Tangent
A = `clip(40*Vin,-9,9);
B = fcube(40*Vin,-9,9);
Ideal C = ftanh(40*Vin,-9,9);
Analog All three functions
output center for
input zero
When passing the signal to the output of a model, it is almost always necessary to use a transition statement, which in some
cases makes it easier for the simulator to converge on a solution. The transition statement can work from a discrete digital
input and waveshape. The delay, rise, and fall times can be added, which will define the digital signal at the output in an
analog simulation.
Vout = $transition(Vin,Td,Tr,Tf);
Vin Vout
Td Tr Td Tf
Transient output waveshaping can be done with RC and the Laplace transfer.
Ro Co
V1/Ro
RoCo
Vin Vout
SRpos SRneg
The output can be expressed as resistance or conductance, and DC and impedance characteristics can be defined.
Separate active and saturated resistance can aid in shaping the output. By using a ftanh() function as described can limit the
input current. An `fclip function can, as defined, produce well-defined diode-like voltage limiting, with zero voltage at isat. A
capacitor can be added for simple pole low-pass response. Limiting the current driving the capacitor can act as slew rate
limiting. The DC active region output resistance is Ro+Rac, and saturated and AC output resistance is Rac.
isat
R C
isat/100 V
-dV 0
I(cur) <+ ftanh(-Vnom/Ro,Isat,-Isat);
real Ro, Co, Isat, Vnom; // establish internal variables used in expressions
analog function real ftanh; // define a tanh function for output smoothing
input x,L,H; real x,L,H,dv;
begin
dv=(H-L) / 2;
ftanh = L+ dv*(1+ tanh(x/dv));
end
endfunction
analog begin
@(initial_step) begin // to establish initial fixed constants
Ro = Rdc-Rac;
Co = 1/(`M_TWO_PI*Ro*GBW/Gain);
Isat = Co*SR;
end
end
endmodule
RL Vcc
RH=big
Vee
Resistors for
Low Output Vo = Vee
// Given relative output level of Kout = 0 to 1.
// Gx term allows additional current at midpoint.
Gx = Kout*(1-Kout)*Ipk/VpsNOM+1n; RL=Rol
I(VCC,Y) <+ V(VCC,Y)*(Kout/Roh+Gx); Vee
I(Y,VEE) <+ V(Y,VEE)*(1-Kout)/Rol+Gx);
There are other effects that can also be modeled, such as additional enable control pins, input impedance and range
limitations, power supply current, parametric supply variations, response to common mode or supply interference, power-on
or off conditions, and warning messages to indicate invalid operating regions. There are many choices as far as specialized
effects to model. But, with complexity, there are tradeoffs. For example, output impedances modeled in a nonlinear fashion
may decrease simulation efficiency. This may also involve more time to develop, extract parameters, and simulate. One
must decide what level of modeling is needed and what is not important. If necessary, you can create both simple and
complex models.
4.4 Modelwriter
Modelwriter is a model utility that is menu driven and allows ready use of a generic model that can be parameterized, placed
in the schematic, and used. There are 11 Cadence library categories:
• Analog Models
• Components
• Continuous Time
• Discrete Time
• Instruments
• Interface
• OpAmp Models
• PLL Components
• Sources
• System Level
• Telecom
module counter4
(result, clock, asynch_reset);
input asynch_reset, clock;
output [3:0] result; // Output is a 4-bit bus (MSB:LSB)
reg [3:0] result;
initial result = 1'b0;
always @ (posedge clock or // Execute code whenever either leading
posedge asynch_reset) begin // edge is detected.
if (asynch_reset) result = 1'b0;
else if (result == 4'd15) result = 1'b0;
else result = result + 1'b1; // Arithmetic operation on bus value
Count4bit
Outputs
VIN
With Incisive-AMS there is a closer connection between the analog and digital solver. In the past, the interprocess
communication (IPC) with Verimix™ was slower and limited.
8 REFERENCES
[1] Ron Vogelsong. AMS Behavioral Modeling Workshop, Cadence User’s Group Meeting, 2002.
[2] Analog Modeling with Verilog-A, Training Manual 4.4.6, Cadence Educational Services, 2001
[3] Dan Fitzpatrick, et al. Analog Behavioral Modeling with the Verilog-A Language, Kluwer, 1998.