Computers and Processors: Reference Manual

T224
Computers and processors

Reference manual
Author: Mirabelle Walker
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First published 2005. Second edition 2007.
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SUP 964145
2.1
Contents
1 The simulated processor 5
1.1 Overview 5
1.2 Registers 5
1.3 Instruction set 5
1.4 Description of the instructions 9
1.5 Interrupt mechanism 17
2 Memory associated with the simulated processor 19
3 Input–output associated with the simulated processor 20
3.1 Overview 20
3.2 Description of the input–output facilities 21
4 The simulation environment 24
4.1 The program editor 24
4.2 The program memory 26
4.3 The registers 26
4.4 The data memory 26
4.5 The menus 27
Appendix: ASCII codes 31
Important
You will be required to take this reference manual into the T224
examination with you, and when you do so it must be free of all
notes and/or highlighting. Therefore do not write in it or highlight
anything while you are studying the course.
Section 1: The simulated processor 5
1 The simulated processor
1.1 Overview
The simulated processor has a load–store, Harvard architecture.
It is essentially a 16-bit machine, in that all the general-purpose registers
are 16-bit, as are the data and address buses to data memory and the
address bus to program memory. The exception is the data bus between
the processor and program memory, which is 24 bits wide because the
instruction codes are all 24-bit.
It uses memory-mapped input–output.
It offers a two-level interrupt-handling facility.
1.2 Registers
The simulated processor has 17 registers (see Figure 1):
l 14 general-purpose registers, each 16 bits wide
l 1 instruction pointer (IP), 16 bits wide
l 1 stack pointer (SP), 16 bits wide
l 1 status register, 16 bits wide but only the least-significant 4 bits
are used.
The 14 general-purpose registers are known, using the hexadecimal

numbering system, as Register r1, Register r2, Register r3, up to
Register rE.
Register rF can act as a fifteenth general-purpose register when the stack
is not being used, but otherwise is the stack pointer.
The status register has four flags: negative flag (N); zero flag (Z);
interrupt 1 flag (IF1); interrupt 2 flag (IF2). The interrupt flags are
implemented only on the extended version of the simulated processor.
1.3 Instruction set

The simulated processor offers eight data-move instructions, eleven
arithmetic/logic instructions and nine control instructions. It is completely
symmetric across all fourteen general-purpose registers; that is, any of
these fourteen registers may be used in any instruction which refers to
registers.
In Tables 1 and 2, ‘R’ refers to a register, labelled with a suffix if more
than one is referenced, and ‘nnnn’ refers to a 2-byte hexadecimal address
or data item.
6 Computers and processors: Reference manual
16 bits
r1
r2
r3
r4
r5
r6
14 general-purpose r7
registers
r8
r9
rA
rB
rC
rD
rE
stack pointer SP (can also function as

general-purpose register rF)
instruction pointer IP
status register
4 bits
Figure 1 The programmer’s model of the simulated processor

Table 1 The instruction set in alphabetical order

Instruction Instruction code
(hexadecimal)
add immediate ARnnnn

add register 020R1R2R3
AND immediate CRnnnn
AND register 040R1R2R3
call absolute 85nnnn
complement register 05000R
copy register 2A00R1R2
jump absolute 81nnnn
jump if negative relative 83nnnn
jump if zero relative 84nnnn
jump relative 82nnnn
load direct ERnnnn
load immediate DRnnnn
load register-indirect 2E00R1R2
no-op 000000
OR immediate 9Rnnnn
OR register 010R1R2R3
pop register 26000R
push register 250R00
return 860000
return from interrupt 870000
shift left register 06000R
shift right register 07000R
stop 880000
store direct FRnnnn
store register-indirect 2F0R1R20
subtract immediate BRnnnn
subtract register 030R1R2R3
Table 2 The instruction set in instruction-code order

Instruction code Instruction
(hexadecimal)
000000 no-op
010R1R2R3 OR register
020R1R2R3 add register
030R1R2R3 subtract register
040R1R2R3 AND register
05000R complement register
06000R shift left register
07000R shift right register
250R00 push register
26000R pop register
2A00R1R2 copy register
2E00R1R2 load register-indirect
2F0R1R20 store register-indirect
81nnnn jump absolute
82nnnn jump relative
83nnnn jump if negative relative
84nnnn jump if zero relative
85nnnn call absolute
860000 return
870000 return from interrupt
880000 stop
9Rnnnn OR immediate
ARnnnn add immediate
BRnnnn subtract immediate
CRnnnn AND immediate
DRnnnn load immediate
ERnnnn load direct
FRnnnn store direct
1.4 Description of the instructions
add immediate
Hexadecimal instruction code
ARnnnn
Assembly language equivalent

add immediate rR nnnn
Actions
l Increase the instruction pointer’s contents by 1.
l Add the value nnnn to the contents of Register rR and put the result
in Register rR.
l Set the zero flag if the result is 0; otherwise clear the zero flag.
l Set the negative flag if the most-significant bit of the result is 1;
otherwise clear the negative flag.
add register
020R1R2R3

add register rR1 rR2 rR3
Actions
l Add the contents of Register rR1 to the contents of Register rR2 and
put the result in Register rR3 (it is permissible for R3 to be the same as
R1 or R2).
AND immediate
CRnnnn

AND immediate rR nnnn
Actions
l Perform an AND operation between the value nnnn and the contents
of Register rR and put the result in Register rR.
AND register
040R1R2R3

AND register rR1 rR2 rR3
Actions
l Perform an AND operation between the contents of Register rR1 and
the contents of Register rR2 and put the result in Register rR3 (it is
permissible for R3 to be the same as R1 or R2).
call absolute
85nnnn

call absolute nnnn
Actions
l Copy the new contents of the instruction pointer into the location in
data memory whose address is in the stack pointer.
l Increase the stack pointer’s contents by 1.
l Put nnnn into the instruction pointer.
l Do not change the zero or negative flags.
complement register
05000R

complement register rR
Actions
l Complement the contents of Register rR.
copy register
2A00R1R2

copy register rR1 rR2
Actions
l Copy the contents of Register rR1 into Register rR2.

jump absolute
81nnnn

jump absolute nnnn
Actions
l Put nnnn into the instruction pointer.
jump if negative relative

83nnnn

jump if negative relative nnnn
Actions
If the negative flag is set to 1
l Add nnnn to the incremented contents of the instruction pointer and
put the result in the instruction pointer.
If the negative flag is cleared to 0

jump if zero relative

84nnnn

jump if zero relative nnnn
Actions
If the zero flag is set to 1
If the zero flag is cleared to 0

jump relative
82nnnn

jump relative nnnn
Actions
load direct
ERnnnn

load direct rR nnnn
Actions
l Copy the contents of the location in data memory whose address is
nnnn into Register rR.
load immediate
DRnnnn

load immediate rR nnnn
Actions
l Load the value nnnn into Register rR.
load register-indirect
2E00R1R2

load register-indirect via rR1 rR2
Actions
l Copy the contents of the location in data memory whose address

corresponds to the contents of Register rR1 into Register rR2.
no-op
000000

no-op
Actions
OR immediate
9Rnnnn

OR immediate rR nnnn
Actions
l Perform an OR operation between the value nnnn and the contents

of Register rR and put the result in Register rR.
OR register
010R1R2R3

OR register rR1 rR2 rR3
Actions
l Perform an OR operation between the contents of Register rR1 and

the contents of Register rR2 and put the result in Register rR3 (it is
permissible for R3 to be the same as R1 or R2).
pop register
26000R

pop register rR
Actions
l Decrease the stack pointer’s contents by 1.
in the stack pointer into Register rR.
push register
250R00

push register rR
Actions
l Copy the contents of Register rR into the location in data memory
whose address is in the stack pointer.
l Increase the stack pointer’s contents by 1.
return
860000

return
Actions
in the stack pointer into the instruction pointer.
return from interrupt

This instruction is available only in the extended version of the
simulated processor.
870000

return from interrupt
Actions

in the stack pointer into the instruction pointer.
in the stack pointer into the status register.
shift left register

06000R

shift left register rR
Actions
l Shift the contents of register rR one bit to the left (towards the most-
significant bit); fill the least-significant bit with 0.
shift right register

07000R

shift right register rR
Actions
l Shift the contents of register rR one bit to the right (towards the least-
significant bit); fill the most-significant bit with 0.
l Clear the negative flag.
stop
880000

stop
Actions
l Halt execution of the processor.
store direct
FRnnnn

store direct rR nnnn
Actions
l Copy the contents of Register rR into the location in data memory
whose address is nnnn.
store register-indirect
2F0R1R20

store register-indirect via rR1 rR2
Actions
l Copy the contents of Register rR2 into the location in data memory
whose address corresponds to the contents of Register rR1.
subtract immediate
BRnnnn

subtract immediate rR nnnn
Actions
l Subtract the value nnnn from the contents of Register rR and put the
result in Register rR.

subtract register
030R1R2R3

subtract register rR1 rR2 rR3
Actions
l Subtract the contents of Register rR1 from the contents of Register rR2
and put the result in Register rR3 (it is permissible for R3 to be the
same as R1 or R2).
1.5 Interrupt mechanism

The interrupt facilities are available only in the extended version of the
simulated processor.
There are two levels of interrupt, Interrupt 1 and Interrupt 2. Interrupt 1
has the higher priority.
The interrupt vector for Interrupt 1 is at 0FFF and has default value 0D00.
The interrupt vector for Interrupt 2 is at 0FFE and has default value 0E00.
Both of these default values can be changed by the user.
Interrupt flags IF1 and IF2 in the processor’s status register indicate
whether Interrupt 1 and Interrupt 2 respectively are enabled. An interrupt
can only be taken if it is enabled – that is, its flag is set to 1. Further, an
interrupt on Interrupt 2 can only be taken if both interrupts are enabled.
When an interrupt occurs on Interrupt 1, then at the start of the next
fetch–execute sequence the processor will automatically and in this order:
l save the status register’s contents on the stack;
l clear both IF1 and IF2 to 0;
l save the instruction pointer’s contents on the stack;
l set the instruction pointer to the value of the interrupt vector for
Interrupt 1.
The procedure is similar for an interrupt on Interrupt 2, except that only

IF2 is cleared to 0 and that the instruction pointer is set to the value of
the interrupt vector for Interrupt 2.
The interrupt service routines for both Interrupt 1 and Interrupt 2 must
end with a return from interrupt instruction.
When an input device causes an interrupt its status register is

automatically set to 1. The program needs to clear the register to 0 after
the interrupt has been serviced.
More than one device can be assigned to Interrupt 1 simultaneously. In
such cases, software must be used to determine the priority of the
devices within the interrupt service routine. Similarly, more than one
device can be assigned to Interrupt 2 simultaneously.
Section 2: Memory associated with the simulated processor 19
2 Memory associated with

the simulated processor
In the simulation, the processor has been implemented with 4096 (4K)
16-bit locations of data memory. These locations have hexadecimal
addresses 0000 to 0FFF inclusive.
The simulated processor has also been implemented with 4096 (4K)
24-bit locations of program memory. These locations have hexadecimal
addresses 0000 to 0FFF inclusive.
In the extended version of the simulated processor, data memory
addresses 0F00 to 0FFF (hexadecimal) are reserved for the memory-
mapped addresses of status and data registers relating to input and output
devices.
3 Input–output associated
with the simulated
processor
The input–output facilities are available only in the extended version of
the simulated processor.
3.1 Overview
In the simulation, the processor is implemented with the following input
devices:
l a bank of 8 switches
l a ‘scalepan’ input
l an interrupt button
and with the following output devices:

l a bank of 8 light-emitting diodes
l a simple 4-digit 7-segment display
l a ‘smart’ 4-digit 7-segment display
l a buzzer
l an analogue gauge.
Table 3 shows the memory-mapped addresses for these devices’ registers.

Table 3 Memory-mapped addresses for the registers in the input and
output devices
Device Register Memory-mapped address
simple 4-digit 7-segment data 0F00 (least-significant digit)

display to 0F03 (most-significant
digit)
‘smart’ 4-digit 7-segment data 0F04
display
buzzer data 0F05
bank of 8 light-emitting diodes data 0F06
analogue gauge data 0F07
interrupt button status 0F10
scalepan data 0F11
scalepan status 0F12
bank of 8 switches data 0F13
bank of 8 switches status 0F14
The processor offers two levels of interrupt, Interrupt 1 and Interrupt 2.

Interrupt 1 has the higher priority.
Section 3: Input–output associated with the simulated processor 21
3.2 Description of the input–output facilities
Bank of 8 switches (input)

By selecting the ‘hardware’ tab for this device, the user can set each
switch independently to ‘on’ (up) or ‘off’ (down) by clicking on it.
Data register
Memory-mapped address 0F13.
Only the least-significant eight bits are used, with the least-significant bit
corresponding to the rightmost switch.
1 corresponds to ‘on’ and 0 to ‘off’.
Status register
The least-significant bit is set to 1 when an interrupt (see below) has
occurred.
Interrupt facility
This facility can be switched on (activated) or switched off, using the
‘properties’ tab. The default setting is off.
When the interrupt facility is on, an interrupt is caused when any one of
the switches changes its state.
Using the ‘properties’ tab, the switch bank’s input can be set up to cause
an interrupt on either Interrupt 1 or Interrupt 2. The default setting for
the interrupt facility is Interrupt 1.
When an interrupt occurs, the status register is set to 0001.
Scalepan (input)
By selecting the ‘hardware’ tab for this device, the user can duplicate the
effects of placing different weights in the scalepan by clicking with the
mouse to move the scalepan up or down.
Data register
The contents are set to the digital equivalent of the vertical position of
the scalepan, with 0000 corresponding to the highest position.
In 3-bit mode (see below) the three least-significant bits of the data
register are used; in 8-bit mode the eight least-significant bits are used.
Status register
The least-significant bit is set to 1 when an interrupt (see below) has
occurred.
Interrupt facility
This facility can be switched on (activated) or switched off, using the
‘properties’ tab. The default setting is off.
When the interrupt facility is on, this device causes an interrupt on

Interrupt 2.
3-bit and 8-bit working

By selecting the ‘properties’ tab, the user can choose between 3-bit and
8-bit working modes. In 3-bit mode the analogue position of the scalepan
is converted into a 3-bit binary representation before being stored in the
data register; in 8-bit mode the analogue position of the scalepan is
converted into an 8-bit binary representation.
The default setting is 8-bit working.
Interrupt button (input)

Clicking on this button causes an interrupt on Interrupt 1.
Status register
Bank of 8 light-emitting diodes (output)

Each of these lights can be independently lit by setting the corresponding
bit in the data register to 1.
Data register
Only the least-significant eight bits are used, with the least-significant bit
corresponding to the rightmost LED.
1 corresponds to ‘on’ and 0 to ‘off’.
Simple 4-digit 7-segment display (output)

Each of the segments in each 7-segment display can be independently lit
by setting the appropriate bit in the appropriate data register to 1.
bit 7 Data registers

Memory-mapped addresses 0F00 to 0F03; the base address is 0F00.
bit 6 bit 5
bit 4 0F00 is used for the least-significant, rightmost, digit of the display and
0F03 for the most-significant, leftmost, digit.
bit 3 bit 2
In each of these registers, bits correspond to segments as shown in
Figure 2.
bit 1 bit 0
‘Smart’ 4-digit 7-segment display (output)
Figure 2 The
relationship between the This device takes the value in its data register and converts it to either the
segments and the bits of denary equivalent or the hexadecimal equivalent, as chosen by the user,
the data registers before displaying it on the four 7-segment displays.
Section 3: Input–output associated with the simulated processor 23
Leading zeros are inserted for hexadecimal displays, but not for denary
ones. The error message ‘Err’ is displayed if denary mode has been
chosen and the binary number in the data register is greater than denary
9999.
Data register
Denary and hexadecimal modes

These are selected by the user via the ‘properties’ tab. The default is
denary mode.
Buzzer (output)
This device buzzes when the least-significant bit of its data register is set
to 1. It is silent when the least-significant bit of its data register is cleared
to 0. There is also an associated on-screen graphic.
Data register
Analogue gauge (output)

This device takes the value in its data register and displays it on a
horizontal analogue scale.
Data register
Only the least-significant eight bits are used, so only values from 0000 to
00FF can be displayed correctly (higher values are displayed as if they
were 00FF).
4 The simulation
environment
4.1 The program editor

The Program editor window is shown in Figure 3. This window can be
re-sized vertically and/or moved around the screen using the mouse.
A duplicate of the window can be opened via the View menu, thus
enabling the user to work with two different program fragments
simultaneously.
Figure 3 The Program editor window
IP field
The leftmost field of the window, IP, shows a c symbol alongside the
address corresponding to the instruction pointer’s contents. By double-
clicking in this field alongside a different address, the user can move the
highlight and also change the instruction pointer’s contents to that
address.
Address and Contents fields

The next two fields of the window, Address and Contents, show the
address and the contents respectively of locations in the program
memory. The default contents are 000000, which correspond to the
no-op instruction.
Instruction field
The rightmost field of the window, Instruction, shows the instruction
corresponding to the adjacent instruction code in the Contents field. The
user can change this instruction by first double-clicking on the instruction
Section 4: The simulation environment 25
already present and then either single-clicking on items in the drop down
menus (using the t symbol to open the menus where necessary) or
typing in a hexadecimal number, as appropriate. A double-click will
terminate the entry at any time.
The instructions can be edited using the cut, copy and paste facilities in
the Edit menu.
Single instructions or blocks of instructions can be deleted by first
highlighting the instruction or instructions and then cutting. No-op
instructions replace the cut instructions.
Single instructions can be moved from one location to another by first
highlighting the instruction, then cutting, then clicking on the line where
the instruction is to go, then pasting.
Blocks of instructions can be moved by first highlighting them, then
cutting, then clicking on the first line where the instructions are to go,
then pasting.
Individual instructions or blocks of instructions can also be copied and
pasted elsewhere in program memory.
All instructions can be simultaneously changed to no-ops by selecting
Reset from the Options menu and then selecting Program memory. This
action clears the contents of all locations in program memory to 000000.
Run button
By clicking on the Run button at the bottom of the window, the user
causes the simulated processor to execute instructions, starting with the
one in the location whose address is in the instruction pointer. While the
processor is running in this way, the Run button becomes a Stop button
and clicking on this button stops the processor.
Step button
By clicking on the Step button at the bottom of the window, the user
causes the simulated processor to execute the instruction in the location
whose address is in the instruction pointer.
Trace button
By clicking on the Trace button at the bottom of the window, the user causes
the simulated processor to execute instructions, starting with the one in the
location whose address is in the instruction pointer. This execution is
sufficiently slow that the user can follow what is happening, and the trace
speed can be set to Fast, Medium or Slow from the Options menu. The
default is Fast. While the processor is tracing in this way, the Trace button
becomes a Stop button and clicking on this button stops the processor.
Go to IP button
Clicking on the Go to IP button at the bottom of the window causes the
Program editor window to scroll to show a block of program memory
which includes the location whose address is currently in the instruction
pointer.
Go to button
Clicking on the Go to button at the bottom of the window opens a
dialogue box which prompts the user to enter an address in program
memory; the Program editor window then scrolls to show the contents of
locations at and near that address.
4.2 The program memory

The Program memory window is shown in Figure 4. This window can be
resized vertically and/or moved around the screen using the mouse.
The default contents of all locations in program memory are 000000. The
user can return the contents of all locations to this default value by
selecting Reset from the Options menu and then selecting Program
memory. This action also changes all instructions in the Instruction field
of the Program editor window to no-ops.
The user cannot alter the contents of individual locations in program
memory via the Program memory window; all changes to individual
locations in program memory must be made by entering, deleting or
moving instructions in the Instruction field in the Program editor.
Figure 4 The Program Clicking on the Go to button at the bottom of the window opens a
memory window dialogue box which prompts the user to enter an address in program
memory; the Program memory window then scrolls to show that address.
4.3 The registers

The Registers window is shown in Figure 5. This window can be moved
around the screen using the mouse.
The default contents of all registers are 0000, except for the stack pointer,
whose default contents are 0800. The user can return the contents to
these default values at any time by selecting Reset from the Options
menu and then selecting Registers.
The user can alter the contents of any of Registers r1 to rE, along with the
stack pointer (Register rF) and the instruction pointer, by double-clicking
in the Contents field alongside them and then entering the new contents
and pressing Enter.
The current contents of the status register are indicated by four flags at
the bottom of the Registers window: N (negative); Z (zero); IF1
(interrupt 1); IF2 (interrupt 2). A tick indicates that the flag’s value is 1; a
blank indicates that it is zero. Only the negative and zero flags are shown
in the basic version of the simulated processor.
Flags are set or cleared by the processor during normal program
operation. The user can also set or clear flags while testing a program, by
clicking under N, Z, IF1 or IF2 as appropriate.
4.4 The data memory

The Data memory window is shown in Figure 6. This window can be
re-sized vertically and/or moved around the screen using the mouse.
A duplicate of the window can be opened via the View menu, thus
enabling the user to view two different blocks of data simultaneously.
Figure 5 The Registers window: (a) in the basic simulated processor; (b) in the
extended simulated processor
The default contents of all locations in data memory are 0000. The user
can return the contents of all locations to this default value by selecting
Reset from the Options menu and then selecting Data memory.
The user can alter the contents of any location in data memory by
double-clicking in the Contents field alongside the address of that
location and then entering the new contents and pressing Enter.
The contents can be edited using the cut, copy and paste facilities in the
Edit menu.
Blocks of data can be deleted by first highlighting them in the Contents
field and then cutting. The contents of these locations become 0000.
Blocks of data can be moved by first highlighting them in the Contents
field, then cutting, then clicking in the Contents field alongside the first
address which is to hold the data block, then pasting.
Data can also be copied and pasted elsewhere in program memory. Figure 6 The Data
memory window
Clicking on the Go to button at the bottom of the window opens a
dialogue box which prompts the user to enter an address in data
memory; the Data memory window then scrolls to show that address.
4.5 The menus
The File menu
Open
This allows the user to open an existing file, which will contain a
program and associated data memory contents and register contents.
The default sub-folder the first time the Open command is chosen is the
CT programs sub-folder. This sub-folder will have been created as part of
the software installation process and resides within the hierarchy of
folders My Documents\T224\Simulated processor\ unless stipulated
otherwise by the user during the installation process. CT programs
remains the default sub-folder for the Open command until the user
opens a program from another sub-folder.
When the new program and data are loaded, any previous instructions,
data values and register contents which the user may have been working
with are lost. Hence the user is prompted, where necessary, to save any
work before the new program is loaded.
Merge
This brings in a program from a specified file and appends it to the
program already in the program memory and shown in the Program
editor window. If the new program and the existing program have
instructions in the same locations(s) in program memory, the instructions
in the new program will overwrite the instructions in the existing
program in those locations.
Merge also brings in any associated data and appends it to the data
already in the data memory. If the new program and the existing
program have associated data in the same locations(s) in data memory,
the data associated with the new program will overwrite the data
associated with the existing program in those locations.
The registers are not affected by the Merge command.
If appropriate, the user is prompted to save any work before the new
program is merged.
Save
If a program was retrieved from the CT programs sub-folder, it is
necessary to use the Save As option to save it to another folder (thus
preventing programs supplied by the course team from being
overwritten).
Otherwise, Save saves the program and associated data memory contents
and register contents with the same file name as the file from which they
were retrieved, thus over-writing the previously saved version of the
program, data memory and register contents.
Save As
This opens a dialogue box so that the user can enter the new file name
and/or choose a new folder. The default sub-folder the first time the
command is chosen is My programs, which will be in My
Documents\T224\Simulated processor\ unless stipulated otherwise by
the user during the installation process. Save As then saves the program
and associated data memory contents and register contents.
Save As does not allow files to be saved to the CT programs sub-folder.
Save workspace
This allows the user to save the current size and window arrangement of
the simulated processor screen. These then become the default.
Print
This allows the user to print the contents either of the currently
highlighted window or of all windows. Except in the case of the registers,
it does not print out any details for locations whose contents are zero.
When ‘print all’ is selected, the contents of the Program memory window
are not printed, as this would duplicate what is shown in the contents of
the Program editor window.
Exit
This closes the simulation program. If appropriate, it prompts the user to
save the current program first.
The Edit menu
Cut
This allows highlighted instructions in the Program editor or highlighted
contents in the Data memory to be cut.
Copy
This allows highlighted instructions in the Program editor or highlighted
contents in the Data memory to be copied.
Paste
This allows cut or copied instructions from the Program editor to be
inserted where the user clicks. In the case of a block of instructions, the
block will be inserted such that the first instruction goes where the user
clicks.
Paste also allows cut or copied contents in the Data memory to be
inserted where the user clicks. In the case of a block of data, the block
will be inserted such that the first data item goes where the user clicks.
The Options menu
Reset
This allows the user to reset any of: Data memory; Program memory;
Registers. In the extended version of the simulation it also allows the user
to reset the Interrupt system. All of these can also be reset
simultaneously. The user is asked to confirm the reset before it is
implemented.
Reset returns the chosen entity to the state it has when the simulation is
first opened.
Set trace speed

This allows the user to select from Fast, Medium or Slow for the trace
speed. The default is Fast.
The View menu

This allows the user to open new Program editor and Data memory
windows. If any of the four default windows has been closed, View
allows the user to open it again.
The Devices menu

This menu is available only in the extended version of the simulation.
Input devices
This allows the user to open Scalepan, Switch bank or Interrupt button.
It is possible to have more than one copy of the windows for these
devices open simultaneously.
Output devices
This allows the user to open LED bank, Analogue gauge, Simple
7-segment display, Smart 7-segment display or Buzzer.
It is possible to have more than one copy of the windows for these
devices open simultaneously.
The Help menu

This takes the user to an electronic version of this Reference Manual via a
hyperlinked contents page.
Appendix: ASCII codes
ASCII
Character Binary code Hexadecimal code Denary code

null 000 0000 00 0
backspace 000 1000 08 8
horizontal tab 000 1001 09 9
line feed 000 1010 0A 10
carriage return 000 1101 0D 13
escape 001 1011 1B 27
space 010 0000 20 32
! 010 0001 21 33
" 010 0010 22 34
# 010 0011 23 35
$ 010 0100 24 36
% 010 0101 25 37
& 010 0110 26 38
’ 010 0111 27 39
( 010 1000 28 40
) 010 1001 29 41
* 010 1010 2A 42
+ 010 1011 2B 43
, 010 1100 2C 44
- 010 1101 2D 45
. 010 1110 2E 46
/ 010 1111 2F 47
0 011 0000 30 48
1 011 0001 31 49
2 011 0010 32 50
3 011 0011 33 51
4 011 0100 34 52
5 011 0101 35 53
6 011 0110 36 54
7 011 0111 37 55
8 011 1000 38 56
9 011 1001 39 57
: 011 1010 3A 58
; 011 1011 3B 59
< 011 1100 3C 60
= 011 1101 3D 61
> 011 1110 3E 62
? 011 1111 3F 63
@ 100 0000 40 64
A 100 0001 41 65
B 100 0010 42 66
C 100 0011 43 67
D 100 0100 44 68
E 100 0101 45 69
F 100 0110 46 70
G 100 0111 47 71
H 100 1000 48 72
I 100 1001 49 73
J 100 1010 4A 74
K 100 1011 4B 75
L 100 1100 4C 76
M 100 1101 4D 77
N 100 1110 4E 78
O 100 1111 4F 79
P 101 0000 50 80
Q 101 0001 51 81
R 101 0010 52 82
S 101 0011 53 83
T 101 0100 54 84
U 101 0101 55 85
V 101 0110 56 86
W 101 0111 57 87
X 101 1000 58 88
Y 101 1001 59 89
Z 101 1010 5A 90
[ 101 1011 5B 91
\ 101 1100 5C 92
] 101 1101 5D 93
^ 101 1110 5E 94
_ 101 1111 5F 95
‘ 110 0000 60 96
a 110 0001 61 97
b 110 0010 62 98
c 110 0011 63 99
d 110 0100 64 100
e 110 0101 65 101
f 110 0110 66 102
g 110 0111 67 103
h 110 1000 68 104
i 110 1001 69 105
j 110 1010 6A 106
k 110 1011 6B 107
l 110 1100 6C 108
m 110 1101 6D 109
n 110 1110 6E 110
o 110 1111 6F 111
p 111 0000 70 112
q 111 0001 71 113
r 111 0010 72 114
s 111 0011 73 115
t 111 0100 74 116
u 111 0101 75 117
v 111 0110 76 118
w 111 0111 77 119
x 111 1000 78 120
y 111 1001 79 121
z 111 1010 7A 122
{ 111 1011 7B 123
|
| 111 1100 7C 124
} 111 1101 7D 125
~ 111 1110 7E 126
delete 111 1111 7F 127
Course team list
Academic staff
Bernie Clark, Production Course Chair
Geoff Einon
David Gorham, Presentation Course Chair
Reza Latif-Shabgahi
Mike Meade
Tony Nixon
Adrian Poulton
Richard Seaton
Mirabelle Walker
Production staff
Deirdre Bethune, Course Secretary
Colin Bluck, Project Officer
Philippa Broadbent, Buyer, Materials Procurement
Roger Courthold, Graphic Artist
Sarah Crompton, Graphic Designer
Daphne Cross, Assistant Buyer, Materials Procurement
Tony Duggan, Learning Projects Manager
Joanne Fellows, QA Engineer
Alison George, Project Manager
David Gosnell, Software Designer
Roger Harris, Production Course Manager
Lori Johnston, Editor
Karen Lemmon, Compositor
Deborah Mairs, Presentation Course Manager
Jane Moore, Editor
Jon Owen, Graphic Artist
Val Price, Rights Executive
Colin Thomas, Software Designer

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T224

Computers and processors

The Open University

1 The simulated processor

The 14 general-purpose registers are known, using the hexadecimal

1.3 Instruction set

stack pointer SP (can also function as

Figure 1 The programmer’s model of the simulated processor

Table 1 The instruction set in alphabetical order

add immediate ARnnnn

Table 2 The instruction set in instruction-code order

1.4 Description of the instructions

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

l Copy the contents of Register rR1 into Register rR2.

Assembly language equivalent

l Do not change the zero or negative ﬂags.

jump if negative relative

Assembly language equivalent

If the negative ﬂag is cleared to 0

jump if zero relative

Assembly language equivalent

If the zero ﬂag is cleared to 0

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

l Copy the contents of the location in data memory whose address

Assembly language equivalent

Assembly language equivalent

l Perform an OR operation between the value nnnn and the contents

Assembly language equivalent

l Perform an OR operation between the contents of Register rR1 and

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

return from interrupt

Assembly language equivalent

l Copy the contents of the location in data memory whose address is

shift left register

Assembly language equivalent

shift right register

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

Assembly language equivalent

l Set the negative ﬂag if the most-signiﬁcant bit of the result is 1;

Assembly language equivalent

1.5 Interrupt mechanism

The procedure is similar for an interrupt on Interrupt 2, except that only

When an input device causes an interrupt its status register is

2 Memory associated with

and with the following output devices:

Table 3 shows the memory-mapped addresses for these devices’ registers.

simple 4-digit 7-segment data 0F00 (least-signiﬁcant digit)

The processor offers two levels of interrupt, Interrupt 1 and Interrupt 2.

3.2 Description of the input–output facilities