This article has been accepted for inclusion in a future issue of this journal.

Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON ADVANCED PACKAGING 1

Is 25 Gb/s On-Board Signaling Viable?

Dong G. Kam, Member, IEEE, Mark B. Ritter, Troy J. Beukema, John F. Bulzacchelli, Member, IEEE,
Petar K. Pepeljugoski, Senior Member, IEEE, Young H. Kwark, Lei Shan, Xiaoxiong Gu,
Christian W. Baks, Richard A. John, Gareth Hougham, Christian Schuster, Senior Member, IEEE,
Renato Rimolo-Donadio, Student Member, IEEE, and Boping Wu, Student Member, IEEE

Abstract—What package improvements are required for dense,

high-aggregate bandwidth buses running at data rates beyond
10 Gb/s per channel, and when might optical interconnects on
the board be required? We present a study of distance and speed
limits for electrical on-board module-to-module links with an
eye to answering these questions. Hardware-validated models of
advanced organic modules and printed circuit boards were used to
explore these limits. Simulations of link performance performed
with an internal link modeling tool allowed us to explore the effect
of equalization and modulation formats at different data rates on
link bit error rate and eye opening. Our link models have been
validated with active, high-speed differential bus measurements
utilizing a 16-channel link chip with programmable equalization
and a per-channel data rate of up to 11 Gb/s. Electrical signaling
limits were then determined by extrapolating these hardware-cor-
related models to higher speeds, and these limits were compared
to the results of recent work on on-board optical interconnects.
Index Terms—Channel equalization, electrical signaling limit,
high-speed bus measurement, high-speed serial link, link modeling,
multilevel signaling.
Fig. 1. Multitiered approach required to solve high-speed link challenges.

I. INTRODUCTION

FF-CHIP bandwidth requirements continue to grow of data rates while overcoming the limitations of the given in-
O to meet the needs of server and storage consolidation,
interprocessor communication, and multicore processor ar-
tegrated circuit (IC) technology [3]. As a result, deep submi-
cron complementary metal–oxide–semiconductor (CMOS) I/O
chitectures [1]. Early work on the Optical Internetworking circuits can function at higher speeds than the channel band-
Forum’s (OIF’s) Common Electrical Interface (CEI-25) stan- width will support [4]. High-speed link design has striven to
dard, aimed at specifying a parallel 20–25 Gb/s electrical increase the link throughput by using signal processing tech-
interface for next generation 40 or 100 Gb/s optical modules, niques commonly used for communication over bandwidth-lim-
has shown that legacy channels are inadequate at speeds beyond ited channels. Pre-emphasis can be used to flatten the steep
17–20 Gb/s [2]. At the same time, future high-port-count roll-off of the channel’s insertion loss, and adaptive equaliza-
switches and high-end servers will require hundreds to thou- tion to remove intersymbol interference (ISI) [5]. Alternative
sands of electrical links running at speeds of 10+ Gb/s to meet multilevel signaling schemes have also received much attention
rising bandwidth demands. of late because they reduce channel bandwidth requirements at
For the last decade, electrical input/output (I/O) research has the cost of signal-to-noise ratio (SNR) [6], [7]. These techniques
focused on improving transceiver circuits to sustain the growth have extended the reach and speed of electrical links, allowing
10 Gb/s on-board links to span up to 75 cm [7]–[9]. Be-
cause electrical signaling rates are reaching practical equaliza-
Manuscript received May 19, 2008; revised November 12, 2008. This work
was supported in part by DARPA, under the IBM Contract HR0011-06-C-0074. tion limits, such high-speed link designs must trade-off the cost
This work was recommended for publication by Associate Editor W. Beyene of improved electrical package elements against increased cir-
upon evaluation of the reviewers comments. cuit area and higher power consumption required by advanced
D. G. Kam, M. B. Ritter, T. J. Beukema, J. F. Bulzacchelli, P. K. Pepeljugoski,
Y. H. Kwark, L. Shan, X. Gu, C. W. Baks, R. A. John, and G. Hougham are equalization. To extend link reach, package designers are con-
with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA sidering the possibility of using low-loss dielectrics, smooth
(email: [email protected]; [email protected]). copper, innovative via-hole techniques, and new connector tech-
C. Schuster and R. Rimolo-Donadio are with the Technical University of
Hamburg-Harburg, D-21073 Hamburg, Germany. nologies [10], [11]. Fig. 1 presents an overview of high-speed
B. Wu is with the Department of Electrical Engineering, University of Wash- link system design. Circuit designers, package designers, and
ington, Seattle, WA 98195 USA. system architects need to work close together to solve system in-
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. terconnect challenges. An accurate link modeling methodology
Digital Object Identifier 10.1109/TADVP.2008.2011138 is essential to this multitiered approach in that one cannot make
1521-3323/$25.00 © 2009 IEEE

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

2 IEEE TRANSACTIONS ON ADVANCED PACKAGING

Fig. 2. Description of link which was studied.

rational trade-offs until each solution’s effect on the overall link land grid array (LGA) sockets for the BGA solder connection
performance is analyzed quantitatively. was also investigated. This chip is a product-level version of the
With this background, one may ask: “Is 25 Gb/s per channel prototype described in [15]. The organic chip packages mea-
on-board electrical signaling viable? What package improve- sured 35 mm 35 mm with an 8-4-8 layer stack-up. Advanced,
ments are required to make it happen, and when might optical reduced-stub Nelco4000-13 and Megtron6 PCBs were built at a
interconnects on the board be required?” We have been inves- total thickness of 4.7 mm with “reverse side treated” copper
tigating the limits of electrical and optical interconnect perfor- foils (the 10 point average surface roughness, )
mance of future advanced packaging technologies with an eye and “profile free” copper layers , respectively.
to answering these questions. Although another study [12] has These packaging options were chosen because they balance the
focused on two modules connected by flex, our study explores need for high-performance designs and materials against prac-
module-on-board packaging topologies seen in switches and tical manufacturing and availability concerns for those solu-
servers where more than two modules are connected via high- tions. The testbed hardware was partitioned into a large area
aggregate-bandwidth buses utilizing a dense signal pitch which low-cost motherboard which fed power, control, and clocking
maximizes escape bandwidth while maintaining adequate signal to a much smaller daughtercard through HMZd mezzanine con-
integrity. A wide variety of high-performance links has been an- nectors. This small-footprint daughtercard allowed a wide va-
alyzed from a holistic standpoint, considering I/O circuits and riety of bus topologies to be fabricated on a single state-of-
equalization, and including all levels of electrical packaging. the-art high-speed panel. By running the differential transmis-
We describe the link configurations and packaging tech- sion lines in a serpentine fashion, we were able to design 15,
nologies aimed at this application space, then show how each 30, 45, and 60 cm PCB transmission line lengths on a common
element in the electrical link was modeled, followed by model coupon size and a variety of near-end crosstalk (NEXT) and
validation against passive hardware measurements. We then far-end crosstalk (FEXT) configurations to explore link perfor-
present active link measurements at 11 Gb/s and show the mance for various aggressor geometries.
correlation with end-to-end link simulations. We use these Correspondingly, the main channel model elements can be
hardware-correlated models in simulations to predict the per- identified as shown in Fig. 2 (bottom). Instead of trying to ob-
formance of dense buses running at 25 Gb/s rates, and we tain one comprehensive model for the entire signal path, in-
compare this to recent work [13], [14] on on-board optical dividual blocks were modeled separately and the end-to-end
channel S-parameters were obtained by concatenating the in-
interconnects. Finally, we discuss maximum achievable data
dividual channel components. These interfaces were located at
rates, module escape bandwidth limits, and communication
stripline boundaries where signal propagation is mostly trans-
metrics with an eye to providing system and chip designers in-
verse electromagnetic (TEM) mode. While a comprehensive
sight into system bandwidth bottlenecks and trade-offs between
end-to-end channel modeling is the most accurate approach, it
electrical and optical on-board technologies.
is also computationally the most inefficient. The different fea-
II. PASSIVE LINK MODELING ture sizes in modules and PCB, the high aspect ratio of the PCB
transmission lines, and the sheer size of the model pose serious
A. Link Description and Modeling Approach problems for any rigorous full-wave simulation. In addition,
The on-board interconnects studied in this paper include two even small variations (e.g., in the via diameter) would require
90-nm CMOS link chips in organic flip-chip plastic ball grid a full rerun. On the other hand, the partitioning of the full link
array (FCPBGA) packages mounted on a printed circuit board into smaller blocks allows the following:
(PCB) through ball grid array (BGA) solder joints (or sockets), 1) application of specialized solvers for each problem type
as shown in Fig. 2 (top). The effect of substituting three different and hence an overall reduction in the computational effort;

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

KAM et al.: IS 25 Gb/s ON-BOARD SIGNALING VIABLE? 3

Fig. 3. Module cross section showing C4 escape (left), core vias, and BGA
(right) with eight differential pairs.

Fig. 4. PCB BGA via escape area showing differential pairs escaping on two
wiring layers with a 2:1 signal-to-reference ratio (left), with a cross-section view
2) fast parametric variations; showing the 24-layer board (right). Eight of these pairs were used in generating
3) a wide range of link topologies to be quickly constructed a 32-port via model for crosstalk analysis.
from a single model library;
4) assessment of the impact of the electrical performance of
C. PCB Via Array Models
individual blocks;
5) direct comparison of modeled blocks with measured data. The board consisted of two (top and bottom) Megtron6 di-
Full-wave simulations of the package elements including electric subcomposites which were then laminated. Each sub-
NEXT and FEXT were concatenated to create S-parameter composite had six signal layers and six power/ground layers.
models of the entire signal path. Full coupling of eight differ- Signal vias were drilled and plated to form half- and full-length
ential pairs was maintained throughout the signal path to allow vias. Half-length vias (vias through the top subcomposite) had a
exploration of different NEXT and FEXT package pin and via via drill diameter of 150 , a pad diameter of 450 , an an-
arrangements. As our link chips had 16 differential transmitters tipad diameter of 700 , and a pitch of 1 mm. The full-length
and 16 receivers, we created 32-port S-parameter models for vias had a via drill diameter of 200 , a pad diameter of
a number of aggressor situations, simulating near-neighbor 500 , an antipad diameter of 750 , and a pitch of 1 mm.
pairs relevant to the NEXT or FEXT aggressor arrangements For power/ground vias, the drill diameter was 200 . The di-
we wished to explore. Some models, particularly the PCB via electric constant of Megtron6 is 3.5. The total thickness of the
arrays beneath the modules, required up to five days CPU time board was 4.7 mm.
to create (using AMD Opteron 2220 SE 2.8 GHz, 2 1 MB We modeled the PCB vias area underneath the module BGA
L2 cache, 24 GB DDR2 memory); therefore, we employed a where striplines pass through the via field in order to analyze
“Distributed Solve” full-wave simulation tool [16] to reduce NEXT and FEXT among neighboring channels. Specifically, to
simulation time to approximately one day. These models were model FEXT of neighboring channels, we included eight pairs
placed in an interconnect element library, and concatenated by of vias connecting eight transmitters (or receivers) in one model.
our link analysis tool for active link simulation. Similarly, to model NEXT of neighboring channels of one link
chip, four transmit and four receive via pairs were modeled.
In either case, we employed 32-port via models for crosstalk
B. Organic Module Models
analysis.
Eight adjacent differential pairs were selected to capture Fig. 4 shows a top view of such a 32-port via model used to
the channel-to-channel crosstalk. The in-package link was model FEXT in the PCB via field for eight differential trans-
segmented into three sections and modeled with the full-wave mitter channels. In this case, the signal-to-reference ratio was
solver. The first section includes controlled collapse chip 2:1. Three-dimensional via geometries were extracted from the
connection (C4) pads, vias, and escape wiring, as shown in board layout file, then imported and analyzed using the full-
Fig. 3 (left). Power/ground pads were parallel to the row of wave solver up to 35 GHz.
signal pads for worst case analysis of 2:1 signal-to-reference
pin ratio at a 200- pitch. Vias in the buildup layers had a D. PCB Transmission Line Models
drill diameter of 60 , a pad diameter of 100 , an antipad An internal 2.5-dimensional tool, CZ2D [17], was used to
diameter of 225 , and a pitch of 200 . The second section create length scalable models of eight differential pairs with full
included 10–15-mm-long coupled differential lines with 25 coupling and geometries based on measured cross-sections of
line widths and 50 spacing, with 300 pair-to-pair transmission lines of Nelco4000-13 or Megtron6 subcomposite
separation. The third section included short transmission lines cards. An RLGC model was first created which could then be
and vias for connections to BGA pads as shown in Fig. 3 used to quickly generate S-parameters for coupled transmission
(right). Vias in the core layers were 150 in drill diameter, lines of the desired length. Accurate data for the transmission
350 in pad diameter, 500 in antipad diameter, 500 line segments on the PCB were obtained separately using the
in pitch, and 650 in length. The BGA pads are on a 1-mm recessed probe launch technique described in [18]. Transmis-
pitch and arranged in a 2:1 signal-to-reference ratio pattern. sion line test coupons with recessed probe launch structures
The dielectric constant is 3.4 in the buildup layers with a loss were designed into each advanced PCB panel. A frequency-de-
tangent of 0.017 at 1 GHz. The dielectric constant of the core pendent effective loss tangent was extracted by fitting RLGC
layers is 4.2 with a loss tangent of 0.02 at 1 GHz. models to the transmission line coupon measurements. Fig. 5

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

4 IEEE TRANSACTIONS ON ADVANCED PACKAGING

Fig. 6. Complete end-to-end passive link measurement on modules soldered to

Megtron6 daughter card.

Fig. 5. Representative measured insertion loss (top) and extracted loss tangent
(bottom) for Megtron6 striplines. Fig. 7. Passive channel simulations for channel comprised of two organic mod-
ules and 45-cm PCB transmission lines agree with VNA measurements to within
6 1.2 dB to 20 GHz.
shows model-hardware correlation for layers S3 and S7 which
have different transmission line widths (see inset at bottom
for the measured cross-section geometries of the transmission up to 10 GHz, and within 1.2 dB up to 20 GHz. Much of
lines). The frequency-dependent effective loss tangent, which the residual ripple in the measured data was due to coupling
accounts for surface roughness induced loss in addition to to adjacent transmission lines which could not be terminated
dielectric loss, was fed back into the transmission line model in the measurement as they were too numerous. When we
generation methodology to assure accuracy. measured the same channel with neighboring nets terminated
by 47- surface mount technology (SMT) chip resistors, the
E. Validation of Modeling Approach discrepancy went away.
Verification of the various elements of the package simula-
tions relied on S-parameter measurements taken with a 4-port III. ACTIVE LINK MODELING
50-GHz vector network analyzer (VNA) using RF microprobes. A. Active Link Characterization
Measurements were also taken at the BGA pad level on the PCB;
additional measurements with unpopulated FCPBGA modules The measurements on the end-to-end active link were per-
soldered onto the BGA pads provided full end-to-end measure- formed using the setup shown in Fig. 8 and schematically in
ments of the passive link as shown in Fig. 6. On-chip parasitics Fig. 2. The heart of the testbed consists of the link chip and
such as pad and electrostatic discharge (ESD) circuit capaci- the physical implementation of the high-speed links with ad-
tances (380 fF, in total) were incorporated into the full link sim- vanced organic modules and various PCB technologies. The rest
ulation as a 4-port S-parameter model. of the hardware provides support to make the links functional.
The segmented package models described above were con- On each end of the link we used the same 90-nm CMOS pro-
catenated using the Agilent ADS tool [19]. Fig. 7 compares grammable 3-tap feed-forward equalizer (FFE) and 5-tap de-
a link comprised of two organic modules and 45-cm-long cision-feedback equalizer (DFE) link chip [15], providing up
Megtron6 striplines to VNA measurements of this channel. to 16 full duplex channels. The signaling rate could be varied
The modeled S-parameters show good correlation with the from 7 to 11 Gb/s, primarily limited by the tuning range of the
VNA measurements, agreeing to within 1.0 dB at frequencies on-chip phase-locked loops (PLLs). By current standards, the

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

KAM et al.: IS 25 Gb/s ON-BOARD SIGNALING VIABLE? 5

Fig. 8. Hardware testbed design.

link chip hardware does not dissipate much power. Since only
the cores relevant to 7–11 Gb/s operation need to be powered
on, the overall dissipation can be kept within 10 W. As shown
in Fig. 8, fans were used on top of the modules since this power Fig. 9. Block diagram of adaptive iterative algorithm for FFE tap settings.
level is too high for simple passive cooling solutions without
a large area penalty (recall the areal cost of the daughtercard
is prohibitive). Preliminary sizings using a test heater module
instrumented with a thermocouple were used to determine an
adequate cooling solution. The link chip temperature was mon-
itored with an on-die temperature sensor. By exercising judi-
cious power control, the chip temperature can be kept below
50 during full link testing. The link chip utilizes many sep-
arate power domains to reduce overall power dissipation and
to maximize flexibility in exploring chip performance. A high- Fig. 10. A is a measure of the ISI.
density power supply rack solution provided eight independent
power banks with individual over-current and over-voltage set-
tings for each bank. Reference clocks are needed to drive the the link simulation package, and then adjusting the FFE taps
on-chip PLLs. Clock boards were designed to provide refer- to check if optimal values have been found.
ence clocks that could be driven from external synthesizers or Due to the number of links, link topologies, lengths, advanced
from a pair of on-board low phase noise precision temperature PCB materials, and link conditions (e.g., variable amount of
controlled crystal oscillators (TCXOs). The frequencies of the crosstalk), it was not possible to manually perform the optimiza-
TCXOs were deliberately offset by 200 ppm so that the phase tion of the FFE taps as there are a total of 4608 combinations. In-
rotators on the clock and data recovery (CDR) circuits aver- stead we customized a link adaptation algorithm [20] and modi-
aged over all phase positions to result in better averaging of eye fied the control software to allow full measurement automation.
parameters. A general block diagram of an adaptive iterative algorithm to
The chip had a slow-speed communication channel, allowing optimize the link is shown in Fig. 9. The chip supplies several
for full programmability of either the transmitter or receiver. In link performance measures that each alone or in combination
addition, the chip had a variety of registers that contained link can be used as a cost function. We used the following:
quality indicators and stored the state of various chip blocks. 1) —the inner eye opening at a bit error rate (BER) of
Reading and writing to the chip registers was achieved through 10 (error rate set by on-chip counters), as illustrated in
software that allowed automated control and data collection. Fig. 10. The measurement is a raw number, and it is then
In the configuration shown in Fig. 8, it is necessary to opti- normalized with (which is the mean eye height),
mize the link performance by selecting optimal FFE and DFE 2) Eye width—the edge-to-edge eye width at the same 10
tap coefficients. The DFE tap coefficients were optimized using BER,
an algorithm built into the on-chip logic, which relies on link 3) Error count.
quality indicators that are continuously updated. Typical exper-
iments involved setting the FFE tap coefficients, then allowing B. End-to-End Active Link Modeling and Validation
the receiver adaptation logic to find the best DFE coefficients. An internal link modeling tool, HSSCDR [21], was used to
The process was aided by a link simulation package, which simulate link performance given various crosstalk and channel
helped choose the best FFE tap coefficients. This required con- impediments. These simulations employed behavioral models
stant validation of the hardware environment, porting it into of the link chip I/O circuits including transmitter FFE, receiver

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

6 IEEE TRANSACTIONS ON ADVANCED PACKAGING

Fig. 12. Good model-hardware correlation was observed for the active links.
Note that correlation is given for a variety of channels (labeled 0–3) with dif-
ferent equalization settings and link distances (45 or 60 cm Megtron6 transmis-
sion lines with 2:1 signal-to-reference ratio).

1 Mbit/min. The LTI model is an accurate representation of the

drivers employed in these link chips, and, of course, the channel
is linear and time invariant. Traditional SPICE-based transient
simulation methods are orders of magnitude slower than this
and cannot accurately capture low-probability events and CDR
dynamics without prohibitively long simulation times.
In Fig. 12 we show the good model-hardware correlation ob-
tained at 11 Gb/s for a variety of links with 45 and 60 cm PCB
transmission lines and with different types of equalization. Also
shown in the figure are four different electrical channels, la-
beled 0 through 3, which had different aggressor geometries.
The black diamond curve is data measured with the active link
chips via the digital interface, the green triangle curve shows
link simulations with full-wave concatenated channel models,
and the red square curve shows link simulations using measured
S-parameters.
Measurement with BGA socketed hardware was also con-
ducted, and the performance at 11 Gb/s was as good as sol-
dered modules. Additionally, measurements were carried out
using three different types of LGA socket held at various pres-
Fig. 11. A sampling of link insertion loss of various interconnect channels on
sures. In all cases performance at 11 Gb/s was at least as good as
either Nelco4000-13 (top) or Megtron6 (middle) with 2:1 signal-to-reference BGA modules once a pressure threshold for each was reached
ratio, studied in this paper. The bottom figure compares the power sum of all where all contacts were electrically closed. This threshold pres-
crosstalk aggressors of a 90-cm Megtron6 channel with 2:1 signal-to-reference
ratio to that of the same length channel with 4:1 signal-to-reference ratio.
sure varied across LGA manufacturers from 10 to 60 g/contact.

IV. EXPLORATION OF MODULATION SCHEMES

DFE, as well as transmitter and receiver contributions to sinu- Good model-hardware correlation and flexible simulation and
soidal, random, and deterministic jitter. Channel behavior was measurement setups have allowed us to explore the performance
captured in 32-port S-parameters, which included all crosstalk of other modulation schemes in order to determine the best mod-
terms for eight differential pairs through the entire packaging ulation format to maximize electrical signaling rates.
path. Fig. 11 shows a sampling of link insertion loss and
crosstalk of various interconnect channels studied in this paper. A. Multilevel I/O Models
In the bottom figure, signal-to-crosstalk ratio, , is Duobinary signaling [7] can be generated by sending non-re-
defined as a ratio of signal attenuation to the power sum of all turn-to-zero (NRZ) data through a delay and sum filter, which
crosstalk aggressors at the frequency of half a given baud rate has a Z-transform of . Since the frequency response
(5 GHz for 10 Gb/s signaling is given as an example here). of a typical backplane channel resembles this, if we provide
The behavioral simulation is based on a linear time-invariant some additional filtering we can generate the required response
(LTI) channel assumption, enabling fast convolution algorithms from the cascade of the filter and the channel. In our link mod-
to be employed which result in simulation speed on the order of eling, the reshaping filter was implemented using a transmitter

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

KAM et al.: IS 25 Gb/s ON-BOARD SIGNALING VIABLE? 7

Fig. 13. 11 Gb/s duobinary eye patterns generated by the link chip (left) shows good correlation with eye diagrams generated using our link models (right).

FFE. Optimal tap coefficients were determined by a minimum

mean-square error (MMSE) optimization routine, carried out in
the time domain. The minimization constraints were error at the
edge crossing and error at the data sample point. Duobinary sig-
naling can be viewed as NRZ signaling with a 100 % ISI from
the previous bit, so it can be decoded with a two-level NRZ par-
tial-response DFE [22].
Fig. 13 (left) shows that we were able to program the link
chip to perform duobinary signaling. In order to see if we can
match the appearance of the eye diagrams generated using our
link models, the S-parameters of a link connecting the output
of the transmitter to a digital sampling oscilloscope were mea-
sured [2]. An eye diagram was generated using the measured
S-parameters and our link models including core parameters and Fig. 14. Simulated vertical (solid curves, left axis) and horizontal eye openings
FFE tap coefficients used for the duobinary measurements, as (dashed, right axis) for different modulations at a raw throughput (before modu-
shown in Fig. 13 (right). Although this comparison is incom- lation) of 25 Gb/s for different PCB transmission line lengths (x-axis). For links
longer than 60 cm, all three signaling methods produced closed eyes.
plete in that the impulse response of the oscilloscope sampler
should be considered as well, the two eye diagrams show sat-
isfactory correlation. Separately, a four-level pulse-amplitude postcursors, and a 5-tap half-rate DFE were assumed for all
modulation (PAM4) [6] I/O model was also developed, and the three signaling options, the launch was 800 differential,
two I/O models were compared to NRZ signaling for different and the bit stream was a pseudo random binary sequence
link lengths and data rates. (PRBS). Both vertical and horizontal eye openings at a BER
of 10 were computed, and the results are shown in Fig. 14.
B. Signaling Comparison Analysis Note that the vertical eye opening does not extrapolate to the 800
The good model-to-hardware correlation found in our test re- launch swing for very short PCB links because the auto-
sults gave us confidence that we could extrapolate our simula- matic gain control (AGC) loop of the receiver attenuates such
tions to explore signaling rates beyond 11 Gb/s and distances large input signals to maintain linearity. Representative eye di-
greater than 60 cm. Each channel model in Fig. 11 was simu- agrams and bathtub curves of each signaling method are shown
lated using the I/O core models which were linearly scaled to 2x in Fig. 15.
frequency to estimate performance at higher data rates. The si- These link simulations show that NRZ signaling with FFE
nusoidal (or deterministic) jitter (SJ) and the random (or nonde- and DFE equalization was superior in performance to either
terministic) jitter (RJ) of the 11 Gb/s link chip transmitter and re- duobinary or PAM4 coding, with the latter showing the poorest
ceiver clocks were approximately 5% unit interval peak-to-peak performance for the channels considered. Using an eye opening
and 0.7% , respectively, resulting in 1% metric requiring 30 mV vertical eye opening and 0.3 UI hori-
clock RJ and 10% clock SJ for the complete asynchronous zontal eye opening (12 ps), our models predict a maximum reach
link. For rate scaling, the jitter terms were modeled as a con- of 45 cm for 25 Gb/s NRZ modulation.
stant percentage of UI. The rate-scaled core models also in- In Fig. 16 we show a contour plot of data rate and link reach
corporated a T-coil network [23] to resonate out ESD capaci- for each modulation type using this eye opening metric. We con-
tance. A 4-tap symbol-spaced FFE with one precursor and two clude that, even with the best signaling scheme, it will be diffi-

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON ADVANCED PACKAGING

Fig. 15. Representative simulated eye diagrams and bathtub curves of signaling comparison analysis at a raw throughput (before modulation) of 25 Gb/s for 30 cm
(left) and 60 cm (right) channels on Megtron6 having 2:1 signal-to-reference ratio.

cult to design dense 25 Gb/s electrical links with a reach greater vantage over the others for application in a range of 25 Gb/s test
than 45 cm without wider lines and/or lower loss materials than channels.
those used in this study, and that NRZ modulation with FFE and
DFE equalization provides the greatest signaling rate at all dis- C. Conventional Wisdom of Multilevel Signaling Revisited
tances we studied. A PAM4 transceiver divides a signal into four levels, which
Although the data presented here does not necessarily repre- can be seen as three stacked eye patterns for every cycle. These
sent the optimum achievable system performance for each sig- are encoded as 00, 01, 10, and 11, allowing two bits to be en-
naling method, we believe the results present a fair relative per- coded for every symbol time. As a result, the symbol rate with
formance assessment of each line signaling approach within a PAM4 is half that of NRZ, so the signal suffers less attenua-
consistent equalization/modeling framework. The resulting data tion. The multilevel nature of PAM4 reduces the level spacing
are useful to determine if one signaling format has a clear ad- by a factor of three (9.5 dB). The common rationale is that if

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

KAM et al.: IS 25 Gb/s ON-BOARD SIGNALING VIABLE? 9

Fig. 17. An example of a duobinary advantageous channel which has (unreal-

Fig. 16. Maximum raw bit rate (before modulation) versus PCB line length for istically) substantial amount of crosstalk only at 10 GHz and above (top); the
different modulation schemes. optimized FFE tap coefficients were [0.506, 0.494] which approximates duobi-
nary signaling at 20 Gb/s (bottom).

the slope of channel loss versus frequency is steep enough, the

improvement in SNR due to baud rate reduction may be greater is three times higher in PAM4 than NRZ. Therefore, PAM4 sys-
than 9.5 dB, justifying use of PAM4 [24]. tems may require significantly more complicated DFE and/or
Our simulations show that, in the channels we studied, the crosstalk cancellation to be viable in challenging channels. Fur-
lower signal bandwidth afforded by multilevel schemes does not thermore, since the error threshold is three times smaller in
result in a better SNR. For the 60 cm link on Nelco4000-13 in PAM4 for a given transmit launch level, higher transmit launch
Fig. 11 (top), insertion loss at 12.5 GHz (Nyquist frequency for level and better linearity may be necessary to compensate for
NRZ) is 12.4 dB higher than at 6.25 GHz (Nyquist frequency for loss in receiver sensitivity, which is disadvantageous in low-
PAM4). Furthermore, the insertion loss difference at 12.5 GHz voltage deep submicron CMOS technology. In [29], Liu and
and 6.25 GHz is much bigger than 9.5 dB in every reference Caroselli indicated that crosstalk cancellation was required to
channel model provided by CEI-25 working group [25], [26]. achieve the necessary performance under the channel model and
Yet, we could find no case where PAM4 showed an advantage crosstalk assumptions they considered. However, crosstalk can-
over NRZ [27]. This does not follow the conventional wisdom. cellation will be very difficult to realize in practical systems.
In [15] and [28], Bulzacchelli et al. explained this dilemma The architecture of crosstalk cancellation is similar to that of
by examining the effect of DFE on insertion loss. DFE feed- DFE; noise at the sampling point is correlated against the ag-
back is used to cancel ISI due to postcursors in channel impulse gressor’s source stream and subtracted off in a linear summer
response. To observe effect of DFE, they compared discrete at the sampling point. Many practical problems arise though,
Fourier transforms of the sampled channel response before and including causality and delay issues with FEXT channels, and
after eliminating postcursors. They found that elimination of intercore routing of high-speed lines in order to be able to de-
these postcursors flattens the frequency response; therefore, the sign canceling receivers. The issue is made even worse for com-
conventional argument for using PAM4 in high-loss channels plex channels, typical in high-end computers, which often ex-
breaks down when a DFE is applied to channel equalization. perience crosstalk from a number of sources, not necessarily
Adding an FFE does not alter this basic analysis though, as such near-neighbor I/O or even from the same bus.
a linear equalizer amplifies high-frequency noise as much as the
desired signal, leaving the high-frequency SNR unchanged. D. Relationship between Duobinary and NRZ Signaling With
The 9.5 dB SNR penalty is actually just a rule of thumb. FFE/DFE Equalization
PAM4 is three times more sensitive to uncompensated ISI and Duobinary signaling is one type of partial response signaling
crosstalk than NRZ since the peak signal to error threshold ratio method in which the binary data are transformed into a three-

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE TRANSACTIONS ON ADVANCED PACKAGING

Fig. 19. Insertion loss and signal-to-crosstalk ratio for various Megtron6 chan-
nels with 2:1 (red solid curves) and 4:1 (blue dotted curves) signal-to-reference
ratios. All curves are shifted downward when signal-to-reference ratio increases
from 2:1 to 4:1.

Fig. 18. Maximum achievable data rate versus distance for different amounts
of equalization including no equalization, FFE or DFE only, and FFE plus DFE. PAM4 signaling produces closed eyes in many cases where
The same metric (30 mV vertical and 0.3 UI horizontal eye openings) was used
in each case. NRZ was still able to provide some operating margin. Although
it may be possible to improve performance of each line sig-
naling approach by employing equalization architectures more
level signal. By introducing correlation between successive bits complex than those for NRZ, practical considerations in the
in a binary signal, the signal spectrum can be forced to be more design of the I/O including power, area, and voltage limitations
concentrated in low-frequency region [30]. favor the relatively simple NRZ-based system architecture in
NRZ signaling combined with FFE equalization can gen- absence of a clear performance advantage of alternate signaling
erate partial response signaling (recall duobinary code can approaches.
be generated and decoded by a baseline FFE/DFE system).
V. MAXIMUM ACHIEVABLE DATA RATES
Thus duobinary as well as other partial response codes should
have been considered by the FFE optimization algorithm as We first present results for the maximum achievable data rates
part of the solution space. The FFE optimization algorithm for electrical interconnects, then compare them to results for
should have homed in on a duobinary solution if it would have optical on-board interconnects published previously [13], [14].
given better system performance. Fig. 17 illustrates an extreme
and rather unrealistic example of a duobinary advantageous A. Effect of Equalization and Crosstalk
channel, which has substantial amount of crosstalk only at In Fig. 18 we show a contour plot of data rate and link reach
10 GHz and above. We had the FFE optimization algorithm for different amounts of equalization. Overall, an FFE alone per-
choose the best tap coefficients of a 2-tap FFE for this channel formed better than a DFE alone for the channels tested because
at 20 Gb/s, and the optimized tap values were [0.506, 0.494], of the following major factors.
which closely approximates duobinary signaling as shown in 1) A DFE is unable to cancel out precursor ISI. Highly dis-
the bottom figure. For other channel and crosstalk scenarios, persive channels may have significant time duration of pre-
the optimal FFE settings would have been different, implying cursor response that can be mitigated through use of an
that duobinary signaling would be a suboptimal solution. FFE with precursor taps.
From our measurements and simulations we conclude that 2) A nonrecursive DFE can only compensate a fixed time
duobinary and PAM4 signaling do not perform as well as NRZ span of ISI. In very low-bandwidth channels, significant
with FFE and DFE equalization for channels representative of postcursor ISI may fall outside the time span covered by
those we anticipate in various high-speed, high-density com- DFE taps. On the other hand, an FFE can compensate ISI
puter and switch boards and backplanes. The links we studied over a very wide time span since the FFE filter response is
have significant loss and enough crosstalk that duobinary or convolved with the impulse response of the channel.

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

KAM et al.: IS 25 Gb/s ON-BOARD SIGNALING VIABLE? 11

Fig. 20. Effect of crosstalk on link performance for 2:1 (top) and 4:1 (bottom) signal-to-reference pin ratios.

However, the functionality of FFE alone systems drops off than 30 mV vertical eye opening. However, this threshold value
rapidly over many legacy channels which have spectral nulls may vary depending on a number of factors, including minimum
(caused by via stubs, connectors, etc.) in the passband requiring sensitivity of the receiver and return loss and crosstalk of the
numerous FFE taps to cancel reflections. Furthermore, use of a channel. As loss gets lower, smaller signal-to-crosstalk ratio can
DFE permits less low-frequency de-emphasis at the transmitter be tolerated. Conversely, more loss can be handled as crosstalk
resulting in a larger received signal envelope. More discussion becomes smaller. Operating boundaries shown in Fig. 19 are
of the merits of a combined FFE/DFE system can be found in rough estimates which may vary significantly as a function of
[5]. The data also indicate that baseline FFE/DFE equalization parameters such as reflection ISI and I/O core characteristics.
does not provide reliable operation at 25 Gb/s for high-aggregate As data rate or link length increases, the channel performance
bandwidth density types of links longer than 45 cm, so further metric moves from the upper-left to the lower-right quadrant.
research is needed in the area of improved equalization system When increasing signal-to-reference pin ratio from 2:1 to 4:1,
designs to make 25 Gb/s links practical. signal-to-crosstalk ratio decreases while insertion loss remains
Fig. 19 is a plot of both insertion loss and signal-to-crosstalk almost the same (see Fig. 11). Thus channels with 4:1 module
ratio for various discussed channels with 2:1 and 4:1 signal-to- footprint patterns are more likely to be crosstalk limited (quad-
reference pin ratios, showing the regime of acceptable operation rant III).
(quadrant II) with contained crosstalk and loss. For those chan- Fig. 20 shows the effect of crosstalk on link performance for
nels which have 25+ dB loss at Nyquist frequency, link simula- different signal pin densities. The 2:1 and 4:1 60 cm Megtron6
tions show that even FFE plus DFE equalization produces less channels were simulated at 20 Gb/s, and both vertical and hor-

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

12 IEEE TRANSACTIONS ON ADVANCED PACKAGING

izontal eye openings were computed at a BER of 10 . The

top left and the bottom left figures are eye diagrams simulated
with turning off all aggressors in 2:1 and 4:1 signal-to-reference
ratio patterns, respectively. The top right and the bottom right
plots show link simulations with worst case crosstalk with 2:1
and 4:1 signal-to-reference ratios, respectively. The transient
response is separately calculated for each aggressor, and then
the link simulator adjusts the delay of each response to capture
the worst case. The degradation of horizontal eye opening due
to crosstalk reached 40% for 4:1 signal-to-reference pin ratio,
showing that crosstalk is a major limiter of link performance in
dense, high-speed buses.
Crosstalk is often beyond the capability of current equaliza-
tion architectures to combat, and needs to be quantified if ac-
curate performance projections are to be made based on ex-
perimental measurements. For short channels, NEXT may be
less of an issue since the insertion loss is not as severe; how- Fig. 21. Maximum achievable data rate as a function of PCB transmission line
length. For links shorter than 60 cm, IC or module performance improvements
ever, in longer links and at higher data rates it has the poten- could increase data rates. Links longer than 60 cm are channel bandwidth limited
tial to become a dominant design consideration. It should be and only superior equalizers can increase data rates.
noted that the particular links studied in this paper may not have
been crosstalk limited at 10 Gb/s, but this does not imply that
crosstalk will not be a limiting factor in other link configurations 2) An ideal case with no IC or module parasitics (channel
with different types of packages and connectors at the same or only) with 4-tap FFE/5-tap DFE (green dotted curve).
even lower data rates. However, these results point out that the 3) Same as 1) except with 4-tap FFE/20-tap DFE (black
escape pattern, as well as proximity of transmit and receive I/O curve).
channels must be carefully simulated and designed with suffi- 4) Same as 2) except with 4-tap FFE/20-tap DFE (blue dotted
cient isolation structures to avoid crosstalk dominate channels. curve).
Although we did not have enough test vehicles to assess skew When the baseline equalization was used, we observed that
on differential pairs caused by dielectric inhomogeneities (fiber passive channel dispersion limited the maximum achievable
weave, etc.), our active link model-hardware correlation showed data rates for links longer than 60 cm; therefore only mar-
this was not a factor for 60-cm links in the board constructions ginal improvement could be achieved by improving the I/O
measured at 11 Gb/s speeds. We do not consider fiber weave circuits and modules. Below 60 cm, however, the channel was
induced skew a fundamental limit, since a simple rotation of the not limiting maximum achievable data rates; consequently,
lines relative to the glass weave largely removes skew issues by improvements in I/O circuit performance (higher bandwidth,
averaging. better sensitivity, lower jitter, etc.) and module loss could lead
to maximum achievable data rates above 30 Gb/s. Although su-
perior equalization (e.g. 4-tap FFE/20-tap DFE) could increase
B. Possible Room for Speed Improvements
bandwidth further, 25 Gb/s on-board signaling is difficult for
Besides the particular electrical 11 Gb/s link implemented links longer than 75 cm.
in hardware and the extrapolated performance of this link to For sake of comparison, we generated analogous curves
higher data rates, we considered the ideal case (no IC or module (Fig. 22) for module-on-card polymer waveguide-based optical
parasitics) and/or using superior equalizers (4-tap FFE plus interconnects [13], [14], [33]. In this case, there is a wide gap
20-tap DFE) to gain insight into the possible room for speed between the performance of a link limited by the passive optical
improvements. waveguide bandwidth [34] (upper line, ideal case) and that of
It was found that both vertical and horizontal eye openings the optical link hardware (lower line). As can be seen from the
monotonically increased as the number of DFE taps was raised. figure, 25 Gb/s on-board optical links are possible to distances
However, a 4-tap FFE with one precursor and two postcursors of 1 m. The short, unequalized electrical links between the
seems close to optimal for the channels studied as little perfor- chips and the optical transceivers limit the maximum achiev-
mance improvement was observed with longer FFEs. Although able data rate of the electrical-optical-electrical (EOE) link to
increasing the number of DFE taps typically raises power con- 26 Gb/s at distances less than 1 m. If FFE and DFE equal-
sumption, a 10-tap DFE has been demonstrated with acceptable ization were employed on the short electrical links, and if the
power efficiency [31]. Furthermore, a number of architectural optoelectronic (OE) conversion elements were not bandwidth
and circuit techniques for implementing even lower power DFEs limiting, then the lower “Hardware” limit in Fig. 22 would
have been developed [32]. move upwards towards 35 Gb/s for distances under 90 cm.
In Fig. 21 we present the maximum achievable data rate for
the electrical links (up to 150 cm) for four cases. C. Electrical Aggregate Bandwidth Limits
1) The experimental hardware (4-tap FFE/5-tap DFE) but For any communication link, there will typically be one or
with scaled chip performance (shown in red curve). more constraining elements limiting the aggregate bandwidth

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

KAM et al.: IS 25 Gb/s ON-BOARD SIGNALING VIABLE? 13

Fig. 24. Physical limits to optical escape bandwidth.

Fig. 22. Maximum achievable data rate as a function of distance for optical
interconnects. Optical media is not the limiting factor in the link performance,
leaving ample space for improvement of the rest of the components. The un-
equalized electrical link between the host and the optical modules limits the
performance of the EOE link.

Fig. 25. Module escape bandwidth summary.

Fig. 23. Physical limits to electrical escape bandwidth. With typical 1-mm
LGA/BGA via/antipad full arrays and conductor widths, it is possible to es- of 2500 LGA contacts) are allocated to high-speed signals with
cape only one differential pair per pad pitch per wiring level around perimeter 2:1 signal-to-reference ratio. For each differential pair, we have
of module. assumed that 20 Gb/s electrical signaling could be used, as the
electrical studies have shown a 60 cm reach for this signaling
rate .
of the entire interconnect subsystem. By studying the signaling PCB wiring, module wiring, and C4 bandwidths are not lim-
and physical (escape density) limits for electrical interconnects iting; in fact, C4 and module bandwidths may increase with fu-
between two 50 mm 50 mm organic modules mounted on an ture C4 and wiring pitch improvements, and PCB wiring band-
organic PCB, we have arrived at our best estimate of the limits width may increase slightly with a small increase in the number
of electrical interconnect bandwidth. In Fig. 23 we show a cross of wiring layers. However, when we analyze the LGA via array
section of the packaging structures (right) comprised of a sil- escape, reducing via pitch will actually first decrease escape
icon chip with I/O drivers and receivers, the organic module, the bandwidth as one will not be able to escape a differential pair in a
LGA or BGA connection from the module to the board, and the channel. In this case, only edge vias are accessible, and one must
PCB. Shown to the left of this cross section is what was found have a stubless board technology to wire out the first “perimeter”
to be the limiting physical constraint—only one differential pair of edge via signals, then drop them, continuing the rest of the
can be wired per channel between the vias in the LGA under the vias down to the next board layer. Thus one would wire out only
module. This wiring density limit, coupled with the maximum perimeter vias on each successive layer, and escape bandwidth
number of signal layers, sets the maximum escape bandwidth would drop until the via pitch was less than 0.64 mm (not likely
at 12.6 Tb/s for this size module, given that 1900 pins (out possible).

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

14 IEEE TRANSACTIONS ON ADVANCED PACKAGING

TABLE I
SUMMARY METRICS COMPARING ELECTRICAL AND OPTICAL LINKS AT 10 AND 20 Gb/s PER CHANNEL

D. Optical Aggregate Bandwidth Limits density systems will be limited by power and complexity (or
silicon die area) constraints in the equalization system.
Since the LGA (or BGA) escape of the electrical module is
Table I presents an overall technology metric (yellow high-
the bandwidth pinch-point, it is obvious that this study under-
light) as well as a number of other metrics which would be
scores the need to place OE transceivers on the module next
useful to system designers when considering either electrical or
to the switch or processor chip to which they are attached, or
optical technologies. The left two columns give the metric and
no bandwidth improvement over electrical interconnects will be
the units for that metric, the right four columns give the metrics
possible. In Fig. 24 (left bottom) we show a cross section of an
for electrical 10 and 20 Gb/s links, and optical 10 and 20 Gb/s
organic module with a processor chip (CPU) and a representa-
on-board links, respectively. There are three groups of rows: the
tive optical transceiver module (CMOS transceiver (TRX) and
first gives overall system metrics, the second gives link or media
surface laminar circuit (SLC), with OE in red). In the top left
metrics, and the third gives chip-level metrics. Link metrics deal
is shown a top-view of the same module with the outline of a
with electrical or optical link, or media, metrics, such as the
20 mm 20 mm processor chip (middle square) and OE trans-
distance-baud rate product. The chip metrics deal with power
ceivers around the perimeter of the 50 mm 50 mm module.
and area efficiency of the I/O on the processor/switch chip. To
Each of the 36 OE transceivers contains 64 transmitters or re-
better represent the state-of-the-art, the electrical 10 Gb/s power
ceivers grouped with four staggered elements in 16 rows, al-
models are based on a newer product core (in 65 nm technology)
lowing 62.5- waveguide pitch (light blue lines to the right)
than the one used in the link demonstrations of Section III. The
on the top of the PCB. This results in the maximum escape band-
electrical 20 Gb/s power models are based on estimates of a
width at 46 Tb/s for this size module
mockup hardware design (also in 65 nm technology). The power
.
numbers of the optical links only include power on the pro-
Shown in Fig. 25 is the comparison of optical and electrical
cessor or switch chip, and do not include the OE conversion
module escape bandwidths, both assuming 50 mm 50 mm
power [13]; if that were included, optical and electrical link ef-
modules. The grey numbers in the electrical column are for
ficiencies would be roughly equivalent at 10 Gb/s. The overall
4:1 signal-to-reference ratio module pinout which allows more
technology metric is a product of the distance-baud rate product
bandwidth , but, as
with escape bandwidth normalized by I/O power and area effi-
found in measurement and simulation, also has more crosstalk
ciency. The higher escape bandwidth and the lower power re-
which we believe will be limiting at 20 Gb/s. For further op-
quired for I/O on the processor/switch chip give optical tech-
tical escape bandwidth improvements, an additional waveguide
nology the advantage.
layer can accommodate another rank of OE transceivers on the
module. The second rank has only 24 OE transceivers due to
the reduced perimeter, giving the maximum escape bandwidth VI. CONCLUSION
at 76.8 Tb/s . This
25 Gb/s on-board signaling is difficult at present, for both
escape bandwidth estimate may be reduced for die requiring sig-
optical and electrical technologies. Electrical signaling reach is
nificant on-module decoupling capacitors.
constrained by channel dispersion characteristics, which may
improve with reduced dielectric and conductor losses. With ex-
E. Technology Metrics
isting organic modules and board materials with 150 PCB
While the data rates of the links discussed in this paper are traces, electrical 25 Gb/s links are limited to 45 cm reach.
mostly limited to less than 25 Gb/s, the ultimate limit of capacity Adding more DFE taps at the costs of more power and area al-
is relatively high [35]. However, data rates in practical high I/O lows increased reach to 75 cm.

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

KAM et al.: IS 25 Gb/s ON-BOARD SIGNALING VIABLE? 15

NRZ signaling with FFE and DFE equalization provides technologies such as waveguide-based on-board optical links.
better margins than multilevel modulation. Since duobinary is However, it will be challenging to implement cost-effective in-
a subset of the potential solution space of FFE equalization, terconnect solutions using either technology beyond 25 Gb/s per
equalized NRZ should be equivalent or better than duobinary channel without significant technological advances.
on most channels. The conventional wisdom for using PAM4
in high-loss channels breaks down when a DFE is applied ACKNOWLEDGMENT
to channel equalization. Although DFE equalization is chal- The authors would like to thank P. Metty, J. Garlett,
lenging at these speeds, there is no fundamental implementation D. Stauffer, D. Friedman, F. Doany, C. Schow, D. Kuchta, and
barrier, especially if parallel path speculation or loop unrolling J. Kash for valuable advice and assistance, and M. Taubenblatt
is employed [36]. and M. Soyuer for technical and managerial support of this
In contrast, optical on-board links of the type referenced here project.
are presently limited by CMOS receiver circuit performance
and by waveguide light scattering loss—not by signal disper- REFERENCES
[1] A. F. Benner, P. K. Pepeljugoski, and R. J. Recio, “A roadmap to 100G
sion in the optical waveguide, which could support signaling Ethernet at the enterprise data center,” IEEE Commun. Mag., vol. 45,
at much higher rates. Theoretically, data rates beyond 30 Gb/s no. 11, pp. 10–17, Nov. 2007.
could be achieved on the short electrical segments of the EOE [2] D. G. Kam, T. J. Beukema, Y. H. Kwark, L. Shan, X. Gu, P. K. Pe-
peljugoski, and M. B. Ritter, “Multi-level signaling in high-density,
link by adding I/O equalization and/or by using higher per- high-speed electrical links,” in IEC DesignCon, Santa Clara, CA, Feb.
formance packaging. New materials and better processing to 4–7, 2008.
reduce waveguide loss will most likely extend on-board optical [3] T.-C. Chen, “Where CMOS is going: Trendy hype vs. real technology,”
in Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 6–9, 2006,
link reach. Error-free vertical-cavity surface-emitting laser pp. 1–18.
(VCSEL) links running at 20 Gb/s have been demonstrated [4] D. G. Kam and J. Kim, “40-Gb/s package design using wire-bonded
[37], and there is no fundamental barrier to direct laser modu- plastic ball grid array,” IEEE Trans. Adv. Packag., vol. 31, no. 2, pp.
258–266, May 2008.
lation at 35+ Gb/s for short-reach links [38]. For higher speeds [5] T. Beukema, M. Sorna, K. Selander, S. Zier, B. L. Ji, P. Murfet, J.
and greater channel density, much effort is being expended on Mason, W. Rhee, H. Ainspan, B. Parker, and M. Beakes, “A 6.4-Gb/s
indirect modulation devices—especially silicon nanophotonics CMOS SerDes core with feed-forward and decision-feedback equal-
ization,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2633–2645,
[39]. Therefore, from a channel and OE device perspective, Dec. 2005.
optical links do show the greatest promise in improving both [6] J. T. Stonick, G.-Y. Wei, J. L. Sonntag, and D. K. Weinlader, “An adap-
bandwidth and reach of dense, high-speed buses. More discus- m
tive PAM-4 5-Gb/s backplane transceiver in 0.25-  CMOS,” IEEE
J. Solid-State Circuits, vol. 38, no. 3, pp. 436–443, Mar. 2003.
sion of electrical and optical trade-offs can be found in [33]. [7] J. H. Sinsky, M. Duelk, and A. Adamiecki, “High-speed electrical
For both optical and electrical links at these speeds, CMOS backplane transmission using duobinary signaling,” IEEE Trans.
I/O circuit designs will be challenging. As CMOS scales toward Microwave Theory Tech., vol. 53, no. 1, pp. 152–160, Jan. 2005.
[8] S. Rylov, S. Reynolds, D. Storaska, B. Floyd, M. Kapur, T. Zwick,
the 22 nm node, and are improving, but not as they S. Gowda, and M. Sorna, “10+ Gb/s 90-nm CMOS serial link demo
have historically; therefore, designers will need to work closer in CBGA package,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp.
to device speed limits, but these seem to be practical rather than 1987–1991, Sep. 2005.
[9] L. Shan, Y. Kwark, P. Pepeljugoski, M. Meghelli, T. Beukema, C Baks,
fundamental issues at 25 Gb/s [40]. I/O power, system power, J. Trewhella, and M. Ritter, “Design, analysis and experimental verifi-
and cost trade-offs are more likely to determine data rate limits cation of an equalized 10 Gbps link,” in IEC DesignCon, Santa Clara,
CA, Feb. 6–9, 2006.
and technology choices. [10] B. Chan, J. Lauffer, S. Rosser, and J. Stack, “PWB solutions for high
Electrical escape bandwidths are limited by the module pin speed systems,” in Electron. Compon. Technol. Conf., Lake Buena
pitch, which is largely set by PCB via pitch and escape wiring. Vista, FL, May/Jun. 2005, pp. 1697–1703.
[11] R. Kollipara, B. Chia, F. Lambrecht, C. Yuan, J. Zerbe, G. Patel, T.
For reduced-stub, low-loss boards and links 45 cm in length, Cohen, and B. Kirk, “Practical design considerations for 10 to 25 Gbps
a maximum escape bandwidth of 12.6 Tb/s could be achieved copper backplane serial links,” in IEC DesignCon, Santa Clara, CA,
for a 50 mm 50 mm organic module and 1-mm pin pitch. Feb. 6–9, 2006.
[12] H. Braunisch, J. E. Jaussi, J. A. Mix, M. B. Trobough, B. D. Horine,
It is clear that optical links must be mounted on the module to V. Prokofiev, D. Lu, R. Baskaran, P. C. H. Meier, D.-H. Han, K. E.
allow greater escape bandwidth, and we estimate that total band- Mallory, and M. W. Leddige, “High-speed flex-circuit chip-to-chip in-
widths as high as 76.8 Tb/s could be brought off a 50-m module terconnects,” IEEE Trans. Adv. Packag., vol. 31, no. 1, pp. 82–90, Feb.
2008.
with compact optical transceivers and limited decoupling on the [13] F. E. Doany, C. L. Schow, C. K. Tsang, N. Ruiz, R. Horton, D. M.
module. DC loss for 850-nm light in state-of-the-art polymer Kuchta, C. S. Patel, J. U. Knickerbocker, and J. A. Kash, “300-Gb/s
waveguides now limits reach of these links to 1 meter, which 24-channel bidirectional Si carrier transceiver optochip for board-level
interconnects,” in Electron. Compon. Technol. Conf., Lake Buena
will likely improve due to processing and materials changes. Vista, FL, May 27–30, 2008, pp. 238–243.
Because the present optical packaging approach requires multi- [14] F. E. Doany, C. L. Schow, C. Baks, R. Budd, Y.-J. Chang, P. Pepelju-
mode organic waveguides, it will be difficult to employ wave- goski, L. Schares, D. Kuchta, R. John, J. A. Kash, F. Libsch, R. Dangel,
F. Horst, and B. J. Offrein, “160-Gb/s bidirectional parallel optical
length-division multiplexing (WDM) emitters to extend channel transceiver module for board-level interconnects using a single-chip
bandwidth. CMOS IC,” in Electron. Compon. Technol. Conf., Reno, NV, May/Jun.
In conclusion, electrical links are approaching channel dis- 2007, pp. 1256–1261.
[15] J. F. Bulzacchelli, M. Meghelli, S. V. Rylov, W. Rhee, A. V. Rylyakov,
persion limits at 25 Gb/s speeds for on-board links and distances H. A. Ainspan, B. D. Parker, M. P. Beakes, A. Chung, T. J. Beukema, P.
greater than 75 cm. 25 Gb/s electrical signaling at distances K. Pepeljugoski, L. Shan, Y. H. Kwark, S. Gowda, and D. J. Friedman,
greater than 45 cm will require more DFE taps, more exotic elec- “A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS tech-
nology,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2885–2900,
trical package technologies, or a transition to new interconnect Dec. 2006.

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

16 IEEE TRANSACTIONS ON ADVANCED PACKAGING

[16] HFSS. Ansoft [Online]. Available: http://www.ansoft.com/prod- Dong G. Kam (S’01–M’06) received the B.S. de-
ucts/hf/hfss gree in physics with a double major in electrical engi-
[17] CZ2D. [Online]. Available: http://www.alphaworks.ibm.com/tech/eip neering, the M.S. and Ph.D. degrees in electrical en-
[18] Y. Kwark, C. Schuster, L. Shan, C. Baks, and J. Trewhella, “The re- gineering, all from KAIST, Daejeon, Korea, in 2000,
cessed probe launch—A new signal launch for high frequency charac- 2002, and 2006, respectively.
terization of board level packaging,” in IEC DesignCon, Santa Clara, From 2006 to 2007, he was with Silicon Image,
CA, Jan./Feb. 2005. Sunnyvale, CA, where he was a Member of Tech-
[19] ADS. Agilent [Online]. Available: http://eesof.tm.agilent.com nical Staff in the Signal Integrity Group. In 2007, he
[20] P. K. Pepeljugoski, J. A. Tierno, A. Risteski, S. K. Reynolds, and L. joined the IBM T. J. Watson Research Center, York-
Schares, “Performance of simulated annealing algorithm in equalized town Heights, NY, where he is currently a Research
multimode fiber links with linear equalizers,” J. Lightw. Technol., vol. Staff Member concentrating in the areas of antenna
24, pp. 4235–4249, Nov. 2006. and package development for 60-GHz wireless systems and subsystem analysis
[21] T. Beukema, “Challenges in serial electrical interconnects at 5 to 10 of 10+ Gb/s serial I/O links.
Gb/s and beyond,” in IEEE SSCS-Denver Section Seminar, Mar. 2007. Dr. Kam was the recipient of the Best Paper Award at DesignCon 2008. He
[22] P. Kabal and S. Pasupathy, “Partial-response signaling,” IEEE Trans. has published over 35 papers.
Commun., vol. 23, pp. 921–934, Sep. 1975.
[23] S. Galal and B. Razavi, “Broadband ESD protection circuits in CMOS
technology,” in Int. Solid-State Circuits Conf., San Francisco, CA, Feb.
9–13, 2003, pp. 182–183.
[24] H. Johnson, “Multi-level signaling,” in IEC DesignCon, Santa Clara, Mark B. Ritter received the B.S. degree in physics
CA, Jan./Feb. 2000. from Montana State University, Bozeman, in 1981
[25] H. Preisach, “Proposals for CEI25 channels based on lower-k dielectric and the M.S., M.Phil., and Ph.D. degrees from Yale
materials for backplanes and daughterboards,” in OIF PLL Working University, New Haven, CT, in 1987.
Group Presentation, Englewood, CO, Apr. 24–26, 2007. He presently manages a group focusing on
[26] G. Oganessyan, “Reference channels and additional considerations for high-speed I/O subsystems, including electromag-
backplane implementation of CEI-25G,” in OIF PLL Working Group netic characterization, link modeling, and subsystem
Presentation, Englewood, CO, Apr. 24–26, 2007. analysis with an eye to optimizing I/O link perfor-
[27] D. G. Kam, D. R. Stauffer, T. J. Beukema, and M. B. Ritter, “Perfor- mance metrics, whether electrical or optical. He
mance comparison of CEI-25 signaling options and sensitivity anal- and his group have contributed to Fibre Channel, 10
ysis,” in OIF PLL Working Group Presentation, Kobe, Japan, Nov. 6–8, Gb/s Ethernet, and other high-speed communication
2007. products and standards, as well as to efficient, physics-based models for vias.
[28] J. Bulzacchelli, T. Beukema, and D. R. Stauffer, “PAM-4 versus NRZ He is an author or coauthor on numerous technical publications and holds 20
signaling: Basic theory,” in OIF PLL Working Group Presentation, Bu- U.S. patents.
dapest, Hungary, May 10–13, 2004. Dr. Ritter was the recipient of the 1982 American Physical Society Apker
[29] C. Y. Liu and J. Caroselli, “Comparison of signaling and equalization Award, three IBM Outstanding Innovation Awards, and several Research Divi-
schemes in high speed SerDes (10–25 Gb/s),” in IEC DesignCon, Santa sion and Technical Group Awards.
Clara, CA, Jan./Feb. 2007.
[30] A. Sekey, “An analysis of the duobinary technique,” IEEE Trans.
Commun. Technol., vol. 14, no. 2, pp. 126–130, Apr. 1966.
[31] B. S. Leibowitz, J. Kizer, H. Lee, F. Chen, A. Ho, M. Jeeradit, A.
Bansal, T. Greer, S. Li, R. Farjad-Rad, W. Stonecypher, Y. Frans, B. Troy J. Beukema received the B.S.E.E. and M.S.E.E
Daly, F. Heaton, B. W. Garlepp, C. W. Werner, N. Nguyen, V. Sto- degrees from Michigan Technological University,
janovic, and J. L. Zerbe, “A 7.5 Gb/s 10-tap DFE receiver with first Houghton, in 1984 and 1988, respectively.
tap partial response, spectrally gated adaptation, and 2nd-order data-fil- From 1984 to 1988, he was a Development Engi-
tered CDR,” in Int. Solid-State Circuits Conf., San Francisco, CA, Feb. neer with Hewlett-Packard in the area of communi-
11–15, 2007, pp. 228–229. cation test instruments. He joined Motorola in 1989
[32] J. F. Bulzacchelli, A. V. Rylyakov, and D. J. Friedman, “Power-effi- where he contributed to research and development of
cient decision-feedback equalizers for multi-Gb/s CMOS serial links,” digital cellular wireless systems. In 1996, he joined
in IEEE Radio Frequency Integrated Circuits Symp., Honolulu, HI, Jun. IBM, Yorktown Heights, NY, where he is presently a
2007, pp. 507–510. Research Staff Member concentrating in the area of
[33] P. Pepeljugoski, M. Ritter, J. A. Kash, F. Doany, C. Schow, Y. Kwark, high data rate serial I/O system designs. His general
L. Shan, D. Kam, X. Gu, and C. Baks, “Comparison of bandwidth limits research interests include communication link system design and analysis, with
for on-card electrical and optical interconnects for 100 Gb/s and be- an emphasis on modulation, equalization, clock generation, and synchroniza-
yond,” in Proc. SPIE, Feb. 2008, vol. 6897, p. 68970I. tion systems realized in mixed-signal deep-submicron CMOS technology for
[34] F. E. Doany, P. K. Pepeljugoski, A. C. Lehman, J. A. Kash, and R. high-density I/O applications.
Dangel, “Measurement of optical dispersion in multimode polymer
waveguides,” in IEEE/LEOS Summer Topical Meetings, San Diego,
CA, Jun. 28–30, 2004, pp. 31–32.
[35] C. E. Shannon, “A mathematical theory of communication,” Bell Syst.
Tech. J., vol. 27, pp. 379–423, Jul./Oct. 1948, 623-656. John F. Bulzacchelli (S’92–M’02) received the
[36] S. Kasturia and J. H. Winters, “Techniques for high-speed implemen- S.B., S.M., and Ph.D. degrees in electrical engi-
tation of nonlinear cancellation,” IEEE J. Sel. Areas Commun., vol. 9, neering, all from the Massachusetts Institute of
no. 5, pp. 711–717, Jun. 1991. Technology (MIT), Cambridge, in 1990, 1990, and
[37] N. Suzuki, H. Hatakeyama, K. Tokutome, K. Fukatsu, M. Yamada, T. 2003, respectively.
m
Anan, and M. Tsuji, “1.1  -range InGaAs VCSELs for high-speed From 1988 to 1990 he was a co-op student at
optical interconnections,” IEEE Photonics Technol. Lett., vol. 18, pp. Analog Devices, Wilmington, MA, where he in-
1368–1370, Jun. 2006. vented a new type of delay-and-phase-locked loop
[38] Y.-C. Chang, C. S. Wang, and L. A. Coldren, “High-efficiency, high- for high-speed clock recovery. From 1992 to 2002,
speed VCSELs with 35 Gb/s error-free operation,” Electron. Lett., vol. he conducted his doctoral research at the IBM T.
43, no. 19, pp. 1022–1023, Sep. 2007. J. Watson Research Center, Yorktown Heights, NY,
[39] W. M. J. Green, M. J. Rooks, L. Sekaric, and Y. A. Vlasov, “Optical in a joint study program between IBM and MIT. In his doctoral work, he
modulation using anti-crossing between paired amplitude and phase designed and demonstrated a superconducting bandpass delta-sigma modulator
resonators,” Optics Express, vol. 15, no. 25, pp. 17264–17272, Dec. for digitizing multi-GHz RF signals. In 2003 he became a Research Staff
2007. Member at this same IBM location, where his primary job is the design of
[40] B. Casper, J. Jaussi, F. O’Mahony, M. Mansuri, K. Canagasaby, J. mixed-signal CMOS circuits for high-speed data communications. He holds
Kennedy, E. Yeung, and R. Mooney, “A 20 Gb/s forwarded clock trans- two U.S. patents.
ceiver in 90 nm CMOS,” in Int. Solid-State Circuits Conf., San Fran- Dr. Bulzacchelli received the Jack Kilby Award for Outstanding Student
cisco, CA, Feb. 6–9, 2006, pp. 263–272. Paper at the 2002 IEEE International Solid-State Circuits Conference.

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

KAM et al.: IS 25 Gb/s ON-BOARD SIGNALING VIABLE? 17

Petar K. Pepeljugoski (S’93–M’93–SM’03) received the Ph.D. degree from Richard A. John received the Associate degree in electronics technology from
University of California, Berkeley, in 1994. RCA Institute, New York, in 1967.
He joined IBM Research as a Research Staff Member in 1994. His research He joined the IBM Research Division that same year, and is currently a Se-
work included design, modeling, prototyping, and characterization of multi- nior Laboratory Specialist working in I/O technology on high-speed electrical,
mode fiber LAN links and parallel optical and electrical interconnects. He was optical, and cell phone packaging. He has worked in a variety of areas, including
involved in the development of several Ethernet (IEEE 802.3z, IEEE 802.3ae, thermal printing, color electro-photographic printing, and involved with the de-
IEEE 802.3aq) standards, as well as the development of the specification of the sign and fabrication of high-resolution active matrix liquid crystal displays.
OM3 fiber, and subsequently recognized for his contributions. He leads the tech-
nical feasibility group for the Call for Interest for 100 Gb Ethernet standard and
is actively involved in the work of the Task Force. He is an author or coauthor
of more than 60 journal or conference articles. Gareth Hougham received the Ph.D. degree in
polymer chemistry from Polytechnic University
(now part of New York University), New York, NY,
in 1992.
Young H. Kwark was born in Korea, in 1956. He He is a Research Staff Member at the IBM T. J.
received the B.S.E.E. degree from the Massachusetts Watson Research Center and works in the area of in-
Institute of Technology, Cambridge, in 1978, and terconnect technology with an emphasis on materials
the M.S. and Ph.D. degrees in electrical engineering science. He and has a long standing interest in low-k
from Stanford University, Stanford, in 1979 and organic dielectrics. He is the editor of two volumes
1984, respectively. on Fluoropolymers published by Kluwer Academic,
From 1984 to 1986, he was a Research Associate at has authored more than 30 papers, and has more than
Stanford University working on high efficiency con- 50 U.S. patents issued or pending.
centrator photovoltaic cells. In 1986, he joined IBM
where he is currently a Research Staff Member at the
Watson Research Center, Yorktown Heights, NY. His
work has included III-V process development and device characterization, and Christian Schuster (S’98–M’00–SM’05) received
circuit design for wireless and fiber optic links. His current work focuses on the Diploma degree in physics from the University of
high-frequency measurements of electrical packaging elements used in high per- Konstanz, Germany, in 1996, and the Ph.D. degree
formance digital systems. in electrical engineering from the Swiss Federal
Institute of Technology (ETH), Zurich, Switzerland,
in 2000.
Since 2006, he is Full Professor and Head of the
Lei Shan received the M.S. degree in electrical Institute for Electromagnetic Theory at the Technical
engineering and the Ph.D. degree in mechanical University of Hamburg-Harburg (TUHH), Germany.
engineering from Georgia Institute of Technology, Prior to that he was with the IBM T. J. Watson Re-
Atlanta, in 2000. search Center, Yorktown Heights, NY, where he was
In 2001, he joined IBM T. J. Watson Research involved in high-speed optoelectronic package and backplane interconnect mod-
Center, Yorktown Heights, NY, as a Research eling and signal integrity design for new server generations.
Staff Member, where he works on high-speed Dr. Schuster received the IEEE Transactions on EMC Best Paper Award in
electronics/optoelectronics packaging designs and 2001, IEC DesignCon Paper Awards in 2005 and 2006, and three IBM Research
multiphysics modeling/simulations. He designed Division Awards between 2003 and 2005. He is a member of the German Phys-
and demonstrated high-speed packages on both ical Society (DPG).
connectorized format and BGA joints for 50 Gb/s
multiplexer and demultiplexer based on IBM SiGe BiCMOS technology. He
led the packaging development for 10G Ethernet and Terabus optical links on
printed circuit board. His recent research interest is on signal/power integrity
in high-performance computing systems and the fundamental electrical limits. Renato Rimolo-Donadio (S’08) received the B.S.
He has authored over 40 publications and owns over 20 U.S. patents. and Lic. degrees in electrical engineering from the
Technical University of Costa Rica, in 1999 and
2004, respectively, and the M.S. degree in micro-
electronics and microsystems from the Technical
Xiaoxiong Gu received the B.S. degree from University of Hamburg-Harburg, Germany, in 2006,
Tsinghua University, Beijing, China, in 2000, the where he is currently working toward the Ph.D.
M.S. degree from University of Missouri, Rolla, degree in electrical engineering.
in 2002, and the Ph.D. degree from the University Since November 2006, he has been a Scientific Re-
of Washington, Seattle, in 2006, all in electrical search Assistant at the Institute of Electromagnetic
engineering. Theory, Technical University of Hamburg-Harburg.
He is currently a research staff member with IBM In 2007, he was an intern at the IBM T. J. Watson Research Center, Yorktown
T. J. Watson Research Center, Yorktown Heights, Heights, NY. His main research interests include system level modeling and op-
NY. His research interests include characterization timization of interconnects, and analysis of signal and power integrity problems
of high-speed interconnect and microelectronic at PCB and package level.
packaging, signal and power integrity, and compu-
tational electromagnetics.

Boping Wu (S’04) received the B.Eng. degree (with

First Class Honors) in electronic and communication
Christian W. Baks received the B.S. degree in engineering from the City University of Hong Kong
applied physics from Fontys College of Technology, in 2005, and the M.S. degree in electrical engi-
Eindhoven, The Netherlands, in 2000, and the M.S. neering, in 2007, from the University of Washington,
degree in physics from the State University of New Seattle, where he is currently working toward the
York (SUNY), Albany, in 2001. Ph.D. degree.
He joined the IBM T. J. Watson Research Center, He was a Graduate Intern at the Intel Corporation
Yorktown Heights, NY, as an Engineer in 2001, and the IBM Corporation, in 2006 and 2007, respec-
where he is involved in high-speed optoelectronic tively. His current research interests include layered
package and backplane interconnect design special- medium Green’s function, high-speed interconnects
izing in signal integrity issues. and packaging, metamaterials, and nano-photonics.

Authorized licensed use limited to: University of Illinois. Downloaded on April 21, 2009 at 11:30 from IEEE Xplore. Restrictions apply.