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DSP Module V
DSP Module V
Address Program
generator control
MAC Shifter
Fetch Execute
Fetch Execute
Fetch Execute
Fetch Execute
Fetch Execute
Fetch Execute
Operand Operand
X-register Y-register
16 16
Multiplier
32
Accumulator
32
Result
register
Shifters are required to scale down or scale up operands & results to avoid errors resulting
from overflows and underflows during computations. Shifting data to the right is the same as
dividing the data by 2 and truncating the fraction part (scale down); shifting data to the left
is equivalent to multiplying the data by 2 (scale up). The digital signal processor often shifts
data by several bits for each data word. To speed up such operation, the special hardware
shift unit is designed to accommodate the scaling operation.
Address generators: The digital signal processor generates the addresses for each da-
tum on the data buffer to be processed. A special hardware unit for circular buffering is
used. Fig. 5 describes the basic mechanism of circular buffering for a buffer having eight
data samples. In circular buffering, a pointer is used and always points to the newest data
4 Module-0
sample. After the next sample is obtained the data will be placed at the location of x(n − 7)
and the oldest sample is pushed out. Thus, the location for x(n − 7) becomes the location
for the current sample. The original location for x(n) becomes a location for the past sample
of x(n − 1). For each new data sample, only one location on the circular buffer needs to
be updated. Further, the circular buffer acts like a first-in/first-out (FIFO) buffer, but each
datum on the buffer does not have to be moved.
Data point
x(n)
x(n-7)
x(n-1)
x(n-6)
x(n-2)
x(n-5)
x(n-4) x(n-3)
• Convert the magnitude in the decimal to its binary number using the required number
Digital Signal Processing 5
of bits.
• If the decimal number is positive, its binary number is its 2’s complement representation;
if the decimal number is negative, perform the 2’s complement operation, where we
negate the binary number by changing the logic 1s to logic 0s and logic 0s to logic 1s
and then add a logic 1 to the data.
Example 1: Convert the following decimal numbers to its 2’s complement form.
(i) 2
(ii) -2
Solution:
(i) Given 2d
2d = (010)2
2’s complement number system has a dynamic range which is very narrow. Since the
basic DSP operations include multiplications and additions, results of operation can cause
overflow problems.
Solution:
(i)
0 1 0 −→ 2d
× 0 0 1 −→ 1d
0 1 0
0 0 0
+ 0 0 0
0 0 0 1 0
The 2’s complement of 00010 = 11110. Removing two extended sign bits give 110. The
answer is 110 = −2, which is within the system range.
(ii)
0 1 0 −→ 2d
× 0 1 1 −→ 3d
0 1 0
0 1 0
+ 1 0 0
0 0 1 1 0
The 2’s complement of 00110 = 11010. Removing two extended sign bits gives 010. Since
the binary number 010 is 2, which is not (-6) as what we expect, overflow occurs; that is, the
result of the multiplication (-6) is out of the dynamic range.
Example 3: Perform the multiplication of 2/4 and -3/4 in fractional binary 2’s complement.
Solution:
2/4 = 0 × 20 + 1 × 2−1 + 0 × 2−2 = 0.10
3/4 = 0 × 20 + 1 × 2−1 + 1 × 2−2 = 0.11
0. 1 0 −→ 2/4
× 0. 1 1 −→ 3/4
0 1 0
0 1 0
+ 0 0 0
0. 0 1 1 0
The 2’s complement of 0.0110 = 1.1010. The answer in decimal form should be 1.1010 =
(−1) × (0.0110)2 = −0 × 2−1 + 1 × 2−2 + 1 × 2−3 + 0 × 2−4 = −3/8. If we truncate the last
two least significant bits to keep the 3-bit binary number, we have an approximate answer:
1.10 = (−1) × (0.10)2 = −(1 × 2−1 + 0 × 2−2 ) = −1/2.
Truncation error occurs. With such a scheme, we can avoid overflow due to multiplication but
cannot prevent overflow due to addition. Consider the addition example (0.11)2 + (0.01)2 =
Digital Signal Processing 7
(0.00)2 , where the result 1.00 is a negative number. Adding two positive fractional numbers
yields a negative number. Hence, overflow occurs.
0.3.2 Q-format
Q-format number representation is the most common one used in fixed-point DSP imple-
mentation. Fig. 6 shows the Q-15 format. Q-15 means that the data are in a sign magnitude
form in which there are 15 bits for magnitude and one bit for sign.
Q15 -20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15
Example 4: Find the signed Q-15 representation for the decimal number 0.450321.
Solution: For a positive fractional number, we multiply the number by 2 if the product
is larger than 1, carry bit 1 as a most significant bit (MSB), and copy the fractional part to
the next line for the next multiplication by 2; if the product is less than 1, we carry bit 0 to
MSB. The procedure continues to collect all 15 magnitude bits.
Example 5: Find the signed Q-15 representation for the decimal number -0.450321.
Solution:
Converting the Q-15 format for the corresponding positive number we have
0.450321=(0.011 1001 1010 0100)2
Applying 2’s complement, the Q-15 format becomes
-0.450321=(1.100 0110 0101 1100)2 = (C65C)h
Example 6: Convert the Q-15 signed number 0.011100110100100 to the decimal number.
Solution:
The decimal number is; 2−2 + 2−3 + 2−4 + 2−7 + 2−8 + 2−10 + 2−13 = 0.450317382
Example 7: Add the two numbers 1.110101110000010 and 0.100011110110010 in Q-15 format.
Solution:
1 1 1 0 1 0 1 1 1 0 0 0 0 0 1 0
+ 0 1 0 0 0 1 1 1 1 0 1 1 0 0 1 0
1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0
Then the result is 0.011001100110100.
The decimal number is 2−2 + 2−3 + 2−6 + 2−7 + 2−10 + 2−11 + 2−13 = 0.400024.
Example 8: Determine the fixed-point multiplication of 0.25 and 0.5 in Q-3 fixed-point 2’s
complement format.
Solution:
0. 0 1 0
x 0. 1 0 0
0 0 0 0
0 0 0 0
0 0 1 0
+ 0 0 0 0
0. 0 0 1 0 0 0
Truncating the least significant bits to convert the result to Q-3 format, we have =0.001.
(0.25 × 0.5 = 0.125 = 0.001).
Example 9: Determine the fixed-point multiplication of 0.75 and 0.5 in Q-3 fixed-point 2’s
complement format.
Solution:
0.75 = 0.110 and 0.5 = 0.100.
0. 1 1 0
x 0. 1 0 0
0 0 0 0
0 0 0 0
0 1 1 0
+ 0 0 0 0
0. 0 1 1 0 0 0
Truncating the least significant bits to convert the result to Q-3 format, we have =0.011.
(0.75 × 0.5 = 0.375 = 0.011).
Example 10: Determine the square of 0.25 in Q-2 fixed-point 2’s complement format.
Solution:
0.25 = 0.01.
0. 0 1
x 0. 0 1
0 0 1
0 0 0
+ 0 0 0
0. 0 0 0 1
10 Module-0
Truncating the least significant bits to convert the result to Q-2 format, we have =0.00,
which is zero. Hence, underflow occurs.
The Q-format number representation is a better choice than the 2’s complement integer
representation, it can prevent multiplication overflow. Some of the issues with the Q-format:
• When converting a decimal number to its Q- format, we may lose accuracy due to the
truncation error (2−N ).
• Addition and subtraction may cause overflow, where adding two positive numbers leads
to a negative number, or adding two negative number yields a positive number; similarly,
subtracting a positive number from a negative number gives a positive number, while
subtracting a negative number from a positive number results in a negative number.
• Multiplying two numbers in Q-15 format leads to Q-30 product. In Q-30 format,
there is one sign-extended bit. We may get rid of it by shifting left by one bit
to obtain Q-31 format and maintaining the Q-31 format for each MAC operation.
• Underflow can happen when the result of multiplication is too small to be represented
in the Q-format.
where M is the mantissa, or fractional part in Q format, and exp is the exponent. The
mantissa and exponent are signed numbers. The bigger the number of bits designated to the
exponent, the larger the dynamic range.
-23 22 21 20 -20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12
Example 11:Convert each of the following decimal numbers to a floating-point number using
12-bit mantissa and 4-bit exponent format.
(i) 0.1601230
(ii) -20.430527
Solution:
(i) Scale the number 0.1601230 to 0.160123/2−2 = 0.640492 with an exponent of -2.
Exponent = 5 = 0101
Now we convert the value 0.638454 using the Q-11 format =(0101 0001 1011).
x1 = M1 · 2exp1
x2 = M2 · 2exp2
M1 + M2 × 2−(exp1 −exp2 ) × 2exp1 , if exp1 ≥ exp2
x1 + x2 =
M1 × 2−(exp2 −exp1 ) + M2 × 2exp2 if exp1 < exp2
Solution:
To perform the addition, both the numbers should have the same exponent value. Therefore
change the first number so it has the same exponent as the second number, Scale the number
0.1601230 = 0.1601230/25
Now, exponent exp1 = 5 = 0101 and M1 = Mantissa in Q-11 =(0000 0000 1010)
0.1601230 = 0101000000001010
That is, the mantissas are multiplied while the exponents are added.
Solution:
Cascading the exponent bits and the mantissa bits yields the product
During an operation, overflow will occur when a number is too large to be represented
in the floating point number system. Adding two mantissa numbers may lead to a number
larger than 1 or less than -1; and multiplying two numbers causes the addition of their two
exponents so that the sum of the two exponents could overflow. Underflow will occur when
a number is too small to be represented in the number system.
is the sign bit S, the next eleven bits are the exponent bits E, and the final 52 bits are the
fraction bits F . The IEEE floating-point format in double precision significantly increases
the dynamic range of number representation.
IEEE single precision: x = (−1)s × (1.F ) × 2E−127
31 30 23 22 0
S exponent fraction
63 62 52 51 0
S exponent fraction
Example 14: Convert the following IEEE 754 standard (single precision) to the decimal
number.
(i) 0 10000000 00000000000000000000000
(ii) 0 10000001 10100000000000000000000
(iii) 1 10000001 10100000000000000000000
(iv) 1 10000000 01000000000000000000000
Example 15: Convert the following IEEE 754 standard (double precision) to the decimal
number.
(i) 0 01000000000 110.....0
(ii) 1 10000000000 110.....0
Digital Signal Processing 15
Program Data
memory memory
I/O
ALU MAC Shifter
devices
The central processing unit (CPU) of TMS320C54xx processors consists of a 40- bit ALU,
two 40-bit accumulators, a barrel shifter, a 17x17 multiplier, a 40-bit adder, data address
generation logic (DAGEN) with its own arithmetic unit, and program address generation
logic (PAGEN). These major functional units are supported by a number of registers and logic
in the architecture. A powerful instruction set with a hardware-supported, single-instruction
repeat and block repeat operations, block memory move instructions, instructions that pack
two or three simultaneous reads, and arithmetic instructions with parallel store and load
make these devices very efficient for running high-speed DSP algorithms. Advanced Harvard
architecture is employed, where several instructions operate at the same time for given a given
single instruction cycle. Processing performance offers 40 million instructions per second
(MIPS).
MCBL/MP Timer
X1 0
Address Address
X2/CLKIN generator 0 generator 1 Timer
VDD 1
8 auxiliary registers
VSS
12 control registers
SHZ
The CPU register file offers 28 registers, which can be operated on by the multiplier
and ALU. It offers implementation of the DSP algorithm without worrying about problems
such as overflows and coefficient quantization. Three floating-point formats are supported.
A short 16-bit floating-point format, a 32-bit single precision format and a 40-bit extended
precision format. The TMS320C30 offers high-speed performance with 60-nanosecond single-
cycle instruction execution time, which is equivalent to 16.7 MIPS.
Z-1
b1/B
Z-1
b2/B
Z-1
Z-1
bk/B
Example 16: Given the FIR filter y(n) = 0.75x(n) + 3x(n − 1) + 0.75x(n − 2) with a passband
gain of 4, and assuming that the input range only occupies one quarter of the full range for
18 Module-0
a particular application, develop the DSP implementation equations in the Q-15 fixed-point
system.
The scale factor is determined using the impulse response, which consists of the FIR filter
coefficients:
1
S = (|h(0)| + |h(1)| + |h(2)|)
4
1
= (0.75 + 3 + 0.75) .
4
4.5
= = 1.125
4
Overflow may occur. Hence, we select S = 2 (a power of 2). We choose B = 4 to scale all
the coefficients to be less than 1. According to Fig. 11, the developed difference equations
are given by;
x(n) x(n)
xs (n) = s = 2 and y(n) = B × S × ys (n) = 4 × 2 × ys (n) = 8ys (n)
The direct-form I implementation of the IIR filter is illustrated in Fig. 12. As shown in
the figure, the purpose of the scale factor C (power of 2) is to scale down the original filter
coefficients to the Q-format.
Example 17: Given the IIR filter, y(n) = 2x(n)+0.5y(n−1), uses the direct-form I realization,
and for a particular application, the maximum input is Imax = 0:25. Develop the DSP
implementation equations in the Q-15 fixed-point system.
Z-1 Z-1
b1/C -a1/C
Z-1 Z-1
Z-1 Z-1
bM/C -aN/C
To prevent overflow in the adder, we can compute the S factor with the help of the
Maclaurin series, we get
0.25×2×1 0.5
S = 0.25 × 2(0.5)0 + 2(0.5)1 + 2(0.5)2 + 2(0.5)3 + · · · =
1−0.5 = 0.5 =1
Hence, we do not need to perform input scaling. However, we need scale down all the
coefficients to use the Q-15 format. A factor of C = 4 is selected. From Fig. 12, we get the
difference equations as
xs (n) = x(n)
ys (n) = 24 xs (n) + 0.5
4 yf (n − 1)
ys (n) = 0.5xs (n) + 0.125yf (n − 1)
yf (n) = 4ys (n) and y(n) = yf (n)
Two scale factors A and B are designated to scale denominator coefficients and numerator
coefficients to their Q-format representations, respectively. Further, S is a special factor to
scale down the input sample so that the numerical overflow in the first sum in Fig. 13, can
be prevented. All the scale factors A, B, and S are usually chosen to be a power of 2.
20 Module-0
ws(n) ys(n)
A w(n) b0/B
x(n) + + y(n)
1/S 1/A B S
Z-1
-a1/A b1/B
Z-1
Z-1
-aM/A bM/B
To avoid the first adder overflow , the scale factor S can be safely determined by
where h(k) is the impulse response due to the denominator polynomial of the IIR filter
h(n) = Z −1 1
1+a1 z −1 +···+aM z −M
Example 18: Given the IIR filter, y(n) = 0.75x(n) + 1.49x(n − 1) + 0.75x(n − 2) − 1.52y(n −
1) − 0.64y(n − 2) with a passband gain of 1 and a full range of input, use the direct-form II
implementation to develop the DSP implementation equations in the Q-15 fixed-point system.
Y (z) = 0.75X(z) + 1.49z −1 X(z) + 0.75z −2 X(z) − 1.52z −1 Y (z) − 0.64z −2 Y (z)
−1 −2 = X(z) 0.75 + 1.49z −1 + 0.75z −2
Y (z) 1 + 1.52z + 0.64z
Y (z) 0.75+1.49z −1 +0.75z −2
X(z) = H(z) = 1+1.52z −1 +0.64z −2
Digital Signal Processing 21
To avoid second adder overflow we have to ensure that each coefficient is less than 1,
along with the sum of the absolute values:
1 x(n)
xs (n) = x(n) =
S 16
1 1
ws (n) = w(n) = w(n)
A 2
1 1 1
ws (n) = x(n) − ∗ 1.52w(n − 1) − ∗ 0.64w(n − 2)
2 2 2
ws (n) = 0.5x(n) − 0.76w(n − 1) − 0.32w(n − 2)
w(n) = 2ws (n)
1 1
ys (n) = y(n) = y(n)
B 4
1 1 1
ys (n) = b0 w(n) + b1 w(n − 1) + b2 w(n − 2)
B B B
1 1 1
ys (n) = 0.75w(n) + 1.49w(n − 1) + 0.75w(n − 2)
4 4 4
ys (n) = 0.1875w(n) + 0.3725w(n − 1) + 0.1875w(n − 2)
y(n) = (B × S)ys (n) = (4 × 16)ys (n) = 64ys (n)