Bluetooth® Low Energy Wireless Network Coprocessor: Bluenrg-2N
Bluetooth® Low Energy Wireless Network Coprocessor: Bluenrg-2N
Datasheet
Features
Description
The BlueNRG-2N is an ultra low power (ULP) network coprocessor solution for
Bluetooth® low energy applications.
It embeds the STMicroelectronics’s state-of-the-art RF radio IPs combining
unparalleled performance with extremely long battery lifetime.
It is fully compliant with Bluetooth core specification version 5.2 and supports
enhanced features such as state-of-the-art security, privacy, and extended packet
length for faster data transfer up to 700 kbps at application level.
The BlueNRG-2N is Bluetooth® 5.2 certified ensuring interoperability with the latest
generation of smartphones and other host devices.
The Bluetooth low energy stack runs on the embedded ARM Cortex-M0 core.
The STMicroelectronics BLE stack is stored into the on-chip non-volatile Flash
memory and it can be easily upgraded via SPI/UART as well through the dedicated
STMicroelectronics software tools.
The BlueNRG-2N shows a reliable communication thanks to the best-in-class output power level assuring a
robust communication even in a noisy corrupted scenario without compromising the overall power consumption.
The BLUENRG-2N collaterals include comprehensive tools for developers such as a full featured SDK including:
• Templates
• High-level abstraction layer APIs (no BLE expertise required)
• Real-time debug capabilities
A dedicated firmware is provided to support the interface with an external application processor. The whole
Bluetooth low energy stack runs in the BlueNRG-2N; the GATT profiles are provided to run in the application
processor together with the application code. The figure below shows the network processor RF software layers.
2 Functional details
2.1 Core
The ARM® Cortex®-M0 processor has been developed to provide a low-cost platform that meets the needs
of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding
computational performance and an advanced system response to interrupts.
The ARM® Cortex®-M0 32-bit RISC processor features exceptional code-efficiency, delivering the high-
performance expected from an ARM core in the memory size usually associated with 8-bit and 16-bit devices.
The BlueNRG-2N has an embedded ARM core and is therefore compatible with all ARM tools and software.
The ARM Cortex M0 processor is reserved for internal operations and it is not open to customer application
developments.
LOCK RX/
Functional blocks RESET STANDBY SLEEP Preactive Active RX TX
LOCK TX
LDO_SOFT_1V2 or
OFF ON ON ON ON ON ON ON
LDO_SOFT_0V9
LDO_STRONG_1V2 OFF OFF OFF ON ON ON ON ON
LDO_DIG_1V8 OFF OFF OFF ON ON ON ON ON
SMPS OFF OFF OFF ON ON ON ON ON
LDO_DIG_1V2 OFF OFF OFF ON ON ON ON ON
BOR OFF OFF OFF ON ON ON ON ON
16 MHz RO OFF OFF OFF ON OFF OFF OFF OFF
32 MHz XO OFF OFF OFF OFF ON ON ON ON
32 kHz RO or XO OFF OFF ON ON ON ON ON ON
The low-frequency clock is used in low power mode and can be supplied either by a 32.7 kHz oscillator that uses
an external crystal and guarantees up to ±50 ppm frequency tolerance, or by a ring oscillator, which does not
require any external components.
The primary high-speed frequency clock is a 32 MHz crystal oscillator. A fast-starting 16 MHz ring oscillator
provides the clock while the crystal oscillator is starting up. Frequency tolerance of the high-speed crystal
oscillator is ±50 ppm.
Usage of the high-speed crystal usage is strictly necessary for RF communications.
If, for any reason, the user would like to power off the device there are two options:
1. Force RESETN pin to ground, keeping VBAT level
2. To put VBAT pins to ground (e.g. via a transistor)
In the second option, care must be taken to ensure that no voltage is applied to any of the other pins as the
device can be powered and have an anomalous power consumption. The ST recommendation is to use RESETN
whenever it is possible.
2.3.1.1 Power-on-Reset
The Power-on-Reset (POR) signal is the combination of the POR signal and the BOR signal generated by the
analog circuitry contained in the BlueNRG-2N device. The combination of these signals is used to generate the
input to the Cortex-M0, which is used to reset the debug access port (DAP) of the processor. It is also used to
generate the signal, which resets the debug logic of the Cortex-M0. The POR signal also resets the TAP controller
of the BlueNRG-2N and a part of the Flash controller (managing the Flash memory boot, which does not need to
be impacted by system resets).
The BOR reset is enabled by default. At software level, it can be decided to change the default values after reset.
VBATx
X=1,2,3
30 µs
RESETN
1.82 ms max.
Internal POR
System clock
• The VBATx power must only be raised when RESETN pin is low.
• The different VBATx (x=1,2,3) power can be raised separately or together.
• Once the VBATx (x=1,2,3) reaches the nominal value, the RESETN pin could be driven high after a 30 us.
• The internal POR is released once internal LDOs are established and RCO clock is ready.
• The system starts on RCO 16 MHz clock system. The software is responsible for configuring the XO 32 MHz
when necessary.
Note: The minimum negative pulse to reset the system must be at least 30 µs.
The POR circuit is powered by a 1.2 V regulator, which must also be powered up with the correct startup
sequence. Before VBAT has reached the nominal value, RESETN line must be kept low. An external RC circuit
on RESETN pin adds a delay that can prevent RESETN signal from going high before VBAT has reached the
nominal value.
If the above conditions are not satisfied, ST cannot guarantee the correct operation of the device.
The BlueNRG-2N could inform the external microcontroller via the host interface protocol on the internal reset
reason, which includes: POR, BOR, watchdog, lockup.
The Cortex-M0 subsystem of the BlueNRG-2N embeds four breakpoints and two watchpoints.
Radio mode differs from active mode as the RF transceiver is also active and is capable of either transmitting or
receiving.
3 Pin description
The BlueNRG-2N comes in two package versions: WCSP34 offering 14 GPIOs, QFN32 offering 15 GPIOs.
Figure 6. BlueNRG-2N pinout top view (QFN32) shows the QFN32 pinout, and Figure 7. BlueNRG-2N ball out top
view (WCSP34) shows the WCSP34 ball out.
SMPSFILT2
SMPSFILT1
RSSETN
VDD1V2
DIO12
DIO13
DIO11
TEST
32 31 30 29 28 27 26 25
DIO10 1 24 VBAT1
DIO9 2 23 SXTAL0
DIO8 3 22 SXTAL1
VBAT3 6 19 VBAT2
DIO5 7 18 FXTAL0
DIO4 8 17 FXTAL1
9 10 11 12 13 14 15 16
DIO3
DIO2
DIO1
DIO0
ADC1
ADC2
ANATEST1
ANATEST0/DIO14
Pins
Name I/O Description
QFN32 WCSP34
Pins
Name I/O Description
QFN32 WCSP34
1. The pin DIO7/BOOT is monitored by bootloader after power-up or hardware reset and it should be low to prevent unwanted
bootloader activation.
2. The pin DIO3 is monitored by the device updater FW after power-up or hardware reset and it should be low to prevent
unwanted updater FW activation.
4 Application circuit
C2
1.7 V to 3.6 V power supply
RESET RESETN
RESET & C3
DIO12 C19 C1
i/f sel SPI/UART
UART_RXD/SPI_CS
UART RXD L6
TXD UART_TXD C4
i/f
SPI_IN C5
SMPSFILT1 26RESETN
SPI_IN
L1
DIO12 30 DIO12
SPI_OUT UART_RXD/SPI_CS R1
SPI_OUT
SPI SPI_CLK
SPI_CLK C7
C6
32
TEST 31
DIO13 29
VDD1V2 28
SMPSFILT2 27
RESETN 25
33
i/f UART_RXD/SPI_CS U1
SPI_CS
GND
DIO11
DIO7
SPI_IRQ
Microcontroller i/f
1 24 XTAL1 C8 L4
2 DIO10 VBAT1 23
UART_TXD 3 DIO9 SXTAL0 22
4 DIO8 GND pad SXTAL1 21 C10 L5 C11
DIO7
ANATEST0/DIO14
8 17 C18
DIO4 FXTAL1 C12
L3
ADC1
ADC2
DIO3
DIO2
DIO1
DIO0
XTAL2
BlueNRG-232N C14
10
11
12
13
14
15
16
9
C17 C16
SPI_OUT
SPI_CLK
L2
SPI_IN
SPI_IN C5
SPI_IN
DIO12 30 DIO12
SPI_OUT UART_RXD/SPI_CS R1 L1
SPI_OUT
SPI SPI_CLK
SPI_CLK C7
C6
DIO11 32
TEST 31
DIO13 29
VDD1V2 28
SMPSFILT2 27
RESETN 25
33
i/f UART_RXD/SPI_CS U1
SPI_CS
GND
DIO7
SPI_IRQ
Microcontroller i/f 1 24 C8 L4
2
DIO10 VBAT1 XTAL1
UART_TXD DIO9 SXTAL0 23
DIO7 4
3
DIO8 GND pad SXTAL1 22 C10 L5 C11
DIO7 RF0 21
ANATEST0/DIO14
XTAL2
C14
10
11
12
13
14
15
16
9
BlueNRG-232N
C17 C16
SPI_CLK
L2
SPI_OUT
SPI_IN
C2
1.7 V to 3.6 V power supply
C1 C4 C19
C5
L1
L6
C3 C7
RESETN C6
RESET & RESET C15
L8 L7
DIO12
VBAT3 A3
VBAT1 E6
GND_ANA A4
VDD1V2 F3
SMPSFILT2 F4
SMPSFILT1 F6
i/f sel
GND_DIG C1
GND_ANA B6
SPI/UART
SMPSGND F5
U5
UART_RXD/SPI_CS
UART RXD
UART_TXD SPI_CLK A2 XTAL1
i/f TXD DIO0
SPI_IN
B2
DIO1 SXTAL0 E5
SPI_OUT A1
SPI_IN SPI_IN B1
DIO2 SXTAL1 E4 C8 L4
SPI_OUT DIO3
SPI_OUT C3
DIO4
SPI SPI_CLK C2
DIO5 C10 L5 C11
SPI_CLK D1 C6
DIO6 RF1
ANATEST0/DIO14
i/f UART_RXD/SPI_CS DIO7 D2
DIO7 RF0 D6 C9
SPI_CS UART_TXD D3
DIO7 E1
DIO8
SPI_IRQ DIO9 C13
F1
ANATEST1
DIO10
Microcontroller i/f UART_RXD/SPI_CS E2
DIO11 FXTAL1 A6 L3 C12
RESETN
DIO12 F2
DIO12 FXTAL0 B5
FTEST
ADC2
ADC1
XTAL2
C14
D5
E3
B3
B4
BlueNRG-234N
D4
A5
C17 C16
RESETN
L2
Figure 12. Application circuit: non active DC-DC converter WCSP34 package
C1 C2
C4
C5
L1
C3 C7
RESETN C6
RESET & RESET C15
i/f sel DIO12
C1
A3
E6
A4
B6
SPI/UART
F3
F4
F5
F6
U5
UART_RXD/SPI_CS
SMPSFILT1
SMPSGND
RXD
SMPSFILT2
VBAT3
VBAT1
GND_ANA
GND_ANA
GND_DIG
VDD1V2
UART XTAL1
TXD UART_TXD A2
SPI_CLK
DIO0
i/f
SPI_IN
B2
SPI_OUT A1
DIO1 SXTAL0 E5
SPI_IN DIO2 SXTAL1 E4
SPI_OUT SPI_IN B1
DIO3 C8 L4
SPI_OUT C3
DIO4
SPI SPI_CLK C2
DIO5 C10 L5 C11
SPI_CLK
UART_RXD/SPI_CS
D1
DIO6 RF1 C6 C9
i/f
ANATEST0/DIO14
DIO7 D2
SPI_CS D3
DIO7 RF0 D6
DIO7
UART_TXD
E1
DIO8 C13
SPI_IRQ F1
DIO9
DIO10
ANATEST1
C12
Microcontroller i/f UART_RXD/SPI_CS E2
DIO11 FXTAL1 A6 L3
RESETN
ADC2
ADC1
XTAL2
C14
D5
B4
B3
E3
D4
BlueNRG-234N
A5
C17 C16
RESETN
L2
Figure 13. Application circuit: active DC-DC converter QFN32 package with BALF-NRG-02D3 balun
C2
1.7 V to 3.6 V power supply
RESET RESETN
RESET & C3
i/f sel DIO12 C19 C1
SPI/UART
UART_RXD/SPI_CS
UART RXD L6
TXD UART_TXD C4
i/f
RESETN 25 RESETN
SPI_IN C5
SPI_IN
DIO12 30 DIO12
SPI_OUT UART_RXD/SPI_CS R1 L1
SPI_OUT
SPI SPI_CLK
SPI_CLK C7
C6
DIO11 32
TEST 31
DIO13 29
VDD1V2 28
SMPSFILT2 27
SMPSFILT1 26
GND 33
i/f UART_RXD/SPI_CS U1
SPI_CS
DIO7
SPI_IRQ
Microcontroller i/f
1 DIO10 VBAT1 24 XTAL1
23
UART_TXD 2 DIO9 SXTAL0 22 U2 L3
3 DIO8 GND pad SXTAL1 21 1
1.7 V to 3.6 V power supply DIO7 4 DIO7 RF0 20 2 B1 A1 4
3
13 ANATEST0/DIO14
5 DIO6 RF1 B2 A2
6 VBAT3 VBAT2 19 C13
7 DIO5 FXTAL0 18 C10
C15 17
14 ANATEST1
8 DIO4 FXTAL1 C18 BALF-NRG-02D3
15 ADC1
16 ADC2
9 DIO3
10 DIO2
11 DIO1
12 DIO0
XTAL2
BlueNRG-232N
C17 C16
SPI_OUT
SPI_CLK
L2
SPI_IN
Component Description
C1 Decoupling capacitor
C2 DC-DC converter output capacitor
C3 Decoupling capacitor for 1.2 V digital regulator
C4 Decoupling capacitor for 1.2 V digital regulator
C5 Decoupling capacitor
C6 32 kHz crystal loading capacitor
C7 32 kHz crystal loading capacitor
C8 RF balun/matching network capacitor
C9 RF balun/matching network capacitor
C10 RF balun/matching network capacitor
C11 RF balun/matching network capacitor
C12 RF balun/matching network capacitor
C13 RF balun/matching network capacitor
C14 RF balun/matching network capacitor
C15 Decoupling capacitor
C16 32 MHz crystal loading capacitor
C17 32 MHz crystal loading capacitor
C18 Decoupling capacitor
C19 DC-DC converter output capacitor
L1 32 kHz crystal filter inductor
L2 32 MHz crystal filter inductor
Component Description
The application controller interface (ACI) is based on a standard UART/SPI module. The ACI defines a protocol
providing access to all services offered by the layers of the embedded Bluetooth stack. ACI commands are
described in the BlueNRG-232N ACI command interface documentation. In addition, ACI provides a set of
commands that allow the BlueNRG-232N firmware to be programmed from an external device connected to SPI
or UART.
The complete description of updater commands and procedures is provided in a separate application note.
The BlueNRG-2N provides a hardware interface to external microcontroller based on two very common protocols:
• SPI slave protocol with interrupt signal
• UART
The selection between SPI or UART mode is done through the DIO12 pin. Refer to Table 3. Pinout description,
DIO12 description for UART, SPI selection options.
The physical layer (SPI or UART) is used to transfer commands and events between the external microcontroller
and the BlueNRG-2N.
The commands and events are collectively named application control interface (ACI) and they are described in
the BlueNRG-2N ACI documentation.
In addition, ACI provides a set of commands that allow the BlueNRG-2N firmware to be programmed/updated
from an external device connected to SPI or UART.
Pin number
Pin function Pin name Information
QFN32 WCSP34
Figure 14. Generic SPI transaction shows a generic SPI transaction. The list of steps is as follows:
1. The external uC lowers the SPI CS signal to start the communication.
2. The BlueNRG-2N raises the SPI IRQ signal to indicate that it is ready for the communication. The time t1
changes according to the state of the BlueNRG-2N. This time t1 can include wakeup of the BlueNRG-2N
and preparation of the header part of the frame.
3. The external uC must wait for the SPI IRQ signal to become high and then start to transfer the five bytes of
the header that includes the control field with the intended operation. In addition, the external uC reads five
bytes from the BlueNRG-2N, which include information about the actual size of the read and write buffer.
4. The external uC, after checking the five bytes of header, performs data transaction.
5. The BlueNRG-2N lowers SPI IRQ signal after the five byte headers are transferred, but due to internal
processing, this could be done also during the data transfer phase.
6. The external uC must wait for the SPI IRQ to be low before raising the SPI CS signal to mark the end of the
communication.
Some important notes are:
• Setting the SPI CS signal low wakes up the BlueNRG-2N if the device is asleep
• If the SPI IRQ signal is low before setting the SPI CS signal low, the BlueNRG-2N has no data events for the
external uC, so the read buffer size is zero (RBUF=0)
• The time t1 is the time between wake-up (point a in Figure 14. Generic SPI transaction) and the
BlueNRG-2N ready to perform the SPI transaction (point b in Figure 14. Generic SPI transaction). The
t1 time range is from minimal value (the BlueNRG-2N already awakes when the SPI CS is asserted), to a
maximum value that involves wake-up sequence and software boot
• Even if there are events pending after the end of the transaction, the SPI IRQ signal goes low to allow the
BlueNRG-2N to update five byte headers and to re-arm the SPI for the next transaction (after this delay the
SPI IRQ signal goes high again if events are pending)
• The SPI CS signal marks the beginning and end of the transaction
• The SPI CS high marks the end of the transaction and must be set to high only when IRQ line is low
• The gap between the header and the data is not mandatory, but it is normally required by the external uC to
process the header and check if there is enough space in the buffers to perform the wanted transaction
• When the SPI IRQ signal is high, the five byte headers are locked and cannot be modified by the
BlueNRG-2N firmware
• The header of the external uC (the SPI master) is on the MOSI line, which is composed of one control byte
(CTRL) and four bytes 0x00. CTRL field can have only the value of 0x0A (SPI write) or 0x0B (SPI read). The
BlueNRG-2N returns the header on the MISO line at the same time. When the BlueNRG-2N asserts the SPI
IRQ signal, it is ready. Otherwise, the BlueNRG-2N is still not initialized. The external uC must wait for the
IRQ line to become high and perform a five bytes transaction.
The five bytes in the MISO line gives one byte of starting frame, two bytes with the size of the write buffer
(WBUF) and two bytes with the size of the read buffer (RBUF). The endianness for WBUF and RBUF is LSB
first. The value in WBUF means how many bytes the master can write to the BlueNRG-2N. The value in
RBUF means how many bytes in the BlueNRG-2N are waiting to be read by the external uC
Read transaction
A read transaction is performed when the BlueNRG-2N raises the SPI IRQ line before the SPI CS signal is
lowered by the external uC.
• In this case, the SPI IRQ signal is high indicating the BlueNRG-2N is awake and ready to perform the SPI
transaction, after a hardware dependent set-up time t2 (>=0.5 us). The transaction is performed as follows:
1. An event has been generated by the BlueNRG-2N (point a in Figure 16. SPI read transaction ).
2. The external uC lowers the SPI CS signal to initiate a transaction (point b in Figure 16. SPI read
transaction).
3. Since the SPI IRQ signal is high, the external uC initiates a data transfer after t2. The external uC
transfers five bytes as follows [0x0B, XX, XX, XX, XX]. The WBUF and RBUF sizes are read by the SPI
MISO signal.
4. The external uC performs the read data transaction for RBUF bytes. (Note: if RBUF is 0, this is
an unexpected condition since the BlueNRG-2N is indicating that data is available; in any case the
transaction needs to be completed by reading no bytes).
5. The BlueNRG-2N lowers SPI IRQ signal after the five bytes header are transferred, but due to internal
processing, this could be done also during the data transfer phase.
6. The external uC must wait for the SPI IRQ to be low before raising the SPI CS signal to mark the end
of the communication.
Write transaction
• A write transaction is performed by the external uC to send a command to the BlueNRG-2N. The
BlueNRG-2N can be awakened or put to sleep when the SPI CS signal is lowered by the external uC.
The assertion of the SPI CS signal wakes up the BlueNRG-2N, if asleep
Error transaction
• This section lists the BlueNRG-2N firmware behavior when some error transactions are performed:
– Incomplete header transaction (0 to 4): the BlueNRG-2N ignores the transaction
– The external uC does not wait for the SPI IRQ signal to be low before raising the SPI CS signal: the
BlueNRG-2N lowers the SPI IRQ signal when the SPI CS signal is high
– The external uC does not wait for the SPI IRQ signal to be high before SPI clock starts: the result is
acquisition of corrupted data both master and slave side
– Incomplete read transaction: the master loses the event
– Incomplete write transaction: the BlueNRG-2N stores the bytes written by the external uC. During the
next write operation the BlueNRG-2N gets the new bytes trying to get a complete frame according to
Bluetooth protocol
– Two commands in a row without reading event for command: the BlueNRG-2N parses the two
commands and then it generates the corresponding events
Boot/transient state
Init - IRQ=0 Configured
Hardware initialization
CS=0 IRQ=1 Waiting_Header
CS=1
Ready to transfer information, 5 byte IRQ=0 Sleep
Configured Event pending=0
header frozen
CS=1
IRQ=1 Configured
Event pending=1
CS=1
IRQ=0 Sleep
Event pending=0
Sleep Sleep state with almost all logic off CS=1
IRQ=0 Configured
Event pending=1
CS=0 IRQ=0 Configured
When 5-byte are received
Receiving 5 byte header from SPI CS=0 IRQ=1
Waiting_Header goes to Header_Received
master
CS=1 IRQ=1 Transaction_Complete
CS=0 IRQ=0 Waiting_Data
Header_Received 5 byte header received
CS=1 IRQ=0 Transaction_Complete
CS=0 IRQ=0 Waiting_Data
Waiting_Data Receiving payload
nCS=1 IRQ=0 Transaction_Complete
Transaction_Complete Transitional nCS=1 IRQ=0 Configured
Init
O:IRQ=0
I:nCS=1,EV_Pending=1
Configured
O:IRQ=1
I:nCS=0
I:nCS=1, EV_Pending=0 I:nCS=0I:EV_Pending=1
O:IRQ=1
O:IRQ=0
Header_Received
I:nCS=1
Timeout expired
O:IRQ=0
I:nCS=1
Transaction_Complete
External uC behavior
• The external uC must act according to the information from the BlueNRG-2N:
– SPI IRQ signal
– Information from header frame WBUF and RBUF
Init
Ready
I:IRQ=1 I:CMD_Pending=1
O:CS=0, CTRL=0x0B O:CS=0, CTRL=0x0A
I:CTRL=0x0A I:CMD_len<=WBUF
O:Read RBUF bytes O:Write WBUF bytes
I:CMD_len>WBUF, IRQ=0
Get_Data Transfert not complete Send_Data Transfert not complete
O: CS=1
I:IRQ=0 I:IRQ=0
O:CS=1 O:CS=1
Transaction_Complete
Note: Absolute maximum ratings are those values above which damage to the device may occur. Functional operation
under these conditions is not implied. All voltages are referred to GND.
34 (QFN32)
Rthj-amb Thermal resistance junction-ambient °C/W
50 (WLCSP34)
2.5 (QFN32)
Rthj-c Thermal resistance junction-case °C/W
25 (WLCSP34)
8 General characteristics
9 Electrical specifications
T(RST)L 1.5 ms
TC 3.3 V
TC1 2.5 V
TC2 1.8 V
VIL 0.3*VDD V
VIH 0.65*VDD V
VOL IOL = 3 mA 0.4 V
VOH IOH = 3 mA 0.7*VDD V
TC (VOL = 0.4 V) 5.6 mA
IOL (low drive strength) TC1 (VOL = 0.42 V) 6.6 mA
TC2 (VOL = 0.45 V) 3 mA
TC (VOL = 0.4 V) 11.2 mA
IOL (high drive strength) TC1 (VOL = 0.42 V) 13.2 mA
TC2 (VOL = 0.45 V) 6 mA
TC (VOL = 0.4 V) 16.9 mA
IOL (Very high drive strength) TC1 (VOL = 0.42 V) 19.9 mA
TC2 (VOL = 0.45 V) 9.2 mA
TC (VOH = 2.4 V) 10.6 mA
IOH (low drive strength) TC1 (VOH = 1.72 V) 7.2 mA
TC2 (VOH = 1.35 V) 3 mA
TC (VOH = 2.4 V) 19.2 mA
IOH (high drive strength) TC1 (VOH = 1.72 V) 12.9 mA
TC2 (VOH = 1.35 V) 5.5 mA
TC (VOH = 2.4 V) 29.4 mA
IOH (very high drive strength) TC1 (VOH = 1.72 V) 19.8 mA
TC2 (VOH = 1.35 V) 8.4 mA
Static supply 1.7 V 5 10 µA
IPUD (current sourced/sinked from IOs with pull enabled)
Static supply 3.6 V 40 60 µA
1. Simulated value.
Low power consumption and fast start-up time is achieved by choosing a quartz crystal with a low load
capacitance C0. A reasonable choice for capacitor C0 is 12 pF. To achieve good frequency stability, the following
equation needs to be satisfied:
∁′ *∁′
∁0 = ∁ 1+ ∁2 (1)
1 2
Where C1’=C1+CPCB1+CPAD, C2’= C2+CPCB2+CPAD, where C1 and C2 are external (SMD) components, CPCB1
and CPCB2 are PCB routing parasites and CPAD is the equivalent small-signal pad-capacitance. The value of CPAD
is around 0.5 pF for each pad. The routing parasites should be minimized by placing quartz and C1/C2 capacitors
close to the chip, not only for an easier matching of the load capacitance C0, but also to ensure robustness
against noise injection. Connect each capacitor of the Xtal oscillator to ground by a separate vias.
Note: These values are the correct ones for NX3215SA-32.768 kHz-EXS00A-MU00003.
Nominal
fNOM – 14 – MHz
frequency
10 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
QFN32_POA_8362854_B
mm
Dim.
Min. Typ. Max.
Figure 26. WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline
See Note 1
WLCSP34_POA_8165249
1. The corner of terminal A1 must be identified on the top surface by using a laser marking dot.
Table 22. WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data
mm.
Dim. Notes
Min. Typ. Max.
A 0.50
A1 0.20
b 0.27 (1)
D1 2.00
E1 2.00
e 0.40
f 0.28
g 0.33
ccc 0.05
For Flip Chip mounting on the PCB, STMicroelectronics recommends the use of a solder stencil aperture of 330 x
330 µm maximum and a typical stencil thickness of 125 µm.
Flip Chips are fully compatible with the use of near eutectic 95.8% Sn, 3.5% Ag, 0.7% Cu solder paste with
no-clean flux. ST's recommendations for Flip-Chip board mounting are illustrated on the soldering reflow profile
shown in Figure 27. Flip Chip CSP (2.71 x 2.58 x 0.5 pitch 0.4 mm) package reflow profile recommendation.
Figure 27. Flip Chip CSP (2.71 x 2.58 x 0.5 pitch 0.4 mm) package reflow profile recommendation
Table 23. Flip Chip CSP (2.71 x 2.58 x 0.5 pitch 0.4 mm) package reflow profile recommendation
Value
Profile
Typ. Max.
Dwell time in the soldering zone (with temperature higher than 220 °C) has to be kept as short as possible to
prevent component and substrate damage. Peak temperature must not exceed 260 °C. Controlled atmosphere
(N2 or N2H2) is recommended during the whole reflow, especially above 150 °C.
Flip Chips are able to withstand three times the previous recommended reflow profile to be compatible with a
double reflow when SMDs are mounted on both sides of the PCB plus one additional repair.
A maximum of three soldering reflows are allowed for these lead-free packages (with repair step included).
The use of a no-clean paste is highly recommended to avoid any cleaning operation. To prevent any bump
cracks, ultrasonic cleaning methods are not recommended.
12 Ordering information
Revision history
Contents
1 High performance and benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Functional details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.1 State description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of tables
Table 1. Relationship between the BlueNRG-2N states and functional blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. SWD port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. External component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. BlueNRG-2N SPI lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. BlueNRG-2N SPI state machine states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. BlueNRG-2N SPI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 10. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. Digital I/O specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. RF general characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. RF transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. RF receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. High speed crystal oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 17. Low speed crystal oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. High speed ring oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19. Low speed ring oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 20. N-Fractional frequency synthesizer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. QFN32 (5 x 5 x 1 pitch 0.5 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 22. WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 23. Flip Chip CSP (2.71 x 2.58 x 0.5 pitch 0.4 mm) package reflow profile recommendation . . . . . . . . . . . . . . . . . . 40
Table 24. Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
List of figures
Figure 1. BlueNRG-2N network processor RF software layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. BlueNRG-2N power management state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Reset and wake-up generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. BlueNRG-2N power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. BlueNRG-2N pinout top view (QFN32). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. BlueNRG-2N ball out top view (WCSP34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. BlueNRG-2N ball out bottom view (WCSP34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Application circuit: active DC-DC converter QFN32 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Application circuit: non-active DC-DC converter QFN32 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. Application circuit: active DC-DC converter WCSP34 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Application circuit: non active DC-DC converter WCSP34 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Application circuit: active DC-DC converter QFN32 package with BALF-NRG-02D3 balun . . . . . . . . . . . . . . . 16
Figure 14. Generic SPI transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 15. SPI header format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 16. SPI read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. SPI write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. SPI protocol state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. Expected uC SPI protocol state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. HCI_READ_LOCAL_VERSION_INFORMATION SPI waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. HCI_READ_LOCAL_VERSION_INFORMATION SPI waveform zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 22. HCI_COMMAND_COMPLETE_EVENT SPI waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 23. High speed oscillator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 24. QFN32 (5 x 5 x 1 pitch 0.5 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 25. QFN32 (5 x 5 x 1 pitch 0.5 mm) package detail "A" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 26. WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 27. Flip Chip CSP (2.71 x 2.58 x 0.5 pitch 0.4 mm) package reflow profile recommendation. . . . . . . . . . . . . . . . . 40